Rev 2; 4/08 106.25MHz/212.5MHz/425MHz Clock Oscillators The DS4106, DS4212, and DS4425 ceramic surfacemount crystal oscillators are part of Maxim’s DS4-XO series of crystal oscillators. These devices offer output frequencies at 106.25MHz, 212.5MHz, and 425MHz. The clock oscillators are suited for systems with tight tolerances because of the jitter, phase noise, and stability performance. The small package provides a format made for applications where PCB space is critical. These clock oscillators are crystal based and use a fundamental crystal with PLL technology to provide the final output frequencies. Each device is offered with LVDS or LVPECL output types. The output enable pin is active-high logic. These clock oscillators have very low phase jitter and phase noise. Typical phase jitter is < 0.9ps RMS from 12kHz to 20MHz. The devices are designed to operate with a 3.3V ±10% supply voltage, and are available in a 5.0mm x 3.2mm x 1.49mm, 10-pin LCCC surface-mount ceramic package. Applications Features ♦ Clock Output Frequencies: DS4106: 106.25MHz DS4212: 212.50MHz DS4425: 425.00MHz ♦ Phase Jitter (RMS): 0.9ps Typical ♦ LVPECL or LVDS Output ♦ Supply Current: 50mA (Typical, Unloaded) at +3.3V Supply (LVPECL) 53mA (Typical) at +3.3V Supply (LVDS) ♦ -40°C to +85°C Temperature Range ♦ Output Disable Ordering Information PART TEMP RANGE PIN-PACKAGE DS4106AN+ -40°C to +85°C 10 LCCC DS4106BN+ -40°C to +85°C 10 LCCC DS4212AN+ -40°C to +85°C 10 LCCC DS4212BN+ -40°C to +85°C 10 LCCC Fibre Channel Hard Disk Drives DS4425AN+ -40°C to +85°C 10 LCCC Host Bus Adapters DS4425BN+ -40°C to +85°C 10 LCCC Raid Controllers +Denotes a lead(Pb)-free package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes. Fibre Channel Switches Pin Configuration and Selector Guide appear at end of data sheet. Typical Operating Circuits VCC VCC VCC OE VCC OUTP VCC OE OUTP VCC 50Ω VCC - 2V DS4106/ DS4212/ DS4425 50Ω 100Ω LVPECL DS4106/ DS4212/ DS4425 OUTN GND 100Ω LVDS OUTN LVPECL OPTION GND LVDS OPTION ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS4106/DS4212/DS4425 General Description DS4106/DS4212/DS4425 106.25MHz/212.5MHz/425MHz Clock Oscillators ABSOLUTE MAXIMUM RATINGS VCC, GND, OE, OUTP, OUTN .....................................-0.3V, +4V Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-40°C to +125°C Soldering Temperature Profile (3 passes max) ...............................See IPC/JEDEC J-STD-020 Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 3.0V to 3.6V, TA = -40°C to +85°C, typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER Supply Voltage SYMBOL VCC CONDITIONS MIN TYP MAX UNITS 3.0 3.3 3.6 V LVPECL (Note 3) 50 65 LVDS 53 67 (Note 2) mA Supply Current ICC TTL Control Input-Voltage High (OE) VIH (Note 2) 2 VCC V TTL Control Input-Voltage Low (OE) VIL (Note 2) 0 0.8 V Input Leakage Current I IL GND OE VCC -50 +10 μA LVPECL OUTPUTS (Note 4) Output High Voltage VOH (Note 2) VCC - 1.085 VCC - 0.88 V Output Low Voltage VOL (Note 2) VCC - 1.825 VCC - 1.62 V Output Leakage Current (Absolute) I OL OE = VIL LVDS Output High Voltage VOH (Note 2) LVDS Output Low Voltage VOL (Note 2) LVDS Differential Output Voltage |VOD| 100 μA LVDS OUTPUTS (Figure 2) LVDS Change in VOD for Complementary States LVDS Offset Output Voltage (Output Common-Mode Voltage) 2 1.475 0.925 250 |VOD| VOS V 400 25 (Note 5) 1.125 _______________________________________________________________________________________ V 1.275 mV V 106.25MHz/212.5MHz/425MHz Clock Oscillators (VCC = 3.0V to 3.6V, TA = -40°C to +85°C, typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL LVDS Change in VOS for Complementary States |VOS| LVDS Differential Output Impedance R OLVDSO LVDS Output Current Output Current ILVDSO CONDITIONS MIN TYP 80 Outputs shorted together MAX UNITS 150 mV 140 12 I VSSLVDSO Short to ground mA 40 mA CLOCK OUTPUT Clock Output Frequency Frequency Stability Total Initial Frequency Tolerance fO f / f O f_TOL Frequency Stability vs. Temperature f / f O |TA Frequency Stability vs. VCC f / f O | V Frequency Stability vs. Load f / f O |LOAD Aging (15 Years) fAGING Phase Jitter (RMS) PJRMS Accumulated Deterministic Jitter Due to Power-Supply Noise (P-P) DS4106 106.25 DS4212 212.5 DS4425 425.0 Temperature, aging, load, and supply -39 +25°C, ±3°C, VCC = 3.3V tR, tF +39 ±20 VCC = 3.3V ±10% ppm -3 +3 ppm/V ±1 -7 12kHz to 20MHz +7 3 100kHz 27 200kHz 15 +25°C Oscillation Startup Time (Note 6) ppm 0.9 10kHz Clock Output Duty Cycle ppm +30 ±10% variation in termination resistance 20% to 80% ppm -30 1MHz Clock Output Edge Speeds MHz ppm ps ps 7 LVPECL 200 LVDS 175 45 ps 55 10 % ms _______________________________________________________________________________________ 3 DS4106/DS4212/DS4425 ELECTRICAL CHARACTERISTICS (continued) DS4106/DS4212/DS4425 106.25MHz/212.5MHz/425MHz Clock Oscillators ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.0V to 3.6V, TA = -40°C to +85°C, typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS 100Hz DS4106 at 106.25MHz Clock Output SSB Phase Noise DS4212 at 212.50MHz DS4425 at 425.00MHz MIN TYP MAX UNITS -90 1kHz -112 10kHz -115 100kHz -123 1MHz -142 10MHz -147 100Hz -82 1kHz -106 10kHz -109 100kHz -117 1MHz -136 10MHz -141 100Hz -76 1kHz -100 10kHz -103 100kHz -111 1MHz -130 10MHz -135 dBc/Hz Limits at -40°C are guaranteed by design and are not production tested. Voltage referenced to ground. Outputs are enabled and unloaded. When the LVPECL output is disabled, the typical output off current is < 100µA for nominal LVPECL signal levels at the output. Note 5: AC parameters are guaranteed by design and characterization. Note 6: Including oscillator startup time and PLL acquisition time, measured after VCC reaches 3.0V from power-on. Note 1: Note 2: Note 3: Note 4: 4 _______________________________________________________________________________________ 106.25MHz/212.5MHz/425MHz Clock Oscillators PIN 1 NAME FUNCTION OE Output Enable. On-chip pullup resistor. Connect OE to logic-high, VCC, or leave open to enable the output clock. Connect OE to logic-low or GND to disable the output clock. The LVPECL output clock is set to high impedance when disabled. The LVDS output clock is latched to a differential high when disabled. 2, 7–10 N.C. No Connection 3 GND Ground 4 OUTP Positive Clock Output, LVPECL or LVDS 5 OUTN Negative Clock Output, LVPECL or LVDS 6 VCC — EP +3.3V Supply Exposed Paddle. Do not connect this pad or place exposed metal under the pad. Detailed Description The DS4106/DS4212/DS4425 combine a crystal and an IC to form a precision clock. Figure 1 shows a functional diagram of the devices. The IC consists of a crystal oscillator, a low-noise PLL, selectable clock-divider circuitry, and an output buffer. The PLL consists of a digital phase/frequency detector (PFD) and low-jitter generation VCO. The VCO signal is scaled by a clockdivider circuit and applied to the output buffer. Output Drivers All devices are available with either LVPECL (DS4106A/DS4212A/DS4425A) or LVDS (DS4106B/ DS4212B/DS4425B) output buffers. When not needed, the output buffers can be disabled. When disabled, the LVPECL output buffer goes to a high-impedance state. However, the LVDS outputs go to a differential logic one (OUTP latched high and OUTN latched low) when the outputs are disabled. Additional Information For more available frequencies, refer to the DS4125 data sheet at www.maxim-ic.com/DS4125. VCC OUTP OSCILLATOR AMPLIFIER PFD LOOP FILTER VCO COUNTER M OUTPUT BUFFER OUTN VCC DS4106/ DS4212/ DS4425 COUNTER N OE GND Figure 1. Functional Diagram _______________________________________________________________________________________ 5 DS4106/DS4212/DS4425 Pin Description DS4106/DS4212/DS4425 106.25MHz/212.5MHz/425MHz Clock Oscillators D RL = 100Ω DC VOH OUTP SINGLE-ENDED OUTPUT IVODI VOS VOL OUTN +VOD DIFFERENTIAL OUTPUT VODP - P = VOUTP - VOUTN 0V (DIFF) -VOD Figure 2. LVDS Level Definitions Selector Guide PART OUTPUTS FREQUENCY (MHz) TOP MARK DS4106AN+ LVPECL 106.25 06A DS4106BN+ LVDS 106.25 06B DS4212AN+ LVPECL 212.50 12A DS4212BN+ LVDS 212.50 12B DS4425AN+ LVPECL 425.00 42A DS4425BN+ LVDS 425.00 42B +Denotes a lead-free package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and leadfree soldering processes. 6 _______________________________________________________________________________________ 106.25MHz/212.5MHz/425MHz Clock Oscillators Thermal Information THETA-JA (°C/W) TOP VIEW N.C. 90 N.C. + OE N.C. GND 6 1 2 3 DS4106/ DS4212/ DS4425 *EP N.C. Package Information VCC For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. 5 4 OUTN PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10 LCCC L1053+H2 21-0389 OUTP N.C. (5.00mm × 3.20mm × 1.49mm) *EXPOSED PAD _______________________________________________________________________________________ 7 DS4106/DS4212/DS4425 Pin Configuration DS4106/DS4212/DS4425 106.25MHz/212.5MHz/425MHz Clock Oscillators Revision History REVISION NUMBER REVISION DATE 0 7/07 1 2 10/07 4/08 DESCRIPTION PAGES CHANGED Initial release. — In the General Description section, corrected power-supply tolerance from 5% to 10%. 1 In the Electrical Characteristics table, added the input voltage max value of VCC and input voltage min of 0 for VIH and VIL; added GND OE VCC for conditions on input leakage (IIL); corrected Accumulated Deterministic Jitter Due to Reference Spurs parameter to Accumulated Deterministic Jitter Due to PowerSupply Noise. 2, 3 In the Electrical Characteristics table, changed the clock output frequency (fO) typ from 106.2MHz to 106.25MHz. 3 In the Pin Description, changed the exposed pad description to indicate that it should not be connected and to avoid placing exposed metal under the pad location. 5 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.