MAXIM MAX3620BETT

19-3550; Rev 0; 1/05
Delay Lines for High-Speed Clock
Distribution Systems
The MAX3620 series is a family of high-performance
passive delay lines for use in QDR/QDRII synchronous
memory systems. These delay lines support high-speed
transceiver logic (HSTL) source terminated transmission
with an unterminated load at the receiver, and deliver
accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns
for the generation of the quarter clock phase. The
MAX3620 is offered in a small 3mm x 3mm package
which contains two delay lines of equal length that can
be driven either differentially or single-endedly.
Features
♦ Supports HSTL Source Terminated Lines
♦ All-Passive Design
♦ Compatible with 100Ω Differential and 50Ω SingleEnded Transmission Lines
♦ Small 3mm x 3mm Package
Ordering Information
Applications
QDR/QDRII Memory Systems
PART
Multiphase Clock Generation
Pin Configuration
TOP VIEW
IN1
1
COMMON
2
IN2
MAX3620
3
6
OUT1
5
COMMON
4
TEMP RANGE
PIN-PACKAGE
MAX3620AETT
-40°C to +85°C
6 TDFN
MAX3620BETT
-40°C to +85°C
6 TDFN
MAX3620CETT
-40°C to +85°C
6 TDFN
MAX3620DETT
-40°C to +85°C
6 TDFN
Selector Guide
PART
OUT2
*EP
PKG CODE
TOP MARK
MAX3620AETT
T633-2
AJX
MAX3620BETT
T633-2
AIY
MAX3620CETT
T633-2
AIZ
MAX3620DETT
T633-2
AJA
TDFN
*EP—EXPOSED PAD. MUST BE CONNECTED TO THE
SAME POTENTIAL AS COMMON.
Typical Application Circuit
QDR II SRAM CLOCK OUTPUT
HSTL SOURCE TERMINATED
50Ω
QDR II SRAM CLOCK INPUT
HSTL HIGH-Z CMOS
DELAY LINE
1/4 CLOCK PERIOD
IN1
OUT1
COMMON
90° PHASE
50Ω
COMMON
MAX3620
50Ω
270° PHASE
IN2
OUT2
50Ω
50Ω
180° PHASE
50Ω
50Ω
0° PHASE
50Ω
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX3620
General Description
MAX3620
Delay Lines for High-Speed Clock
Distribution Systems
ABSOLUTE MAXIMUM RATINGS
Maximum DC Voltage between COMMON and IOs
(IN1, IN2, OUT1, OUT2)......................................................±2.0V
Operating Temperature Range ...........................-45°C to +85°C
Storage Temperature Range .............................-55°C to +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical ambient temperature is +25°C. See Table 1 for more information.)
PARAMETER
Characteristic Impedance
Delay Values
Delay Matching
SYMBOL
Z0
CONDITIONS
TYP
MAX3620A
0.65
0.75
0.85
MAX3620B
0.90
1.00
1.10
MAX3620C
1.15
1.25
1.35
MAX3620D
1.40
1.50
1.60
See Table 1 clock frequency
ZLOAD = ZSOURCE
(Note 1)
IN2-to-OUT2 relative to IN1-to-OUT1,
ZLOAD = ZSOURCE
ZLOAD = ZSOURCE
(Notes 1, 2, 4)
Insertion Loss
ZLOAD >> Z SOURCE,
source termination only
(Notes 5, 6)
Cutoff Frequency,
3dB Loss Relative to 10MHz
MIN
ZLOAD = ZSOURCE
(Note 3)
MAX
Ω
50
-20
+20
MAX3620A
2.5
MAX3620B
2.1
MAX3620C
2.3
MAX3620D
2.2
MAX3620A
4.6
MAX3620B
3.8
MAX3620C
3.1
MAX3620D
3.4
MAX3620A
450
MAX3620B
370
MAX3620C
320
MAX3620D
300
UNITS
ns
ps
dB
MHz
Input Return Loss
ZLOAD = ZSOURCE, 50MHz to 1GHz
(Note 3)
12
dB
Output Return Loss
ZLOAD = ZSOURCE, 50MHz to 1GHz
(Note 3)
15
dB
Input Leakage at ±1.5V
IN1 or IN2 to grounded COMMON
-10
+10
µA
Output Leakage at ±1.5V
OUT1 or OUT2 to grounded COMMON
-10
+10
µA
ZLOAD = ZSOURCE
(Notes 1, 2)
Output Transition Time
(20% to 80%)
ZLOAD >> Z SOURCE,
source termination only
(Note 5)
2
MAX3620A
540
MAX3620B
620
MAX3620C
700
MAX3620D
760
MAX3620A
590
MAX3620B
720
MAX3620C
810
MAX3620D
890
_______________________________________________________________________________________
ps
Delay Lines for High-Speed Clock
Distribution Systems
(Typical ambient temperature is +25°C. See Table 1 for more information.)
Load and source resistance = 50Ω ±1%, capacitance ≤ 1pF. Input transition time (20% to 80%) = 300ps.
The clock frequency is the maximum operational clock frequency listed in Table 1.
Load and source resistance = 50Ω ±1%, capacitance ≤ 1pF.
Insertion loss is relative to a lossless 50Ω transmission line. Ideally, an insertion loss of 0dB will result in 0.5 times the opencircuit transmitter output.
Note 5: Source termination only (no-load termination), 5pF and 20kΩ at load, 300ps input transition time (20% to 80%). Load capacitance dominates performance.
Note 6: Insertion loss is relative to an ideal open 20kΩ load. Ideally, an insertion loss of 0dB will result in 0.998 times the open-circuit
transmitter output.
Note 1:
Note 2:
Note 3:
Note 4:
Table 1. Recommended Operating Conditions
PARAMETER
CONDITIONS
Operating Ambient Temperature
MIN
TYP
MAX
-40
+25
+85
UNITS
°C
Recommended Load Capacitance
ZLOAD >> 50Ω, source termination only
5
pF
Recommended Load Resistance
ZLOAD >> 50Ω, source termination only
20
kΩ
Clock Frequency
MAX3620A
250
MAX3620B
190
250
MAX3620C
150
200
MAX3620D
125
167
1.5
VP-P
-1.5
+1.5
V
Input Amplitude
Input Voltage Range
333
MHz
_______________________________________________________________________________________
3
MAX3620
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
1.50
CLOAD = 5.0pF
1.75
1.50
MAX3620D
1.50
MAX3620D
MAX3620D
RLOAD = 50Ω
MAX3620 toc03
CLOAD = 1.0pF
MAX3620 toc02
1.75
MAX3620 toc01
1.75
DELAY vs. CLOAD
(LOW LOAD RESISTANCE)
DELAY vs. RLOAD
(HIGH LOAD RESISTANCE)
DELAY vs. RLOAD
(LOW LOAD RESISTANCE)
1.25
MAX3620C
1.00
1.25
MAX3620C
1.00
0.75
0.50
0.50
0.50
50
60
15 16 17 18 19 20 21 22 23 24 25
70
DELAY vs. CLOAD
(HIGH LOAD RESISTANCE)
MAX3620C
-6
dB
DELAY (ns)
1.25
-3
1.00
MAX3620B
-3
-6
-9
-9
-12
-12
-15
MAX3620A
-18
-21
-21
2
4
6
8
-30
10
10
MAX3620C S11
10
-3
-6
-3
-6
-12
-12
dB
-9
-12
dB
-9
-15
-15
-18
-18
-18
-21
-21
-21
-24
-24
-27
-27
50MHz
-30
-24
50MHz
100
FREQUENCY (MHz)
1000
50MHz
-27
-30
10
1000
MAX3620A S22
0
-9
-15
100
FREQUENCY (MHz)
MAX3620 toc08
-6
1000
MAX3620D S11
0
MAX3620 toc07
-3
100
FREQUENCY (MHz)
CLOAD (pF)
0
50MHz
-27
-30
0
10
-24
50MHz
-27
0.50
8
-15
-18
-24
0.75
6
MAX3620B S11
dB
MAX3620D
1.50
4
0
MAX3620 toc05
RLOAD = 20Ω
2
CLOAD (pF)
MAX3620A S11
0
MAX3620 toc04
1.75
0
RLOAD (kΩ)
RLOAD (Ω)
MAX3620 toc06
40
MAX3620A
0.75
MAX3620A
MAX3620A
30
MAX3620B
1.00
MAX3620 toc09
0.75
1.25
MAX3620B
MAX3620B
4
DELAY (ns)
DELAY (ns)
DELAY (ns)
MAX3620C
dB
MAX3620
Delay Lines for High-Speed Clock
Distribution Systems
-30
10
100
FREQUENCY (MHz)
1000
10
100
FREQUENCY (MHz)
_______________________________________________________________________________________
1000
Delay Lines for High-Speed Clock
Distribution Systems
-6
MAX3620D S22
0
MAX3620 toc11
MAX3620 toc10
-3
-3
-6
-3
-6
-9
-9
-12
-12
-12
-15
dB
-9
dB
dB
MAX3620C S22
0
-15
-15
-18
-18
-18
-21
-21
-21
-24
-24
-24
-27
-27
50MHz
-30
-27
50MHz
-30
10
1000
100
FREQUENCY (MHz)
MAX3620 toc12
MAX3620B S22
0
50MHz
-30
10
1000
100
10
FREQUENCY (MHz)
100
1000
FREQUENCY (MHz)
Pin Description
PIN
NAME
1
IN1
2
COMMON
3
IN2
4
OUT2
5
COMMON
6
OUT1
—
Exposed
Pad
FUNCTION
Single-Ended Input 1
Common
IN1
COMMON
OUT1
COMMON
Single-Ended Input 2
Single-Ended Output 2
IN2
OUT2
Common
Single-Ended Output 1
Connect to same potential as COMMON
Figure 1. Functional Diagram
Detailed Description
The MAX3620 delay lines are transmission lines constructed with a series of L-C sections. Figure 1 is a
functional diagram of the MAX3620. The distributed
architecture of the MAX3620 allows for symmetrical
impedance looking into each terminal. When the
MAX3620 is used in single-ended operation, leave
unused input/output open.
_______________________________________________________________________________________
5
MAX3620
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted.)
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
MAX3620
Delay Lines for High-Speed Clock
Distribution Systems
D
N
PIN 1
INDEX
AREA
E
E2
DETAIL A
C
L
A
C
L
L
L
e
e
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
-DRAWING NOT TO SCALE-
21-0137
G
1
2
COMMON DIMENSIONS
SYMBOL
MIN.
MAX.
A
0.70
0.80
D
2.90
3.10
E
2.90
3.10
A1
0.00
0.05
L
0.20
0.40
k
0.25 MIN.
A2
0.20 REF.
PACKAGE VARIATIONS
PKG. CODE
N
D2
E2
e
JEDEC SPEC
b
[(N/2)-1] x e
DOWNBONDS
ALLOWED
T633-1
6
1.50±0.10
2.30±0.10
0.95 BSC
MO229 / WEEA
0.40±0.05
1.90 REF
NO
T633-2
6
1.50±0.10
2.30±0.10
0.95 BSC
MO229 / WEEA
0.40±0.05
1.90 REF
NO
T833-1
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
NO
T833-2
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
NO
T833-3
8
1.50±0.10
2.30±0.10
0.65 BSC
MO229 / WEEC
0.30±0.05
1.95 REF
YES
T1033-1
10
1.50±0.10
2.30±0.10
0.50 BSC
MO229 / WEED-3
0.25±0.05
2.00 REF
NO
T1433-1
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
YES
T1433-2
14
1.70±0.10
2.30±0.10
0.40 BSC
----
0.20±0.05
2.40 REF
NO
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
21-0137
-DRAWING NOT TO SCALE-
G
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.