NSC DS92LV1224

DS92LV1224
30-66 MHz 10 Bit Bus LVDS Deserializer
General Description
Features
The DS92LV1224 is a 300 to 660 Mb/s deserializer for
high-speed unidirectional serial data transmission over FR-4
printed circuit board backplanes and balanced copper
cables. It receives the Bus LVDS serial data stream from a
compatible 10–bit serializer, transforms it back into a 10-bit
wide parallel data bus and recovers parallel clock. This
single serial data stream simplifies PCB design and reduces
PCB cost by narrowing data paths that in turn reduce PCB
size and number of layers. The single serial data stream also
reduces cable size, the number of connectors, and eliminates clock-to-data and data-to-data skew.
n 30–66 MHz Single 1:10 Deserializer with 300–660 Mb/s
troughput
n Robust Bus LVDS serial data transmission with
embedded clock with embedded clock for exceptional
noise immunity and low EMI
n Clock recovery from PLL lock to random data patterns.
n Guaranteed transition every data transfer cycle
n Low power consumption < 300 mW (typ) @ 66 MHz
n Single differential pair eliminates multi-channel skew
n Flow-through pinout for easy PCB layout
n Synchronization mode and LOCK indicator
n Programmable edge trigger on clock
n High impedance on receiver inputs when power is off
n Small 28-lead SSOP package
The DS92LV1224 works well with any National Semiconductor’s Bus LVDS 10–bit serializer within its specified frequency operating range. It features low power consumption,
and high impedance outputs in power down mode.
The DS92LV1224 was designed with the flow-through pinout
and is available in a space saving 28–lead SSOP package.
Block Diagrams
20138701
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation
DS201387
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DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer
April 2005
DS92LV1224
Block Diagrams
(Continued)
Application
20138702
The user’s application determines control of the SYNC1 and
SYNC 2 pins. One recommendation is a direct feedback loop
from the LOCK pin. Under all circumstances, the Serializer
stops sending SYNC patterns after both SYNC inputs return
low.
Functional Description
The DS92LV1224 is a 10-bit Deserializer device which together with a compatible serializer (i.e. DS92LV1023E)
forms a chipset designed to transmit data over FR-4 printed
circuit board backplanes and balanced copper cables at
clock speeds from 30 MHz to 66 MHz.
The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two passive
states: Powerdown and TRI-STATE ® .
The following sections describe each operation and passive
state.
When the Deserializer detects edge transitions at the Bus
LVDS input, it will attempt to lock to the embedded clock
information. When the Deserializer locks to the Bus LVDS
clock, the LOCK output will go low. When LOCK is low, the
Deserializer outputs represent incoming Bus LVDS data.
Data Transfer
After initialization, the Serializer will accept data from inputs
DIN0–DIN9. The Serializer uses the TCLK input to latch
incoming Data. The TCLK_R/F pin selects which edge the
Serializer uses to strobe incoming data. TCLK_R/F high
selects the rising edge for clocking data and low selects the
falling edge. If either of the SYNC inputs is high for 5*TCLK
cycles, the data at DIN0-DIN9 is ignored regardless of clock
edge.
Initialization
Initialization of both devices must occur before data transmission begins. Initialization refers to synchronization of the
Serializer and Deserializer PLL’s to local clocks, which may
be the same or separate. Afterwards, synchronization of the
Deserializer to Serializer occurs.
Step 1: When you apply VCC to both Serializer and/or Deserializer, the respective outputs enter TRI-STATE ® , and onchip power-on circuitry disables internal circuitry. When VCC
reaches VCCOK (2.5V) the PLL in each device begins locking to a local clock. For the Serializer, the local clock is the
transmit clock (TCLK) provided by the source ASIC or other
device. For the Deserializer, you must apply a local clock to
the REFCLK pin.
The Serializer outputs remain in TRI-STATE while the PLL
locks to the TCLK. After locking to TCLK, the Serializer is
now ready to send data or SYNC patterns, depending on the
levels of the SYNC1 and SYNC2 inputs or a data stream.
The SYNC pattern sent by the Serializer consists of six ones
and six zeros switching at the input clock rate.
Note that the Deserializer LOCK output will remain high
while its PLL locks to the incoming data or to SYNC patterns
on the input.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete initialization. The Deserializer will lock to
non-repetitive data patterns. However, the transmission of
SYNC patterns enables the Deserializer to lock to the Serializer signal within a specified time.
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After determining which clock edge to use, a start and stop
bit, appended internally, frame the data bits in the register.
The start bit is always high and the stop bit is always low.
The start and stop bits function as the embedded clock bits
in the serial stream.
The Serializer transmits serialized data and clock bits (10+2
bits) from the serial data output (DO ± ) at 12 times the TCLK
frequency. For example, if TCLK is 66 MHz, the serial rate is
66 x 12 = 792 Mega-bits-per-second. Since only 10 bits are
from input data, the serial “payload” rate is 10 times the
TCLK frequency. For instance, if TCLK = 66 MHz, the payload data rate is 66 x 10 = 660 Mbps. The data source
provides TCLK and must be in the range of 30 MHz to 66
MHz nominal.
The Serializer outputs (DO ± ) can drive a point-to-point connection or in limited multi-point or multi-drop backplanes.
The outputs transmit data when the enable pin (DEN) is
high, PWRDN = high, and SYNC1 and SYNC2 are low.
When DEN is driven low, the Serializer output pins will enter
TRI-STATE.
When the Deserializer synchronizes to the Serializer, the
LOCK pin is low. The Deserializer locks to the embedded
2
low state and the adjacent bit is held high, creating a 0-1
transition. In the worst case, the Deserializer could become
locked to the data pattern rather than the clock. Circuitry
within the DS92LV1224 can detect that the possibility of
“false lock” exists. The circuitry accomplishes this by detecting more than one potential position for clocking bits. Upon
detection, the circuitry will prevent the LOCK output from
becoming active until the potential “false lock” pattern
changes. The false lock detect circuitry expects the data will
eventually change, causing the Deserializer to lose lock to
the data pattern and then continue searching for clock bits in
the serial data stream. Graphical representations of RMT are
shown in Figure 1. Please note that RMT only applies to bits
DIN0-DIN8.
(Continued)
clock and uses it to recover the serialized data. ROUT data
is valid when LOCK is low. Otherwise ROUT0–ROUT9 is
invalid.
The ROUT0-ROUT9 pins use the RCLK pin as the reference
to data. The polarity of the RCLK edge is controlled by the
RCLK_R/F input. See Figure 6.
ROUT(0-9), LOCK and RCLK outputs will drive a maximum
of three CMOS input gates (15 pF load) with a 66 MHz clock.
Resynchronization
When the Deserializer PLL locks to the embedded clock
edge, the Deserializer LOCK pin asserts a low. If the Deserializer loses lock, the LOCK pin output will go high and the
outputs (including RCLK) will enter TRI-STATE.
Powerdown
When no data transfer occurs, you can use the Powerdown
state. The Serializer and Deserializer use the Powerdown
state, a low power sleep mode, to reduce power consumption. The Deserializer enters Powerdown when you drive
PWRDN and REN low. The Serializer enters Powerdown
when you drive PWRDN low. In Powerdown, the PLL stops
and the outputs enterTRI-STATE, which disables load current and reduces supply current to the milliampere range. To
exit Powerdown, you must drive the PWRDN pin high.
Before valid data exchanges between the Serializer and
Deserializer, you must reinitialize and resynchronize the devices to each other. Initialization of the Serializer takes 510
TCLK cycles. The Deserializer will initialize and assert LOCK
high until lock to the Bus LVDS clock occurs.
The user’s system monitors the LOCK pin to detect a loss of
synchronization. Upon detection, the system can arrange to
pulse the Serializer SYNC1 or SYNC2 pin to resynchronize.
Multiple resynchronization approaches are possible. One
recommendation is to provide a feedback loop using the
LOCK pin itself to control the sync request of the Serializer
(SYNC1 or SYNC2). Dual SYNC pins are provided for multiple control in a multi-drop application. Sending sync patterns for resynchronization is desirable when lock times
within a specific time are critical. However, the Deserializer
can lock to random data, which is discussed in the next
section.
Random Lock Initialization and
Resynchronization
TRI-STATE
The initialization and resynchronization methods described
in their respective sections are the fastest ways to establish
the link between the Serializer and Deserializer. However,
the DS92LV1224 can attain lock to a data stream without
requiring the Serializer to send special SYNC patterns. This
allows the DS92LV1224 to operate in “open-loop” applications. Equally important is the Deserializer’s ability to support
hot insertion into a running backplane. In the open loop or
hot insertion case, we assume the data stream is essentially
random. Therefore, because lock time varies due to data
stream characteristics, we cannot possibly predict exact lock
time. However, please see Table 1 for some general random
lock times under specific conditions. The primary constraint
on the “random” lock time is the initial phase relation between the incoming data and the REFCLK when the Deserializer powers up. As described in the next paragraph, the
data contained in the data stream can also affect lock time.
If a specific pattern is repetitive, the Deserializer could enter
“false lock” - falsely recognizing the data pattern as the
clocking bits. We refer to such a pattern as a repetitive
multi-transition, RMT. This occurs when more than one LowHigh transition takes place in a clock cycle over multiple
cycles. This occurs when any bit, except DIN 9, is held at a
The Serializer enters TRI-STATE when the DEN pin is driven
low. This puts both driver output pins (DO+ and DO−) into
TRI-STATE. When you drive DEN high, the Serializer returns
to the previous state, as long as all other control pins remain
static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
When you drive the REN pin low, the Deserializer enters
TRI-STATE. Consequently, the receiver output pins
(ROUT0–ROUT9) and RCLK will enter TRI-STATE. The
LOCK output remains active, reflecting the state of the PLL.
TABLE 1.
Random Lock Times for the DS92LV1224
40 MHz
66 MHz
Units
µs
Maximum
26
18
Mean
4.5
3.0
µs
Minimum
0.77
0.43
µs
Conditions:
PRBS 215, VCC = 3.3V
1) Difference in lock times are due to different starting points in the data
pattern with multiple parts.
3
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DS92LV1224
Data Transfer
DS92LV1224
Ordering Information
NSID
Function
DS92LV1224TMSA
Deserializer
20138726
20138724
DIN8 Held Low-DIN9 Held High Creates an RMT Pattern
DIN0 Held Low-DIN1 Held High Creates an RMT Pattern
20138725
DIN4 Held Low-DIN5 Held High Creates an RMT Pattern
FIGURE 1. RMT Patterns Seen on the Bus LVDS Serial Output
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Package
MSA28
4
Supply Voltage (VCC)
−0.3V to +4V
LVCMOS/LVTTL Input
Voltage
−0.3V to (VCC +0.3V)
LVCMOS/LVTTL Output
Voltage
−0.3V to (VCC +0.3V)
10.3 mW/˚C above
+25˚C
28L SSOP
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
θja
97˚C/W
θjc
27˚C/W
ESD Rating
> 2kV
HBM (1.5kOhm, 100pF)
Bus LVDS Receiver Input
Voltage
+150˚C
Storage Temperature
−65˚C to +150˚C
Recommended Operating
Conditions
Lead Temperature
(Soldering, 4 seconds)
> 250V
MM
−0.3V to +3.9V
Junction Temperature
+260˚C
Min
Nom
Max
Units
Supply Voltage (VCC)
3.0
3.3
3.6
V
Operating Free Air
Temperature (TA)
−40
+25
+85
˚C
2.4
V
Maximum Package Power Dissipation Capacity
Receiver Input Range
@ 25˚C Package:
Supply Noise Voltage
(VCC)
28L SSOP
DS92LV1224
Absolute Maximum Ratings (Note 1)
1.27 W
0
100 mVP-P
Package Derating:
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (apply to pins PWRDN, RCLK_R/ F, REN, REFCLK = inputs; apply
to pins ROUT, RCLK, LOCK = outputs)
VIH
High Level Input Voltage
2.0
VCC
V
VIL
Low Level Input Voltage
GND
0.8
V
VCL
Input Clamp Voltage
ICL = −18 mA
−0.62
−1.5
V
+15
µA
IIN
Input Current
VIN = 0V or 3.6V
−10
±1
VOH
High Level Output Voltage
IOH = −9 mA
2.2
3.0
VCC
V
VOL
Low Level Output Voltage
IOL = 9 mA
GND
0.25
0.5
V
IOS
Output Short Circuit Current
VOUT = 0V
−15
−47
−85
mA
IOZ
TRI-STATE Output Current
PWRDN or REN = 0.8V, VOUT = 0V or VCC
−10
± 0.1
+10
µA
+6
+50
mV
DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−)
VTH
Differential Threshold High Voltage
VTL
Differential Threshold Low Voltage
IIN
Input Current
VCM = +1.1V
−50
−12
VIN = +2.4V, VCC = 3.6V or 0V
−10
±1
+15
mV
µA
VIN = 0V, VCC = 3.6V or 0V
−10
± 0.05
+10
µA
f = 30 MHz
58
75
mA
f = 40 MHz
58
75
mA
f = 66 MHz
90
110
mA
0.36
1.0
mA
DESERIALIZER SUPPLY CURRENT (apply to pins DVCC and AVCC)
ICCR
Deserializer Supply Current Worst
Case
CL = 15 pF
Figure 2
ICCXR
Deserializer Supply Current
Powerdown
PWRDN = 0.8V, REN = 0.8V
5
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DS92LV1224
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
15.15
T
33.33
ns
REFCLK Duty Cycle
30
50
70
%
Ratio of REFCLK to
TCLK
95
1
105
3
6
tRFCP
REFCLK Period
tRFDC
tRFCP /
tTCP
tRFTT
REFCLK Transition Time
ns
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
tRCP
Receiver out Clock
Period
tCLH
CMOS/TTL Low-to-High
Transition Time
tCHL
CMOS/TTL High-to-Low
Transition Time
tDD
tROS
tROH
Deserializer Delay
Figure 5
ROUT Data Valid
before RCLK
ROUT Data valid after
RCLK
tRDC
RCLK Duty Cycle
tHZR
HIGH to TRI-STATE
Delay
tLZR
LOW to TRI-STATE
Delay
tZHR
TRI-STATE to HIGH
Delay
tZLR
TRI-STATE to LOW
Delay
tDSR1
Deserializer PLL Lock
time from PWRDWN
(with SYNCPAT)
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Conditions
tRCP = tTCP
CL = 15 pF
Figure 3
Pin/Freq.
Min
RCLK
15.15
Rout(0-9),
LOCK,
RCLK
Typ
Max
Units
33.33
ns
1.2
4
ns
1.1
4
ns
All Temp./
All Freq.
1.75*tRCP+1.25
1.75*tRCP+3.75
1.75*tRCP+6.25
ns
Room
Temp./
3.3V/30MHz
1.75*tRCP+2.25
1.75*tRCP+3.75
1.75*tRCP+5.25
ns
Room
Temp./
3.3V/40MHz
1.75*tRCP+2.25
1.75*tRCP+3.75
1.75*tRCP+5.25
ns
Room
Temp./
3.3V/66MHz
1.75*tRCP+2.75
1.75*tRCP+3.75
1.75*tRCP+4.75
ns
RCLK
30MHz
0.4*tRCP
0.5*tRCP
ns
RCLK
40MHz
0.4*tRCP
0.5*tRCP
ns
RCLK
66MHz
0.38*tRCP
0.5*tRCP
ns
30MHz
−0.4*tRCP
−0.5*tRCP
ns
40MHz
−0.4*tRCP
−0.5*tRCP
ns
66MHz
−0.38*tRCP
−0.5*tRCP
45
50
55
%
2.8
10
ns
2.8
10
ns
4.2
10
ns
4.2
10
ns
30MHz
1.68
3
µs
40MHz
1.31
3
µs
66MHz
0.84
3
µs
Figure 6
Figure 6
Figure 7
ns
Rout(0-9)
6
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tDSR2
Parameter
Conditions
Deserializer PLL Lock
time from SYNCPAT
tZHLK
TRI-STATE to HIGH
Delay (power-up)
tRNM
Deserializer Noise
Margin
Figure 10
(Note 7)
Pin/Freq.
Typ
Max
Units
30MHz
Min
0.62
1
µs
40MHz
0.47
1
µs
66MHz
0.29
0.8
µs
LOCK
3.7
12
ns
30 MHz
650
950
ps
40 MHz
450
730
ps
66 MHz
250
400
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply that
the devices should be operated at these limits. The table of “Electrical
Characteristics” specifies conditions of device operation.
specific conditions for the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1 timing or tDSR2
timing. tDSR1 is the time required for the deserializer to indicate lock upon
power-up or when leaving the power-down mode. Synchronization patterns
should be sent to the device before initiating either condition. tDSR2 is the time
required to indicate lock for the powered-up and enabled deserializer when
the input (RI+ and RI-) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs).
Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device
pins is defined as negative. Voltages are referenced to ground except VOD,
∆VOD, VTH and VTL which are differential voltages.
Note 7: tRNM is a measure of how much phase noise (jitter) the deserializer
can tolerate in the incoming data stream before bit errors occur. The Deserializer Noise Margin is Guaranteed By Design (GBD) using statistical
analysis.
Note 4: tLLHT and tLHLT specifications are Guranteed By Design (GBD)
using statistical analysis.
Note 5: Because the Serializer is in TRI-STATE mode, the Deserializer will
lose PLL lock and have to resynchronize before data transfer.
Note 6: For the purpose of specifying deserializer PLL performance, tDSR1
and tDSR2 are specified with the REFCLK running and stable, and with
AC Timing Diagrams and Test Circuits
20138704
FIGURE 2. “Worst Case” Deserializer ICC Test Pattern
20138706
FIGURE 3. Deserializer CMOS/TTL Output Load and Transition Times
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DS92LV1224
Deserializer Switching Characteristics
DS92LV1224
AC Timing Diagrams and Test Circuits
(Continued)
20138723
FIGURE 4. SYNC Timing Delays
20138712
FIGURE 5. Deserializer Delay
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8
DS92LV1224
AC Timing Diagrams and Test Circuits
(Continued)
20138713
Timing shown for RCLK_R/F = LOW
Duty Cycle (tRDC) =
FIGURE 6. Deserializer Data Valid Out Times
20138714
FIGURE 7. Deserializer TRI-STATE Test Circuit and Timing
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DS92LV1224
AC Timing Diagrams and Test Circuits
(Continued)
20138715
FIGURE 8. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
20138722
FIGURE 9. Deserializer PLL Lock Time from SyncPAT
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10
DS92LV1224
AC Timing Diagrams and Test Circuits
(Continued)
20138721
SW - Setup and Hold Time (Internal Data Sampling Window)
tDJIT - Serializer Output Bit Position Jitter that results from Jitter on TCLK
tRNM = Receiver Noise Margin Time
FIGURE 10. Receiver Bus LVDS Input Skew Margin
Deserializer Truth Table
INPUTS
OUTPUTS
PWRDN
REN
H
H
ROUT [0:9]
LOCK
RCLK
H
Z
H
Z
H
Active
L
Active
L
X
Z
Z
Z
H
L
Z
Active
Z
1) LOCK Active indicates the LOCK output will reflect the state of the Deserializer with regard to the selected data stream.
2) RCLK Active indicates the RCLK will be running if the Deserializer is locked. The Timing of RCLK with respect to ROUT is determined by RCLK_R/F.
3) ROUT and RCLK are TRI-STATED when LOCK is asserted High.
11
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DS92LV1224
clock information be received 4 times in a row to indicate
loss of lock. Since clock information has been lost, it is
possible that data was also lost during these cycles. Therefore, after the Deserializer relocks to the incoming data
stream and the Deserializer LOCK pin goes low, at least
three previous data cycles should be suspect for bit errors.
Application Information
USING THE SERIALIZER AND DESERIALIZER CHIPSET
The Serializer and Deserializer chipset is an easy to use
transmitter and receiver pair that sends 10 bits of parallel
LVTTL data over a serial Bus LVDS link up to 660 Mbps. An
on-board PLL serializes the input data and embeds two clock
bits within the data stream. The Deserializer uses a separate
reference clock (REFCLK) and an onboard PLL to extract
the clock information from the incoming data stream and
then deserialize the data. The Deserializer monitors the
incoming clock information, determines lock status, and asserts the LOCK output high when loss of lock occurs.
The Deserializer can relock to the incoming data stream by
making the Serializer resend SYNC patterns, as described
above, or by random locking, which can take more time,
depending on the data patterns being received.
HOT INSERTION
All the BLVDS devices are hot pluggable if you follow a few
rules. When inserting, ensure the Ground pin(s) makes contact first, then the VCC pin(s), and then the I/O pins. When
removing, the I/O pins should be unplugged first, then the
VCC, then the Ground. Random lock hot insertion is illustrated in Figure 13
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. In addition, the constant
current source nature of the Bus LVDS outputs minimizes
the slope of the speed vs. ICC curve of conventional CMOS
designs.
PCB CONSIDERATIONS
The Bus LVDS Serializer and Deserializer should be placed
as close to the edge connector as possible. In multiple
Deserializer applications, the distance from the Deserializer
to the slot connector appears as a stub to the Serializer
driving the backplane traces. Longer stubs lower the impedance of the bus, increase the load on the Serializer, and
lower the threshold margin at the Deserializers. Deserializer
devices should be placed much less than one inch from slot
connectors. Because transition times are very fast on the
Serializer Bus LVDS outputs, reducing stub lengths as much
as possible is the best method to ensure signal integrity.
POWERING UP THE DESERIALIZER
The DS92LV1224 can be powered up at any time by following the proper sequence. The REFCLK input can be running
before the Deserializer powers up, and it must be running in
order for the Deserializer to lock to incoming data. The
Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission at its inputs and locks to
the incoming data stream.
TRANSMITTING DATA
Once you power up the Serializer and Deserializer, they
must be phase locked to each other to transmit data. Phase
locking occurs when the Deserializer locks to incoming data
or when the Serializer sends patterns. The Serializer sends
SYNC patterns whenever the SYNC1 or SYNC2 inputs are
high. The LOCK output of the Deserializer remains high until
it has locked to the incoming data stream. Connecting the
LOCK output of the Deserializer to one of the SYNC inputs of
the Serializer will guarantee that enough SYNC patterns are
sent to achieve Deserializer lock.
The Deserializer can also lock to incoming data by simply
powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
While the Deserializer LOCK output is low, data at the Deserializer outputs (ROUT0-9) is valid, except for the specific
case of loss of lock during transmission which is further
discussed in the "Recovering from LOCK Loss" section below.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-topoint configuration of a backplane, through a PCB trace, or
through twisted pair cable. In point-to-point configuration, the
transmission media need only be terminated at the receiver
end. Please note that in point-to-point configuration, the
potential of offsetting the ground levels of the Serializer vs.
the Deserializer must be considered. Also, Bus LVDS provides a +/− 1.2V common mode range at the receiver inputs.
Failsafe Biasing for the DS92LV1224
The DS92LV1224 has an improved input threshold sensitivity of +/− 50mV versus +/− 100mV for the DS92LV1210 or
DS92LV1212. This allows for greater differential noise margin in the DS92LV1224. However, in cases where the receiver input is not being actively driven, the increased sensitivity of the DS92LV1224 can pickup noise as a signal and
cause unintentional locking . For example, this can occur
when the input cable is disconnected.
External resistors can be added to the receiver circuit board
to prevent noise pick-up. Typically, the non-inverting receiver
input is pulled up and the inverting receiver input is pulled
down by high value resistors. the pull-up and pull-down
resistors (R1 and R2) provide a current path through the
termination resistor (RL) which biases the receiver inputs
when they are not connected to an active driver. The value of
the pull-up and pull-down resistors should be chosen so that
enough current is drawn to provide a +15mV drop across the
termination resistor. Please see Figure 11 for the Failsafe
Biasing Setup.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic
factors include:
Serializer: TCLK jitter, VCC noise (noise bandwidth and
out-of-band noise)
Media: ISI, Large VCM shifts
Deserializer: VCC noise
RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data
transmission, up to 3 cycles of data that were previously
received can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
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12
The parameter tRNM is calculated by first measuring how
much of the ideal bit the receiver needs to ensure correct
sampling. After determining this amount, what remains of the
ideal bit that is available for external sources of noise is
called tRNM. It is the offset from tDJIT(min or max) for the test
mask within the eye opening.
(Continued)
USING TDJIT AND TRNM TO VALIDATE SIGNAL
QUALITY
The parameters tDJIT and tRNM can be used to generate an
eye pattern mask to validate signal quality in an actual
application or in simulation.
The parameter tDJIT measures the transmitter’s ability to
place data bits in the ideal position to be sampled by the
receiver. The typical tDJIT parameter of −80 ps indicates that
the crossing point of the Tx data is 80 ps ahead of the ideal
crossing point. The tDJIT(min) and tDJIT(max) parameters
specify the earliest and latest, respectively, time that a crossing will occur relative to the ideal position.
The vertical limits of the mask are determined by the
DS92LV1224 receiver input threshold of +/− 50 mV.
Please refer to the eye mask pattern of Figure 11 for a
graphic representation of tDJIT and tRNM.
20138727
FIGURE 11. Failsafe Biasing Setup
20138728
FIGURE 12. Using tDJIT and tRNM to Generate an Eye Pattern Mask and Validate Signal Quality
13
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DS92LV1224
Application Information
DS92LV1224
20138717
FIGURE 13. Random Lock Hot Insertion
Pin Diagrams
DS92LV1224TMSA - Deserializer
20138719
Deserializer Pin Description
Pin Name
I/O
No.
Description
Data Output. ± 9 mA CMOS level outputs.
ROUT
O
15–19, 24–28
RCLK_R/F
I
2
Recovered Clock Rising/Falling strobe select. TTL level input.
Selects RCLK active edge for strobing of ROUT data. High selects
rising edge. Low selects falling edge.
RI+
I
5
+ Serial Data Input. Non-inverting Bus LVDS differential input.
RI−
I
6
− Serial Data Input. Inverting Bus LVDS differential input.
PWRDN
I
7
Powerdown. TTL level input. PWRDN driven low shuts down the PLL
and TRI-STATEs outputs putting the device into a low power sleep
mode.
LOCK
O
10
LOCK goes low when the Deserializer PLL locks onto the embedded
clock edge. CMOS level output. Totem pole output structure, does
not directly support wire OR connection.
RCLK
O
9
Recovered Clock. Parallel data rate clock recovered from embedded
clock. Used to strobe ROUT, CMOS level output.
REN
I
8
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9, LOCK
and RCLK when driven low.
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14
Pin Name
DS92LV1224
Deserializer Pin Description
(Continued)
I/O
No.
DVCC
I
21, 23
DGND
I
14, 20, 22
AVCC
I
4, 11
AGND
I
1, 12, 13
REFCLK
I
3
Description
Digital Circuit power supply.
Digital Circuit ground.
Analog power supply (PLL and Analog Circuits).
Analog ground (PLL and Analog Circuits).
Use this pin to supply a REFCLK signal for the internal PLL
frequency.
15
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DS92LV1224 30-66 MHz 10 Bit Bus LVDS Deserializer
Physical Dimensions
inches (millimeters)
unless otherwise noted
Order Number DS92LV1224TMSA
NS Package Number MSA28
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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