DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz General Description Features The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side. The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together. n 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps full duplex throughput) n Independent transmitter and receiver operation with separate clock, enable, and power down pins n Hot plug protection (power up high impedance) and synchronization (receiver locks to random data) n Wide ± 5% reference clock frequency tolerance for easy system design using locally-generated clocks n Line and local loopback modes n Robust BLVDS serial transmission across backplanes and cables for low EMI n No external coding required n Internal PLL, no external PLL components required n Single +3.3V power supply n Low power: 90mA (typ) transmitter, 100mA (typ) at 66 MHz with PRBS-15 pattern n ± 100 mV receiver input threshold n Loss of lock detection and reporting pin n Industrial −40 to +85˚C temperature range n > 2.0kV HBM ESD n Compact, standard 80-pin PQFP package Block Diagram DS92LV18 20031201 © 2003 National Semiconductor Corporation DS200312 www.national.com DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz October 2003 DS92LV18 Absolute Maximum Ratings Maximum Package Power Dissipation Capacity (Note 1) Package Derating: If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) −0.3V to +4V LVCMOS/LVTTL Input Voltage −0.3V to (VCC +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VCC +0.3V) Bus LVDS Receiver Input Voltage −0.3V to +3.9V Bus LVDS Driver Output Voltage −0.3V to +3.9V Bus LVDS Output Short Circuit Duration 10ms Junction Temperature +150˚C Storage Temperature −65˚C to +150˚C 23.2 mW/˚C above +25˚C 80L PQFP θJA 43˚C/W θJC 11.1˚C/W > 2.0kV ESD Rating (HBM) Recommended Operating Conditions Min Nom Max Units Supply Voltage (VCC) 3.15 3.3 3.45 V Operating Free Air Temperature (TA) −40 +25 +85 ˚C Clock Rate 15 66 MHz 100 mV Supply Noise Lead Temperature (Soldering, 4 seconds) (p-p) +260˚C Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units 2.0 VCC V GND 0.8 V −1.5 V LVCMOS/LVTTL DC Specifications VIH High Level Input Voltage DEN, TCLK, TPWDN, DIN, VIL Low Level Input Voltage VCL Input Clamp Voltage ICL = −18 mA SYNC, RCLK_R/F, REN, REFCLK, RPWDN -0.7 IIN Input Current VIN = 0V or 3.6V −10 ±2 +10 µA VOH High Level Output Voltage IOH = −9 mA 2.3 3.0 VCC V VOL Low Level Output Voltage IOL = 9 mA GND 0.33 0.5 V IOS Output Short Circuit Current VOUT = 0V −15 −48 −85 mA TRI-STATE Output Current PWRDN or REN = 0.8V, VOUT = 0V or VCC −10 ± 0.4 +10 µA +100 mV IOZ ROUT, RCLK, LOCK ROUT, RCLK Bus LVDS DC specifications VTH VTL IIN www.national.com Differential Threshold High Voltage Differential Threshold Low Voltage Input Current VCM = +1.1V RI+, RI- −100 mV VIN = +2.4V, VCC = 3.6V or 0V −10 ±5 +10 µA VIN = 0V, VCC = 3.6V or 0V −10 ±5 +10 µA 2 (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions VOD Output Differential Voltage (DO+) - (DO-) Pin/Freq. Figure 18, RL = 100Ω ∆VOD Output Differential Voltage Unbalance VOS Offset Voltage ∆VOS Offset Voltage Unbalance Min Typ Max Units 350 500 550 mV 2 15 mV 1.2 1.25 V 2.7 15 mV -35 -50 -70 mA 1.05 IOS Output Short Circuit Current DO = 0V, Din = H, TPWDN and DEN = 2.4V IOZ TRI-STATE Output Current TPWDN or DEN = 0.8V, DO = 0V OR VDD -10 ±1 10 µA IOX Power-Off Output Current VDD = 0V, DO = 0V or 3.6V -10 ±1 10 µA DO+, DO- SER/DES SUPPLY CURRENT (DVDD, PVDD and AVDD pins) ICCT ICCX Total Supply Current (includes load current) Supply Current Powerdown CL = 15pF, RL = 100 Ω f = 66 MHz, PRBS-15 pattern 190 CL = 15 pF, RL = 100 Ω f = 66 MHz, Worst case pattern (Checker-board pattern) 220 320 mA 1.5 3.0 mA PWRDN = 0.8V, REN = 0.8V mA Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units tTCP Transmit Clock Period Conditions 15.2 T 66.7 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns tCLKT TCLK Input Transition Time 3 6 ns tJIT TCLK Input Jitter 80 ps (RMS) Typ Max Units 0.2 0.4 ns 0.2 0.4 ns (Note 8) Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter tLLHT Bus LVDS Low-to-High Transition Time tLHLT Bus LVDS High-to-Low Transition Time tDIS DIN (0-17) Setup to TCLK tDIH DIN (0-17) Hold from TCLK Conditions Min Figure 3, (Note 8) RL = 100Ω, CL=10pF to GND Figure 6, (Note 8) RL = 100Ω, CL=10pF to GND 3 2.4 ns 0 ns www.national.com DS92LV18 Electrical Characteristics DS92LV18 Serializer Switching Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter tHZD DO ± HIGH to TRI-STATE Delay Conditions tLZD DO ± LOW to TRI-STATE Delay tZHD DO ± TRI-STATE to HIGH Delay tZLD DO ± TRI-STATE to LOW Delay tSPW SYNC Pulse Width Figure 9, RL = 100Ω tPLD Serializer PLL Lock Time tSD Min Typ Max Units 2.3 10 ns 1.9 10 ns 1.0 10 ns 1.0 10 ns 5*tTCP 6*tTCP ns Figure 8, RL = 100Ω 510*tTCP 1024*tTCP ns Serializer Delay Figure 10 , RL = 100Ω tTCP + 1.0 tTCP + 4.0 ns tRJIT Random Jitter Room Temp., 3.3V, 66 MHz tDJIT Deterministic Jitter Figure 16, (Note 8) Figure 7 (Note 4) RL = 100Ω, CL=10pF to GND tTCP + 2.0 ps (RMS) 4.5 15 MHz -430 190 ps 66 MHz -40 70 ps Deserializer Timing Requirements for REFCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Min Typ Max Units tRFCP REFCLK Period Conditions 15.2 T 66.7 ns tRFDC REFCLK Duty Cycle 40 50 60 % tRFCP / tTCP Ratio of REFCLK to TCLK 0.95 tRFTT REFCLK Transition Time 1.05 6 ns Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min tRCP Receiver out Clock Period tRCP = tTCP RCLK 15.2 tRDC RCLK Duty Cycle RCLK 45 tCLH CMOS/TTL Low-to-High Transition Time tCHL CMOS/TTL High-to-Low Transition Time tROS ROUT (0-9) Setup Data to RCLK tROH ROUT (0-9) Hold Data to RCLK www.national.com CL = 15 pF Figure 4 ROUT(0-17), LOCK, RCLK Typ Max Units 66.7 ns 50 55 % 2.2 4 ns 2.2 4 ns 0.35*tRCP 0.5*tRCP ns −0.35*tRCP −0.5*tRCP ns Figure 12 4 (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter tHZR HIGH to TRI-STATE Delay tLZR LOW to TRI-STATE Delay Conditions Figure 13 Pin/Freq. Min Typ Max Units 2.2 10 ns 2.2 10 ns 2.3 10 ns 2.9 10 ns 1.75*tRCP + 4.0 1.75*tRCP + 6.1 ns 15MHz 3.7 10 µs 66 MHz 1.9 4 µs 15MHz 1.5 5 µs 66 MHz 0.9 2 µs ps ROUT(0-17), LOCK tZHR TRI-STATE to HIGH Delay tZLR TRI-STATE to LOW Delay tDD Deserializer Delay tDSR1 Deserializer PLL Lock Time from Powerdown (with SYNCPAT) Figure 14, (Note 7) (Note 8) Deserializer PLL Lock time from SYNCPAT Figure 15, (Note 7) (Note 8) Ideal Deserializer Noise Margin Right Figure 17 (Note 6) (Note 8) 15 MHz 1490 66 MHz 180 ps Figure 17 (Note 6) (Note 8) 15 MHz 1460 ps tDSR2 tRNMI-R tRNMI-L Ideal Deserializer Noise Margin Left tJI Total Interconnect Jitter Budget RCLK (Note 9) 1.75*tRCP + 2.1 66 MHz 330 ps 15 MHz 1060 ps 66 MHz 160 ps Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C. Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD, VTH and VTL which are differential voltages. Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer. Note 5: tDSR1 is the time required by the deserializer to obtain lock when exiting powerdown mode. tDSR1 is specified with synchronization patterns (SYNCPATs) present at the LVDS inputs (RI+ and RI-) before exiting powerdown mode. tDSR2 is the time required to obtain lock for the powered-up and enabled deserializer when the LVDS input (RI+ and RI-) conditions change from not receiving data to receiving synchronization patterns. Both tDSR1 and tDSR2 are specified with the REFCLK running and stable. Note 6: tRNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement in reference with the ideal bit position, please see National’s AN-1217 for detail. Note 7: A sync pattern is a fixed pattern with 9-bits of data high followed by 9-bits of data low. The SYNC pattern is automatically generated by the transmitter when the SYNC pin is pulled high. Note 8: Guaranteed by Design (GBD) using statistical analysis. Note 9: Total Interconnect Jitter Budget (tJI) specifies the allowable jitter added by the interconnect assuming both transmitter and receiver are DS92LV18 circuits. tJI is GBD using statistical analysis. 5 www.national.com DS92LV18 Deserializer Switching Characteristics DS92LV18 AC Timing Diagrams and Test Circuits 20031203 FIGURE 1. “Worst Case” Serializer ICC Test Pattern 20031204 FIGURE 2. “Worst Case” Deserializer ICC Test Pattern 20031205 FIGURE 3. Serializer Bus LVDS Distributed Output Load and Transition Times 20031206 FIGURE 4. Deserializer CMOS/TTL Distributed Output Load and Transition Times www.national.com 6 DS92LV18 AC Timing Diagrams and Test Circuits (Continued) 20031207 FIGURE 5. Serializer Input Clock Transition Time 20031208 FIGURE 6. Serializer Setup/Hold Times 20031209 FIGURE 7. Serializer TRI-STATE Test Circuit and Timing 7 www.national.com DS92LV18 AC Timing Diagrams and Test Circuits (Continued) 20031210 FIGURE 8. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays 20031234 FIGURE 9. SYNC Timing Delay 20031211 FIGURE 10. Serializer Delay www.national.com 8 DS92LV18 AC Timing Diagrams and Test Circuits (Continued) 20031212 FIGURE 11. Deserializer Delay 20031213 FIGURE 12. Deserializer Setup and Hold Times 20031214 FIGURE 13. Deserializer TRI-STATE Test Circuit and Timing 9 www.national.com DS92LV18 AC Timing Diagrams and Test Circuits (Continued) 20031215 FIGURE 14. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays 20031222 FIGURE 15. Deserializer PLL Lock Time from SYNCPAT www.national.com 10 DS92LV18 AC Timing Diagrams and Test Circuits (Continued) 20031229 FIGURE 16. Deterministic Jitter and Ideal Bit Position 20031232 tRNMI-L is the noise margin on the left of the figure above. tRNMI-R is the noise margin on the right of the above figure. FIGURE 17. Deserializer Noise Margin (tRNMI) and Sampling window 11 www.national.com DS92LV18 AC Timing Diagrams and Test Circuits (Continued) 20031216 VOD = (DO+)–(DO−). Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. FIGURE 18. VOD Diagram 20031235 FIGURE 19. Typical ICC vs. Frequency with PRBS-15 Pattern (Transmitter Only) 20031236 FIGURE 20. Typical ICC vs. Frequency with PRBS-15 Pattern (Receiver Only) www.national.com 12 The DS92LV18 combines a serializer and deserializer onto a single chip. The serializer accepts an 18-bit LVCMOS or LVTTL data bus and transforms it into a BLVDS serial data stream with embedded clock information. The deserializer then recovers the clock and data to deliver the resulting 18-bit wide words to the output. clock, the LOCK pin goes low and valid data appears on the output. Note that the LOCK signal is synchronous to valid data appearing on the outputs. The user’s application determines whether SYNC or lock-torandom-data mode is the preferred method for synchronization. If sync-patterns are preferred, the associated Deserializer’s LOCK pin is a convenient way to provide control of the Serializer’s SYNC pin. The device has a separate transmit block and receive block that can operate independently of each other. Each has a power down control to enable efficient operation in various applications. For example, the transceiver can operate as a standby in a redundant data path but still conserve power. The part can be configured as a Serializer, Deserializer, or as a Full Duplex SER/DES. Data Transfer After initialization, the DS92LV18 Serializer is able to transfer data to the Deserializer. The serial data stream includes a start bit and stop bit appended by the serializer, which frames the eighteen data bits. The start bit is always high and the stop bit is always low. The start and stop bits also function as clock bits embedded in the serial stream. The DS92LV18 serializer and deserializer blocks each have three operating states. They are the Initialization, Data Transfer, and Resynchronization states. In addition, there are two passive states: Powerdown and TRI-STATE. The Serializer block accepts data from the DIN0-DIN17 parallel inputs. The TCLK signal latches the incoming data on the rising edge. If the SYNC input is high for 6 TCLK cycles, the DS92LV18 does not latch data from DIN0-DIN17. The following sections describe each operation mode and passive state. Initialization The Serializer transmits the data and clock bits (18+2 bits) at 20 times the TCLK frequency. For example, if TCLK is 60 MHz, the serial rate is 60 X 20= 1200 Mbps. Since only 18 bits are from input data, the serial ’payload’ rate is 18 times the TCLK frequency. For instance, if TCLK = 60 MHz, the payload data rate is 60 X 18 = 1080 Mbps. TCLK is provided by the data source and must be in the range of 15 MHz to 66 MHz. When the Deserializer channel synchronizes to the input from a Serializer, it drives its LOCK pin low and synchronously delivers valid data on the output. The Deserializer locks to the embedded clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin. The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[0:17] pins. While LOCK is low, data on ROUT[0:17] is valid. Otherwise, ROUT[0:17] is invalid. ROUT[0:17], LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF total load) at a 66 MHz clock rate. This drive capacity allows bussing outputs of multiple Deserializers to multiple destination ASIC inputs. REN controls TRI-STATE for ROUTn and the RCLK pin on the Deserializer. The Deserializer input pins are high impedance during receiver powerdown (RPWDN low) and power-off (VCC = 0V). Before the DS92LV18 sends or receives data, it must initialize the links to and from another DS92LV18. Initialization refers to synchronizing the Serializer’s and Deserializer’s PLL’s to local clocks. The local clocks must be the same frequency or within a specified range if from different sources. After the Serializers synchronize to the local clocks, the Deserializers synchronize to the Serializers as the second and final initialization step. Step 1: When VCC is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE and internal circuitry is disabled by on-chip power-on circuitry. When VCC reaches VCC OK (2.2V) the PLL in each device begins locking to a local clock. For the Serializer, the local clock is the transmit clock, TCLK. For the Deserializer, the local clock is applied to the REFCLK pin. A local on-board oscillator or other source provides the specified clock input to the TCLK and REFCLK pin. The Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the Serializer block is now ready to send data or synchronization patterns. If the SYNC pin is high, then the Serializer block generates and sends the synchronization patterns (sync-pattern). The Deserializer output will remain in TRI-STATE while its PLL locks to the REFCLK. Also, the Deserializer LOCK output will remain high until its PLL locks to incoming data or a sync-pattern on the RIN pins. Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. The Serializer that is generating the stream to the Deserializer must send random (non-repetitive) data patterns or sync-patterns during this step of the Initialization State. The Deserializer will lock onto sync-patterns within a specified amount of time. The lock to random data depends on the data patterns and therefore, the lock time is unspecified. In order to lock to the incoming LVDS data stream, the Deserializer identifies the rising clock edge in a sync-pattern and locks to it. If the Deserializer is locking to a random data stream from the Serializer, then it performs a series of operations to identify the rising clock edge and locks to it. Because this locking procedure depends on the data pattern, it is not possible to specify how long it will take. At the point when the Deserializer’s PLL locks to the embedded Resynchronization If the Deserializer loses lock, it will automatically try to resynchronize. For example, if the embedded clock edge is not detected two times in succession, the PLL loses lock and the LOCK pin is driven high. The Deserializer then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock edge, identifies it and then proceeds through the synchronization process. The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is low, the data is valid. The system must monitor the LOCK pin to determine whether data on the ROUT is valid. Because there is a short delay in the LOCK signal’s response to the PLL losing synchronization to the incoming data stream, the system must determine the validity of data for the cycles before the LOCK signal goes high. 13 www.national.com DS92LV18 Functional Description DS92LV18 Resynchronization DEN signal high, the Serializer output will return to the previous state as long as all other control and data input pins remain in the same condition before DEN was driven low. (Continued) The user can choose to resynchronize to the random data stream or to force fast synchronization by pulsing the Serializer’s SYNC pin. Lock times depend on serial data stream characteristics. The primary constraint on the "random" lock time is the initial phase relation between the incoming data and the REFCLK when the Deserializer powers up. An advantage of using the SYNC pattern to force synchronization is the ability for the user to predict the delay before the PLL regains lock. This scheme is left up to the user discretion. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the Serializer, which is the SYNC pin. Loopback Test Operation The DS92LV18 includes two Loopback modes for testing the device functionality and the transmission line continuity. Asserting the Line Loopback control signal connects the serial data input (RIN ± ) to the serial data output (DO ± ) and to the parallel data output (ROUT[0:17]). The serial data goes through deserializer and serializer blocks. Asserting the Local Loopback control signal connects the parallel data input (DIN[0:17]) back to the parallel data output (ROUT[0:17]). The connection route includes all the functional blocks of the SER/DES Pair. The serial data output (DO ± ) is automatically disabled during the Local Loopback operating mode. If a specific pattern is repetitive, the Deserializer’s PLL will not lock in order to prevent the Deserializer from locking to the data pattern rather than the clock. We refer to such pattern as a repetitive multi-transition, RMT. This occurs when more than one Low-High transition takes places in a clock cycle over multiple cycles. This occurs when any bit, except DIN 17, is held at a low state and the adjacent bit is held high, creating a 0-1 transition. The internal circuitry accomplishes this by detecting more than one potential position for clocking bits. Upon detection, the circuitry will prevent the LOCK output from becoming active until the RMT pattern changes. Once the RMT pattern changes and the internal circuitry recognizes the clock bits in the serial data stream, the PLL of the Deserializer will lock, which will drive the LOCK output to low and the output data ROUTn will become valid. Please note that when switching between normal, line, or loopback modes, the deserializer will need to relock. In order for the serializer and deserializer to resync, the TCLK and REFCLK frequencies must be within ± 5% of each other. Application Information USING THE DS92LV18 The DS92LV18 combines a Serializer and Deserializer onto a single chip that sends 18 bits of parallel TTL data over a serial Bus LVDS link up to 1.32 Gbps. Serialization of the input data is accomplished using an on-board PLL at the Serializer which embeds two clock bits with the data. The Deserializer uses a separate reference clock (REFCLK) and an on-board PLL to extract the clock information from the incoming data stream and deserialize the data. The Deserializer monitors the incoming clock information to determine lock status and will indicate loss of lock by asserting the LOCK output high. Powerdown The Powerdown state is a low power sleep mode that the Serializer and Deserializer will occupy while waiting for initialization. You can also use TPWDN and RPWDN to reduce power when there are no pending data transfers. The Deserializer enters powerdown mode when RPWDN is driven low. In powerdown mode, the PLL stops and the outputs enter TRI-STATE, which reduces supply current to the µA range. POWER CONSIDERATIONS An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally, the constant current source nature of the LVDS outputs minimize the slope of the speed vs. ICC curve of CMOS designs. To bring the Deserializer block out of the Powerdown state, the system drives RPWDN high. When the Deserializer exits Powerdown, it automatically enters the Initialization state. The system must then allow time for Initialization before data transfer can begin. The TPWDN pin driven low forces the Serializer block into low power consumption, where the supply current is in the µA range. The Serializer PLL stops and the output goes into a TRI-STATE condition. To bring the Serializer block out of the powerdown state, the system drives TPWDN high. When the Serializer exits Powerdown, its PLL must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization before data transfer can begin. POWERING UP THE DESERIALIZER The REFCLK input can be running before the Deserializer is powered up and it must be running in order for the Deserializer to lock to incoming data. The Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission at its inputs and locks to the incoming serial data stream. NOISE MARGIN The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reliably recover data. Various environmental and systematic factors include: Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise) Media: ISI, VCM noise Deserializer: VCC noise For a graphical representation of noise margin, please see Figure 17. TRI-STATE When the system drives the REN pin low, the Deserializer’s outputs enter TRI-STATE. This will TRI-STATE the receiver output pins (ROUT[0:17]) and RCLK. When the system drives REN high, the Deserializer will return to the previous state as long as all other control pins remain static (RPWDN). When the system drives the DEN pin low, the Serializer’s LVDS outputs enter TRI-STATE. When the system drives the www.national.com 14 via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. (Continued) RECOVERING FROM LOCK LOSS In the case where the Serializer loses lock during data transmission, up to 5 cycles of data that were previously received could be invalid. This is due to a delay in the lock detection circuit. The lock detect circuit requires that invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been lost, it is possible that data was also lost during these cycles. If the Deserializer LOCK pin goes low, data from at least the previous 5 cycles should be resent upon regaining lock. A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate CMOS (TTL) signals away from the LVDS lines to prevent coupling from the CMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ohms are typically recommended for LVDS interconnect. The closelycoupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Termination of the LVDS interconnect is required. For pointto-point applications, termination should be located at the load end. Nominal value is 100 Ohms to match the line’s differential impedance. Place the resistor as close to the receiver inputs as possible to minimize the resulting stub between the termination resistor and receiver. Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the national web site at: www.national.com/lvds Specific guidance for this device is provided next. Lock can be regained at the Deserializer by causing the Serializer to resend SYNC patterns as described above or by random data locking which can take more time depending upon the data patterns being received. INPUT FAILSAFE In the event that the Deserializer is disconnected from the Serializer, the failsafe circuitry is designed to reject a certain amount of noise from being interpreted as data or clock. The outputs will enter TRI-STATE and the Deserializer will lose lock. HOT INSERTION All of National’s LVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s) makes contact first, then the VCC pin(s), then the I/O pin(s). When removing, the I/O pins should be unplugged first, then VCC, then Ground. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the BLVDS devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate highfrequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies above approximately 50MHz, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. It is a recommended practice to use two vias at each power pin as well as at all RF bypass capacitor terminals. Dual vias reduce the interconnect inductance by up to half, thereby reducing interconnect inductance and extending the effective frequency range of the bypass components. Locate RF capacitors as close as possible to the supply pins, and use wide low impedance traces (not 50 Ohm traces). Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with DS92LV18 BLVDS SER/DES PAIR General device specific guidance is given below. Exact guidance can not be given as it is dictated by other board level /system level criteria. This includes the density of the board, power rails, power supply, and other integrated circuit power supply needs. DVDD = DIGITAL SECTION POWER SUPPLY These pins supply the digital portion of the device as well as the receiver output buffers. The Deserializer’s DVDD requires more bypass to power the outputs under synchronous switching conditions. The Serializer’s DVDD is less critical. The receiver’s DVDD pins power 4 outputs from each DVDD pin. An estimate of local capacitance required indicates a minimum of 22nF is required. This is calculated by taking 4 times the maximum short current (4 X 70 = 280mA), multiplying by the rise time of the part (4ns), and dividing by the maximum allowed droop in VDD (assume 50mV) yields 22.4nF. Rounding up to a standard value, 0.1uF is selected for each DVDD pin. 15 www.national.com DS92LV18 Application Information DS92LV18 Application Information capacitor is sufficient for these pins. If space is available, a 0.01uF capacitor may be used in parallel with the 0.1uF capacitor for additional high frequency filtering. (Continued) PVDD = PLL SECTION POWER SUPPLY The PVDD pin supplies the PLL circuit. Note that the DS92LV18 has two separate PLL and supply pins. The PLL(s) require clean power for the minimization of Jitter. A supply noise frequency in the 300 kHz to 1 MHz range can cause increased output jitter. Certain power supplies may have switching frequencies or high harmonic content in this range. If this is the case, filtering of this noise spectrum may be required. A notch filter response is best to provide a stable VDD, suppression of the noise band, and good highfrequency response (clock fundamental). This may be accomplished with a pie filter (CRC or CLC). If employed, a separate pie filter is recommended for each PLL to minimize drop in potential due to the series resistance. The pie filter should be located close to the PVDD power pin. Separate power planes for the PVDD pins is typically not required. GROUNDS The AGND pin should be connected to the signal common in the cable for the return path of any common-mode current. Most of the LVDS current will be odd-mode and return within the interconnect pair. A small amount of current may be even-mode due to coupled noise and driver imbalances. This current should return via a low impedance known path. A solid ground plane is recommended for both DVDD, PVDD or AVDD. Using a split plane may cause ground loops or a difference in ground potential at various ground pins of the device. AVDD = LVDS SECTION POWER SUPPLY The AVDD pins power the LVDS portion of the circuit. The DS92LV18 has four AVDD pins. Due to the nature of the design, current draw is not excessive on these pins. A 0.1uF Truth Tables Transmitter Truth Table TPWDN (Pin 42) DEN (Pin 19) TX PLL Status (Internal) LVDS Outputs (Pins 13 and 14) L X X Hi Z H L X Hi Z H H Not Locked Hi Z H H Locked Serialized Data with Embedded Clock Receiver Truth Table RPWDN (Pin 01) REN (Pin 02) RX PLL Status (Internal) ROUTn & RCLK (See Pin Diagram) L X X Hi Z Hi Z Hi Z L = PLL Locked; H = PLL Unlocked LOCK (Pin 63) H L X H H Not Locked H H H H Locked Data & CLK Active L www.national.com 16 DS92LV18 Footprint Changes between the DS92LV16 and the DS92LV18 DS92LV16 vs. DS92LV18 Footprint Changes Pin Number DS92LV16 DS92LV18 3 CONFIG1 DIN17 18 CONFIG2 DIN16 62 DVDD ROUT16 80 DGND ROUT17 PCB Compatibility Between the DS92LV16 and DS92LV18 20031233 FIGURE 21. 17 www.national.com DS92LV18 Pin Diagram DS92LV18TVV Top View 20031202 www.national.com 18 Pin # Pin Name I/O Description 1 RPWDN CMOS, I RPWDN = Low will put the Receiver in low power, stand-by, mode. Note: The Receiver PLL will lose lock.(Note 10) 2 REN CMOS, I REN = Low will disable the Receiver outputs. Receiver PLL remains locked. (See LOCK pin description)(Note 10) 4 REFCLK CMOS, I Frequency reference clock input for the receiver. 5, 10, 11, 15 AVDD 6,9,12,16 AGND 7 RIN+ LVDS, I Receiver LVDS True Input 8 RIN- LVDS, I Receiver LVDS Inverting Input 13 DO+ LVDS, O Transmitter LVDS True Output 14 DO- LVDS, O Transmitter LVDS Inverting Output 17 TCLK CMOS, I Transmitter reference clock. Used to strobe data at the DIN Inputs and to drive the transmitter PLL. See TCLK Timing Requirements. 19 DEN CMOS, I DEN = Low will disable the Transmitter outputs. The transmitter PLL will remain locked.(Note 10) 20 SYNC CMOS, I SYNC = High will cause the transmitter to ignore the data inputs and send SYNC patterns to provide a locking reference to receiver(s). See Functional Description.(Note 10) DIN (0:17) CMOS, I Transmitter data inputs.(Note 10) 3, 18,21, 22, 23, 24, 25, 26, 27, 28, 33, 34, 35, 36, 37, 38, 39, 40 29,32 Analog Voltage Supply Analog Ground PGND PLL Ground. 30,31 PVDD PLL Voltage supply. 41, 44, 51, 52, 59, 60, 61, 68 DGND Digital Ground. 42 43, 50, 53, 58, 69 45, 46, 47, 48, 54, 55, 56, 57, 62, 64, 65, 66, 67, 70, 71, 72, 73, 80 TPWDN CMOS, I DVDD ROUT (0:17) TPWDN = Low will put the Transmitter in low power, stand-by mode. Note: The transmitter PLL will lose lock.(Note 10) Digital Voltage Supplies. CMOS, O Receiver Outputs. 49 RCLK CMOS, O Recovered Clock. Parallel data rate clock recovered from embedded clock. Used to strobe ROUT (0:17). LVCMOS Level output. 63 LOCK CMOS, O LOCK indicates the status of the receiver PLL. LOCK = H receiver PLL is unlocked, LOCK = L - receiver PLL is locked. 74,76 PGND 75,77 PVDD PLL Grounds. PLL Voltage Supplies. 78 LINE_LE CMOS, I LINE_LE = High enables the receiver loopback mode. Data received at the RIN ± inputs is fed back through the DO ± outputs.(Note 10) 79 LOCAL_LE CMOS, I LOCAL_LE = High enables the transmitter loopback mode. Data received at the DIN inputs is fed back through the ROUT outputs.(Note 10) Note 10: Input defaults to "low" state when left open due to an internal on-chip pull-down circuit. 19 www.national.com DS92LV18 Pin Descriptions DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz Physical Dimensions inches (millimeters) unless otherwise noted Dimensions shown in millimeters only Order Number DS92LV18TVV NS Package Number VHG80A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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