19-3098; Rev 0; 12/03 MAX1124 Evaluation Kit Features ♦ Up to 250Msps Sampling Rate with the MAX1124 ♦ Low Voltage and Power Operation ♦ Fully Differential Signal Input Configuration ♦ On-Board Differential Output Drivers ♦ Optional On-Board Secondary Transformer ♦ Fully Assembled and Tested ♦ Also Evaluates the MAX1121 (8-bit), MAX1122 (10-bit), and MAX1123 (10-bit) Ordering Information Part Selection Table PART RESOLUTION SPEED (Msps) PART TEMP RANGE MAX1121EGK 8 250 MAX1124EVKIT 0°C to +70°C MAX1122EGK 10 170 MAX1123EGK 10 210 MAX1124EGK 10 250 IC PACKAGE 68 QFN Note: To evaluate the MAX1121/MAX1122/MAX1123, request a MAX1121EGK, MAX1122EGK, or MAX1123EGK free sample with the MAX1124 EV kit. Component List DESIGNATION QTY DESCRIPTION C1–C11, C13–C16, C18, C19, C20, C36–C39 22 0.1µF ±20%, 10V X5R ceramic capacitors (0402) TDK C1005X5R1A104M C12, C17 0 Not installed (0402) C21–C24 4 0.22µF ±20%, 6.3V X5R ceramic capacitors (0402) TDK C1005X5R0J224M C25, C26 2 Not installed (0603) C27, C28, C40 3 47µF ±20%, 10V tantalum capacitors (C-case) AVX TAJC476M010 DESIGNATION QTY DESCRIPTION C29, C30, C31, C41 4 10µF ±20%, 6.3V X5R ceramic capacitors (0805) TDK C2012X5R0J106M C32, C33, C34, C42 4 1.0µF ±20%, 10V X5R ceramic capacitors (0603) TDK C1608X5R1A105M C35 1 0.01µF ±20%, 25V X7R ceramic capacitor (0402) TDK C1005X7R1E103M J1, J2, J3 3 SMA PC-mount connectors J4–J7 4 Dual-row, 40-pin headers ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 Evaluates: MAX1121–MAX1124 General Description The MAX1124 evaluation kit (EV kit) is a fully assembled and tested circuit board that contains all the components for evaluating the MAX1121 (8-bit, 250Msps), MAX1122 (10-bit, 170Msps), MAX1123 (10-bit, 210Msps), and MAX1124 (10-bit, 250Msps) analog-todigital converters (ADCs). The MAX1121–MAX1124 accept differential analog input signals; however, the EV kit generates these signals from a user-provided single-ended signal source. The digital output produced by the ADCs can be easily captured with a userprovided high-speed logic analyzer or data-acquisition system. The EV kit operates from 1.8V and 3.3V power supplies. It includes circuitry that generates a differential clock signal from a user-provided AC signal. The EV kit comes with the MAX1124 installed. Contact the factory for free samples of the pin-compatible MAX1121/ MAX1122/MAX1123 to evaluate these parts. Evaluates: MAX1121–MAX1124 MAX1124 Evaluation Kit Component List (continued) DESIGNATION JU1 QTY 0 DESCRIPTION Not installed JU3, JU4, JU5 3 Jumper, 3-pin headers R1, R2, R3 3 49.9Ω ±1% resistors (0603) R4, R5 2 150Ω ±5% resistors (0603) R6–R9 0 Not installed (0603) R10–R15, R42, R43 0 Not installed (0603) R16, R17 2 10Ω ±1% resistors (0603) R18–R24, R28–R32, R34, R35 14 100Ω ±1% resistors (0603) R25, R26, R27, R33 4 R36, R37 2 R38, R39, R41, R44–R68 28 DESIGNATION R40 QTY 1 T1, T2 2 DESCRIPTION Not installed 1:1 800MHz RF transformers Mini-Circuits ADT1-1WT TP1, TP2 2 Test points (Black) U1 1 Maxim MAX1124EGK (QFN-68) U2 1 3.3V differential receiver (SO-8) Fairchild 100LVEL16M ON Semiconductor MC100LVEL16D U3–U6 4 3.3V ECL quad differential receivers (SO-20) ON Semiconductor MC100LVEL17DW 100Ω ±5% resistors (0603) Y1 0 Not installed 510Ω ±5% resistors (0603) None 3 Shunts None 1 MAX1124 PC board 510Ω ±5% resistors (0402) Component Suppliers SUPPLIER PHONE FAX WEBSITE AVX 843-946-0238 843-626-3123 Fairchild 888-522-5372 — Mini-Circuits 718-934-4500 718-332-4661 www.minicircuits.com TDK 847-803-6100 847-390-4405 www.component.tdk.com www.avxcorp.com www.fairchildsemi.com Note: Please indicate that you are using the MAX1124 when contacting these component suppliers. Quick Start Recommended Equipment • DC power supplies: Analog (VCC) 1.8V, 300mA • • • • Clock (VCLK) 3.3V, 150mA Buffers (VPECL) 3.3V, 350mA Signal generator with low phase noise and low jitter for clock input (e.g., HP8662A, HP8644B) Signal generator for analog signal input (e.g., HP8662A, HP8644B) Logic analyzer or data-acquisition system (e.g., HP16500C, TLA621) Digital voltmeter Procedure The MAX1124 EV kit is a fully assembled and tested surface-mount board. Follow the steps below for board operation. Do not turn on power supplies or enable signal generators until all connections are completed: 1) Verify that shunts are installed in the following locations: JU3 (2-3)—two’s complement output JU4 (1-2)—divide-by-two disabled JU5 (2-3)—internal reference enabled 2) Connect the clock signal generator to the SMA connector labeled J2. 3) Connect the analog input signal generator to the SMA connector labeled J3. 4) Connect the logic analyzer to either headers J4/J5 2 _______________________________________________________________________________________ MAX1124 Evaluation Kit 5) Connect a 1.8V, 300mA power supply to VCC. Connect the ground terminal of this supply to GND. 6) Connect a 3.3V, 150mA power supply to VCLK. Connect the ground terminal of this supply to GND. 7) Connect a 3.3V, 350mA power supply to VPECL. Connect the ground terminal of this supply to GND. 8) Turn on all of the power supplies. 9) Enable the signal generators. Set the clock signal generator to output a 250MHz signal with an amplitude of 2.4VP-P. Set the analog input signal generators to output the desired frequency with an amplitude ≤ 2V P-P . The signal generators should be phase-locked. 10) Enable the logic analyzer. 11) Collect data using the logic analyzer. Detailed Description The MAX1124 EV kit is a fully assembled and tested circuit board that contains all the components necessary to evaluate the performance of the MAX1121 (8-bit, 250Msps), MAX1122 (10-bit, 170Msps), MAX1123 (10-bit, 210Msps), and MAX1124 (10-bit, 250Msps) LVDS-output ADCs. The EV kit comes with the MAX1124 installed, which can be evaluated with a maximum clock frequency (fCLK) of 250MHz. The MAX1124 accepts differential input signals; however, an on-board transformer (T2) converts a readily available single-ended source output to the required differential signal. Output level translators (U3–U6) buffer and convert the LVDS output signals of the MAX1124 to higher-voltage LVPECL signals, which can be captured by a wide variety of logic analyzers. The LVDS outputs are accessed at headers J4 and J5. The LVPECL outputs are accessed at headers J6 and J7. The EV kit is designed as a four-layer PC board to optimize the performance of the MAX1124. Separate analog, clock, and buffer power planes minimize noisecoupling between analog and digital signals. For analog and clock inputs, 50Ω coplanar transmission lines are used. For all digital LVDS outputs, 100Ω differential coplanar transmission lines are used. All LVDS differential outputs are properly terminated with 100Ω termination resistors between true and complementary digital outputs. The trace lengths of the 100Ω differential LVDS lines are matched to within a few thousandths of an inch to minimize layout-dependent delays. Power Supplies The MAX1124 EV kit requires separate analog, clock, and buffer power supplies for best performance. A 1.8V power supply is used to power the analog and digital portion of the MAX1124. The on-board clock circuitry is powered by a 3.3V power supply. A separate 3.3V power supply is used to power the output buffers (U3–U6) of the EV kit. Clock The MAX1124 requires a differential clock input signal. An on-board clock-shaping circuit generates a differential clock signal from an AC sine-wave signal applied to the clock-input SMA connector (J2). The input signal should not exceed an amplitude of 2.6VP-P. The frequency of the signal should not exceed 250MHz for the MAX1124. The frequency of the sinusoidal input signal determines the sampling frequency (fCLK) of the ADC. A differential line receiver (U2), processes the input signal to generate the required clock signal. Clock Divider The MAX1124 features an internal divide-by-two clock divider. Use jumper JU4 to enable/disable this feature. See Table 1 for shunt positions. Input Signal The MAX1124 accepts differential analog input signals. The MAX1124 EV kit only requires a single-ended analog input signal with an amplitude ≤2VP-P provided by the user. An on-board transformer takes the singleended analog input and generates a differential analog signal at the ADCs differential input pins. Table 1. Clock Divider Shunt Settings (JU4) SHUNT POSITION MAX1124 CLKDIV PIN DESCRIPTION 1-2* VCC Clock signal divided by 1 2-3 GND Clock signal divided by 2 *Default Configuration: JU4 (1-2). _______________________________________________________________________________________ 3 Evaluates: MAX1121–MAX1124 (LVDS-compatible signals) or J6/J7 (LVPECL-compatible signals). See the Output Bit Locations section for header connections. Evaluates: MAX1121–MAX1124 MAX1124 Evaluation Kit Optional Secondary Input Transformer Using the optional on-board secondary transformer can reduce common-mode signal levels and marginally improve performance of the MAX1124. To use this transformer, follow the directions below: 1) Cut the trace at R43. 2) Install 0Ω resistors at R10 and R12. 3) Remove C14. 4) Connect the analog signal source to J1 instead of J3. Reference Voltage There are two methods to set the full-scale range of the MAX1124. The MAX1124 EV kit can be configured to use the MAX1124’s internal reference, or a stable, lownoise external reference can be applied to the REFIO pad. Jumper JU5 controls which reference source is used. See Table 2 for shunt settings. Table 2. Reference Shunt Settings (JU5) SHUNT POSITION DESCRIPTION 1-2 Internal reference disabled; apply a stable reference voltage at the REFIO pad 2-3* Internal reference enabled Output Bit Locations The digital outputs of the ADC are connected to two 40pin headers (J4 and J5). PC board trace lengths are matched to minimize output skew and improve performance of the device. In addition, four drivers (U3–U6) buffer and level-translate the ADC’s digital outputs to LVPECL-compatible signals. The drivers increase the differential voltage swing, and are able to drive large capacitive loads, which may be present at the logic analyzer connection. The outputs of the buffers are connected to two 40-pin headers (J6 and J7). See Table 4 for header J4–J7 bit locations. Table 4. Output Bit Locations (MAX1122/MAX1123/MAX1124) (JU3) P UNBUFFERED (LVDS) J6-10 BUFFERED (LVPECL) J4-10 N J6-9 J4-9 P J6-16 J4-16 N J6-15 J4-15 P J6-22 J4-22 N J6-21 J4-21 BIT D9 D8 D7 P J6-28 J4-28 N J6-27 J4-27 P J6-34 J4-34 Output Signal N J6-33 J4-33 The MAX1124 features a single,10-bit, parallel, LVDScompatible, digital output bus. The digital outputs also feature a clock bit (CLK) for data synchronization, and a data overrange bit. See the Output Bit Locations section for header connections. P J6-40 J4-40 N J6-39 J4-39 D6 *Default configuration: JU5 (2-3). D5 Output Format The digital output coding can be chosen to be either in two’s complement or straight offset binary format by configuring jumper JU3. See Table 3 for shunt settings. D4 D3 D2 D1 D0 Table 3. Output Format Shunt Settings (JU3) SHUNT POSITION MAX1124 T/B PIN DESCRIPTION 1-2 VCC Digital output in straight offset binary 2-3* GND Digital output in two's complement OR DCO P J7-8 J5-8 N J7-7 J5-7 P J7-14 J5-14 N J7-13 J5-13 P J7-20 J5-20 N J7-19 J5-19 P J7-26 J5-26 N J7-25 J5-25 P J6-4 J4-4 N J6-3 J4-3 P J7-2 J5-2 N J7-1 J5-1 *Default configuration: JU3 (2-3). *Default configuration: JU3 (2-3). 4 _______________________________________________________________________________________ DESCRIPTION MSB Data bits LSB Overrange bit Clock output signal MAX1124 Evaluation Kit The MAX1124 EV kit is also capable of evaluating the MAX1121/MAX1122/MAX1123. To evaluate the MAX1121, MAX1122, or MAX1123, replace the MAX1124 with the desired IC. When evaluating the 8-bit MAX1121, do not connect the logic analyzer to the header pins marked D0 and D1. See Table 5 for output bit locations of headers J4–J7. Table 5. Output Bit Locations (MAX1121) BIT D7 D6 D5 D4 D3 D2 D1 D0 OR DCO UNBUFFERED (LVDS) BUFFERED (LVPECL) P J6-10 J4-10 N J6-9 J4-9 P J6-16 J4-16 N J6-15 J4-15 P J6-22 J4-22 N J6-21 J4-21 P J6-28 J4-28 N J6-27 J4-27 P J6-34 J4-34 N J6-33 J4-33 P J6-40 J4-40 N J6-39 J4-39 P J7-8 J5-8 N J7-7 J5-7 P J7-14 J5-14 N J7-13 J5-13 P J6-4 J4-4 N J6-3 J4-3 P J7-2 J5-2 N J7-1 J5-1 DESCRIPTION MSB Data bits LSB Overrange bit Clock output signal _______________________________________________________________________________________ 5 Evaluates: MAX1121–MAX1124 Evaluating the MAX1121/MAX1122/MAX1123 Evaluates: MAX1121–MAX1124 MAX1124 Evaluation Kit VCC ORP J4–4 J4–2 J4 ORN J4–3 J4–5 J4–1 J4–6 D9P J4–10 J4–8 D9N J4–9 J4–7 J4–11 J4–12 D8P J4–16 J4–14 ORN D9P D8N J4–15 J4–13 J4–17 J4–18 J4–22 J4–20 J4–21 J4–19 J4–23 J4–24 J4–28 J4–26 J4–27 J4–25 J4–29 J4–30 J4–34 J4–32 J4–33 J4–31 J4–35 J4–36 J4–40 J4–38 J4–39 J4–37 J5–2 J5–3 J5–1 J5–4 J5–5 J5–6 J5–8 J5–9 J5–7 J5–10 J5–11 J5–12 J5–14 J5–115 J5–13 J5–16 J5–17 J5–18 J5–20 J5–21 J5–19 J5–22 J5–23 J5–24 J5–26 J5–27 J5–25 J5–28 J5–29 J5–30 J5–32 J5–33 J5–31 J5–34 J5–35 J5–36 J5–38 J5–39 J5–37 J5–40 VCC C23 0.22µF C7 0.1µF C6 0.1µF C24 0.22µF C8 0.1µF J1 C9 0.1µF 1 T1 4 R1 49.9Ω 5 1% 3 2 6 C14 0.1µF J3 R11 OPEN 3 T2 R43 SHORT R6 OPEN 5 C10 0.1µF R7 OPEN R12 OPEN R16 10Ω 1% C25 SHORT 6 R8 OPEN TP1 4 1 R9 OPEN C26 SHORT C11 0.1µF R17 10Ω 1% J2 2 R2 49.9Ω 1% Q D 3 D R36 510Ω C17 OPEN 22 23 CLKN 7 INN 54 D8N D7P 53 CLKP 52 D7N D6P 51 CLKN R4 150Ω U2 MC100LVEL16 R37 510Ω 9 C19 0.1µF 8 VCC 58 ORN 57 D9P 56 D9N D8P 55 C16 0.1µF C15 0.1µF CLKP 1 N.C. VEE Q VBB C35 5 4 0.01µF 59 INP C12 OPEN VCLK C13 0.1µF 8 ORP 2 R13 OPEN R3 49.9Ω 1% AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC AVCC R10 OPEN 27 28 41 44 60 C22 0.22µF OVCC OVCC OVCC OVCC OVCC C2 0.1µF 1 6 11 12 13 14 20 25 62 63 65 C1 0.1µF 50 D6N D5P 49 6 48 D5N D4P 47 R5 150Ω U1 46 D4N DCLKP 43 VCLK C18 0.1µF 1 N.C. OUT 4 Y1 OPEN VCLK 1 2 3 6 VCC VCLK JU1 2 MAX1124 R25 R14 100Ω OPEN CLKP R26 100Ω OE OUT 42 DCLKN D3P 40 5 VCLK 39 D3N D2P 38 R27 R15 100Ω OPEN CLKN VCC GND R33 100Ω 3 VCC 37 D2N D1P 36 1 JU3 68 2 T/B 3 35 1 JU4 2 3 17 REFIO 3 C21 0.22µF C3 0.1µF C4 0.1µF C5 0.1µF R42 1 JU5 SHORT 2 3 31 N.C. N.C. 30 REFADJ TP2 26 OGND 45 OGND 61 OGND VCC 33 D0N N.C. 32 REFIO AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND VCC CLKDIV 16 2 5 7 10 15 18 19 21 24 64 66 67 R40 OPEN C20 0.1µF 4 D1N D0P 34 N.C. 29 ORP R18 100Ω 1% R19 100Ω 1% R20 100Ω 1% R21 100Ω 1% R22 100Ω 1% D7P D9N D8P D7N D8N D6P D7P D6N D7N D5P D6P D5N D6N D5P D4P R23 D4N 100Ω 1% D5N D4P DCOP R24 100Ω DCON 1% D4N DCOP R28 D3P 100Ω 1% D3N DCON D3P R29 D2P 100Ω 1% D3N D2N D2P R30 100Ω D1P 1% D2N D1N D1P R31 100Ω D0P 1% D1N D0N D0P R32 100Ω NC1 1% D0N NC2 NC1 R34 100Ω 1% NC3 NC2 NC3 NC4 R35 100Ω 1% NC4 Figure 1. MAX1124 EV Kit Schematic (Sheet 1 of 3) 6 _______________________________________________________________________________________ J5 MAX1124 Evaluation Kit 1 VCC ORP ORN 2 3 20 VCC 1 VCC Q0 DO 19 D9N 4 5 D6P BORP R41 510Ω DO U3 MC100LVEL17 D9P VPECL D6N Q0 D1 Q1 D5P 18 BORN 17 3 D5N BD9P 4 5 1 VCC Q0 19 D8N 6 7 R46 510Ω Q1 Q2 D7P D7N 8 9 16 15 D4N D1 Q0 D1 Q1 6 Q3 13 BD6N 17 BD5P 5 D3N 1 VCC Q0 19 7 R52 510Ω D2 BD8P Q2 8 9 16 15 R57 510Ω DO 7 D2N D1 Q0 D1 Q1 BD7P Q3 Q2 8 D1P 9 16 15 VEE Q3 11 Q0 19 4 5 R56 510Ω D1 Q0 D1 Q1 18 Q2 13 Q3 14 13 BDON 17 NC4 6 BNC1 7 D2 R66 510Ω D2 Q1 BD2P Q2 8 9 16 BNC2 15 BNC3 R67 510Ω D3 D3 R62 510Ω BD4N BDOP R55 510Ω DO BD3N D3 R68 510Ω BD2N Q2 BD1P Q3 14 BNC4 13 R63 510Ω R50 510Ω VBB 10 3 20 VCC DO R65 510Ω R61 510Ω D3 R49 510Ω 12 NC2 BD3P R60 510Ω D2 R54 510Ω 14 BDCON 17 NC3 BD4P D1N Q2 NC1 18 2 U6 MC100LVEL17 D2 Q1 D3 BD8N DON R58 510Ω BD5N R53 510Ω D3 DOP BDCOP C39 0.1µF R59 510Ω 6 D2P R48 510Ω 14 4 D3P 18 VPECL 20 VCC DO U5 MC100LVEL17 D2 Q1 D3 Q2 3 DCON R39 510Ω BD9N R47 510Ω D3 2 DCOP C37 0.1µF R51 510Ω D4P D2 D2 BD6P R38 510Ω DO R45 510Ω D8P VPECL 20 VCC DO U4 MC100LVEL17 R44 510Ω D1 2 C38 0.1µF Evaluates: MAX1121–MAX1124 C36 0.1µF VPECL R64 510Ω BD7N VBB 10 VEE Q3 11 12 VBB 10 VEE Q3 11 12 J6 BD1N VBB 10 VEE Q3 11 12 J7 B0RP J6–4 J6–2 BDCOP J7–2 J7–3 B0RN J6–3 J6–5 BDCON J7–1 J7–4 J6–1 J6–6 J7–5 J7–6 BD9P J6–10 J6–8 BD3P J7–8 J7–9 BD9N J6–9 J6–7 BD3N J7–7 J7–10 J6–11 J6–12 J7–11 J7–12 BD8P J6–16 J6–14 BD2P J7–14 J7–15 BD8N J6–15 J6–13 BD2N J7–13 J7–16 J6–17 J6–18 J7–17 J7–18 BD7P J6–22 J6–20 BD1P J7–20 J7–21 BD7N J6–21 J6–19 BD1N J7–19 J7–22 J6–23 J6–24 J7–23 J7–24 BD6P J6–28 J6–26 BD0P J7–26 J7–27 BD6N J6–27 J6–25 BD0N J7–25 J7–28 J6–29 J6–30 J7–29 J7–30 BD5P J6–34 J6–32 BNC1 J7–32 J7–33 BD5N J6–33 J6–31 BNC2 J7–31 J7–34 J6–35 J6–36 J7–35 J7–36 BD4P J6–40 J6–38 BNC3 J7–38 J7–39 BD4N J6–39 J6–37 BNC4 J7–37 J7–40 Figure 1. MAX1124 EV Kit Schematic (Sheet 2 of 3) _______________________________________________________________________________________ 7 Evaluates: MAX1121–MAX1124 MAX1124 Evaluation Kit VCLK VCLK GND C27 47µF 10V C32 1.0µF C29 10µF VCC VCC GND C28 47µF 10V C33 1.0µF C30 10µF C31 10µF C34 1.0µF VPECL VPECL GND C40 47µF 10V C41 10µF C42 1.0µF Figure 1. MAX1124 EV Kit Schematic (Sheet 3 of 3) Figure 2. Component Placement Guide—Component Side 8 _______________________________________________________________________________________ MAX1124 Evaluation Kit Evaluates: MAX1121–MAX1124 Figure 3. PC Board Layout—Component Side Figure 4. PC Board Layout (Inner Layer 2)—Ground Planes _______________________________________________________________________________________ 9 Evaluates: MAX1121–MAX1124 MAX1124 Evaluation Kit Figure 5. PC Board Layout (Inner Layer 3)—Power Planes Figure 6. PC Board Layout—Solder Side Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.