13-3087; Rev 0; 1/04 KIT ATION EVALU E L B A AVAIL Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers Critical loads often employ parallel-connected power supplies with redundancy to enhance system reliability. The MAX8555/MAX8555A are highly integrated, inexpensive MOSFET controllers that provide isolation and redundant power capability in high-reliability systems. The MAX8555/MAX8555A are used in 0.5V to 3.3V systems, and have an internal charge pump to drive the gates of the N-channel pass elements to (VCS+ + 5V). During startup, the MAX8555/MAX8555A monitor the voltage drop across the external MOSFETs. Once VCS+ approaches or exceeds the bus voltage (VCS-), the MOSFETs are turned on. The MAX8555/MAX8555A feature a dual-purpose TIMER input. A single external resistor from TIMER to ground sets the turn-on speed of the external MOSFETs. Optionally, the TIMER input can be used as a logic enable input. Once the external MOSFET is turned on, these controllers monitor the load, protecting the bus against overvoltage, undervoltage, and reverse-current fault conditions. The MAX8555 is available with a 40mV reverse-current threshold, while the MAX8555A is available with a 20mV reverse-current threshold. Overvoltage and undervoltage fault thresholds are adjustable and can be disabled. The current-limit trip points are set by the external MOSFETs’ R DS(ON) , reducing component count. An open-drain, logic-low fault output indicates if an overvoltage, undervoltage, or reverse-current fault occurs. The MAX8555 and the MAX8555A can shut down in response to a reversecurrent fault condition as quickly as 200ns. Both devices come in space-saving 10-pin µMAX or TDFN packages and are specified over the extended -40°C to +85°C temperature range. Applications Features ♦ Simple, Integrated, and Inexpensive MOSFET Controllers ♦ ORing FET Drive for 0.5V to 3.3V ♦ Eliminate ORing Diode Power Dissipation ♦ Provide N+1 Redundant Supply Capability for Highly Reliable Systems ♦ Isolate Failed Short-Circuit Supply from Output BUS ♦ Respond to Reverse Short-Circuit Current in 200ns ♦ Adjustable Blank Time ♦ Programmable Soft-Start ♦ Logic Enable Input ♦ Adjustable Overvoltage and Undervoltage Trip Points ♦ Fault-Indicator Output ♦ Space-Saving Packages Ordering Information TEMP RANGE PART MAX8555ETB -40°C to 85°C 10 TDFN 3mm x 3mm* MAX8555EUB -40°C to 85°C 10 µMAX MAX8555AETB -40°C to 85°C 10 TDFN 3mm x 3mm* MAX8555AEUB -40°C to 85°C 10 µMAX TOP MARK ACC 8555EUB ADD 8555AEUB *Exposed paddle Point-of-Load Supplies Pin Configurations Power-Supply Modules Servers PINPACKAGE TOP VIEW Telecom Power Supplies Rectifiers GATE 1 Redundant Power Supplies in High-Availability Systems Typical Operating Circuit appears at end of data sheet. 10 CS+ GATE 1 9 CS- GND 2 8 OVP VL 3 10 CS+ GND 2 VL 3 VDD 4 7 FAULT VDD 4 7 FAULT UVP 5 6 TIMER UVP 5 6 TIMER MAX8555/ MAX8555A µMAX MAX8555/ MAX8555A 9 CS8 OVP TDFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8555/MAX8555A General Description MAX8555/MAX8555A Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers ABSOLUTE MAXIMUM RATINGS GATE to GND .........................................................-0.3V to +12V FAULT, VL to GND ...................................................-0.3V to +6V OVP, UVP, TIMER, CS+, CS- to GND .......-0.3V to +(VVL + 0.3V) VDD to GND..................................................(VVL - 0.3V) to +18V Continuous Power Dissipation (TA = +70°C) 10-Pin µMAX (derate 5.6mW/°C above +70°C) ...........444mW 10-Pin TDFN (derate 24.4mW/°C above +70°C) .......1951mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.25V, RFAULT = 50kΩ, CVDD = CGATE = CVL = 0.01µF, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX VL unconnected 8.00 13.25 VL = VDD 3.0 5.5 UNITS VDD SUPPLY VDD Input Voltage VDD Supply Current VTIMER = 2.5V VL unconnected, VTIMER = 2.5V, VDD = 13.25V 2.0 3.3 VDD = VVL = 5V, VTIMER = 2.5V 0.04 0.2 VDD Shutdown Current VTIMER = 0V, VDD = 13.25V VDD Overvoltage Internal Threshold Rising threshold 14.0 14.4 15.0 3.0 Falling threshold 13.3 13.8 14.5 VDD = VVL 3.0 V mA mA V VL SUPPLY VL Input Voltage 5.5 V VL Supply Current VDD = VVL = 5V, VTIMER = 2.5V 1.8 3.0 mA VL Current in Shutdown Mode TIMER = GND, VDD = VVL = 5V 1.6 3.0 mA VL Output Voltage VDD = 8V to 13.25V, IVL = 0A 3.80 4.1 4.45 V VL = VDD, rising threshold 2.78 2.82 2.90 VL = VDD, falling threshold 2.68 2.75 2.82 VL Undervoltage Lockout V CS INPUTS CS+, CS- Input Current VTIMER = 2.5V, VCS = 3.0V Offset Input Current (CS+, CS-) VCS = 3.0V, Figure 4 CS+/CS- Input Range (Note 1) CS Isolation 5.2 µA -250 +250 nA 0.5 VVL - 0.5 V VCS+ = +3V, VCS- = 0V, ICS- -0.5 VCS- = +3V, VCS+ = 0V, ICS+ -0.5 µA CHARGE-PUMP VOLTAGE GATE Voltage, VGATE Charge-Pump Switching Frequency 2 Measured from GATE to CS+ VDD = 8V to 13.25V VDD = VVL = 5V 5.0 5.25 RTIMER = 20kΩ 187 RTIMER = 125kΩ 450 RTIMER = open 500 VTIMER = 1.5V 550 _______________________________________________________________________________________ 5.5 V kHz Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers (VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.25V, RFAULT = 50kΩ, CVDD = CGATE = CVL = 0.01µF, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS 1.22 1.25 1.28 V 85 100 115 µA 10 15 µA VVL V TIMER TIMER Voltage TIMER Maximum Source Current VTIMER = 1.0V TIMER High Input Current VTIMER = 1.5V TIMER Maximum Frequency Select Voltage Input Range (Note 1) 1.5 TIMER Logic High, VIH Charge pump enabled 1.0 TIMER Logic Low, VIL Charge pump disabled V 0.5 V FAULT Fault Output Low Voltage IFAULT = 10mA Fault Sink Current V FAULT = 0.4V Fault Leakage Current V FAULT = 5.5V, TA = +25°C 0.2 15 V mA 1 µA GATE Gate-On Threshold Measured from CS- to CS+ VGATE = VCS+ = 2.5V Gate-Drive Current MAX8555 80 100 120 MAX8555A 35 50 65 RTIMER = open 17 25 33 RTIMER = 25kΩ 8 12 16 VGATE = VCS+ = 2.5V, VDD = VVL = 3V RTIMER = open 15 RTIMER = 25kΩ 7.5 VGATE = VCS+ = 2.5V, VDD = VVL = 5V RTIMER = open 30 µA RTIMER = 25kΩ 15 VTIMER falling 100 200 IREV fault 60 150 Gate Shutdown Delay (Note 2) Gate Discharge Current VGATE = VCS+= +5V GATE Fall Time Gate voltage fall from FAULT to VGATE = VCS+, R1 = 2Ω, Figure 3 or Figure 4 mV ns 1000 mA 0.2 µs CURRENT SENSE Reverse-Current Threshold Measured from CS- to CS+ Startup IREV Blank Time TIMER = unconnected Forward-Current Threshold Measured from CS+ to CS- MAX8555 34 40 46 MAX8555A 16 20 24 4.1 6 10 mV ms 14 mV _______________________________________________________________________________________ 3 MAX8555/MAX8555A ELECTRICAL CHARACTERISTICS (continued) MAX8555/MAX8555A Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers ELECTRICAL CHARACTERISTICS (continued) (VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.25V, RFAULT = 50kΩ, CVDD = CGATE = CVL = 0.01µF, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX 0.5 0.51 UNITS OVERVOLTAGE PROTECTION OVP Fault Threshold, VOVP OVP Bias Current OVP rising 0.49 OVP falling 0.4 TA = +25°C 0.1 TA = +85°C 0.021 V µA UNDERVOLTAGE PROTECTION UVP Fault Threshold, VUVP UVP Bias Current UVP rising 0.488 UVP falling 0.5 0.512 0.4 TA = +25°C 0.1 TA = +85°C 0.003 V µA ELECTRICAL CHARACTERISTICS (VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.25V, RFAULT = 50kΩ, CVDD = CGATE = CVL = 0.01µF, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS VDD SUPPLY VDD Input Voltage VTIMER = 2.5V VL unconnected 8.00 13.25 VL = VDD 3.0 5.5 V VL unconnected, VTIMER = 2.5V, VDD = 13.25V 3.3 VDD = VVL = 5V, VTIMER = 2.5V 0.2 VDD Shutdown Current VTIMER = 0V, VDD = 13.25V 3.0 VDD Overvoltage Internal Threshold Rising threshold 14.0 15.0 Falling threshold 13.3 14.5 VL Input Voltage VDD = VVL 3.0 5.5 V VL Supply Current VDD = VVL = 5V, VTIMER = 2.5V 3.0 mA VL Current in Shutdown Mode TIMER = GND, VDD = VVL= 5V 3.0 mA VL Output Voltage VDD = 8V to 13.25V, IVL = 0A 3.80 4.45 V VL = VDD, rising threshold 2.78 2.90 VL = VDD, falling threshold 2.68 2.82 Offset Input Current (CS+, CS-) VCS = 3.0V, Figure 4 -250 +250 nA CS+/CS- Input Range (Note 1) 0.5 VVL - 0.5 V 5.0 5.5 V VDD Supply Current mA mA V VL SUPPLY VL Undervoltage Lockout V CS INPUTS CHARGE-PUMP VOLTAGE GATE Voltage, VGATE 4 Measured from GATE to CS+ VDD = 8V to 13.25V VDD = VVL = 5V _______________________________________________________________________________________ Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers (VDD = 12V, VCS- = 1.4V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.25V, RFAULT = 50kΩ, CVDD = CGATE = CVL = 0.01µF, TA = -40°C to +85°C, unless otherwise noted.) (Note 3) PARAMETER CONDITIONS MIN TYP MAX UNITS 1.22 1.28 V 85 115 µA 15 µA VVL V TIMER TIMER Voltage TIMER Maximum Source Current VTIMER = 1.0V TIMER High Input Current VTIMER = 1.5V TIMER Maximum Frequency Select Voltage Input Range (Note 1) 1.5 TIMER Logic High, VIH Charge pump enabled 1.1 TIMER Logic Low, VIL Charge pump disabled V 0.5 V FAULT Fault Output Low Voltage IFAULT = 10mA Fault Sink Current V FAULT = 0.4V 0.2 15 V mA GATE Gate-On Threshold Measured from CS- to CS+ Gate-Drive Current VGATE = VCS+ = 2.5V Gate Shutdown Delay MAX8555 80 120 MAX8555A 35 65 RTIMER = open 17 33 RTIMER = 25kΩ 8 16 VTIMER falling 200 IREV fault 150 mV µA ns CURRENT SENSE MAX8555 34 46 MAX8555A 16 24 6 14 mV OVP rising 0.49 0.51 V UVP rising 0.488 0.512 V Reverse-Current Threshold Measured from CS- to CS+ Forward-Current Threshold Measured from CS+ to CS- mV OVERVOLTAGE PROTECTION OVP Fault Threshold, VOVP UNDERVOLTAGE PROTECTION UVP Fault Threshold, VUVP Note 1: Guaranteed by design. Not production tested. Note 2: Gate shutdown delay is measured from reverse-current fault to the start of gate-voltage falling or from TIMER to the start of gate-voltage falling. Note 3: Specifications to -40°C are guaranteed by design and not production tested. _______________________________________________________________________________________ 5 MAX8555/MAX8555A ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = 12V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.4V, RFAULT = 50kΩ to output bus, CVDD = CGATE = CVL = 0.01µF, TA = +25°C, R1 = 2Ω in Figure 3, MAX8555A, unless otherwise noted.) 5 TA = +85°C 16 14 12 TA = -40°C TA = +25°C 10 8 6 TIMER = OPEN 2.5 VDD CURRENT (mA) 10 VDD CURRENT vs. TEMPERATURE 3.0 MAX8555/55A toc02 TA = -40°C TA = +25°C 15 18 GATE-CHARGE CURRENT (µA) TA = +85°C 20 MAX8555/55A toc01 25 GATE-CHARGE CURRENT vs. TIMER RESISTOR (VDD = VVL = 3V) MAX8555/55A toc03 GATE-CHARGE CURRENT vs. TIMER RESISTOR (VDD = 12V) GATE CURRENT (µA) 2.0 1.5 TIMER = GND 1.0 4 0.5 2 0 0 -5 100 1000 10 26.0 24.0 22.0 20.0 18.0 16.0 45.0 40.0 30.0 20.0 15.0 10.0 5.0 10.0 0 60 OVP 25.0 12.0 40 40 35.0 14.0 20 20 50.0 LEAKAGE CURRENT (nA) 28.0 0 0 TEMPERATURE (°C) OVP AND UVP LEAKAGE CURRENT vs. TEMPERATURE MAX8555/55A toc04 30.0 -20 -20 TIMER RESISTOR (kΩ) REVERSE-CURRENT THRESHOLD vs. TEMPERATURE -40 -40 1000 100 TIMER RESISTOR (kΩ) MAX8555/55A toc05 10 VDD = 13.25V 0 -2 REVERSE-CURRENT THRESHOLD (mV) MAX8555/MAX8555A Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers 80 UVP -40 -20 0 20 40 60 TEMPERATURE (°C) TEMPERATURE (°C) POWER-UP WAVEFORMS BUS VOLTAGE HIGH IMPEDANCE POWER-UP WAVEFORMS BUS VOLTAGE IS LIVE MAX8555/55A toc06 80 MAX8555/55A toc07 1V/div VGATE 5V/div 5V/div VCS+ 1V/div VCS- 1V/div VCS+ VGATE 1V/div VCS- 1A/div 500mA/div IMOSFET IMOSFET 1ms/div 6 2ms/div _______________________________________________________________________________________ 60 80 Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers POWER-UP AND DOWN WAVEFORMS USING TIMER REVERSE-CURRENT SHUTDOWN WAVEFORMS MAX8555/55A toc08 VTIMER MAX8555/55A toc09 2V/div VGATE 5V/div 5V/div VFAULT 1V/div VGATE VCS- 1A/div IMOSFET 100mV/div 0A IMOSFET -2A 5ms/div 200ns/div UVP SHUTDOWN WAVEFORMS OVP SHUTDOWN WAVEFORMS MAX8555/55A toc10 MAX8555/55A toc11 2V/div VFAULT 2V/div VOVP 5V/div VGATE VCSAC-COUPLED VCSAC-COUPLED 100mV/div VUVP 2V/div 100mV/div VGATE 5V/div VFAULT 200ns/div 1V/div 200ns/div POWER-SUPPLY OUTPUT SHORT-CIRCUIT SHUTDOWN WAVEFORMS VDD FAULT SHUTDOWN WAVEFORMS MAX8555/55A toc12 MAX8555/55A toc13 5V/div VGATE1 VCS+ 1V/div VCSAC-COUPLED 100mV/div IMOSFET2 200mA/div 200ns/div VCS- 1V/div VGATE 5V/div VDD 10V/div 1V/div VFAULT 1µs/div _______________________________________________________________________________________ 7 MAX8555/MAX8555A Typical Operating Characteristics (continued) (VDD = 12V, VCS+ = 1.5V, RTIMER = 25kΩ, VUVP = 1V, VOVP = 0.4V, RFAULT = 50kΩ to output bus, CVDD = CGATE = CVL = 0.01µF, TA = +25°C, R1 = 2Ω in Figure 3, MAX8555A, unless otherwise noted.) MAX8555/MAX8555A Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers Pin Description 8 PIN NAME FUNCTION 1 GATE Gate-Drive Output. Nominal GATE load is a 0.01µF capacitor to ground. Gate is discharged to GND in shutdown. 2 GND Ground 3 VL Low-Voltage Optional Input Power. Leave disconnected when VDD = 8V to 13.25V, or connect VDD to VL when VDD = 3V to 5.5V. Bypass VL to GND with a 0.01µF capacitor. 4 VDD Power-Supply Input. Connect to an 8V to 13.25V supply or connect to VL when using a 3V to 5.5V supply. Bypass VDD with a 0.01µF capacitor to ground. 5 UVP Undervoltage-Protection Input. Connect UVP to the center of a resistor-divider from CS+ to GND. Connect UVP to VL to disable the undervoltage protection. 6 TIMER Timer Input. Connect a resistor from TIMER to GND to select the charge-pump operating frequency. Drive TIMER low (< 0.5V) to disable the gate drive. Drive TIMER high (above 1.5V) for charge-pump operation at 550kHz. 7 FAULT Open-Drain Fault Output. FAULT is high impedance during normal operation and is pulled to GND when a fault condition occurs. Connect a pullup resistor of 10kΩ or higher value (50kΩ typ) to a voltage rail of 5.5V or lower. 8 OVP Overvoltage-Protection Input. Connect OVP to the center of a resistor-divider from the output bus to GND. Connect OVP to GND to disable the overvoltage protection. 9 CS- Current-Sensing Input. Connect CS- to the positive side of the system bus. Bypass with a 1000pF capacitor to GND. 10 CS+ Current-Sensing Input. Connect CS+ to the positive side of the input power. Bypass with a 1000pF capacitor to GND. _______________________________________________________________________________________ Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers 100mV (50mV) CHARGE PUMP MAX8555/MAX8555A VL CS- CS+ GATE 40mV (20mV) 10mV CLK SHUTDOWN VL VOLTAGE SHARE REVERSE CURRENT CONTROL LOGIC FAULT FORWARD CURRENT OVERVOLTAGE INTERNAL OVERVOLTAGE EXTERNAL 14.5V UNDERVOLTAGE OVP 0.5V IOSC ENABLE UVP VL TIMER 1.25V REF 0.4V VL REGULATOR MAX8555/ (MAX8555A) VDD GND VL Figure 1. MAX8555/MAX8555A Functional Diagram _______________________________________________________________________________________ 9 Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers MAX8555/MAX8555A State Diagram VCC > VCCOK ALL TRANSITIONS ARE ASYNCHRONOUS CS- CS- + 10mV CS- - 40mV/20mV CS- - 100mV/50mV STANDBY: CPMP: OFF GATE: LOW VSHARE LATCH SET CS+ TIMER > 1V IFORWARD 4.1ms IREVERSE CS- - CS+ > 0.1V WAIT FOR VSHARE VSHARE = ((CS-) - CS+) < 0.1V/0.05V IFORWARD = ((CS+) - CS-) > 0.01V IREVERSE = ((CS-) -CS+ ) > 40mV/20mV CS- - CS+ < 0.1V UVP FAULT ON: SET VSHARE LATCH, CHARGE PUMP ON UVP FAULT SHUTDOWN GATE FAULT NOT LATCHED IFORWARD and OVP Fault UVP-OK VCC OR TIMER CYCLED OVP OK AND IREVERSE DURING FIRST 4.1ms FAULT SHUTDOWN GATE FAULT LATCHED UVP = OK IREVERSE CONDITION DETECTED AFTER 4.1ms BLANK TIME VDD OR TIMER CYCLED FAULT SHUTDOWN GATE: FAULT LATCHED 10 ______________________________________________________________________________________ Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers Critical loads often employ parallel-connected power supplies with redundancy to enhance system reliability. The MAX8555/MAX8555A are highly integrated, inexpensive MOSFET controllers that provide isolation and redundant power capability in high-reliability systems. The MAX8555/MAX8555A are used in 0.5V to 3.3V systems, and have an internal charge pump to drive the gates of the N-channel pass elements to VCS+ + 5V. During startup, the MAX8555/MAX8555A monitor the voltage drop across the external MOSFETs. Once VCS+ approaches or exceeds the bus voltage (V CS-), the MOSFETs are turned on. The MAX8555/MAX8555A feature a dual-purpose TIMER input. A single external resistor from TIMER to ground sets the turn-on speed of the external MOSFETs. Optionally, the TIMER input can be used as a logic enable input. Once the external MOSFET is turned on, these controllers monitor the load, protecting the bus against overvoltage, undervoltage, and reverse-current fault conditions. The MAX8555 is available with a 40mV reverse-current threshold, while the MAX8555A is available with a 20mV reverse-current threshold. Overvoltage and undervoltage fault thresholds are adjustable and can be disabled. The current-limit trip points are set by the external MOSFETs’ RDS(ON) , reducing component count. An open-drain, logic-low fault output indicates if an overvoltage, undervoltage, or reverse-current fault occurs. The MAX8555 and the MAX8555A can shut down in response to a reversecurrent fault condition as quickly as 200ns. VDD V DD is the power-supply input for the MAX8555/ MAX8555A and the input to the internal preregulator. Bypass VDD to GND with a 0.01µF capacitor. The input supply range for V DD is 8V to 13.25V. The internal charge pump is disabled for input voltages above 14.4V (typ). For 3V to 5.5V input voltages, connect VDD to VL. VL VL is the regulated power supply for the MAX8555/MAX8555A. The MAX8555/MAX8555A monitor VL at all times. During startup the device turns on when VL rises above VL OK (2.82V typ). After V VL exceeds VL OK and V CS+ is typically greater than (VCS- - 100mV), the charge pump turns on and drives GATE high, turning on the external MOSFETs. For operation from 3V to 5.5V input supplies, connect VL to VDD. TIMER GATE is the output of the internal charge pump that drives the external MOSFETS. During startup, the voltage at GATE ramps up according to the charge-pump frequency. At 250kHz, the GATE drive current for the MAX8555/MAX8555A is 12µA. Increasing the chargepump frequency increases the GATE drive current. To change charge-pump frequency, change the value of RTIMER. See the Selecting the TIMER Resistor section. CS+, CSThe voltage drop across the external MOSFETs is measured between the CS+ and CS- inputs. CS+ connects to the positive side of the input voltage. CS- connects to the positive side of the system bus. The MAX8555/ MAX8555A use the voltage drop across CS+ and CS- to determine operating mode. I FORWARD is defined as VCS+ - VCS- and must be greater than 0.01V (typ) to properly detect an overvoltage fault condition. IREVERSE is defined as VCS- - VCS+ and must be greater than 0.02V (MAX8555A) or 0.04V (MAX8555) (typ) for a reverse-current fault. The I FORWARD and I REVERSE thresholds can be effectively increased by placing an external divider such as R8 and R9 as shown in Figure 4. The values shown increase the thresholds by 50%. When R8 and R9 are used, also add R10 (a parallel combination of R8 and R9) to eliminate any input offset errors caused by impedance differences and input-bias-current differences. Fault Conditions The MAX8555/MAX8555A have an open-drain FAULT output that signals overvoltage, undervoltage, or reverse-current fault conditions. During a fault condition, FAULT is pulled to GND, the charge pump shuts down, and GATE discharges to CS- in 200ns (typ). See Table 1 for fault modes. Undervoltage Fault The MAX8555/MAX8555A turn off the external MOSFETs if VUVP falls below the UVP threshold (0.4V). Connect UVP to the center of a resistor-divider from the input supply to GND. Once VUVP rises above the UVP rising threshold (0.5V), FAULT clears and GATE is driven high. FAULT is not latched. Connect UVP to VL to disable the undervoltage-protection feature. Overvoltage Fault The MAX8555/MAX8555A are protected from overvoltage conditions using an adjustable overvoltage-protection input. A resistor-divider from the output bus to GND with OVP connected to the center tap sets the overvoltage threshold. When VOVP exceeds the OVP threshold (0.5V) and the device is in the I FORWARD condition ______________________________________________________________________________________ 11 MAX8555/MAX8555A General Description MAX8555/MAX8555A Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers Table 1. Fault Modes GATE FAULT LATCHING VL UVLO VL < VLOK LOW High Impedance NO UVP Undervoltage Protection VUVP < 0.4V LOW LOW NO OVP Overvoltage Protection VOVP > 0.5V VCS+ > VCS- + 0.01V LOW LOW YES Reverse-Current Protection VCS+ < VCS- - 0.04V (0.02V for MAX8555A) and GATE is on for > 2048 charge-pump cycles LOW LOW YES VDD Internal Overvoltage Protection VDD > 14.5V LOW LOW NO FAULT MODE CONDITIONS SYSTEM BUS R5 2.87kΩ R2A 47kΩ R2B 6.04kΩ FAULT 150pF R2A 47kΩ R6 1kΩ 150pF R2B 6.04kΩ FAULT Reverse-Current Fault The MAX8555/MAX8555A provide a reverse-current fault-protection feature that turns off the oring MOSFET when a reverse-current fault condition is detected. Once a reverse-current fault condition is detected, the MAX8555/MAX8555A discharge GATE to GND and latch FAULT low. Toggle VDD, VL, or TIMER to reset the IC. The reverse-current-protection feature is blanked for 2048 charge-pump cycles at startup. Selecting the TIMER Resistor Connect a resistor from TIMER to GND to set the internal charge pump’s frequency of operation. Determine the TIMER resistor with the following equation: OVP OVP R TIMER = Figure 2. OVP Connection when Multiple MAX8555s Are Used (defined as V CS+ > V CS- + 0.01V), the MAX8555/ MAX8555A discharge GATE to GND and FAULT is latched low. If the IFORWARD condition is not detected, OVP is disabled. In redundant systems, when one input supply approaches its OVP threshold, some of the other input supplies may be pulled up with it, thereby tripping those OVP comparators with a slightly lower set point. The I FORWARD condition for the pulled-up supplies may not be detected until the first supply is shut down. An alternate application schematic for FAULT and OVP is shown in Figure 2. The FAULT output of the first channel, which has both OVP and IFORWARD conditions, temporarily reduces the common OVP signal by 125mV. This ensures that only the input supply, which is causing the overvoltage condition, is turned off in a redundant power-system application. Exceeding the OVP threshold causes the MAX8555/ MAX8555A to be latched off. Toggle VDD or TIMER to reset the IC. Connect OVP to GND to disable the overvoltage-protection feature. 12 1.25V 100µA − f 5kHz / µA Drive TIMER above 1.5V for the maximum chargepump frequency (550kHz). Drive TIMER below 0.5V to disable the charge pump and shut down the MAX8555/ MAX8555A. Selecting the GATE Capacitor and GATE Resistor The charge pump uses an internal monolithic transfer capacitor to charge the external MOSFET gates. Normally, the external MOSFET’s gate capacitance is sufficient to serve as a reservoir capacitor. To slow down turn-on times further, add a small capacitor between GATE and GND. Adding a small resistor between GATE and the gate of the Oring MOSFET reduces the high-frequency ringing due to gate trace inductance. However, the resistor increases the turn-off time. ______________________________________________________________________________________ Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers OUTPUT: 1.5V/20A -VO Q2 +VO Q1 OUT+ C1 1000pF R3 5kΩ R5 15kΩ 12V FAULT VL MAX8555/ MAX8555A VDD UVP C2 0.01µF OVP GND TIMER R4 10kΩ R2 51kΩ OUTPUT BUS CS- GATE CS+ C4 0.01µF INPUT SUPPLY C3 1000pF R1 2Ω R6 10kΩ R7 24.9kΩ OUT- Figure 3. Application Circuit for 12V IC Supply Voltage R9 2kΩ Q2 OUTPUT: 1.5V/20A -VO Q1 +VO R8 1kΩ OUT+ R10 665Ω 5V INPUT SUPPLY R1 2Ω C1 0.01µF R3 5kΩ GATE CS+ C3 1000pF CS- MAX8555/ MAX8555A VDD UVP TIMER C2 0.01µF R2 51kΩ FAULT VL R4 10kΩ R5 15kΩ OUTPUT BUS C4 1000pF OVP GND R6 10kΩ R7 24.9kΩ OUT- Figure 4. Application Circuit for 5V IC Supply Voltage ______________________________________________________________________________________ 13 MAX8555/MAX8555A Applications Information MAX8555/MAX8555A Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers Set the UVP Fault Threshold Use a resistor-divider from the input supply to GND with the center tap connected to UVP to set the undervoltage threshold. Use a 10kΩ resistor from UVP to GND (R4 in Figure 4) and calculate R3 as follows: V R3 = R4 UV − 1 VUVP where VUV is the desired undervoltage trip point and VUVP is the UVP reference threshold (0.4V typ). Connect UVP to VL to disable the undervoltage-protection feature. Set the OVP Fault Threshold For a single-supply application, use a resistor-divider from the output bus to GND with the center tap connected to OVP to set the overvoltage threshold. Use a 10kΩ resistor from OVP to GND (R6 in Figure 4) and calculate R5 as follows: V R5 = R6 OV − 1 VOVP where VOV is the desired overvoltage threshold and VOVP is the OVP reference threshold (0.5V typ). Connect OVP to GND to disable the overvoltage-protection feature. For (n + 1) applications, the required circuit values are: R6 = 1kΩ V R5 = R6 × OV − 1 VOVP R2A = 47kΩ R2B = 2 × R5 where the resistors are as shown in Figure 2. MOSFET Selection The MAX8555/MAX8555A drive N-channel MOSFETs. The most important specification of the MOSFETs is RDS(ON). As load current flows through the external MOSFET, VDS is generated from source to drain due to the MOSFET’s on-resistance, RDS(ON). The MAX8555/ MAX8555A monitor VDS of the MOSFETs at all times to determine the state of the monitored power supply. Selecting a MOSFET with a low RDS(ON) allows more current to flow through the MOSFETs before the MAX8555/MAX8555A detect reverse-current (IREVERSE) and forward-current (IFORWARD) conditions. 14 Using Two MOSFETs Two MOSFETs must be used for overvoltage protection. When using two external MOSFETs, the monitored voltage equation becomes: VDSTOTAL = RDS(ON)1 x ILOAD + RDS(ON)2 x ILOAD Using One MOSFET A single MOSFET can be used if the overvoltage-protection function is not needed. Connect CS+ to the source of the MOSFET and CS- to the drain of the MOSFET. Calculating GATE Current The charge-pump output current is proportional to both oscillator frequency and VVL. There is also a small internal load of approximately 6MΩ. The GATE current for a given VVL and RTIMER is calculated as: (V − 0.8) 12, 500 IGATE ≈ 24.12 × L × 1 − − 0.4 µA 3 . 4 R TIMER Layout Guidelines It is important to keep all traces as short as possible and to maximize the high-current trace dimensions to reduce the effect of undesirable parasitic inductance. The MOSFET dissipates a fair amount of heat due to the high currents involved, especially during an overcurrent condition. To dissipate the heat generated by the MOSFET, make the power traces very wide with a large amount of copper area and place the MAX8555 as close as possible to the drain of the external MOSFET. A more efficient way to achieve good power dissipation on a surface-mount package is to lay out two copper pads directly under the MOSFET package on both sides of the board. Use enlarged copper mounting pads on the top side of the board. Use a ground plane to minimize impedance and inductance. In addition to the usual high-power considerations, here are three tips to prevent false faults: 1) Kelvin connect CS+ and CS- to the external MOSFET and route the two traces in parallel, as close as possible, back to the IC. 2) Bypass VDD with a 0.01µF capacitor to ground and bypass CS+ and CS- with a 1000pF capacitor to ground. 3) Make the traces connected to UVP and OVP as short as possible. Refer to the MAX8555/MAX8555A evaluation kit for an example of good PC board layout. ______________________________________________________________________________________ Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers -VO +VO OUTPUT: 1.5V AT 20A INPUT SUPPLY 8V TO 13.25V CS- GATE CS+ VDD UVP VL OUTPUT BUS OUT+ FAULT MAX8555/ MAX8555A TIMER OVP GND OUT- Chip Information TRANSISTOR COUNT: 2309 PROCESS: BiCMOS ______________________________________________________________________________________ 15 MAX8555/MAX8555A Typical Operating Circuit Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 6, 8, &10L, DFN THIN.EPS MAX8555/MAX8555A Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers L A D D2 A2 PIN 1 ID 1 N 1 C0.35 b E PIN 1 INDEX AREA [(N/2)-1] x e REF. E2 DETAIL A e k A1 CL CL L L e e A DALLAS SEMICONDUCTOR PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY APPROVAL DOCUMENT CONTROL NO. 21-0137 REV. D 1 2 COMMON DIMENSIONS SYMBOL A MIN. MAX. 0.70 0.80 D 2.90 3.10 E 2.90 3.10 A1 0.00 0.05 L k 0.20 0.40 0.25 MIN. A2 0.20 REF. PACKAGE VARIATIONS PKG. CODE N D2 E2 e JEDEC SPEC b T633-1 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF T833-1 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF T1033-1 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF [(N/2)-1] x e DALLAS SEMICONDUCTOR PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm APPROVAL DOCUMENT CONTROL NO. 21-0137 16 REV. D 2 2 ______________________________________________________________________________________ Low-Cost, High-Reliability, 0.5V to 3.3V ORing MOSFET Controllers 10LUMAX.EPS e 4X S 10 INCHES 10 H ÿ 0.50±0.1 0.6±0.1 1 1 0.6±0.1 BOTTOM VIEW TOP VIEW D2 MILLIMETERS MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 D1 0.116 0.120 0.114 0.118 D2 0.116 E1 0.120 E2 0.114 0.118 H 0.187 0.199 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S α 0∞ 6∞ MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0∞ 6∞ E2 GAGE PLANE A2 c A b D1 A1 α FRONT VIEW E1 L L1 SIDE VIEW PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, 10L uMAX/uSOP APPROVAL DOCUMENT CONTROL NO. 21-0061 REV. I 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX8555/MAX8555A Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)