19-3649; Rev 0; 4/05 Overvoltage Protection Controllers with Low Standby Current Features The MAX4843–MAX4846 overvoltage protection controllers protect low-voltage systems against high-voltage faults of up to 28V. When the input voltage exceeds the overvoltage threshold, these devices turn off a low-cost, external n-channel FET(s) to prevent damage to the protected components. An internal charge pump eliminates the need for external capacitors and drives the FET gate for a simple, robust solution. The overvoltage trip level is set to 7.4V (MAX4843), 6.35V (MAX4844), 5.8V (MAX4845), or 4.65V (MAX4846). When the input voltage drops below the undervoltage lockout (UVLO) threshold, the devices enter a low standby current mode (10µA). The MAX4843/MAX4844/ MAX4845 have a UVLO threshold of 4.15V, and the MAX4846 has a UVLO threshold of 2.5V. In addition to the single FET configuration, the devices can be configured with back-to-back external FETs to prevent currents from being back-driven into the adapter. An additional feature includes a ±15kV ESD-protected input when bypassed with a 1µF capacitor to ground. All devices are offered in a small (1.5mm x 1.0mm) 6-pin µDFN package and are specified for operation over the -40°C to +85°C temperature range. ♦ Overvoltage Protection Up to 28V ♦ Preset 7.4V, 6.35V, 5.8V, or 4.65V Overvoltage Trip Level ♦ Low (10µA) Undervoltage Lockout Standby Current ♦ Drives Low-Cost n MOSFET ♦ ♦ ♦ ♦ Internal 50ms Startup Delay Internal Charge Pump Overvoltage Fault FLAG Indicator 6-Pin (1.5mm x 1.0mm) µDFN Package Ordering Information PART* PINPACKAGE UVLO (V) OVLO (V) TOP MARK MAX4843ELT 6 µDFN 4.15 7.40 BE MAX4844ELT 6 µDFN 4.15 6.35 BF MAX4845ELT 6 µDFN 4.15 5.80 BG MAX4846ELT 6 µDFN 2.50 4.65 BH *All devices are specified over the -40°C to +85°C temperature range. Applications Cell Phones Digital Still Cameras PDAs and Palmtop Devices MP3 Players Pin Configuration Typical Operating Circuit TOP VIEW INPUT +1.2V TO +28V N OUTPUT IN 1 1 GATE IN 4 GND 2 1µF MAX4843– MAX4846 6 N.C. 5 N.C. 4 GATE VIO MAX4843– MAX4846 2 GND FLAG FLAG 3 3 µDFN ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX4843–MAX4846 General Description MAX4843–MAX4846 Overvoltage Protection Controllers with Low Standby Current ABSOLUTE MAXIMUM RATINGS IN to GND ..............................................................-0.3V to +30V GATE to GND ........................................................-0.3V to +12V FLAG to GND ..........................................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C) 6-Pin µDFN (derate 2.1mW/°C above +70°C) .........167.7mW Operating Temperature Range ..........................-40°C to +85°C Junction Temperature .................................................... +150°C Storage Temperature Range ............................-65°C to +150°C Lead Temperature (soldering, 10s) ................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, CGATE = 500pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER Input Voltage Range Undervoltage Lockout Threshold SYMBOL UVLO Undervoltage Lockout Hysteresis Overvoltage Trip Level OVLO Overvoltage Lockout Hysteresis IN Supply Current CONDITIONS VIN IIN UVLO Supply Current IUVLO Gate Voltage VGATE VIN falling UNITS 28.0 V MAX4843/MAX4844/MAX4845 3.9 4.15 4.4 2.3 2.5 2.7 MAX4843/MAX4844/MAX4845 41 MAX4846 25 VIN rising MAX MAX4846 7.0 7.4 7.8 MAX4844 6.0 6.35 6.7 MAX4845 5.5 5.8 6.1 MAX4846 4.35 4.65 4.95 MAX4843 75 MAX4844 65 MAX4845 55 MAX4846 50 70 120 MAX4846 VIN = 3.8V MAX4843/MAX4844/MAX4845 60 10 110 22 VIN = 2.2V MAX4846 8 18 MAX4843/MAX4844/MAX4845 MAX4846 IPD VIN > OVLO, VGATE = 5.5V VOL ISINK = 1mA, FLAG deasserted 9 9.83 10 7.5 7.85 8.0 10 27 VFLAG = 5.5V, FLAG asserted _______________________________________________________________________________________ V mV MAX4843/MAX4844/MAX4845 1µA load V mV MAX4843 FLAG Output Low Voltage 2 TYP 1.2 GATE Pulldown Current FLAG Leakage Current MIN µA µA V mA 0.4 V 1 µA Overvoltage Protection Controllers with Low Standby Current (VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, CGATE = 500pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING Startup Delay tSTART VIN = UVLO rising to VGATE = 0.3V rising (Figure 1) 20 50 80 ms FLAG Blanking Time tBLANK VGATE = 0.3V rising to VFLAG = 0.3V falling (Figure 1) 20 50 80 ms tGON VGATE = 0.3V to 8V (MAX4843/MAX4844/MAX4845), VGATE = 0.3V to 7V (MAX4846) (Figure 1) 10 tGOFF VIN rising at 1V/µs from 5V to 8V (MAX4843/MAX4844/MAX4845) or from 4V to 7V (MAX4846) to VGATE = 0.3V (Figure 2) 6 FLAG Assertion Delay tFLAG VIN rising at 1V/µs from 5V to 8V (MAX4843/MAX4844/MAX4845) or from 4V to 7V (MAX4846), to VFLAG = 2.4V, RFLAG = 10kΩ to 3V (Figure 2) 5.8 µs Initial Overvoltage Fault Delay tOVP VIN rising at 1V/µs from 0V to 9V, time from VIN = 5V to IGATE = 80% of IPD (Figure 3) 1.5 µs Gate Turn-On Time Gate Turn-Off Time ms 20 µs Note 1: All devices are 100% tested at +25°C. Electrical limits across the full temperature range are guaranteed by design and correlation. Typical Operating Characteristics (VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, TA = +25°C, unless otherwise noted.) 40 100 10 1 SINGLE FET 0.1 0.01 BACK-TO-BACK FET 0.001 0.0001 20 MAX4843 MAX4844 12 GATE VOLTAGE (V) 60 15 MAX4843-46 toc02 SUPPLY CURRENT (µA) 80 1000 REVERSE CURRENT (µA) MAX4843-46 toc01 100 GATE VOLTAGE vs. INPUT VOLTAGE (MAX4843/MAX4844/MAX4845) REVERSE CURRENT vs. OUTPUT VOLTAGE (MAX4843) MAX4843-46 toc03 SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX4843) MAX4845 9 6 3 0.00001 0 0 0.000001 0 5 10 15 20 SUPPLY VOLTAGE (V) 25 30 1 2 4 3 5 6 OUTPUT VOLTAGE (V) 7 3 4 5 6 7 8 INPUT VOLTAGE (V) _______________________________________________________________________________________ 3 MAX4843–MAX4846 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (VIN = +5V for MAX4843/MAX4844/MAX4845, VIN = +4V for MAX4846, TA = +25°C, unless otherwise noted.) GATE VOLTAGE vs. INPUT VOLTAGE (MAX4846) GATE VOLTAGE vs. INPUT VOLTAGE (MAX4843) 6 4 MAX4843-46 toc06 5V/DIV VIN 0 VGATE 5V/DIV 10.00 0 GATE CURRENT = 1µA 9.75 2 MAX4843-46 toc05 GATE CURRENT = 0 10.25 GATE VOLTAGE (V) 8 POWER-UP RESPONSE 10.50 MAX4843-46 toc04 10 GATE VOLTAGE (V) MAX4843–MAX4846 Overvoltage Protection Controllers with Low Standby Current VFLAG 5V/DIV 0 0 9.50 1 2 3 4 5 6 3 INPUT VOLTAGE (V) 4 5 6 7 20ms/DIV 8 INPUT VOLTAGE (V) POWER-UP RESPONSE OVERVOLTAGE RESPONSE MAX4843-46 toc07 POWER-UP OVERVOLTAGE RESPONSE MAX4843-46 toc08 MAX4843-46 toc09 8V 5V/DIV VIN VIN 5V/DIV 0 5V/DIV VGATE VOUT 0 1A/DIV IGATE VGATE 0 5V/DIV VFLAG 2V/DIV 0 VFLAG 5V/DIV 0 5V/DIV 0 20ms/DIV 5V/DIV 0 10mA/DIV 0 VFLAG VIN 10V/DIV 0 IIN 8V 0 0 4µs/DIV 20µs/DIV Pin Description 4 PIN NAME FUNCTION 1 IN 2 GND Ground 3 FLAG Fault Indication Output. FLAG is asserted high during undervoltage lockout and overvoltage lockout conditions. FLAG is deasserted during normal operation. FLAG is an open-drain output. 4 GATE Gate-Drive Output. GATE is the output of an on-chip charge pump. When VUVLO < VIN < VOVLO, GATE is driven high to turn on the external n-channel MOSFET(s). 5, 6 N.C. Voltage Input. IN is both the power-supply input and the overvoltage sense input. Bypass IN to GND with a 1µF capacitor or larger. No Connection. Not internally connected. _______________________________________________________________________________________ Overvoltage Protection Controllers with Low Standby Current 5.5V REGULATOR IN 2x CHARGE PUMP GATE GATE DRIVER GND UVLO AND OVLO DETECTOR MAX4843– MAX4846 CONTROL LOGIC AND TIMER FLAG 5V VIN VIN VUVLO VOVLO 5V tGON tFLAG tGOFF 8V tSTART VGATE VGATE 0.3V 0.3V VFLAG tBLANK Figure 1. Startup Timing Diagram VIN 0.3V VFLAG 2.4V Figure 2. Shutdown Timing Diagram VOVLO 0V tOVP 80% IGATE Figure 3. Power-Up Overvoltage Timing Diagram _______________________________________________________________________________________ 5 MAX4843–MAX4846 Functional Diagram MAX4843–MAX4846 Overvoltage Protection Controllers with Low Standby Current Detailed Description The MAX4843–MAX4846 provide up to 28V overvoltage protection for low-voltage systems. When the input voltage exceeds the overvoltage trip level, the MAX4843–MAX4846 turn off a low-cost external n-channel FET(s) to prevent damage to the protected components. An internal charge pump (see the Functional Diagram) drives the FET gate for a simple, robust solution. On power-up, the device waits for 50ms before driving GATE high. The open-drain FLAG output is kept at high impedance for an additional 50ms after GATE goes high before deasserting. The FLAG output asserts high immediately to an overvoltage fault. Undervoltage Lockout (UVLO) The MAX4843/MAX4844/MAX4845 have a fixed 4.15V typical UVLO level, while the MAX4846 has a 2.5V typical UVLO. When VIN is less than the UVLO, the GATE driver is held low and FLAG is asserted. Device Operation The MAX4843–MAX4846 have an on-board state machine to control device operation. A flowchart is shown in Figure 4. On initial power-up, if VIN < UVLO or if VIN > OVLO, GATE is held at 0V, and FLAG is high. If UVLO < VIN < OVLO, the device enters startup after a 50ms internal delay. The internal charge pump is enabled, and GATE begins to be driven above VIN by the internal charge pump. FLAG is held high during startup until the FLAG blanking period expires, typically 50ms after the GATE starts going high. At this point the device is in its on state. At any time if VIN drops below UVLO or VIN is greater than OVLO, FLAG is driven high and GATE is driven to ground. STANDBY GATE = 0 FLAG = HIGH Overvoltage Lockout (OVLO) The MAX4843 has a 7.4V typical OVLO; the MAX4844 has a 6.35V typical OVLO; and the MAX4845 has a 5.8V typical OVLO. The MAX4846 has a 4.65V typical overvoltage threshold. When VIN is greater than OVLO, the GATE driver is held low and FLAG is asserted. VIN > UVLO VIN < UVLO TIME STARTS COUNTING FLAG Output The open-drain FLAG output is used to signal to the host system that there is a fault with the input voltage. FLAG asserts immediately to an overvoltage fault. FLAG is held high for 50ms after GATE turns on before deasserting. Connect a pullup resistor from FLAG to the logic I/O voltage of the host system. t = 50ms OVLO CHECK GATE = 0 FLAG = HIGH VIN < OVLO GATE Driver An on-chip charge pump is used to drive GATE above IN, allowing the use of low-cost n-channel MOSFETs. The charge pump operates from the internal 5.5V regulator. The actual GATE output voltage tracks approximately two times VIN until VIN exceeds 5.5V or the OVLO trip level is exceeded, whichever comes first. The MAX4843 has a 7.4V typical OVLO, therefore GATE remains relatively constant at about 10.5V for 5.5V < VIN < 7.4V. The MAX4845 has a 5.8V typical OVLO, but this can be as low as 5.5V. The GATE output voltage as a function of input voltage is shown in the Typical Operating Characteristics. 6 VIN > OVLO STARTUP GATE DRIVEN HIGH FLAG = HIGH t = 50ms ON GATE HIGH FLAG = LOW Figure 4. State Diagram _______________________________________________________________________________________ Overvoltage Protection Controllers with Low Standby Current MAX4843–MAX4846 Applications Information MOSFET Configuration The MAX4843–MAX4846 can be used with either a single MOSFET configuration as shown in the Typical Operating Circuit, or can be configured with a back-toback MOSFET as shown in Figure 5. The back-to-back configuration has almost zero reverse current when the input supply is below the output. If reverse current leakage is not a concern, a single MOSFET can be used. This approach has half the loss of the back-to-back configuration when used with similar MOSFET types and is a lower cost solution. Note that if the input is actually pulled low, the output is also pulled low due to the parasitic body diode in the MOSFET. If this is a concern, the back-to-back configuration should be used. In a typical application of the MAX4846, an external adapter with built-in battery charger is connected to IN and a battery is connected to the source of the external FET. When the adapter is unplugged, IN is directly connected to the battery through the external FET. Since the battery voltage is typically greater than 3V, the GATE voltage stays high and the device remains powered by the battery. MOSFET Selection The MAX4843–MAX4846 are designed for use with either a single n-channel MOSFET or dual back-to-back n-channel MOSFETs. In most situations, MOSFETs with RDS(ON) specified for a VGS of 4.5V work well. If the input supply is near the UVLO maximum of 3.5V, consider using a MOSFET specified for a lower VGS voltage. Also the VDS should be 30V for the MOSFET to withstand the full 28V IN range of the MAX4843–MAX4846. Table 1 shows a selection of MOSFETs appropriate for use with the MAX4843–MAX4846. INPUT +1.2V TO +28V N 1 GATE IN N 4 1µF VIO MAX4843– MAX4846 2 GND FLAG 3 Figure 5. Back-to-Back External MOSFET Configuration IN Bypass Considerations For most applications, bypass IN to GND with a 1µF ceramic capacitor. If the power source has significant inductance due to long lead length, take care to prevent overshoots due to the LC tank circuit and provide protection if necessary to prevent exceeding the 30V absolute maximum rating on IN. The MAX4843–MAX4846 provide protection against voltage faults up to 28V, but this does not include negative voltages. If negative voltages are a concern, connect a Schottky diode from IN to GND to clamp negative input voltages. ESD Test Conditions ESD performance depends on a number of conditions. The MAX4843–MAX4846 are protected from ±15kV typical ESD on IN when IN is bypassed to ground with a 1µF ceramic capacitor. Table 1. MOSFET Suggestions PART CONFIGURATION/ PACKAGE VDS MAX (V) RON at 4.5V (mΩ) Si5902DC Dual/1206-8 30 143 Si1426DH Single/SSOT-6 30 115 FDC6561AN Dual/SSOT-6 30 145 FDC6305N Dual/SSOT-6 20 80 FDG315N Single/SC70-6 30 160 MANUFACTURER Vishay Siliconix www.vishay.com Fairchild Semiconductor www.fairchildsemi.com _______________________________________________________________________________________ 7 Human Body Model Figure 6 shows the Human Body Model and Figure 7 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the device through a 1.5kΩ resistor. IEC 1000-4-2 Since January 1996, all equipment manufactured and/or sold in the European Union has been required to meet the stringent IEC 1000-4-2 specification. The IEC 1000-4-2 standard covers ESD testing and performance of finished equipment; it does not specifically refer to integrated circuits. The MAX4843–MAX4846 RC 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF help users design equipment that meets Level 3 of IEC 1000-4-2, without additional ESD-protection components. The main difference between tests done using the Human Body Model and IEC 1000-4-2 is higher peak current in IEC 1000-4-2. Because series resistance is lower in the IEC 1000-4-2 ESD test model (Figure 8), the ESD withstand voltage measured to this standard is generally lower than that measured using the Human Body Model. Figure 9 shows the current waveform for the ±8kV IEC 1000-4-2 Level 4 ESD Contact Discharge test. The Air-Gap test involves approaching the device with a charger probe. The Contact Discharge method connects the probe to the device before the probe is energized. RD 1.5Ω RC 50Ω to 100Ω DISCHARGE RESISTANCE CHARGE-CURRENTLIMIT RESISTOR DEVICE UNDER TEST STORAGE CAPACITOR Figure 6. Human Body ESD Test Model IP 100% 90% Ir HIGHVOLTAGE DC SOURCE Cs 150pF RD 330Ω DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 8. IEC 1000-4-2 ESD Test Model I 100% 90% PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) IPEAK MAX4843–MAX4846 Overvoltage Protection Controllers with Low Standby Current AMPERES 36.8% 10% 10% 0 0 tRL TIME tDL CURRENT WAVEFORM Figure 7. Human Body Model Current Waveform 8 tr = 0.7ns to 1ns 30ns t 60ns Figure 9. IEC 1000-4-2 ESD Generator Current Waveform _______________________________________________________________________________________ Overvoltage Protection Controllers with Low Standby Current PROCESS TECHNOLOGY: BiCMOS Package Information 6L UDFN.EPS (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 3 e A b 5 4 6 TOPMARK 2 PIN 1 0.075x45¡ AAA PIN 1 INDEX AREA L2 L E 3 1 A1 D SIDE VIEW TOP VIEW 1 A BOTTOM VIEW b SECTION A-A 2 A L1 COMMON DIMENSIONS MIN. 0.64 -1.45 0.95 0.30 --0.17 A A1 D E L L1 L2 b e NOM. 0.72 0.20 1.50 1.00 0.35 --0.20 0.50 BSC. MAX. 0.80 -1.55 1.05 0.40 0.08 0.05 0.23 TITLE: PACKAGE OUTLINE, 6L uDFN, 1.5x1.0x0.8mm APPROVAL DOCUMENT CONTROL NO. 21-0147 -DRAWING NOT TO SCALE- REV. C 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. MAX4843–MAX4846 Chip Information