MAXIM MAX1458CAE

19-1373; Rev 0; 5/98
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Features
♦ Medium Accuracy (±1%), Single-Chip Sensor
Signal Conditioning
♦ Sensor Errors Trimmed Using Correction
Coefficients Stored in Internal EEPROM—
Eliminates the Need for Laser Trimming and
Potentiometers
♦ Compensates Offset, Offset-TC, FSO, FSOTC,
FSO Linearity
♦ Programmable Current Source (0.1mA to 2.0mA)
for Sensor Excitation
♦ Fast Signal-Path Settling Time (<1ms)
♦ Accepts Sensor Outputs from 10mV/V to 40mV/V
♦ Fully Analog Signal Path
• Pretest: Data acquisition of sensor performance
under the control of a host test computer.
• Calibration and compensation: Computation and
storage (in an internal EEPROM) of calibration and
compensation coefficients computed by the test
computer and downloaded to the MAX1458.
• Final test operation: Verification of transducer calibration and compensation without removal from the
pretest socket.
Although optimized for use with piezoresistive sensors,
the MAX1458 may also be used with other resistive
sensors (i.e., accelerometers and strain gauges) with
some additional external components.
Ordering Information
PART
TEMP. RANGE
0°C to +70°C
16 SSOP
MAX1458C/D
MAX1458AAE
0°C to +70°C
-40°C to +125°C
Dice*
16 SSOP
*Dice are tested at TA = +25°C, DC parameters only.
Functional Diagram appears at end of data sheet.
Pin Configuration
______________________Customization
Maxim can customize the MAX1458 for unique requirements. With a dedicated cell library consisting of more
than 90 sensor-specific functional blocks, Maxim can
quickly provide customized MAX1458 solutions. Please
contact Maxim for further information.
________________________Applications
Piezoresistive Pressure and Acceleration
Transducers and Transmitters
MAP (Manifold Absolute Pressure) Sensors
Automotive Systems
Hydraulic Systems
PIN-PACKAGE
MAX1458CAE
TOP VIEW
16 LIMIT
SCLK 1
15 VDD
CS 2
14 INP
I.C. 3
TEMP 4
MAX1458
13 BDRIVE
FSOTC 5
12 INM
DIO 6
11 I.C.
WE 7
10 OUT
VSS 8
9
ISRC
Industrial Pressure Sensors
SSOP
________________________________________________________________ Maxim Integrated Products
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
1
MAX1458
General Description
The MAX1458 highly integrated analog-sensor signal
processor is optimized for piezoresistive sensor calibration and compensation without any external components. It includes a programmable current source for
sensor excitation, a 3-bit programmable-gain amplifier
(PGA), a 128-bit internal EEPROM, and four 12-bit
DACs. Achieving a total error factor within 1% of the
sensor’s repeatability errors, the MAX1458 compensates offset, offset temperature coefficient, full-span
output (FSO), FSO temperature coefficient (FSOTC),
and FSO nonlinearity of silicon piezoresistive sensors.
The MAX1458 calibrates and compensates first-order
temperature errors by adjusting the offset and span of
the input signal via digital-to-analog converters (DACs),
thereby eliminating quantization noise. Built-in testability features on the MAX1458 result in the integration of
three traditional sensor-manufacturing operations into
one automated process:
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD to VSS......................................-0.3V to +6V
All Other Pins ...................................(VSS - 0.3V) to (VDD + 0.3V)
Short-Circuit Duration, FSOTC, OUT, BDRIVE ...........Continuous
Continuous Power Dissipation (TA = +70°C)
SSOP (derate 8.00mW/°C above +70°C) .....................640mW
Operating Temperature Ranges
MAX1458CAE ......................................................0°C to +70°C
MAX1458AAE .................................................-40°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V, VSS = 0, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.5
5.0
5.5
V
3
6
mA
GENERAL CHARACTERISTICS
Supply Voltage
VDD
Supply Current
IDD
(Note 1)
ANALOG INPUT (PGA)
Input Impedance
RIN
Input-Referred Offset Tempco
1
MΩ
±0.5
µV/°C
0.01
%VDD
63% of final value
1
ms
From VSS to VDD
90
dB
±150
mV
10 to 40
mV/V
(Notes 2, 3)
Amplifier Gain Nonlinearity
Output Step Response
Common-Mode Rejection Ratio
CMRR
Input-Referred Adjustable Offset
Range
At minimum gain (Note 4)
Input-Referred Adjustable FSO
Range
(Note 5)
ANALOG OUTPUT (PGA)
Differential Signal-Gain Range
Selectable in eight steps
Minimum Differential Signal Gain
TA = TMIN to TMAX
41 to 230
36
Differential Signal-Gain Tempco
VLIMIT = 4.6V
VDD - 0.25
10kΩ load to VSS
or VDD
VSS + 0.25
VLIMIT ± 0.3
No load
VSS + 0.1
VLIMIT ± 0.2
VLIMIT = 4.6V,
VOUT = (VSS + 0.25V) to (VLIMIT - 0.3V)
Output Noise
DC to 10Hz (gain = 41,
source impedance = 5kΩ)
V/V
ppm/°C
VSS + 0.15
Output Current Range
2
V/V
45
±50
VLIMIT = 5.0V, no load
Output Voltage Swing
41
-0.45
(sink)
0.45
(source)
500
_______________________________________________________________________________________
V
mA
µVRMS
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
MAX1458
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V, VSS = 0, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
0.1
0.5
MAX
UNITS
2.0
mA
CURRENT SOURCE
Bridge Current Range
IBDRIVE
Bridge Voltage Swing
VBDRIVE
VSS + 1.3
VDD - 1.3
V
VISRC
VSS + 1.3
VDD - 1.3
V
Reference Input Voltage Range
(ISRC)
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
12
Differential Nonlinearity
DNL
Offset DAC Bit Weight
∆VOUT
∆Code
Offset TC DAC Bit Weight
FSO DAC Bit Weight
FSO TC DAC Bit Weight
Bits
±1.5
LSB
DAC reference = VDD = 5.0V
2.8
mV/bit
∆VOUT
∆Code
DAC reference = VBDRIVE = 2.5V
1.4
mV/bit
∆VISRC
∆Code
DAC reference = VDD = 5.0V
1.22
mV/bit
DAC reference = VBDRIVE = 2.5V
0.6
mV/bit
∆VFSOTC
∆Code
IRO DAC
DAC Resolution
DAC Bit Weight
Input referred, VDD = 5V (Note 6)
3
Bits
9
mV/bit
FSOTC BUFFER
Output Voltage Swing
No load
Current Drive
VFSOTC = 2.5V
VSS + 0.3
VDD - 1.3
-20
20
V
µA
INTERNAL RESISTORS
Current-Source Reference
Resistor
RISRC
75
kΩ
FSO Trim Resistor
RFTC
75
kΩ
100
kΩ
Temperature-Dependent
Resistor
RTEMP
Typically 4600ppm/°C tempco
Excludes the sensor or load current.
All electronics temperature errors are compensated together with sensor errors.
The sensor and the MAX1458 must always be at the same temperature during calibration and use.
This is the maximum allowable sensor offset.
This is the sensor’s sensitivity normalized to its drive voltage, assuming a desired full-span output of 4V and a bridge
voltage of 2.5V.
Note 6: Bit weight is ratiometric to VDD.
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
_______________________________________________________________________________________
3
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
MAX1458
Pin Description
PIN
NAME
FUNCTION
1
SCLK
Data Clock Input. Used only during programming/testing. Internally pulled to VSS with a 1MΩ (typical) resistor. Data is clocked in on the rising edge of the clock. The maximum SCLK frequency is 10kHz.
2
CS
Chip-Select Input. The MAX1458 is selected when this pin is high. When low, OUT and DIO become high
impedance. Internally pulled to VDD with a 1MΩ (typical) resistor. Leave unconnected for normal operation.
3, 11
I.C.
Internally Connected. Leave unconnected.
4
TEMP
5
FSOTC
6
DIO
Data Input/Output. Used only during programming/testing. Internally pulled to VSS with a 1MΩ (typical)
resistor. High impedance when CS is low.
7
WE
Dual-Function Input Pin. Used to enable EEPROM erase/write operations. Also used to set the DAC refreshrate mode. Internally pulled to VDD with a 1MΩ (typical) resistor. Refer to the Chip-Select (CS) and WriteEnable (WE) section.
8
VSS
Negative Power-Supply Input
9
ISRC
Current-Source Reference. An internal 75kΩ resistor (RISRC) connects ISRC to VSS (see Functional
Diagram). Optionally, external resistors can be used in place of or in parallel with RFTC and RISRC.
10
OUT
PGA Output Voltage
12
INM
Negative Sensor Input. Input impedance >1MΩ. Rail-to-rail input range.
13
BDRIVE
Sensor Excitation Current Output. This current source drives the bridge.
14
INP
Positive Sensor Input. Input impedance >1MΩ. Rail-to-rail input range.
15
VDD
Positive Power-Supply Input. Connect a 0.1µF capacitor from VDD to VSS.
16
LIMIT
Temperature Sensor Output. An internal temperature sensor (a 100kΩ, 4600ppm/°C TC resistor) which can
provide a temperature-dependent voltage.
Buffered FSOTC DAC Output. An internal 75kΩ resistor (RFTC) connects FSOTC to ISRC (see Functional
Diagram). Optionally, external resistors can be used in place of or in parallel with RFTC and RISRC.
Voltage Limit Input. This pin sets the maximum voltage at OUT. If left unconnected, the output voltage will be
limited to 4.6V (VDD = 5V). Connect to VDD for maximum output swing. The acceptable range is 4.5V ≤
VLIMIT ≤ VDD.
_______________Detailed Description
The MAX1458 provides an analog amplification path for
the sensor signal. Calibration and temperature compensation are achieved by varying the offset and gain
of a programmable-gain amplifier (PGA) and by varying
the sensor bridge current. The PGA uses a switchedcapacitor CMOS technology, with an input-referred
coarse offset trimming range of approximately ±63mV
(9mV steps). An additional output-referred fine offset
trim is provided by the Offset DAC (approximately
2.8mV steps). The PGA provides eight gain values from
+41V/V to +230V/V. The bridge current source is programmable from 0.1mA to 2mA.
The MAX1458 uses four 12-bit DACs and one 3-bit
DAC, with calibration coefficients stored by the user in
4
an internal 128-bit EEPROM. This memory contains the
following information as 12-bit-wide words:
• Configuration register
• Offset calibration coefficient
• Offset temperature error compensation coefficient
• FSO (full-span output) calibration coefficient
• FSO temperature error compensation coefficient
• 24 user-defined bits for customer programming of
manufacturing data (e.g., serial number and date)
Figure 1 shows a typical pressure-sensor output and
defines the offset, full-scale, and full-span output values
as a function of voltage.
_______________________________________________________________________________________
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
FSOTC compensation is accomplished by resistor
RFTC and the FSOTC DAC, which modulate the excitation reference current at ISRC as a function of temperature (Figure 3). FSO DAC sets V ISRC and remains
constant with temperature while the voltage at FSOTC
varies with temperature. FSOTC is the buffered output
of the FSOTC DAC. The reference DAC voltage is
VBDRIVE, which is temperature dependent. The FSOTC
DAC alters the tempco of the current source. When the
tempco of the bridge voltage is equal in magnitude and
opposite in polarity to the TCS, the FSOTC errors are
compensated and FSO will be constant with temperature.
OFFSET TC Compensation
Compensating offset TC errors involves first measuring
the uncompensated offset TC error, then determining
the percentage of the temperature-dependent voltage
VBDRIVE that must be added to the output summing
junction to correct the error. Use the Offset TC DAC to
adjust the amount of BDRIVE voltage that is added to
the output summing junction (Figure 2).
Analog Signal Path
The fully differential analog signal path consists of four
stages:
• Front-end summing junction for coarse offset correction
• 3-bit PGA with eight selectable gains ranging from
41 through 230
• Three-input-channel summing junction
• Differential to single-ended output buffer (Figure 2)
Coarse Offset Correction
The sensor output is first fed into a differential summing
junction (INM (negative input) and INP (positive input))
with a CMRR > 90dB, an input impedance of approximately 1MΩ, and a common-mode input voltage range
from VSS to VDD. At this summing junction, a coarse offset-correction voltage is added, and the resultant voltage is fed into the PGA. The 3-bit (plus sign)
input-referred Offset DAC (IRO DAC) generates the
coarse offset-correction voltage. The DAC voltage reference is 1.25% of VDD; thus, a VDD of 5V results in a
front-end offset-correction voltage ranging from -63mV
to +63mV, in 9mV steps (Table 1). To add an offset to
the input signal, set the IRO sign bit high; to subtract an
offset from the input signal, set the IRO sign bit low.
The IRO DAC bits (C2, C1, C0, and IRO sign bit) are
programmed in the configuration register (see Internal
EEPROM section).
1.25% VDD
4.5
BDRIVE
SOTC
OFFTC
DAC
IRO
DAC
A2 A1 A0
±
A = 2.3
LIMIT
VOLTAGE (V)
FULL-SPAN OUTPUT (FSO)
INP
FULL-SCALE (FS)
INM
Σ
Σ
PGA
A = 2.3
A=1
OUT
±
0.5
VDD
OFFSET
PMIN
PMAX
PRESSURE
Figure 1. Typical Pressure-Sensor Output
Offset
DAC
SOFF
Figure 2. Signal-Path Block Diagram
_______________________________________________________________________________________
5
MAX1458
FSOTC Compensation
Silicon piezoresistive transducers (PRTs) exhibit a large
positive input resistance tempco (TCR) so that, while
under constant current excitation, the bridge voltage
(V BDRIVE ) increases with temperature. This dependence of VBDRIVE on the sensor temperature can be
used to compensate the sensor temperature errors.
PRTs also have a large negative full-span output sensitivity tempco (TCS) so that, with constant voltage excitation, full-span output (FSO) will decrease with
temperature, causing a full-span output temperature
coefficient (FSOTC) error. However, if the bridge voltage can be made to increase with temperature at the
same rate that TCS decreases with temperature, the
FSO will remain constant.
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Table 1. Input-Referred Offset DAC
Correction Values
Table 2. PGA Gain Settings and IRO DAC
Step Size
OFFSET
CORRECTION AT
VDD = 5V
(mV)
PGA
VALUE
A2
A1
A0
PGA
GAIN
(V/V)
OUTPUTREFERRED IRO
DAC STEP SIZE
(VDD = 5V) (V)
VALUE
SIGN
C2
C1
C0
OFFSET
CORRECTION
% of VDD
(%)
0
0
0
0
41
0.369
+7
1
1
1
1
+1.25
+63
1
0
0
1
68
0.612
+6
1
1
1
0
+1.08
+54
2
0
1
0
95
0.855
+5
1
1
0
1
+0.90
+45
3
0
1
1
122
1.098
+4
1
1
0
0
+0.72
+36
4
1
0
0
149
1.341
+3
1
0
1
1
+0.54
+27
5
1
0
1
176
1.584
+2
1
0
1
0
+0.36
+18
6
1
1
0
203
1.827
+1
1
0
0
1
+0.18
+9
7
1
1
1
230
2.070
+0
1
0
0
0
0
0
-0
0
0
0
0
0
0
-1
0
0
0
1
-0.18
-9
-2
0
0
1
0
-0.36
-18
-3
0
0
1
1
-0.54
-27
-4
0
1
0
0
-0.72
-36
-5
0
1
0
1
-0.90
-45
-6
0
1
1
0
-1.08
-54
-7
0
1
1
1
-1.25
-63
IRO DAC
Output Buffer
OUT can drive 0.1µF of capacitance. If CS is brought
low, OUT becomes high impedance (resulting in typical
output impedance of 1MΩ). The output is current limited and can be shorted to either VDD or VSS indefinitely.
The maximum output voltage can be limited using the
LIMIT pin. Output limiting can be performed for sensor
diagnostic purposes. Connect LIMIT to VDD to disable
the voltage-limiting feature.
Bridge Drive
Programmable-Gain Amplifier
The programmable-gain amplifier (PGA), which is used
to set the coarse FSO, uses a switched-capacitor
CMOS technology and contains eight selectable gain
levels from 41 to 230, in increments of 27 (Table 2). The
output of the PGA is fed to the output summing junction. The three PGA gain bits A2, A1, and A0 are stored
in the configuration register.
Output Summing Junction
The third stage in the analog signal path consists of a
summing junction for the PGA output, offset correction,
and the offset TC correction. Both the offset and the offset TC correction voltages are gained by a factor of 2.3
before being fed into the summing junction, increasing
the offset and offset TC correction range. The offset
sign bit and offset TC sign bit are stored in the configuration register. The offset sign bit determines if the offset correction voltage is added to (sign bit is high) or
subtracted from (sign bit is low) the PGA output.
Negative offset TC errors require a logic high for the
offset TC sign bit. Alternately, positive offset TC errors
dictate a logic low for the offset TC sign bit. The output
of the summing junction is fed to the output buffer.
6
Fine FSO correction is accomplished by varying the
sensor excitation current with the 12-bit FSO DAC
(Figure 3). Sensor bridge excitation is performed by a
programmable current source capable of delivering up
to 2mA. The reference current at ISRC is established by
resistor RISRC and by the voltage at node ISRC (controlled by the FSO DAC). The reference current flowing
through this pin is multiplied by a current mirror (AA ≅
14) and then made available at BDRIVE for sensor excitation. Modulation of this current with respect to temperature can be used to correct FSOTC errors, while
modulation with respect to the output voltage (VOUT)
can be used to correct FSO linearity errors.
Digital-to-Analog Converters
The four 12-bit, sigma-delta DACs typically settle in
less than 100ms. The four DACs have a corresponding
memory register in EEPROM for storage of correction
coefficients.
Use the FSO DAC for fine FSO adjustments. The FSO
DAC takes its reference from VDD and controls VISRC
which, in conjunction with RISRC, sets the baseline sensor excitation current. The Offset DAC also takes its reference from VDD and provides a 1.22mV resolution with
_______________________________________________________________________________________
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
MAX1458
VDD
VDD
FSO
DAC
I = IISRC
AA ≈ 14IISRC = IBDRIVE
ISRC
BDRIVE
FSOTC
DAC
FSOTC
RFTC
RISRC
EXTERNAL
SENSOR
Figure 3. Bridge Excitation Circuit
a VDD of 5V. The output of the Offset DAC is fed into
the output summing junction where it is gained by
approximately 2.3, which increases the resulting output-referred offset correction resolution to 2.8mV.
Both the Offset TC and FSOTC DACs take their reference from BDRIVE, a temperature-dependent voltage. A
nominal VBDRIVE of 2.5V results in a step size of 0.6mV.
The Offset TC DAC output is fed into the output summing junction where it is gained by approximately 2.3,
thereby increasing the Offset TC correction range. The
buffered FSOTC DAC output is available at FSOTC and
is connected to ISRC via RFTC to correct FSOTC errors.
Internal Resistors
The MAX1458 contains three internal resistors (RISRC,
RFTC, and RTEMP) optimized for common silicon PRTs.
RISRC (in conjunction with the FSO DAC) programs the
nominal sensor excitation current. RFTC (in conjunction
with the FSOTC DAC) compensates the FSOTC errors.
Both RISRC and RFTC have a nominal value of 75kΩ. If
external resistors are used, RISRC and RFTC can be disabled by resetting the appropriate bit (address 07h
reset to zero) in the configuration register (Table 3).
R TEMP is a high-tempco resistor with a TC of
+4600ppm/°C and a nominal resistance of 100kΩ at
+25°C. This resistor can be used with certain sensor
types that require an external temperature sensor.
Table 3. Configuration Register
EEPROM
ADDRESS (hex)
DESCRIPTION
00h
Offset TC Sign Bit, SOTC
01h
Offset Sign Bit, SOFF
02h
PGA Gain (MSB), A2
03h
PGA Gain, A1
04h
PGA Gain (LSB), A0
05h
Reserved “0”
06h
Reserved “0”
07h
Internal Resistor (RFTC and RISRC)
Selection
08h
Input-Referred Offset (IRO) Sign Bit
09h
Input-Referred Offset (MSB)
0Ah
Input-Referred Offset
0Bh
Input-Referred Offset (LSB)
Internal EEPROM
The MAX1458 has a 128-bit internal EEPROM arranged
as eight 16-bit words. The four uppermost bits for each
register are reserved. The internal EEPROM is used to
store the following (also shown in the memory map in
Table 4):
_______________________________________________________________________________________
7
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Table 4. EEPROM Memory Map
EE Address
Contents
0F
0E
0D
0C
1
0
0
0
EE Address
Contents
1F
1E
1D
1C
1B
1
0
0
1
MSB
EE Address
Contents
2F
2E
2D
2C
2B
1
0
1
0
MSB
EE Address
Contents
3F
3E
3D
3C
3B
1
0
1
1
MSB
EE Address
Contents
4F
4E
4D
4C
4B
1
1
0
0
MSB
5F
5E
5D
5C
5B
5A
59
58
57
56
55
54
53
52
51
50
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EE Address
Contents
6F
6E
6D
6C
6B
6A
69
68
67
66
65
64
63
62
61
60
0
0
0
0
EE Address
Contents
7F
7E
7D
7C
73
72
71
70
0
0
0
0
Reserved*
0B
0A
09
08
07
06
05
04
03
02
01
14
13
12
11
00
Configuration
1A
19
18
17
16
15
Offset
2A
29
28
27
26
25
24
23
22
21
Offset TC
3A
39
38
37
36
35
49
48
47
46
20
LSB
34
33
32
31
FSO
4A
10
LSB
30
LSB
45
44
43
42
41
FSOTC
40
LSB
User defined bits
7B
7A
79
78
77
76
75
74
User defined bits
= Reserved Bits
Note: The MAX1458 processes the Reserved Bits in the EEPROM. If these bits are not properly programmed, the configuration
and DAC registers will not be updated correctly.
* The contents of the Reserved EE Address 50–5F must all be reset to zero.
• Configuration register (Table 3)
• 12-bit calibration coefficients for the Offset and FSO
DACs
• 12-bit compensation coefficients for the Offset TC
and FSOTC DACs
• Two general-purpose registers available to the user
for storing process information such as serial number, batch date, and check sums
Program the EEPROM one bit at a time. The bits have
addresses from 0 to 127 (7F hex).
8
Configuration Register
The configuration register (Table 3) determines the
PGA gain, the polarity of the offset and offset TC coefficients, and the coarse offset correction (IRO DAC). It
also enables/disables internal resistors (R FTC and
RISRC).
DAC Registers
The Offset, Offset TC, FSO, and FSOTC registers store
the coefficients used by their respective calibration/
compensation DACs.
_______________________________________________________________________________________
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Chip-Select (CS) and Write-Enable (WE)
CS is used to enable OUT, control serial communication, and force an update of the configuration and DAC
registers.
In input mode (the default mode), data on DIO is
latched on each rising edge of SCLK. Therefore, data
on DIO must be stable at the rising edge of SCLK and
should transition on the falling edge of SCLK.
DIO will switch to output mode after receiving a “READ
EEPROM” command, and will return the data bit
addressed by the digital value in the “READ EEPROM”
command. After a low-to-high transition or CS, DIO
returns to input mode and is ready to accept more
commands.
• A low on CS disables serial communication and
places OUT in a high-impedance state.
• A transition from low to high on CS forces an update
of the configuration and DAC registers from the
EEPROM when the “U” bit is zero.
• A transition from high to low on CS terminates programming mode.
• A logic high on CS enables OUT and serial communication (see Communication Protocol section).
WE controls the refresh rate for the internal configuration and DAC registers from the EEPROM and enables
the erase/write operations. If communication has been
initiated (see Communication Protocol section), internal
register refresh is disabled.
Communication Protocol
To initiate communication, the first six bits on DIO after
CS transitions from low to high must be 1010U0
(defined as the INIT SEQUENCE). The MAX1458 will
then begin accepting 16-bit control words (Figure 4).
If the INIT SEQUENCE is not detected, all subsequent
data on DIO is ignored until CS again transitions from
low to high and the correct INIT SEQUENCE is received.
• A low on WE disables the erase/write operations and
also disables register refreshing from the EEPROM.
• A high on WE selects a refresh rate of approximately
400 times per second and enables EEPROM
erase/write operations.
The “U” bit of the INIT SEQUENCE controls the updating of the DACs and configuration register from the
internal EEPROM. If this bit is low (U = 0), all four internal DACs and the configuration register will be updated
from the EEPROM on the next rising edge of CS (this is
also the default on power-up). If the “U” bit is high, the
DACs and configuration register will not be updated
from the internal EEPROM; they will retain their current
value on any subsequent CS rising edge. The
MAX1458 continues to accept control words until CS is
brought low.
• It is recommended that WE be connected to V SS
after the MAX1458 EEPROM has been programmed.
SCLK (Serial Clock)
SCLK must be driven externally and is used to input
commands to the MAX1458 and read EEPROM contents. Input data on DIO is latched on the rising edge of
SCLK. Noise on SCLK may disrupt communication. In
noisy environments, place a capacitor (0.01µF)
between SCLK and VSS.
CS
16 CLK
CYCLES
tMIN = 200µs
16 CLK
CYCLES
n x 16 CLK
CYCLES
SCLK
DIO
X
1
0
1
0
U
BEGIN
PROGRAMMING
SEQUENCE
0
D0
D1 CM3 D0
CONTROL
WORD
D1 CM3
CONTROL
WORD
CONTROL
WORDS
Figure 4. Communication Sequence
_______________________________________________________________________________________
9
MAX1458
Data Input/Output (DIO)
The DIO line is an input/output pin used to issue commands to the MAX1458 (input mode) or read the
EEPROM contents (output mode).
Detailed Description of the Digital Lines
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Control Words
Table 5. MAX1458 Commands
After receiving the INIT SEQUENCE on DIO, the MAX1458
begins latching in 16-bit control words, LSB first (Figure 5).
The first 12 bits (D0–D11) represent the data field. The
last four bits of the control word (the MSBs, CM0–CM3)
are the command field. The MAX1458 supports the
commands listed in Table 5.
HEX
CM3 CM2 CM1 CM0
CODE
FUNCTION
ERASE EEPROM Command
When an ERASE EEPROM command is issued, all of
the memory locations in the EEPROM are reset to a
logic “0.” The data field of the 16-bit word is ignored.
Important: An internal charge pump develops voltages
greater than 20V for EEPROM programming operations.
The EEPROM control logic requires 50ms to erase the
EEPROM. After sending a WRITE or ERASE command,
failure to wait 50ms before issuing another command
may result in data being accidentally written to the
EEPROM. The maximum number of ERASE EEPROM
cycles should not exceed 100.
BEGIN EEPROM WRITE Command
The BEGIN EEPROM WRITE command stores a logic
high at the memory location specified by the lower
seven bits of the data field (A0–A6). The higher bits of
the data field (A7–A11) are ignored (Figure 6). Note that
to write to the internal EEPROM, WE and CS must be
ERASE EEPROM
1h
0
0
0
1
BEGIN EEPROM WRITE at
Address
2h
0
0
1
0
READ EEPROM at Address
3h
0
0
1
1
Maxim Reserved
4h
0
1
0
0
END EEPROM WRITE at
Address
5h
0
1
0
1
WRITE Data to
Configuration Register
8h
1
0
0
0
WRITE Offset DAC
9h
1
0
0
1
WRITE Offset TC DAC
Ah
1
0
1
0
WRITE FSO DAC
Bh
1
0
1
1
WRITE FSOTC DAC
Ch
1
1
0
0
No Operation
0h
0
0
0
0
Load Register
6h,
7h,
Dh,
Eh,
Fh
0
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
SCLK
DATA
COMMAND
LSB
DIO
D0
MSB LSB
D1
D2
D3
D4
D5
D6
D7
D8
D9
MSB
D10 D11 CM0 CM2 CM2 CM3
16-BIT CONFIGURATION WORD
LSB
MSB LSB
MSB
Figure 5. Control-Word Timing Diagram
CS
WE
16 CLK
CYCLES
tMIN = 200µs
16 CLK
CYCLES
n x 16 CLK
CYCLES
SCLK
DIO
X
1
0
1
0
U
INIT SEQUENCE
0
A0
A1 CM3
BEGIN
EEPROM
WRITE
A0
TWRITE
A1 CM3
END
EEPROM
WRITE
D0
tWAIT
D1 CM3
n
COMMAND
WORDS
Figure 6. Timing Diagram for WRITE EEPROM Operation
10
______________________________________________________________________________________
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
8)
9)
Wait 1ms.
Return to Step 5 until all necessary bits have been
set.
10) Read EEPROM to verify that the correct calibration/compensation coefficients have been stored.
READ EEPROM Command
The READ EEPROM command returns the bit stored at
the memory location addressed by the lower seven bits
of the data field (A0–A6). The higher bits of the data
field (A7–A11) are ignored. Note that after a read command has been issued, the DIO lines become an output and the state of the addressed EEPROM location
will be available on DIO 200µs (tREAD) after the falling
edge of the 16th SCLK cycle (Figure 8). After issuing
the READ EEPROM command, DIO returns to input
mode on the falling edge of CS. Reading the entire
EEPROM requires the READ EEPROM command be
issued 128 times.
SCLK
DATA
COMMAND
LSB
DIO
A0
MSB LSB
A1
A2
A3
A4
A5
A6
0
0
0
0
0
0
MSB
1
0
0
16-BIT COMMAND WORD – BEGIN EEPROM WRITE AT ADDRESS COMMAND
LSB
MSB
SCLK
DATA
COMMAND
LSB
DIO
A0
MSB LSB
A1
A2
A3
A4
A5
A6
0
0
0
0
0
1
MSB
0
1
0
16-BIT COMMAND WORD – END EEPROM WRITE AT ADDRESS COMMAND
LSB
MSB
Figure 7. Begin WRITE EEPROM and End WRITE EEPROM Timing Diagrams
CS
tMIN = 200µs
16 CLOCK CYCLES
SCLK
tREAD
DIO
X
1
0
1
0
U
0
INIT SEQUENCE
A0
A1 A2 A3 A4 A5 A6
0
0
0
0
0
1
1
0 0
X
EE DATA
X
READ EEPROM AT ADDRESS COMMAND
DIO IS AN INPUT PIN
DIO IS AN
OUTPUT PIN
Figure 8. READ EEPROM Timing Diagram
______________________________________________________________________________________
11
MAX1458
high. In addition, the EEPROM should only be written to
at TA = +25°C and VDD = 5V.
Writing to the internal EEPROM is a time-consuming
process and should only be required once. All calibration/compensation coefficients are determined by writing directly to the DAC and configuration registers. Use
the following procedure to write these calibration/compensation coefficients to the EEPROM:
1) Issue an ERASE EEPROM command.
2) Wait 50ms (tWRITE).
3) Issue on END EEPROM WRITE command at
address 00h.
4) Wait 1ms (tWAIT).
5) Issue a BEGIN EEPROM WRITE command
(Figure 7) at the address of the bit to be set.
6) Wait 50ms.
7) Issue an END EEPROM WRITE command (Figure 7)
using the same address as in Step 5.
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
Writing to the Configuration and DAC Registers
When writing to the configuration register or directly to
the internal 12-bit DACs, the data field (D0–D11) contains the data to be written to the respective register.
Note that all four DACs and the configuration register
can be updated without toggling the CS line. Every
register write command must be followed by a LOAD
REGISTER command.
__________Applications Information
Power-Up
At power up, the following occurs:
1) The DAC and configuration registers are reset to
zero.
2) CS transitions from low to high after power-up (an
internal pull-up resistor ensures that this happens if
CS is left unconnected), and the EEPROM contents
are read and processed.
3) The DAC and configuration registers are updated
either once or approximately 400 times per second
(as determined by the state of WE).
4) The MAX1458 begins accepting commands in a serial format on DIO immediately after receiving the INIT
SEQUENCE.
The MAX1458 is shipped with all memory locations in
the internal EEPROM uninitialized. Therefore, the
MAX1458 must be programmed for proper operation.
Coefficient Initialization
Select the resistor values and the PGA gain to prevent
overload of the PGA and bridge current source. These
values depend on sensor behavior and require some
sensor characterization data, which may be available
from the sensor manufacturer. If not, the data can be
generated by performing a two-temperature, two-pressure sensor evaluation. The required sensor information
is shown in Table 6 and can be used to obtain the values for the parameters listed in Table 7.
Table 6. Sensor Information for Typical
PRT
PARAMETER
2)
3)
4)
5)
12
Perform FSO Calibration
Perform FSOTC Compensation
Perform Offset TC Compensation
Perform Offset Calibration
TYPICAL
VALUES
Rb(T)
Bridge Impedance
5kΩ at +25°C
TCR
Bridge Impedance
Tempco
2600ppm/°C
S(T)
Sensitivity
1.5mV/V per
PSI at +25°C
TCS
Sensitivity Tempco
-2100ppm/°C
O(T)
Offset
12mV/V at
+25°C
OTC
Offset Tempco
-1000ppm/°C
of FSO
S(p)
Sensitivity Linearity Error
as % FSO, BSLF
(Best Straight-Line Fit)
0.1% FSO,
BSLF
PMIN
Minimum Input Pressure
0 PSI
PMAX
Maximum Input Pressure
10 PSI
Compensation Procedure
The following compensation procedure was used to
obtain the results shown in Figure 9 and Table 8. It
assumes a pressure transducer with a +5V supply and
an output voltage that is ratiometric to the supply voltage. The desired offset voltage (VOUT at PMIN) is 0.5V,
and the desired FSO voltage (VOUT(PMAX) - VOUT(PMIN))
is 4V; thus the full-scale output voltage (VOUT at PMAX)
will be 4.5V (refer to Figure 1). The procedure requires
a minimum of two test pressures (e.g., zero and full
scale) at two arbitrary test temperatures, T1 and T2.
Ideally, T1 and T2 are the two points where we wish to
perform best linear fit compensation. The following outlines a typical compensation procedure:
1) Perform Coefficient Initialization
SENSOR
DESCRIPTION
Selecting RISRC
When using an external resistor, use the equation
below to determine the value of RISRC, and place the
resistor between ISRC and VSS. Since the 12-bit FSO
DAC provides considerable dynamic range, the RISRC
value need not be exact. Generally any resistor value
within ±50% of the calculated value is acceptable. If
both the internal resistors RISRC and RFTC are used, set
the IRS bit at EEPROM address bit 7 high. Otherwise,
set IRS low and connect external resistors as shown in
Figure 10.
RISRC ≈ 14 x Rb(T1)
≈ 14 x 5kΩ = 70kΩ
where Rb(T) is the sensor input impedance at temperature T1 (+25°C in this example).
______________________________________________________________________________________
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
PARAMETER
DESCRIPTION
RISRC
Internal (approximately 75kΩ) or usersupplied resistor that programs the nominal sensor excitation current.
RFTC
Internal (approximately 75kΩ) or usersupplied resistor that compensates
FSO TC errors.
APGA
Programmable-gain amplifier gain
Input-referred offset correction DAC
value
IRO
IRO Sign
Input-referred offset sign bit
IRS
Internal resistor selection bit
OFF COEF
OFF Sign
OFFTC COEF
Offset correction DAC coefficient
Offset sign bit
Offset TC compensation DAC coefficient
OFFTC Sign
Offset TC sign bit
FSO COEF
FSO trim DAC coefficient
FSOTC COEF
FSO TC compensation DAC coefficient
Selecting RFTC
When using an external resistor, use the equation
below to determine the value for RFTC, and place the
resistor between ISRC and FSOTC. Since the 12-bit
FSOTC DAC provides considerable dynamic range, the
RFTC value need not be exact. Generally, any resistor
value within ±50% of the calculated value is acceptable.
RISRC x 500ppm/ °C
TCR - | TCS |
70kΩ x 500ppm/ °C
≅
= 70kΩ
2600ppm/ ° C - | -2100ppm/ ° C |
RFTC ≅
This approximation works best for bulk, micromachined,
silicon PRTs. Negative values for RFTC indicate unconventional sensor behavior that cannot be compensated
by the MAX1458 without additional external circuitry.
Selecting the PGA Gain Setting
To select the PGA gain setting, first calculate
SensorFSO, the sensor full-span output voltage at T1:
SensorFSO = S x VBDRIVE x ∆P
= 1.5mV/V per PSI x 2.5V x 10 PSI
= 0.0375V
where S is the sensor sensitivity at T1, VBDRIVE is the
sensor excitation voltage (initially 2.5V), and ∆P is the
maximum pressure differential.
Then calculate the ideal gain using the following formula,
and select the nearest gain setting from Table 2:
OUTFSO
SensorFSO
4V
=
= 106V/V
0.0375V
APGA =
where OUTFSO is the desired calibrated transducer
full-span output voltage, and SensorFSO is the sensor
full-span output voltage at T1.
In this example, a PGA value of 2 (gain of +95V/V) is
the best selection.
Determining Input-Referred OFFSET (IRO)
The input-referred offset register is used to null any
front-end sensor offset errors prior to amplification by
the PGA. This reduces the possibility of saturating the
PGA and maximizes the useful dynamic range of the
PGA (particularly at the higher gain values.)
First, calculate the ideal IRO correction voltage using
the following formula, and select the nearest setting
from Table 1:
[
]
IROideal = - O( T1) x VBDRIVE ( T1)
= - (0.012V/V) x 2.5V
= - 30mV
where IROideal is the exact voltage required to perfectly null the sensor, O(T1) is the sensor offset voltage in
V/V at +25°C, and VBDRIVE(T1) is the nominal sensor
excitation voltage at +25°C. In this example, 30mV
must be subtracted from the amplifier front end to null
the sensor perfectly. From Table 1, select an IRO value
of 3 to set the IRO DAC to 27mV, which is nearest the
ideal value. To subtract this value, set the IRO sign bit
to 0. The residual output-referred offset error will be
corrected later with the Offset DAC.
Determining OFFTC COEF Initial Value
Generally, OFFTC COEF can initially be set to 0, since
the offset TC error will be compensated in a later step.
However, sensors with large offset TC errors may
require an initial coarse offset TC adjustment to prevent
the PGA from saturating during the compensation procedure as temperature is increased. An initial coarse
offset TC adjustment is required for sensors with an offset TC greater than about 10% of the FSO. If an initial
______________________________________________________________________________________
13
MAX1458
Table 7. Compensation Components and
Values
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
coarse offset TC adjustment is required, use the following equation:
OFFTC COEF =
≅
=
( )
4096 x ∆VOUT T
( )
∆VBDRIVE T x 2.3
(
)
4096 x OTC x FSO x ∆T
TCS x VBDRIVE x 2.3 x ∆T
(
)
4096 x -1000ppm/ °C x 4V
-2100ppm/ °C x 2.5V x 2.3
= 1357
where OTC is the sensor offset TC error as a ppm/°C of
OUTFSO (Table 6), ∆T is the operating temperature
range in °C, and OFFTC COEF is the numerical decimal
value to be loaded into the DAC. For positive values,
set the OFFTC sign bit high; for negative values, set the
OFFTC sign bit low. If the absolute value of the OFFTC
COEF is larger than 4096, the sensor has a very large
offset TC error, which the MAX1458 is unable to completely correct.
FSO Calibration
Perform FSO calibration at room temperature with a fullscale sensor excitation.
1) Set FSOTC COEF to 1000.
2) At T1, adjust FSO DAC until VBDRIVE is about 2.5V.
3) Adjust Offset DAC (and OFFSET sign bit, if needed)
until the T1 offset voltage is 0.5V (see OFFSET
Calibration section).
4) Measure the full-span output (measuredVFSO).
5) Calculate the ideal bridge voltage, V BIDEAL (T1),
using the following equation:
VBIDEAL ( T1) = VBDRIVE x

desiredVFSO - measuredVFSO ( T1)
1 +
measuredVFSO ( T1)






Note: If VBIDEAL(T1) is outside the allowable bridge
voltage swing of (VSS + 1.3V) to (VDD - 1.3V), readjust
the PGA gain setting. If V BIDEAL (T1) is too low,
decrease the PGA gain setting by one step and return
to Step 2. If VBIDEAL(T1) is too high, increase the PGA
gain setting by one step and return to Step 2.
6) Set VBIDEAL(T1) by adjusting the FSO DAC.
7) Readjust Offset DAC until the offset voltage is 0.5V
(see OFFSET Calibration section).
14
Three-Step FSOTC Compensation
Step 1
Use the following procedure to determine FSOTC
COEF. Four variables, A–D, will be used.
1) Name the existing FSO DAC coefficient “A”.
2) Change FSOTC DAC to 3000.
3) Adjust FSO DAC until V BDRIVE (T1) is equal to
VBIDEAL(T1).
4) Name the existing FSO DAC coefficient “B”.
5) Readjust the offset voltage (by adjusting the Offset
DAC), if required, to 0.5V.
At this point, it is important that no other changes be
made to the Offset or Offset TC DACs until the Offset
TC Compensation step has been completed.
Step 2
To complete linear FSOTC compensation, take data
measurements at a second temperature, T2 (T2 > T1).
Perform the following steps:
1) Measure the full-span output (measuredVFSO(T2).
2) Calculate VBIDEAL(T2) using the following equation:
VBIDEAL ( T2) = VBDRIVE x

desiredVFSO - measuredVFSO ( T2) 
1 +

measuredVFSO ( T2)


3) Set VBIDEAL(T2) by adjusting the FSO DAC.
4) Name the current FSO DAC coefficient “D”.
5) Change FSOTC DAC to 1000.
6) Adjust FSO DAC until V BDRIVE is equal to
VBIDEAL(T2).
7) Name the FSO DAC coefficient “C”.
Step 3
Insert the data previously obtained from Steps 1 and 2
into the following equation to compute FSOTC COEF:
FSOTC COEF =
( )
(B - D)
(
)
1000 B - D + 3000 C - A
(
)
+ C- A
1) Load this FSOTC COEF value into the FSOTC DAC.
2) Adjust the FSO DAC until VBDRIVE(T2) is equal to
VBIDEAL(T2).
This completes both FSO calibration and FSO TC compensation.
______________________________________________________________________________________
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
1) Measure the offset voltage at T2.
2) Use the following equation to compute the correction required:
NewOFFTC COEF = CurrentOFFTC COEF +
[
[
] 
 4096 VOFFSET ( T1) - VOFFSET ( T2)

 2.3 VBDRIVE ( T1) - VBDRIVE ( T2)

]


Note: CurrentOFFTC COEF is the current value
stored in the Offset TC DAC. If the Offset TC sign bit
(SOTC) is low, this number is negative.
3) Load this value into the Offset TC DAC.
4) If NewOFFTC COEF is negative, set the SOTC bit
low; otherwise, set it high.
Offset TC Compensation is now complete.
OFFSET Calibration
At this point the sensor should still be at temperature
T2. The final offset adjustment can be made at T2 or T1
by adjusting the Offset DAC (and optionally the offset
sign bit, SOFF) until the output (VOUT(PMIN)) reads 0.5V
at zero input pressure. Use the following procedure:
1) Set Offset DAC to zero (Offset COEF = 0).
2) Measure the voltage at OUT.
3) If VOUT is greater than the desired offset voltage
(0.5V in this example), set SOFF low; otherwise set it
high.
4) Increase Offset COEF until VOUT equals the desired
offset voltage.
Offset calibration is now complete. Table 8 and Figure 9
compare an uncompensated input to a typical compensated transducer output.
Table 8. MAX1458 Calibration and Compensation
Typical Uncompensated Input (Sensor)
Typical Compensated Transducer Output
Offset ..........................................................................±80% FSO
FSO ..................................................................................15mV/V
Offset TC ......................................................................-17% FSO
Offset TC Nonlinearity ..................................................0.7% FSO
FSO TC.........................................................................-35% FSO
FSO TC Nonlinearity.....................................................0.5% FSO
Temperature Range...........................................-40°C to +125°C
VOUT ...................................................Ratiometric to VDD at 5.0V
Offset at +25°C ......................................................0.500V ±5mV
FSO at +25°C .........................................................4.000V ±5mV
Offset Accuracy Over Temp. Range ..........±28mV (±0.7% FSO)
FSO Accuracy Over Temp. Range .............±20mV (±0.5% FSO)
COMPENSATION TRANSDUCER ERROR
UNCOMPENSATED SENSOR ERROR
0.8
30
0.6
0.4
10
ERROR (% SPAN)
ERROR (% FSO)
20
FSO
0
OFFSET
FSO
0.2
0
-0.2
-0.4
OFFSET
-10
-0.6
-0.8
-20
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
100
150
TEMPERATURE °(C)
Figure 9. Comparison of an Uncalibrated Sensor and a Temperature-Compensated Transducer
______________________________________________________________________________________
15
MAX1458
Offset TC Compensation
The offset voltage at T1 was previously set to 0.5V;
therefore, any variation from this voltage at T2 is an
offset TC error. Perform the following steps:
Ratiometric Output Configuration
Test System Configuration
Ratiometric output configuration provides an output that
is proportional to the power-supply voltage. When used
with ratiometric A/D converters, this output provides
digital pressure values independent of supply voltage.
Most automotive and some industrial applications
require ratiometric outputs.
The MAX1458 is designed to support an automated
production pressure-temperature test system with integrated calibration and temperature compensation.
Figure 11 shows the implementation concept for a lowcost test system capable of testing up to 12 transducer
modules connected in parallel. Three-state outputs on
the MAX1458 allow for parallel connection of transducers. The test system shown in Figure 11 includes a
dedicated test bus consisting of five wires:
The MAX1458 provides a high-performance ratiometric
output with a minimum number of external components
(Figure 10). These external components include the following:
• One power-supply bypass capacitor (C1)
• Two optional resistors, one from FSOTC to ISRC, and
another from ISRC to VSS, depending on the sensor
type
• Two power-supply lines
• One analog output voltage line from the transducers
to a system digital voltmeter
• Two serial-interface lines: DIO (input/output) and
SCLK (clock)
• One optional capacitor C2 from BDRIVE to VSS
For simultaneous testing of more than 12 sensor modules, use buffers to prevent overloading the data bus. A
digital multiplexer controls the chip-select signal for
each transducer.
+5V
VDD
OFFSET
(IRODAC)
BDRIVE
C2
0.1µF
C1
0.1µF
MAX1458
LIMIT
INP
Σ
INM
PGA
OUT
SENSOR
ISRC
VDD
RISRC
FSOTC
RFTC
RFTC
RISRC
VSS
CS
WE
SCLK
DIO
128-BIT
EEPROM
DIGITAL
INTERFACE
CONFIGURATION REGISTER
12-BIT D/A - OFFSET
12-BIT D/A - OFFSET TC
12-BIT D/A - FSO
12-BIT D/A - FSOTC
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
A=1
TEMP
TEMP
VSS
Figure 10. Basic Ratiometric Output Configuration
16
______________________________________________________________________________________
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
MAX1458
CS[1:N]
CS1
MODULE 1
MODULE 2
CS
BDRIVE
INP
INP
INP
INM
INM
INM
MAX1458
CS
BDRIVE
MAX1458
+5V
VDD
MODULE N
CS
BDRIVE
SCLK
DIO
CSN
CS2
MAX1458
DIGITAL
MULTIPLEXER
SCLK
DIO
OUT
VSS
VDD
SCLK
DIO
OUT
VSS
VDD
OUT
VSS
VOUT
DVM
SCLK
DIO
TEST
OVEN
Figure 11. Automated Test System Concept
MAX1458 Evaluation
____________________________________Development Kit
To expedite the development of MAX1458 based transducers and test systems, Maxim has produced the
MAX1458 evaluation kit (EV kit). First-time users of the
MAX1458 are strongly encouraged to use this kit. The
MAX1458 EV kit is designed to facilitate manual programming of the MAX1458 and includes the following:
3) MAX1458 Communication Software, which enables
programming of the MAX1458 from a computer (IBM
compatible), one module at a time.
4) Interface Adapter and Cable, which allow the connection of the evaluation board to a PC parallel port.
1) Evaluation Board with a silicon pressure sensor.
2) Design/Applications Manual, which describes in
detail the architecture and functionality of the
MAX1458. This manual was developed for test engineers familiar with data acquisition of sensor data
and provides sensor compensation algorithms and
test procedures.
______________________________________________________________________________________
17
Functional Diagram
VDD
OFFSET
(IRODAC)
BDRIVE
INP
Σ
INM
Chip Information
TRANSISTOR COUNT: 7772
SUBSTRATE CONNECTED TO VSS
MAX1458
LIMIT
PGA
OUT
ISRC
VDD
RFTC
FSOTC
RISRC
VSS
CS
WE
SCLK
DIO
128-BIT
EEPROM
DIGITAL
INTERFACE
CONFIGURATION REGISTER
12-BIT D/A - OFFSET
12-BIT D/A - OFFSET TC
12-BIT D/A - FSO
12-BIT D/A - FSOTC
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
A=1
TEMP
TEMP
VSS
18
______________________________________________________________________________________
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
SSOP.EPS
______________________________________________________________________________________
19
MAX1458
Package Information
MAX1458
1%-Accurate, Digitally Trimmed
Sensor Signal Conditioner
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 1998 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.