Revised August 1999 74F401 CRC Generator/Checker General Description Features The 74F401 Cycle Redundancy Check (CRC) Generator/ Checker provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. A 3-bit control input selects one-ofeight generator polynomials. The list of polynomials includes CRC-16 and CRC-CCITT as well as their reciprocals (reverse polynomials). Automatic right justification is incorporated for polynomials of degree less than 16. Separate clear and preset inputs are provided for floppy disk and other applications. The Error output indicates whether or not a transmission error has occurred. Another control input inhibits feedback during check word transmission. The 74F401 is fully compatible with all TTL families. ■ Eight selectable polynomials ■ Error indicator ■ Separate preset and clear controls ■ Automatic right justification ■ Fully compatible with all TTL logic families ■ 14-pin package ■ 9401 equivalent ■ Typical applications: Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems Ordering Code: Order Number Package Number Package Description 74F401SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 74F401PC N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol © 1999 Fairchild Semiconductor Corporation Connection Diagram DS009534 www.fairchildsemi.com 74F401 CRC Generator/Checker April 1988 74F401 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL S0–S2 Polynomial Select Inputs 1.0/1.0 20 µA/−0.6 mA D Data Input 1.0/1.0 20 µA/−0.6 mA 20 µA/−0.6 mA CP Clock Input (Operates on HIGH-to-LOW Transition) 1.0/1.0 CWE Check Word Enable Input 1.0/1.0 20 µA/−0.6 mA P Preset (Active LOW) Input 1.0/1.0 20 µA/−0.6 mA MR Master Reset (Active HIGH) Input 1.0/1.0 20 µA/−0.6 mA Q Data Output 50/33.3 −1 mA/20 mA ER Error Output 50/33.3 −1 mA/20 mA Functional Description transition of the Clock input (CP). This data is gated with the most significant output (Q) of the register, and controls the Exclusive OR gates Figure 1. The Check Word Enable (CWE) must be held HIGH while the data is being entered. After the last data bit is entered, the CWE is brought LOW and the check bits are shifted out of the register and appended to the data bits using external gating Figure 2. The 74F401 is a 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream (message polynomial) is divided by a selected polynomial. This division results in a remainder which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F401 implements the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S0, S1 and S2. To check an incoming message for errors, both the data and check bits are entered through the D input with the CWE input held HIGH. The 74F401 is not in the data path, but only monitors the message. The Error Output becomes valid after the last check bit has been entered into the 74F401 by a HIGH-to-LOW transition of CP. If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output (ER) is LOW. If a detectable error has occurred, ER is HIGH. The 74F401 consists of a 16-bit register, a Read Only Memory (ROM) and associated control circuitry as shown in the block diagram. The polynomial control code presented at inputs S0, S1 and S2 is decoded by the ROM, selecting the desired polynomial by establishing shift mode operation on the register with Exclusive OR gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data inputs (D), using the HIGH-to-LOW A HIGH on the Master Reset input (MR) asynchronously clears the register. A LOW on the Preset input (P) asynchronously sets the entire register if the control code inputs specify a 16-bit polynomial; in the case of 12- or 8-bit check polynomials only the most significant 12 or 8 register bits are set and the remaining bits are cleared. TABLE 1. Select Code S2 S1 Polynomial S0 Remarks L L L X16 + X15 + X2 + 1 CRC-16 L L H X16 + X14 + X + 1 CRC-16 REVERSE L H L X16 + X15 + X13 + X7 + X4 + X2 + X1 + 1 L H H X12 + X11 + X3 + X2 + X + 1 H L L X8 + X7 + X5 + X4 + X + 1 H L H X8 + 1 LRC-8 H H L X16 + X12 + X5 + 1 CRC-CCITT H H H X16 + X11 + X4 + 1 CRC-CCITT REVERSE www.fairchildsemi.com 2 CRC-12 74F401 Block Diagram FIGURE 1. Equivalent Circuit for X16 + X15 + X2 + 1 FIGURE 2. Check Word Generation Note 1: Check word Enable is HIGH while data is being clocked, LOW while transmission of check bits. Note 2: 74F401 must be reset or preset before each computation. Note 3: CRC check bits are generated and appended to data bits. 3 www.fairchildsemi.com 74F401 Absolute Maximum Ratings(Note 4) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 5) −0.5V to +7.0V Input Current (Note 5) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 5: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH V Min 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V −150 mA Max VOUT = 0V 105 mA Max VO = HIGH VOL Output LOW Voltage IIH Input HIGH Current IBVI Input HIGH Current 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage Voltage 2.0 Units VIH 10% VCC Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage Circuit Current IIL Input LOW Current IOS Output Short-Circuit Current ICCH Power Supply Current www.fairchildsemi.com −60 70 4 Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded 74F401 AC Electrical Characteristics Symbol Parameter Min TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Typ Max Min Units Max fMAX Maximum Clock Frequency 100 tPLH Propagation Delay 4.5 11.5 4.5 13.5 tPHL CP to Q 4.0 10.0 4.0 11.0 tPHL Propagation Delay 3.0 7.5 3.0 8.0 ns 3.0 8.5 3.0 9.5 ns 3.5 11.0 3.5 12.0 ns 3.0 8.5 3.0 10.0 ns MR to Q tPLH Propagation Delay P to Q tPHL Propagation Delay MR to ER tPLH Propagation Delay P to ER 85 MHz tPLH Propagation Delay 5.0 13.0 5.0 14.5 tPHL CP to ER 4.5 11.5 4.5 12.5 ns ns AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA = 0°C to +70°C VCC = +5.0V Min Units Max tS(H) Set-up Time, HIGH or LOW 5.0 tS(L) D to CP 5.0 5.5 tS(H) Set-up Time, HIGH or LOW 4.0 4.5 tS(L) CWE to CP 4.0 4.5 tH(H) Hold Time, HIGH or LOW 2.0 2.0 tH(L) D and CWE to CP 2.0 2.0 tW(L) P Pulse Width, LOW 7.0 8.0 tW(H) Clock Pulse Width, 5.0 6.0 tW(L) HIGH or LOW 5.0 6.0 tW(H) MR Pulse Width, HIGH 5.0 5.5 ns tREC Recovery Time 4.0 4.5 ns 2.0 2.0 ns MR to CP tREC Recovery Time P to CP 5 5.5 ns ns ns www.fairchildsemi.com 74F401 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A www.fairchildsemi.com 6 74F401 CRC Generator/Checker Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com