256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM SMALL-OUTLINE SDRAM MODULE MT16LSDF3264(L)H – 256MB MT16LSDF6464(L)H – 512MB For the latest data sheet, please refer to the Micron® Web site: www.micron.com/products/modules Features Figure 1: 144-Pin SODIMM (MO-190) • PC100- and PC133-compliant, 144-pin, smalloutline, dual in-line memory module (SODIMM) • Utilizes 100 MHz and 133 MHz SDRAM components • Unbuffered • 256MB (32 Meg x 64) and 512MB (64 Meg x 64) • Single +3.3V power supply • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto precharge and auto refresh modes • Self refresh mode: standard and low-power • 256MB module: 64ms, 4,096-cycle refresh (15.625µs refresh interval); 512MB: 64ms, 8,192-cycle refresh (7.81µs refresh interval) • LVTTL-compatible inputs and outputs • Serial presence-detect (SPD) • Gold edge connectors Table 1: PCB height: 1.25in (31.75mm) Options • Self refresh current Standard Low power • Package 144-pin SODIMM (standard) 144-pin SODIMM (lead-free) • Memory Clock/CL 7.5ns (133 MHz)/CL = 2 7.5ns (133 MHz)/CL = 3 10ns (100 MHz)/CL = 2 • PCB Height 1.25in (31.75mm) Timing Parameters CL = CAS (READ) latency ACCESS TIME MODULE CLOCK MARKING FREQUENCY CL = 2 CL = 3 -13E -133 -10E Table 2: 133 MHz 133 MHz 100 MHz 5.4ns – 6ns – 5.4ns – SETUP HOLD TIME TIME 1.5ns 1.5ns 2ns Marking 0.8ns 0.8ns 1ns NOTE: None L1 G Y1 -13E -133 -10E See page 2 note 1. Contact Micron for product availability. Address Table Refresh count Device banks Device configuration Row addressing Column addressing Module ranks pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 256MB 512MB 4K 4 (BA0, BA1) 128Mb (16 Meg x 8) 4K (A0–A11) 1K (A0–A9) 2 (S0#, S1#) 8K 4 (BA0, BA1) 256Mb (32 Meg x 8) 8K (A0–A12) 1K (A0–A9) 2 (S0#, S1#)) 1 ©2006 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 3: Part Numbers PART NUMBER MT16LSDF3264(L)HG-13E_ MT16LSDF3264(L)HY-13E_ MT16LSDF3264(L)HG-133_ MT16LSDF3264(L)HY-133_ MT16LSDF3264(L)HG-10E_ MT16LSDF3264(L)HY-10E_ MT16LSDF6464(L)HG-13E_ MT16LSDF6464(L)HY-13E_ MT16LSDF6464(L)HG-133_ MT16LSDF6464(L)HY-133_ MT16LSDF6464(L)HG-10E_ MT16LSDF6464(L)HY-10E_ MODULE DENSITY CONFIGURATION SYSTEM BUS SPEED 256MB 256MB 256MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB 512MB 512MB 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 133 MHz 133 MHz 133 MHz 133 MHz 100 MHz 100 MHz 133 MHz 133 MHz 133 MHz 133 MHz 100 MHz 100 MHz NOTE: 1. The designators for component and PCB revision are the last two characters of each part number Consult factory for current revision codes. Example: MT16LSDF32264(L)HG-133B1. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 4: Pin Assignment (144-Pin SODIMM Front) Table 5: Pin Assignment (144-Pin SODIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQMB0 DQMB1 VDD A0 A1 A2 VSS 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 DQ14 DQ15 VSS NC NC CK0 VDD RAS# WE# S0# S1# 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 NC Vss NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VDD A6 A8 VSS 109 A9 111 A10 113 VDD 115 DQMB2 117 DQMB3 119 VSS 121 DQ24 123 DQ25 125 DQ26 127 DQ27 129 VDD 131 DQ28 133 DQ29 135 DQ30 137 DQ31 139 VSS 141 SDA 143 VDD Vss DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQMB4 DQMB5 VDD A3 A4 A5 VSS 38 DQ40 40 DQ41 42 DQ42 44 DQ43 46 VDD 48 DQ44 50 DQ45 52 DQ46 54 DQ47 56 VSS 58 NC 60 NC 62 CKE0 64 VDD 66 CAS# 68 CKE1 70 NC/A121 72 NC 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 CK1 VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 DQ54 DQ55 VDD A7 BA0 VSS 110 BA1 112 A11 114 VDD 116 DQMB6 118 DQMB7 120 VSS 122 DQ56 124 DQ57 126 DQ58 128 DQ59 130 VDD 132 DQ60 134 DQ61 136 DQ62 138 DQ63 140 VSS 142 SCL 144 VDD NOTE: 1. Pin 70 is No Connect for 256MB modules, or A12 for 512MB modules. Figure 2: Pin Locations (144-Pin SODIMM) Front View Back View U2 U1 U3 PIN 1 U4 U5 (all odd pins) U6 U7 U10 U17 U8 U16 PIN 143 U15 U14 PIN 144 Indicates a VDD or VDDQ pin pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN U9 3 U13 (all even pins) U12 U11 PIN 2 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 6: Pin Descriptions Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information PIN NUMBERS 65, 66, 67 SYMBOL RAS#, CAS#, WE# 61, 74 CK0, CK1 62, 68 CKE0, CKE1 69, 71 S0#,S1# 23, 24, 25, 26, 115, 116, 117, 118 DQMB0–DQMB7 106, 110 BA0, BA1 29, 30, 31, 32, 33, 34, 70 (512MB), 103, 104, 105, 109, 111, 112 A0–A11 (256MB) A0–A12 (512MB) 142 SCL 141 SDA 3, 4, 5, 6, 7, 8, 9, 10, 13, 14, 15, 16, 17, 18,19, 20, 37, 38, 39, 40, 41, 42, 43, 44, 47, 48, 49, 50, 51, 52, 53, 54, 83, 84, 85, 86, 87, 88, 89, 90, 93, 94, 95, 96, 97, 98, 99, 100, 121, 122, 123, 124, 125, 126, 127, 128, 131, 132, 133, 134, 135, 136, 137, 138 DQ0–DQ63 pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN TYPE Input DESCRIPTION Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Input Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Deactivating the clock provides PRECHARGE powerdown and SELF REFRESH operation (all device banks idle), ACTIVE power-down (row ACTIVE in any device bank), or CLOCK SUSPEND operation (burst access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK, are disabled during power-down and self refresh modes, providing low standby power. Input Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Input Input/output mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) when DQMB is sampled HIGH during a READ cycle. Input Bank address: BA0 and BA1 define to which device bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Input Address inputs: Provide the row address for ACTIVE commands and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. Input Serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. Input/ Serial presence-detect data: sda is a bidirectional pin used to Output transfer addresses and data into and data out of the presencedetect portion of the module. Input/ Data I/O: Data bus. Output 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 6: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to the Pin Assignment tables on page 3 for more information PIN NUMBERS 11, 12, 27, 28, 45, 46, 63, 64, 81, 82, 101, 102, 113, 114, 129, 130, 143, 144 1, 21, 35, 55, 75, 91, 107, 119, 139, 2, 22, 36, 56, 76, 92, 108, 120, 140 57, 58, 59, 60, 70 (256MB), 72, 73, 77, 78, 79, 80 pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN SYMBOL VDD VSS NC TYPE DESCRIPTION Supply Power supply: +3.3V ±0.3V. Supply Ground. – Not connected: These pins should be left unconnected. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Figure 3: Functional Block Diagram S1# S0# 0Ω 0Ω DQMB0 0Ω CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 U3 DQM CS# DQ DQ DQ DQ U11 DQ DQ DQ DQ DQM U5 DQM CS# DQ DQ DQ DQ U13 DQ DQ DQ DQ DQMB6 DQM U7 DQM CS# DQ DQ DQ DQ U15 DQ DQ DQ DQ DQMB7 CS# DQM DQ DQ DQ U8 DQ DQ DQ DQ DQ RAS# RAS#: SDRAMs CAS# WE# CAS#: SDRAMs WE#: SDRAMs (256MB) A0–A11 A0-A11: SDRAMs (512MB) A0–A12 A0-A12: SDRAMs BA0, BA1 DQM CS# DQ DQ DQ U16 DQ DQ DQ DQ DQ CKE0 BA0, BA1: SDRAMs CKE0 (U1–U8) CKE1 CKE1 (U9–U16) SCL WP SDRAMs VSS SDRAMs SERIAL PD U17 A0 A1 A2 U1 DQM CS# DQ DQ DQ DQ U9 DQ DQ DQ DQ DQM U4 DQM CS# DQ DQ DQ DQ U12 DQ DQ DQ DQ 0Ω CS# DQ DQ DQ DQ DQ DQ DQ DQ DQM DQM CS# DQ DQ DQ DQ DQ DQ DQ DQ U6 U14 0Ω CS# DQ DQ DQ DQ DQ DQ DQ DQ DQM U2 DQM CS# DQ DQ DQ DQ U10 DQ DQ DQ DQ 0Ω CK0 CK1 SDA CLK (U1, U3, U9, U11) CLK (U4, U5, U12, U13) CLK (U6, U7, U14, U15) CLK (U2, U8, U10, U16) Standard modules use the following SDRAM devices: MT48LC16M8A2FB (256MB); MT48LC32M8A2FB (512MB) NOTE: 1. All resistor values are 10Ω unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the module part numbering guide at www.micron.com/ support/numbering.html. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VDD DQM 0Ω DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 0Ω DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 0Ω CS# DQ DQ DQ DQ DQ DQ DQ DQ 0Ω DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 CS# DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQM 0Ω DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB2 DQMB4 Lead-free modules use the following SDRAM devices: MT48LC16M8A2BB (256MB); MT48LC32M8A2BB (512MB) 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM General Description Serial Presence Detect Operation The MT16LSDF3264(L)H and MT16LSDF6464(L)H are high-speed CMOS, dynamic random-access 256MB and 512MB unbuffered memory modules, organized in x64 configurations. These modules use internally configured quad-bank SDRAMs with a synchronous interface (all signals are registered on the positive edge of the clock signal CK). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select the device bank, A0–A11 [256MB] or A0–A12 [512MB] select the device row). The address bits A0–A9 (for both 256MB and 512MB modules) registered coincident with the READ or WRITE command are used to select the starting device column location for the burst access. These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. These modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also enables the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. These modules are designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a fast data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 128Mb or 256Mb SDRAM component data sheets. These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes are programmed by Micron to identify the module type, SDRAM characteristics and module timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0], which provide eight unique DIMM/ EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. When power is applied to VDD and VDDQ (simultaneously), and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. When the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All device banks must then be precharged, thereby placing the device in the all banks idle state. When in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Mode Register Definition The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CL, an operating mode, and a write burst mode, as shown in Figure 4 on page 8. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Figure 4: Mode Register Definition Diagram Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4–M6 specify the CL, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. For the 256MB and 512MB, M12 (A12) is undefined, but should be driven LOW during loading of the mode register. The mode register must be loaded when all device banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. 256MB Module A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 11 10 8 7 6 5 4 3 2 1 0 Mode Register (Mx) Reserved* WB Op Mode CAS Latency BT Burst Length *Should program M11 and M10 = “0, 0” to ensure compatibility with future devices. 512MB Module A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in Table 7 on page 9. The block is uniquely selected by A1–A9 when the burst length is set to two; by A2–A9 when the burst length is set to four; and by A3–A9 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached, as shown in Table 7 on page 9. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 9 Address Bus 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Bus Mode Register (Mx) Reserved* WB Op Mode CAS Latency BT Burst Length *Should program M12, M11, and M10 = “0, 0, 0” to ensure compatibility with future devices. Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Burst Type M3 0 Sequential 1 Interleaved M6 M5 M4 8 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 0 0 Defined - - - M9 Write Burst Mode 0 Programmed burst length 1 Single location access Operating Mode Standard operation All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 7: Burst Definition Table STARTING BURST COLUMN LENGTH ADDRESS 2 4 8 Full Page (y) Figure 5: CL Diagram ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL A0 0 0-1 1 1-0 A1 A0 0 0 0-1-2-3 0 1 1-2-3-0 1 0 2-3-0-1 1 1 3-0-1-2 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 0 1 0 2-3-4-5-6-7-0-1 0 1 1 3-4-5-6-7-0-1-2 1 0 0 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 1 1 0 6-7-0-1-2-3-4-5 1 1 1 7-0-1-2-3-4-5-6 n = A0-A9 Cn, Cn + 1, Cn + 2 (location Cn + 3, Cn + 4... 0-y) …Cn - 1, Cn… TYPE = INTERLEAVED COMMAND T1 T2 READ NOP NOP tLZ T3 tOH DOUT DQ 0-1 1-0 tAC CAS Latency = 2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not supported tOH DOUT DQ tAC CAS Latency = 3 DON’T CARE UNDEFINED Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 7. NOTE: 1. For full-page accesses: y = 1,024 (both 256MB and 512MB modules) 2. For a burst length of two, A1–A9 select the block-oftwo burst; A0 selects the starting column within the block. 3. For a burst length of four, A2–A9 select the block-offour burst; A0–A1 select the starting column within the block. 4. For a burst length of eight, A3–A9 select the block-ofeight burst; A0–A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0–A9 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0–A9 select the unique column to be accessed, and mode register bit M3 is ignored. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN T0 CLK CAS Latency (CL) CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ will start driving after T1 and the data will be valid by T2, as shown in Figure 4 on page 8. Table 8 on page 10 indicates the operating frequencies at which each CL setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Operating Mode Table 8: The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. CL Table ALLOWABLE OPERATING CLOCK FREQUENCY (MHz) SPEED CL = 2 CL = 3 -13E -133 -10E ≤ 133 ≤ 100 ≤ 100 < 143 < 133 ≤ NA Write Burst Mode When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Commands The Truth Table provides a quick reference of available commands. This is followed by written description of each command. For a more detailed Table 9: description of commands and operations, refer to the 128Mb or 256Mb SDRAM component data sheet. Truth Table – SDRAM Commands and DQMB Operation CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) CS# RAS# CAS# WE# DQMB COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (select bank and activate row) READ (select bank and column, and start READ burst) H L L L X H L H X H H L X H H H X X X WRITE (select bank and column, and start WRITE burst) L H L L BURST TERMINATE PRECHARGE (deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (enter self refresh mode) LOAD MODE REGISTER Write enable/output enable Write inhibit/output High-Z L L L H L L H H L L L H L/H8 X X X L – – L – – L – – L – – X L H 8 L/H ADDR DQ NOTES X X Bank/Row Bank/Col X X X X 1 2 Bank/Col Valid 2 X Code X Active X X 3 4, 5 Op-code – – X Active High-Z 6 7 7 NOTE: 1. A0–A11 (256MB) or A0–A12 (512MB) provide device row address, and BA0, BA1 determine which device bank is made active. 2. A0–A9 (256MB and 512MB) provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to. 3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and BA0, BA1 are “Don’t Care.” 4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 6. A0–A11 define the op-code written to the mode register; for the 256MB and 512MB, A12 should be driven low. 7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply, Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS . . . . . . . . . . . . . . . . . . . -1V to +4.6V Operating Temperature, TOPR (Commercial - ambient) . . . . . .0°C to +65°C Storage Temperature (plastic) . . . . . . -55°C to +125°C Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1, 5, 6; notes appear on page 16; VDD, VDDQ = +3.3V ±0.3V PARAMETER/CONDITION Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Input leakage current: Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) Output leakage current: DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ Output levels: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) Command and Address Inputs CK, CKE, S# DQMB DQ SYMBOL MIN MAX UNITS NOTES VDD, VDDQ VIH VIL II 3 2 –0.3 3.6 VDD + 0.3 0.8 V V V µA 22 22 33 IOZ –80 –40 –10 –10 80 40 10 10 µA 33 VOH VOL 2.4 – – 0.4 V V Table 11: IDD Specifications and Conditions – 256MB Notes: 1, 5, 6, 11, 13; SDRAM components only; notes appear on page 16; VDD, VDDQ = +3.3V ±0.3V MAX PARAMETER/CONDITION Operating current: Active mode; Burst = 2; READ or WRITE; RC = tRC (MIN) Standby current: Power-down mode; All device banks idle; CKE = LOW Standby current: Active mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress Operating current: Burst mode; Continuous burst; READ or WRITE; All device banks active t Auto refresh current RFC = tRFC (MIN) CKE = HIGH; S# = HIGH tRFC = 15.625µs Self refresh current: CKE ≤ 0.2V Standard SYMBOL -13E -133 IDD1a -10E UNITS NOTES 1,296 1,216 1,136 mA 3, 17, 19, 32 IDD2b 32 32 32 mA 32 IDD3a 416 416 336 mA 3, 12, 19, 32 IDD4a 1,336 1,216 1,136 mA 3, 18, 19, 32 IDD5b 5,280 4,960 4,320 mA 3, 12, 18, 19, 32,30 t Low power (L) b IDD6 48 48 48 mA IDD7b 32 32 32 mA IDD7b 16 16 16 mA 4 a - Value calculated as one module rank in this operating condition, and all other ranks in power-down mode. b - Value calculated reflects all module ranks in this operation condition. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 12: IDD Specifications and Conditions – 512MB Notes: 1, 5, 6, 11, 13; SDRAM components only; notes appear on page 16; VDD, VDDQ = +3.3V ±0.3V MAX PARAMETER/CONDITION SYMBOL Operating current: Active mode; Burst = 2; READ or WRITE; = tRC (MIN) Standby current: Power-down mode; All device banks idle; CKE = LOW STANDBY CURRENT: Active mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst mode; Continuous burst; READ or WRITE; All device banks active tRFC = tRFC (MIN) Auto refresh current CKE = HIGH; S# = HIGH tRFC = 7.8125µs tRC Self refresh current: CKE < 0.2V -13E -133 IDD1 1,096 1,016 1,016 IDD2b 32 32 IDD3a 336 336 IDD4a 1,096 IDD5b 4,560 IDD6b 56 56 56 IDD7b 40 40 40 a Standard -10E UNITS NOTES mA 3, 17,19, 32 32 mA 32 336 mA 3, 12, 19, 32 1,096 1,096 mA 3, 18, 19, 32 4,320 4,320 mA mA 3, 12, 18, 19, 32,30 mA 4 Low power (L) 24 24 24 mA IDD7b a - Value calculated as one module rank in this operating condition, and all other ranks in power-down mode. b - Value calculated reflects all module ranks in this operation condition. Table 13: Capacitance Note 2; notes appear on page 16 PARAMETER SYMBOL MIN MAX UNITS CI1 CI2 CI3 CI4 CIO 40 20 20 5 8 60.8 28 30.4 7.6 12 pF pF pF pF pF Input capacitance: Address and command Input capacitance: CK Input capacitance: CKE, S# Input capacitance: DQMB Input/output capacitance: DQ pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 14: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 8, 9, 11, 31; notes appear on page 16; comply with PC100 and PC133 specifications, based on SDRAM device AC CHARACTERISTICS -13E PARAMETER Access time from CLK (positive edge) SYMBOL MIN -133 MAX CL = 3 t AC(3) 5.4 CL = 2 tAC(2) 5.4 MIN -10E MAX MAX UNITS NOTES 5.4 MIN 6 ns 27 6 6 ns Address hold time t AH 0.8 0.8 1 ns Address setup time t AS 1.5 1.5 2 ns CLK high-level width t CH 2.5 2.5 3 ns CLK low-level width tCL 3 ns 2.5 2.5 CL = 3 tCK(3) 7 7.5 8 ns 23 CL = 2 tCK(2) 7.5 10 10 ns 23 CKE hold time tCKH 0.8 0.8 1 ns CKE setup time tCKS 1.5 1.5 2 ns tCMH 0.8 0.8 1 ns tCMS 1.5 1.5 2 ns tDH 0.8 0.8 1 ns tDS 1.5 1.5 2 ns Clock cycle time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out High-Z time CL = 3 tHZ(3) CL = 2 tHZ(2) 5.4 5.4 5.4 6 6 ns 10 6 ns 10 Data-out Low-Z time tLZ 1 1 1 ns Data-out hold time (load) tOH 3 3 3 ns Data-out hold time (no load) tOHN 1.8 1.8 1.8 ns 28 ACTIVE-to-PRECHARGE command tRAS 37 ns 32 tRC 60 66 70 ns ACTIVE-to-READ or WRITE delay tRCD 15 20 20 ns Refresh period tREF AUTO REFRESH period t ACTIVE-to-ACTIVE command period PRECHARGE command period 44 64 120,000 50 64 120,000 64 ms RFC 66 66 70 ns tRP 15 20 20 ns RRD 14 15 20 ns ACTIVE bank a to ACTIVE bank b command Transition time t tT 0.3 WRITE recovery time tWR Exit SELF REFRESH to ACTIVE command tXSR 1 CLK + 7ns 14 67 pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 120,000 1.2 0.3 1 CLK + 7.5ns 15 75 14 1.2 0.3 1 CLK + 7ns 15 80 1.2 ns 7 ns 24 ns ns 25 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 15: AC Functional Characteristics Notes: 5, 6, 7, 8, 9, 11, 31; notes appear on page 16; comply with PC100 and PC133 specifications, based on SDRAM device PARAMETER SYMBOL -13E -133 -10E CCD 1 1 1 t CK 17 tCKED 1 1 1 tCK 14 PED 1 1 1 t CK 14 t READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode t CKE to clock enable or power-down exit setup mode UNITS NOTES DQM to input data delay t DQD 0 0 0 t CK 17 DQM to data mask during WRITEs t DQM 0 0 0 t CK 17 DQM to data High-Z during READs t DQZ 2 2 2 t CK 17 WRITE command to input data delay tDWD 0 0 0 tCK 17 Data-in to ACTIVE command tDAL 4 5 4 tCK 15, 21 Data-in to PRECHARGE command tDPL 2 2 2 tCK 16, 21 Last data-in to burst STOP command tBDL 1 1 1 tCK 17 Last data-in to new READ/WRITE command tCDL 1 1 1 tCK 17 16, 21 Last data-in to PRECHARGE command tRDL 2 2 2 tCK LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to High-Z from PRECHARGE command CL = 3 tMRD 2 2 2 tCK 26 tROH(3) 3 3 3 tCK 17 CL = 2 tROH(2) 2 2 2 tCK 17 pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test biased at 1.4V. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0°C ≤ TA ≤ +70°C). 6. An initial pause of 100µs is required after powerup, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH-command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 10ns for -10E, and tCK = 7.5ns for 133 and -13E. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge time (tRP) begins at 7ns for -13E; 7.5ns for -133 and 7ns for -10E after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC100 specify three clocks. 27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. For -10E, CL = 2 and tCK = 10ns; for -133, CL = 3 and tCK = 7.5ns; for -13E, CL = 2 and tCK = 7.5ns. 30. CKE is HIGH during refresh command period tRFC (MIN), else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 31. Refer to device data sheet for timing waveforms. 32. The value of tRAS used in -13E speed grade module SPDs is calculated from tRC - tRP = 45ns. 33. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals can change no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (see Figures 6, and 7). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (see Figure 8). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 6: Data Validity Figure 7: Definition of Start and Stop SCL SCL SDA SDA Data stable Data change Start bit Data stable Stop bit Figure 8: Acknowledge Response From Receiver (( )) SCL from master (( )) (( )) Data output from transmitter (( )) Data output from receiver Acknowledge pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 16: EEPROM Device Select Code Most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Memory area select code (two arrays) Protection register select code Table 17: EEPROM Operating Modes MODE Current address READ Random address READ Sequential READ Byte WRITE Page WRITE RW# BIT WC BYTES 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 ≥1 1 ≤16 INITIAL SEQUENCE START, device select, RW = 1 START, device select, RW = 0, Address RESTART, device select, RW = 1 similar to current or random address READ START, device select, RW = 0 START, device select, RW# = 0 Figure 9: SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA In t DH t AA t BUF SDA Out UNDEFINED pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = 2.3V to 3.6V PARAMETER/CONDITION SYMBOL Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage: IOUT = 3mA Input leakage current: VIN = GND to VDD Output leakage current: VOUT = GND to VDD Standby current: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V ±10% Power supply current: SCL clock frequency = 100 KHz VDD VIH VIL VOL ILI ILO ISB ICC MIN MAX 3 3.6 VDD × 0.7 VDD × 0.5 –1 VDD × 0.3 – 0.4 – 10 – 10 – 30 – 2 UNITS V V V V µA µA µA mA Table 19: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = 2.3V to 3.6V PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL MIN MAX UNITS NOTES tAA 0.2 1.3 200 0.9 µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT tSU:STA t SU:STO tWRC 100 0.6 0.6 10 2 2 3 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 20: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; VDD = +3.3V ±0.3V BYTE ENTRY (VERSION) MT16LSDF3264H MT16LSDF6464H 128 256 SDRAM 12 or 13 10 2 64 0 LVTTL 7ns (-13E) 7.5ns (-133) 8ns (-10E) 5.4ns (-13E/-133) 6ns (-10E) 80 08 04 0C 0A 02 40 00 01 70 75 80 54 60 80 08 04 0D 0A 02 40 00 01 70 75 80 54 60 NONE 15.6µs or 7.81µs/self 8 00 80 00 82 1 08 00 01 08 00 01 SDRAM cycle time, tCK (CL = 2) 1, 2, 4, 8, page 4 2, 3 0 0 Unbuffered 14 7.5ns (13E) 10ns (-133/-10E) 8F 04 06 01 01 00 0E 75 A0 8F 4 6 01 01 00 0E 75 A0 24 SDRAM access from CLK, tAC (CL = 2) 5.4ns (-13E) 6ns (-133/-10E) 54 60 54 60 25 SDRAM cycle time, tCK (CL = 1) – 00 00 26 SDRAM access from CLK, tAC (CL = 1) – 00 00 27 MIN row precharge time, tRP 28 MIN row active-to-row active, tRRD 29 MIN RAS#-to-CAS# delay, tRCD 30 MIN RAS# pulse width, tRAS 15ns (-13E) 20ns (-133/-10E) 14ns (-13E) 15ns (-133) 20ns (-10E) 15ns (-13E) 20ns (-133/-10E) 45ns (-13E) 44ns (133) 50ns (-10E) 0F 14 0E 0F 14 0F 14 2D 2C 32 0F 14 0E 0F 14 0F 14 2D 2C 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DESCRIPTION Number of bytes used by Micron Total number of SPD memory bytes Memory type Number of row addresses Number of column addresses Number of banks Module data width Module data width (continued) Module voltage interface levels SDRAM cycle time, tCK (CL = 3) SDRAM access from clock, tAC (CL = 3) Module configuration type Refresh rate/type SDRAM width (primary SDRAM) Error-checking SDRAM data width MIN clock delay from back-to-back random column addresses, tCCD Burst lengths supported Number of banks on SDRAM device CAS latencies supported CS latency WE latency SDRAM module attributes SDRAM device attributes: General pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Table 20: Serial Presence-Detect Matrix (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; VDD = +3.3V ±0.3V BYTE DESCRIPTION 31 32 Module rank density 33 Command and address hold time, tAH, tCMH 34 Data signal input setup time, tDS 35 Data signal input hold time, tDH Command and address setup time, tAS, tCMS 36–40 41 Reserved Device MIN ACTIVE/AUTO-REFRESH time, tRC 42–61 62 63 Reserved SPD revision Checksum for bytes 0-62 64 65–71 72 73–90 91 92 93 94 95-98 99–125 126 Manufacturer’s JEDEC ID code Manufacturer’s JEDEC ID code (continued) Manufacturing location Module part number (ASCII) PCB identification code Identification code (continued) Year of manufacture in BCD Week of manufacture in BCD Module serial number Manufacturer-specific data (RSVD) System frequency 127 ENTRY (VERSION) MT16LSDF3264H MT16LSDF6464H 128MB or 256MB 1.5ns (-13E/-133) 2ns (-10E) 0.8ns (-13E/-133) 1ns (-10E) 1.5ns (-13E/-133) 2ns (-10E) 0.8ns (-13E/-133) 1ns (-10E) 20 15 20 08 10 15 20 08 10 00 3C 42 46 00 02 95 E1 2D 2C FF 01–0C Variable Data 01–09 00 Variable Data Variable Data Variable Data 40 15 20 08 10 15 20 08 10 00 3C 42 46 00 02 B8 04 50 2C FF 01– 0C Variable Data 01–09 00 Variable Data Variable Data Variable Data 64 64 CF CF 66ns (-13E) 71ns (-133) 66ns (-10E) REV. 2.0 (-13E) (-133) (-10E) MICRON 1–12 1–9 0 100 MHz/133 MHz (-13E/-133/-10E) SDRAM component and clock detail NOTE: 1. The value of tRAS used for the -13E module is calculated from tRC - tRP. Actual device spec value is 37ns. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved. 256MB, 512MB (x64, DR) 144-PIN SDRAM SODIMM Figure 10: 144-Pin SODIMM Dimensions 0.150 (3.80) MAX FRONT VIEW 2.666 (67.72) 2.655 (67.45) U2 U1 0.079 (2.00) R (2X) 0.071 (1.80) (2X) U3 U4 U5 U6 U17 1.255 (31.88) 1.245 (31.62) U8 U7 0.787 (20.00) TYP 0.236 (6.00) 0.157 (4.00) 0.100 (2.55) 0.043 (1.10) 0.035 (0.90) 0.079 (2.00) PIN 1 83.82 (3.30) 0.059 (1.50) 0.024 (0.60) TYP TYP 0.0315 (0.80) TYP PIN 143 2.386 (60.60) 2.504 (63.60) BACK VIEW U10 U9 U15 U16 U14 U12 U13 U11 PIN 144 PIN 2 NOTE: MAX All dimensions in inches (millimeters); MIN or typical where noted. Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. pdf: 09005aef807924d2, source: 09005aef807924f1 SDF16C32_64x64HG.fm - Rev. E 4/06 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2006 Micron Technology, Inc. All rights reserved.