ACD2200S8 CATV/TV/Cable Modem Data Downconverter With Dual Synthesizer Advanced Product Information - Rev 1 • • • • • • • • • • • FEATURES Integrated Downconverter Integrated Dual Synthesizer 256 QAM Compatibility Single +5V Power Supply Operation Low Power Consumption Low Noise Figure High Conversion Gain Low Distortion Small Size Low Cost High Reliability APPLICATIONS • • • CATV Data Tuner Digital TV Tuners Cable Modems S8 28 Lead SSOP Package Description The ACD2200 uses both GaAs and Si technology to provide the downconverter and dual synthesizer functions in a double conversion tuners gain block, local oscillator, balanced mixer and dual synthesizer. The specifications meet the requirements of CATV, TV and Cable Modem Data applications. The ACD2200 is supplied in a 28 lead SSOP package and requires a single +5V supply voltage. The IC is well suited for situations where small size, low cost, low auxiliary parts count and a no-compromise performance is important. It provides for cost reduction by lowering the component and packaged IC count and decreasing the amount of labor-intensive production alignment steps, while significantly improving performance and reliability. Functional Block Diagram fINRF2 RF2: 64/65 Prescaler 18 Bit RF2 N Counter IF1+5V RF2 Phase Detector RF2 Charge Pump DO2 RF1 Phase Detector RF1 Charge Pump DO1 RFIN Low Noise VGA 15 Bit RF2 R Counter IF2+5V Mixer OSCIN OSCOUT Oscillator 15 Bit RF1 R Counter Phase Splitter fINRF1 TCKT RF1: 64/65 Prescaler 18 Bit RF1 N Counter OSCOUT Clock Data Enable Powered by ICminer.com Electronic-Library Service CopyRight 2003 22 Bit Data Registar Package and Pin Description Symbol Pin GND GND 1 28 IF1+VDD RFIN 2 27 IF2+VDD GND 3 26 GND ISET 4 25 VDDLO TCKT 5 24 OSCOUT OSCGND 6 23 GND OSCGND 7 22 GND VSS 8 21 VSS VSS 9 20 VSS EN 10 19 RFD DATA 11 18 CPD CLK 12 17 CPU REFIN 13 16 RFU REFOUT 14 15 VDDSYN TOP VIEW Description Symbol Pin Description 1 Downconverter ground. (Must be connected) VDDSYN 15 Synthesizer Supply (+VDD). RFIN 2 Downconverter RF Input. RFU 16 Synthesizer Upconverter RF Input. GND 3 Downconverter ground. (Must be connected) C PU 17 Synthesizer Upconverter Charge Pump Output. ISET 4 Downconverter Gilbert Cell Current Source Resistor. C PD 18 Synthesizer Downconverter Charge Pump Output. TCKT 5 Oscillator Input Port. (Tank circuit connection). RFD 19 Synthesizer Downconverter RF Input. OSCGND 6 Oscillator Tank Circuit Ground. (Not to be connected to any other circuit ground) V SS 20 Synthesizer Ground. (Required) OSCGND 7 Same as pin 6. V SS 21 Synthesizer Ground. (Required) V SS 8 Synthesizer Ground. (Required) GND 22 Downconverter ground. (Must be connected) V SS 9 Synthesizer Ground. (Required) GND 23 Downconverter ground. (Must be connected) EN 10 3-Wire Interface Enable. OSCOUT 24 Oscillator Output. (Connected to Synthesizer RF Input) DATA 11 3-Wire Interface Data. V D D LO 25 Oscillator and Phase Splitter Supply (+VDD). C LK 12 3-Wire Interface Clock. GND 26 Downconverter ground. (Must be connected) REFIN 13 Crystal Reference Input. IF2+VDD 27 Non-Inverting IF Output inductively coupled to +VDD. REFOUT 14 Crystal Reference Output. IF1+VDD 28 Inverting IF Output inductively coupled to +VDD. 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Absolute Maximum Ratings PAR AMETER MIN Supply Voltage (pi ns 26, 27 & 28) (pi n 15) Voltage on pi ns 10 through 19 wi th VSS=0V -0.3 Input Voltages (pi ns 1 & 5) Input Power (pi n 1) (pi n 5) (pi ns 13, 16 & 19) Storage Temperature -55 Solderi ng Temperature Solderi ng Ti me MAX U N ITS 9 6.5 V DC VDDSYN+0.3 V DC 0 V DC +10 +17 +20 dB m +150 °C 260 °C 4 S ec MAX U N IT MHz Operating Range PAR AMETER D ownconverter Frequency Synthesi zer Frequency MIN TYP (RF) (IF) (LO) 900 35 900 1200 150 1250 (RFU) (RFD) (RFIN) 400 400 2 2100 1400 25 Supply Voltage (pi ns 15, 26, 27 & 28) 4.75 5 5.25 MHz V IF Supply C urrent (pi n 27 + pi n 28) 50 65 mA Osc/Phase Spli tter Supply C urrent (pi n 10) 30 45 mA 50 mA +85 °C Synthesi zer Supply C urrent Operati ng C ase Temperature 40 -40 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Electrical Specifications Downconverter Section (TA=25C, VDD=+5V, RF=1170 MHz, IF=75 MHz) PARAMETER Conversion Gain1 MIN TYP 8 10 8 SSB Noise Figure1 Cross Modulation2 3 Order Intermodulation Distortion (IMD3) rd 3 2-Tone 3 Order Input Intercept Point (IIP3) rd 3 MAX UNIT dB 9.5 dB -48 dB c -53 dB c +12 dB m LO Phase Noise (@ 10KHz Offset) -90 dBc/Hz LO Power Out (OSCOUT Port) -5 dB m Spurious @ IF Output LO Signals and Harmonics Beats Within Output Channel Other Beats from 2 to 200 MHz Other Spurious -10 -48 -50 -10 dB m dB c dB m dB m IF Supply Current (pin 1 + pin 16) 50 65 mA Osc/Phase Splitter Supply Current (pin 10) 30 45 mA 400 550 mW Power Consumption Notes: 1. As measured in ANADIGICS test fixture. 2. 137 Channels, 99% Modulation @ 15 KHz. 3. Two Tones @ -15 dBm each. Synthesizer Section (TA=25C, VDD=+5V, RF=1170 MHz, IF=75 MHz) PARAMETER MIN Supply Current Operating Frequency TYP MAX UNIT 40 50 mA 2.1 1.4 GHz 20 MHz 10 MHz 20 dB m (RFU) (RFD) Reference Oscillator Frequency 2 4 Phase Detector Frequency RF Input Sensitivity (Over Operating Freq.) -10 Oscillator Sensitivity High-Level Digital Input Voltage 0.5 V PP 0.8 VDD Low-Level Digital Input Voltage Charge Pump Output Current CPU & CPD =VDD/2 (SINK) (SOURCE) 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 0.2 VDD 1.25 -1.25 mA Schematic for Tuner Reference Design 1 1 6 2 5 6 C40 RF AGC 2 IF OUT 5 100pF TRANS1 3 L1 220uH +5 V 3 4 4 L866B GND C34 100pF GND +5V +5V R23 10K C8 0.1uF R3 12K R8 100 R5 51 R2 750 C2 .01uF Q2 R24 L7 68nH ACU2200 MMBT2907 GND GND 1 GND GND GND C33 .01uF C11 .5pF L8 15nH RFInput L3 C31 3pF GND 3 15 3 14 16 15 GND R25 1K L1 3.3nH 8 6 11 7 10 8 9 C7 11 GND 9 4 5 R20 3.9nH 8 2K GND 6 7 GND 9 10 C34 30pF GND D1 11 1 GND 2 RF IN2 3 GND GND 26 4 ISET LO Vdd 25 5 TCKT LO OUT 24 6 LO GND GND 23 7 LO GND GND 22 8 GND GND 21 26 PLL IN 19 11 DAT CP OUT 18 CP OUT 17 12 12 CLK 13 13 XTAL PLL IN 16 14 14 XTAL PLL Vdd 15 R16 0 GND +5V C28 .1uF 25 GND 24 23 C25 .022u GND 22 21 GND 20 GND 20 10 ENA 2K R10 10K 27 IF1 27 9 GND GND 28 IF2 28 U2 V DT2 GND R21 C35 30pF 1.8nH C24 100pF C 1 GND 19 18 17 FMMTA13 16 Q1 15 C21 1uF +5 V GND GND R4 51 C36 30pF C9 1000pF C8 .1uF GND 10 C12 3pF L6 +5V L5 GND C42 .01uF +30V 3 CON8 1SV245 4.3pF 10 +5V +5V 8 7 6 5 4 3 2 1 2 R6 D2 1SV245 J1 C6 100pF GND 14 GND 7 D3 HSMP-3810 2 C1 .01uF 6 C5 3pF GND 2 ACU2109 U1 1 16 R1 240 15nH C32 1.3pF GND GND C4 .01uF L2 15nH 1 GND GND 100K ETC4-1-2 C30 1000pF GND GND X1 R22 2K + C14 30pF GND GND GND L4 68nH GND R11 100 GND R12 100 R13 100 4MHz C13 30pF GND GND GND C15 220uF C16 .1uF GND C17 1000pF C20 .022uF R15 1K GND R 1 C18 100pF GND 1 GND C10 1000pF GND 5 Register Programming with Serial Data Programable reference dividers (RF1 and RF2 Counters) If the control bits are 00 or 01 (00 for RF2 and 01 for RF1) data is transfered from the 22-bit shift register into a latch which sets the 15-bit R Counter. Serial data format is shown below. C o n t ro l C1 C2 D ivid e R atio o f th e R eferen ce D ivid er, R R 1 R 2 R 3 R 4 R 5 R 6 R 7 R 8 R 9 R 10 P ro g ram Mo d e R R 11 12 R 13 R 14 R 15 R 16 R 17 R 18 LSB R R 19 20 MSB 15-BIT Programable Reference Dividers (RF1 and RF2 Counters) D ivid e R atio R R R R 15 14 13 12 R R 11 10 R 9 R 8 R 7 R 6 R 5 R 4 R 3 R 2 R 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 - - - - - - - - - - - - - - - - 32767 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Notes: Divide ratios less than 3 are prohibited. Data is shifted in MSB first Divide Ratio: 3 to 32767 Programmable N Dividers (RF1 and RF2 Counters) Each N divider consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bits are 10 to 11 (10 for RF2 counter and 11 for RF1 counter) data is tranferred from 22-bit shift register into a 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data format is shown below. C o n tro l C1 C2 D ivid e R atio o f th e R F D ivid er, N N 1 N 2 N 3 N 4 N 5 N 6 N 7 N 8 N 9 P rg . N N N N N N N N N N N 10 11 12 13 14 15 16 17 18 19 20 LSB MSB 7-bit Swallow Counter Divide Ratio (A Counter) D ivid e R atio A N 7 N 6 N 5 N 4 N 3 N 2 N 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 - - - - - - - - 127 1 1 1 1 1 1 1 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Notes: Divide Ratio: 0 to 127. B>A A<P 11-Bit Programmable Counter Divide Ratio (B Counter) D ivid e R atio B N 18 N 17 N 16 N 15 N 14 N 13 N 12 N 11 N 10 N 9 N 8 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 - - - - - - - - - - - - 2047 1 1 1 1 1 1 1 1 1 1 1 Notes: Divide Ratio: 3 to 2047 (Divide ratios less than 3 prohibited).. B>A Pulse Swallow Function fVCO = [(P x B) + A] x fOSC/R Output frequency of external voltage controlled oscillator (VCO). fVCO: B: Preset divide ratio of binary 11-bit programmable counter (3 to 2047). A: Preset divide ratio of 7-bit swallow counter (0 < A < P; A < B). fOSC: Output frequency of the external reference frequency crystal or oscillator. R: Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767). P: Preset modulus of dual modulus prescaler (P = 64). Programmable Modes Several modes of operation can be programmed with bits R16-R20 including the phase detector polarity and the output of the LDfo pin. The programmable modes are shown in Table I. Truth tables for the programmable mdoes and LDfo output are shown in Table II and Table III. TABLE I. Programmable Modes C1 C2 R 16 R 17 R 18 R 19 R 20 0 0 RF2 Phase Detector Polarity na na RF2LD RF2fO 0 1 RF1 Phase Detector Polarity na na RF1LD RF1fO C1 C2 N 19 N 29 1 0 na na 1 1 na na 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Table II. Mode Select Truth Table VCO CHARACTERISTICS P ha se De te cto r P o la ri ty 0 Ne g a ti ve 1 P o si ti ve NOTE: (1) Depending upon VCO characteristics. The R16 bits should be set accordingly: When VCO characteristics are like (1), R16 should be set HIGH; When VCO characteristics are like (2), R16 should be set LOW VCO OUTPUT FREQUENCY (2) VCO INPUT VOLTAGE Table III. The LDfO Output Truth Table R F 1 R 19 (R F 1 L D ) R F 2 R 19 R F2 LD ) R F 1 R 20 R F 1 fO) R F 2 R 20 (R F 2 fO) 0 0 0 0 Disabled (Note 1) 0 1 0 0 RF2 Lock Detect (Note 2) 1 0 0 0 RF1 Lock Detect (Note 2) 1 1 0 0 RF1/RF2 Lock Detect (Note 2) X 0 0 1 RF2 Reference Divider Output X 0 1 0 RF1 Reference Divider Output X 1 0 1 RF2 Programmable Divider Output X 1 1 0 RF1 Programmable Divider Output 0 0 1 1 na 0 1 1 1 na 1 0 1 1 na 1 1 1 1 na X na - L D fO Ou tp u t S tate don’t care condition not applicable Note 1: When the LDfO output is disabled it is actively pulled to a low logic state. Note 2: Lock detect output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and a lock detect mode is selected, the pins output is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked. 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Serial Data Input Timing DATA N20: MSB N19 (R20: MSB) N10 (R19) N9 R10 C2 (R9) (R8) (C2) C1: LSB (C1: LSB) CLOCK tCWL LE tES OR tCS tCWH tCH tEW LE Phase Comparator and Internal Charge Pump Characteristics fr fP LD Do H Z I fr > fp fr = fp I I I fr < fp fr < fp L fr < fp Notes: Phase difference detection range: -2p to +2p The minimum width pump up and pump down current pulses occur at the DO pin when the loop is locked 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 NOTES 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 NOTES 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 ANADIGICS, Inc. 35 Technology Drive Warren, New Jersey 07059 Tel: (908) 668-5000 Fax: (908) 668-5132 http://www.anadigics.com [email protected] IMPORTANT NOTICE ANADIGICS, Inc. reserves the right to make changes to its products or discontinue any product at any time without notice. The Advanced Product data sheets and product specifications contained in this data sheet are subject to change prior to a products formal introduction. The information in this data sheet has been carefully checked and is assumed to be reliable. However, ANADIGICS assumes no responsibility for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders. WARNING ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS product in any such application without written consent is prohibited. 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003