LMX2335/LMX2336/LMX2337 PLLatinum™ Dual Frequency Synthesizer for RF Personal Communications LMX2335 LMX2336 LMX2337 1.1 GHz/1.1 GHz 2.0 GHz/1.1 GHz 550 MHz/550 MHz General Description The LMX2335, LMX2336 and LMX2337 are monolithic, integrated dual frequency synthesizers, including two high frequency prescalers, and are designed for applications requiring two RF phase-lock loops. They are fabricated using National’s ABiC IV silicon BiCMOS process. The LMX2335/36/37 contains two dual modulus prescalers. A 64/65 or a 128/129 prescaler can be selected for each RF synthesizer. A second reference divider chain is included in the IC for improved system noise. LMX2335/36/37, which employ a digital phase locked loop technique, combined with a high quality reference oscillator and loop filters, provide the tuning voltages for voltage controlled oscillators to generate very stable low noise RF local oscillator signals. Serial data is transferred into the LMX2335/36/37 via a three wire interface (Data, Enable, Clock). Supply voltage can range from 2.7V to 5.5V. The LMX2335/36/37 feature very low current consumption; LMX2335/37 −10 mA at 3V, LMX2336 −13 mA at 3V. The LMX2335/37 are available in both a JEDEC SO and TSSOP 16-pin surface mount plastic package. The LMX2336 is available in a TSSOP 20-pin surface mount plastic package. Features n 2.7V to 5.5V operation n Low current consumption n Selectable powerdown mode: ICC = 1 µA (typ) n Dual modulus prescaler: 64/65 or 128/129 n Selectable charge pump TRI-STATE ® mode n Selectable charge pump current levels n Selectable FastLock™ mode Applications n Cellular telephone systems (AMPS, ETACS, RCR-27) n Cordless telephone systems (DECT, ISM, PHS, CT-1+) n Personal Communication Systems (DCS-1800, PCN-1900) n Dual Mode PCS phones n CATV n Other wireless communication systems Functional Block Diagram DS012332-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. Fastlock™, MICROWIRE™ and PLLatinum™ are trademarks of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS012332 www.national.com LMX2335/LMX2336/LMX2337 PLLatinum Dual Frequency Synthesizer for RF Personal Communications September 1996 Connection Diagrams LMX2335/LMX2337 LMX2336 DS012332-2 Order Number LMX2335M/LMX2335TM or LMX2337M/LMX2337TM NS Package Number M16A and MTC16 DS012332-16 Order Number LMX2336TM NS Package Number MTC20 Pin Descriptions Pin No. 2335/37 Pin No. 2336 Pin Name 1 1 VCC1 2 2 Vp1 3 3 Do1 4 4 GND I/O Description Power supply voltage input for RF1 analog and RF1 digital circuits. Input may range from 2.7V to 5.5V. VCC1 must equal VCC2. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Power supply for RF1 charge pump. Must be ≥ VCC. O RF1 charge pump output. For connection to a loop filter for driving the input of an external VCO. LMX2335/37: Ground for RF1 analog and RF1 digital circuits. LMX2336: Ground for RF digital circuitry. 5 5 fIN1 I First RF prescaler input. Small signal input from the VCO. X 6 fIN1 I RF1 prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with loss of some sensitivity. X 7 GND 6 8 OSCin I Oscillator input. The input has a VCC/2 input threshold and can be driven from an external CMOS or TTL logic gate. 7 9 OSCout O Oscillator output. 8 10 FoLD O Multiplexed output of the programmable or reference dividers, lock detect signals and Fastlock mode. CMOS output (see Programmable Modes). 9 11 Clock I High impedance CMOS Clock input. Data for the various latches is clocked in on the rising edge, into the 20-bit shift register. 10 12 Data I Binary serial data input. Data entered MSB first. The last two bits are the control bits. High impedance CMOS input. 11 13 LE I Load enable high impedance CMOS input. When LE goes HIGH, data stored in the shift registers is loaded into one of the 4 appropriate latches (control bit dependent). X 14 GND X 15 fIN2 I 12 16 fIN2 I 13 17 GND 14 18 Do2 15 19 Vp2 www.national.com Ground for RF1 analog circuitry. Ground for RF2 analog circuitry. RF2 prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. Capacitor is optional with loss of some sensitivity. RF2 prescaler input. Small signal input from the VCO. LMX2335/37: Ground for RF2 analog, RF2 digital, MICROWIRE™, FoLD and Oscillator circuits. LMX2336: Ground for RF2 digital, MICROWIRE, FoLD and Oscillator circuits. O RF2 charge pump output. For connection to a loop filter for driving the input of an external VCO. Power supply for RF2 charge pump. Must be ≥ VCC. 2 Pin Descriptions (Continued) Pin No. 2335/37 Pin No. 2336 Pin Name 16 20 VCC2 I/O Description Power supply voltage input for RF2 analog. RF2 digital, MICROWIRE, FoLD and Oscillator circuits. Input may range from 2.7V to 5.5V. VCC2 must equal VCC1. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. Block Diagram DS012332-17 Note: VCC1 supplies power to the RF1 prescaler, N-counter, R-counter, and phase detector. VCC2 supplies power to the RF2 prescaler, N-counter, phase detector, R-counter along with the OSCin buffer, MICROWIRE, and FoLD. VCC1 and VCC2 are clamped to each other by diodes and must be run at the same voltage level. VP1 and VP2 can be run separately as long as VP ≥ VCC. LMX2335/37 Pin # → 8/10 ← LMX2336 Pin # Pin Name → FoLD X signifies a function not available 3 www.national.com Absolute Maximum Ratings (Notes 1, 2) Lead Temperature (solder 4 sec.) (TL) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Power Supply Voltage VCC VP Voltage on Any Pin with GND = 0V (VI) Storage Temperature Range (TS) +260˚C Recommended Operating Conditions Power Supply Voltage VCC VP Operating Temperature (TA) −0.3V to +6.5V −0.3V to +6.5V −0.3V to VCC +0.3V −65˚C to +150˚C 2.7V to 5.5V VCC to +5.5V −40˚C to +85˚C Electrical Characteristics VCC = 5.0V, Vp = 5.0V; TA = 25˚C, except as specified Symbol ICC Parameter Power Supply Current LMX2335/37 RF1 and RF2 Conditions Value Min VCC = 2.7V to 5.5V Units Typ Max 10 15 mA ICC LMX2335/37 RF1 only 6 8 mA ICC LMX2336 RF1 and RF2 13 18 mA LMX2336 RF1 only fIN1 fIN2 Operating Frequency fIN1 7 0.050 1.1 GHz LMX2336 0.200 2.0 GHz LMX2337 fIN2 ICC-PWDN 0.050 1.1 GHz 100 550 MHz 550 MHz 50 Powerdown Current LMX2335/2336 VCC = 5.5V 1 LMX2337 fOSC mA GHz 0.100 fIN2 fIN1 11 1.1 LMX2335 Oscillator Frequency fOSC fφ Phase Detector Frequency PfIN 1 and Pfin 2 RF Input Sensitivity 25 100 µA With resonator load on OSCout 5 20 MHz No load on OSCOUT 5 40 MHz 10 MHz VCC = 3.0V, f > 100 MHz −15 +4 VCC = 5.0V, f > 100 MHz −10 +4 VCC = 2.7 to 5.5V, f > 100 MHz −10 0 dBm VOSC Oscillator Sensitivity OSCIN 0.5 VPP VIH High-Level Input Voltage (Note 4) 0.8 VCC V VIL Low-Level Input Voltage (Note 4) IIH High-Level Input Current VIH = VCC = 5.5V (Note 4) IIL Low-Level Input Current VIL = 0V, VCC = 5.5V (Note 4) IIH Oscillator Input Current VIH = VCC = 5.5V IIL Oscillator Input Current VIL = 0V, VCC = 5.5V IDo-SOURCE Charge Pump Output Current VDo = Vp/2, ICPo = LOW (Note 3) −1.25 mA IDo-SINK VDo = Vp/2, ICPo = LOW (Note 3) 1.25 mA IDo-SOURCE VDo = Vp/2, ICPo = HIGH (Note 3) −5.0 mA IDo-SINK VDo = Vp/2, ICPo = HIGH (Note 3) 5.0 mA www.national.com 4 0.2 VCC V −1.0 1.0 µA −1.0 1.0 µA 100 µA −100 µA Electrical Characteristics (Continued) VCC = 5.0V, Vp = 5.0V; TA = 25˚C, except as specified Symbol IDo-TRI IDo-TRI Parameter Conditions Charge Pump TRI-STATE CURRENT LMX2335 LMX2336 0.5V ≤ VDo ≤ Vp − 0.5V T = 25˚C Charge Pump TRI-STATE CURRENT LMX2337 0.5V ≤ VDo ≤ Vp − 0.5V T = 25˚C Value Min Typ −5.0 Max 5.0 ±5 Units nA nA VOH High-Level Output Voltage IOH = −500 µA VCC − 0.4 VOL Low-Level Output Voltage IOL = 500 µA tCS Data to Clock Setup Time See Data Input Timing 50 ns ICH Data to Clock Hold Time See Data Input Timing 10 ns tCWH Clock Pulse Width High See Data Input Timing 50 ns tCWL Clock Pulse Width Low See Data Input Timing 50 ns tES Clock to Load Enable Set Up Time See Data Input Timing 50 ns tEW Load Enable Pulse Width See Data Input Timing 50 ns V 0.4 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee specific performanced limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: This device is a high performance RF integrated circuit with an ESD rating < 2 keV and is ESD sensitive. Handling and assembly of this device should only be done at ESD protected workstations. Note 3: See PROGRAMMABLE MODES for ICPo description. Note 4: Clock, Data and LE does not include fIN1, fIN2 and OSCin. Typical Performance Characteristics ICC vs VCC LMX2335/37 ICC vs VCC LMX2336 DS012332-19 DS012332-20 5 www.national.com Typical Performance Characteristics (Continued) Charge Pump Current vs Do Voltage ICP = HIGH Charge Pump Current vs Do Voltage ICP = LOW DS012332-21 LMX2335/37 Input Impedance (for SO package) VCC = 2.7V to 5.5V, fIN = 50 MHz to 1.5 GHz DS012332-22 LMX2335/37 Input Impedance (for TSSOP package) LMX2336 Input Impedance VCC = 2.7V to 5.5V, fIN = 50 MHz to 2.5 GHz DS012332-23 Marker Marker Marker Marker 1 2 3 4 = = = = 1 GHz, Real = 94, Imaginary = −118 1.2 GHz, Real = 72, Imaginary = −88 1.5 GHz, Real = 53, Imaginary = −45 500 MHz, Real = 201, Imaginary = −224 www.national.com DS012332-24 Marker Marker Marker Marker 6 1 2 3 4 = = = = 1 GHz, Real = 97, Imaginary = −146 1.89 GHz, Real = 43, Imaginary = −67 2.5 GHz, Real = 30, Imaginary = −33 500 MHz, Real = 189, Imaginary = −233 Typical Performance Characteristics (Continued) IDo TRI-STATE vs Do Voltage LMX2335/37 RF1 Sensitivity vs Frequency DS012332-26 DS012332-25 LMX2335/37 RF2 Sensitivity vs Frequency LMX2336 RF1 Sensitivity vs Frequency DS012332-27 DS012332-28 LMX2336 RF2 Sensitivity vs Frequency Oscillator Input Sensitivity vs Frequency DS012332-29 DS012332-30 7 www.national.com Functional Description The simplified block diagram below shows the 22-bit data register, two 15-bit R Counters and two 18-bit N Counters (intermediate latches are not shown). The data stream is clocked (on the rising edge of Clock) into the DATA register, MSB first. The data stored in the shift register is loaded into one of the 4 appropriate latches on the rising edge of LE. The last two bits are the Control Bits. The DATA is transferred into the counters as follows: Control Bits DATA Location C1 C2 0 0 RF2 R Counter 0 1 RF1 R Counter 1 0 RF2 N Counter 1 1 RF1 N Counter DS012332-1 PROGRAMMABLE REFERENCE DIVIDERS (RF1 AND RF2 R COUNTERS) If the Control Bits are 00 or 01 (00 for RF2 and 01 for RF1) data is transferred from the 22-bit shift register into a latch which sets the 15-bit R Counter. Serial data format is shown below. DS012332-4 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER) Divide R R R R R R R R R R R R R R R Ratio 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 • 32767 • 1 • 1 • 1 • 1 • 1 • 1 • • • • • • • • • 1 1 1 1 1 1 1 1 1 Notes: Divide ratios less than 3 are prohibited. Divide ratio: 3 to 32767 R1 to R15: These bits select the divide ratio of the programmable reference divider. Data is shifted in MSB first. www.national.com 8 Functional Description (Continued) PROGRAMMABLE DIVIDER (N COUNTER) Each N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control Bits are 10 or 11 (10 for RF2 counter and 11 for RF1 counter) data is transferred from the 20-bit shift register into a 7-bit latch (which sets the Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter), MSB first. Serial data format is shown below. DS012332-5 7-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) Divide Ratio A N 7 N 6 N 5 N 4 N 3 N 2 N 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 • 127 • 1 • 1 • 1 • 1 • 1 • 1 1 • Notes: Divide ratio: 0 to 127 B≥A A<P 11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO (B COUNTER) Divide Ratio B N 18 N 17 N 16 N 15 N 14 N 13 N 12 N 11 N 10 N 9 N 8 3 0 0 0 0 0 0 0 0 0 1 1 4 0 0 0 0 0 0 0 0 1 0 0 • 2047 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 • 1 1 • Notes: Divide ratio: 3 to 2047 (Divide ratios less than 3 are prohibited) B≥A PULSE SWALLOW FUNCTION fVCO = [(P x B) + A] x fOSC/R fVCO: Output frequency of external voltage controlled oscillator (VCO) B: A: fOSC: R: P: Preset divide ratio of binary 11-bit programmable counter (3 to 2047) Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ P; A ≤ B) Output frequency of the external reference frequency oscillator Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767) Preset modulus of dual moduIus prescaler (P = 64 or 128) PROGRAMMABLE MODES Several modes of operation can be programmed with bits R16–R20 including the phase detector polarity, charge pump tristate and the output of the FoLD pin. The prescaler and power down modes are selected with bits N19 and N20. The programmable modes are shown in Table 1. Truth table for the programmable modes and FoLD output are shown in Tables 2, 3. 9 www.national.com Functional Description (Continued) TABLE 1. Programmable Modes C1 C2 R16 R17 R18 R19 R20 0 0 RF2 Phase Detector Polarity RF2 ICPo RF2 Do TRI-STATE RF2 LD RF2 Fo 0 1 RF1 Phase Detector Polarity RF1 ICPO RF1 Do TRI-STATE RF1 LD RF1 Fo C1 C2 N19 N20 1 0 RF2 Prescaler Pwdn RF2 1 1 RF1 Prescaler Pwdn RF1 TABLE 2. Mode Select Truth Table RF1 Prescaler RF2 Prescaler Pwdn (Note 6) Phase Detector Polarity (Note 7) DoTRI-STATE 0 Negative Normal Operation LOW 64/65 64/65 pwrd up 1 Positive TRI-STATE HIGH 128/129 128/129 pwrd dn ICPo (Note 5) Note 5: The ICPo LOW current state = 1/4 x ICPo HIGH current. Note 6: Activation of the RF2 PLL or RF1 PLL powerdown modes result in the disabling of the respective N counter divider and debiasing of its respective fIN inputs (to a high impedance state). The powerdown function is gated by the charge pump to prevent unwanted frequency jumps. Once the powerdown program mode is loaded, the part will go into powerdown mode when the charge pump reaches a TRI-STATE condition. The R counter and Oscillator functionality does not become disabled until both RF2 and RF1 powerdown bits are activated. The OSCin is connected to VCC through 100 kΩ resistor and the OSCout goes HIGH when this condition exists. The MICROWIRE control register remains active and capable of loading and latching data during all of the powerdown modes. Note 7: PHASE DETECTOR POLARITY Depending upon VCO characteristics, the R16 bits should be set accordingly: When VCO characteristics are positive like (1), R16 should be set HIGH; When VCO characteristics are negative like (2), R16 should be set LOW. Note 8: VCO Characteristics DS012332-7 TABLE 3. The FoLD Output Truth Table RF1 R[19] (RF1 LD) RF2 R[19] (RF2 LD) RF1 R[20] (RF1 Fo) RF2 R[20] (RF2 Fo) 0 0 0 0 Disabled (Note 9) 0 1 0 0 RF2 Lock Detect (Note 10) 1 0 0 0 RF1 Lock Detect (Note 10) 1 1 0 0 RF1/RF2 Lock Detect (Note 10) X 0 0 1 RF2 Reference Divider Output X 0 1 0 RF1 Reference Divider Output X 1 0 1 RF2 Programmable Divider Output X 1 1 0 RF1 Programmable Divider Output 0 0 1 1 Fastlock (Note 11) 0 1 1 1 For Internal use only 1 0 1 1 For Internal use only 1 1 1 1 Counter Reset (Note 12) X — don’t care condition www.national.com 10 FoLD Output State Functional Description (Continued) Note 9: When the FoLD output is disabled it is actively pulled to a low logic state. Note 10: Lock detect output provided to indicate when the VCO frequency is in “lock”. When the loop is locked and a lock detect mode is selected, the pins output is HIGH, with narrow pulses LOW. In the RF1/RF2 lock detect mode a locked condition is indicated when RF2 and RF1 are both locked. Note 11: The Fastlock mode utilized the FoLD output pin to switch a second loop filter damping resistor to ground during fastlock operation. Activation of Fastlock occurs whenever the RF loop’s Icpo magnitude bit #17 is selected HIGH (while the #19 and #20 mode bits are set for Fastlock). Note 12: The Counter Reset mode bits R19 and R20 when activated reset all counters. Upon removal of the Reset bits the N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle). If the Reset bits are activated the R counter is also forced to Reset, allowing smooth acquisition upon powering up. SERIAL DATA INPUT TIMING DS012332-8 Notes: Parenthesis data indicates programmable reference divider data. Data shifted into register on clock rising edge. Data is shifted in MSB first. Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6V/ns with amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V. PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS DS012332-9 Notes: Phase difference detection range: −2π to +2π The minimum width pump up and pump down current pulses occur at the Do pin when the loop is locked. 11 www.national.com Typical Application Example DS012332-10 Operational Notes: * VCO is assumed AC coupled. RIN increases impedance so that VCO output power is provided to the load rather than the PLL. Typical values are 10Ω to 200Ω depending on the VCO power level. fIN RF impedance ranges from 40Ω to 100Ω. fIN IF impedances are higher. *** 50Ω termination is often used on test boards to allow use of external reference oscillator. For most typical products a CMOS clock is used and no terminating resistor is required. OSCin may be AC or DC coupled. AC coupling is recommended because the input circuit provides its own bias. (See Figure below). **** Adding RC filters to the VCC lines is recommended to reduce loop-to-loop noise coupling. ** DS012332-11 Application Hints: Proper use of grounds and bypass capacitors is essential to achieve a high level of performance. Crosstalk between pins can be reduced by careful board layout. This is an electrostatic sensitive device. It should be handled only at static free work stations. Application Information A block diagram of the basic phase locked loop is shown in Figure 1. DS012332-12 FIGURE 1. Conventional PLL Architecture www.national.com 12 Application Information A plot of the magnitude and phase of G(s) H(s) for a stable loop, is shown in Figure 4 with a solid trace. The parameter φp shows the amount of phase margin that exists at the point the gain drops below zero (the cutoff frequency wp of the loop). In a critically damped system, the amount of phase margin would be approximately 45 degrees. If we were now to redefine the cut off frequency, wp’, as double the frequency which gave us our original loop bandwidth, wp, the loop response time would be approximately halved. Because the filter attenuation at the comparison frequency also diminishes, the spurs would have increased by approximately 6 dB. In the proposed Fastlock scheme, the higher spur levels and wider loop filter conditions would exist only during the initial lock-on phase — just long enough to reap the benefits of locking faster. The objective would be to open up the loop bandwidth but not introduce any additional complications or compromises related to our original design criteria. We would ideally like to momentarily shift the curve Figure 4 over to a different cutoff frequency, illustrated by dotted line, without affecting the relative open loop gain and phase relationships. To maintain the same gain/phase relationship at twice the original cutoff frequency, other terms in the gain and phase Equations (5), (6) will have to compensate by the corresponding “1/w” or “1/w2” factor. Examination of Equations (3), (4), (5) indicates the damping resistor variable R2 could be chosen to compensate with “w” terms for the phase margin. This implies that another resistor of equal value to R2 will need to be switched in parallel with R2 during the initial lock period. We must also ensure that the magnitude of the open loop gain, H(s)G(s) is equal to zero at wp’ = 2 wp. KVCO, Kφ, N, or the net product of these terms can be changed by a factor of 4, to counteract with w2 term present in the denominator of Equations (3), (4). The Kφ term was chosen to complete the transformation because it can readily be switched between 1X and 4X values. This is accomplished by increasing the charge pump output current from 1 mA in the standard mode to 4 mA in Fastlock. (Continued) Loop Gain Equations A linear control system model of the phase feedback for a PLL in the locked state is shown in Figure 2 . The open loop gain is the product of the phase comparator gain (Kφ), the VCO gain (KVCO/s), and the loop filter gain Z(s) divided by the gain of the feedback counter modulus (N). The passive loop filter configuration used is displayed in Figure 3 , while the complex impedance of the filter is given in Equation (2). DS012332-14 FIGURE 2. PLL Linear Model DS012332-13 FIGURE 3. Passive Loop Filter (1) (2) The time constants which determine the pole and zero frequencies of the filter transfer function can be defined as Fastlock Circuit Implementation A diagram of the Fastlock scheme as implemented in National Semiconductors LMX2335/36/37 PLL is shown in Figure 5. When a new frequency is loaded, and the RF1 ICPo bit is set high, the charge pump circuit receives an input to deliver 4 times the normal current per unit phase error while an open drain NMOS on chip device switches in a second R2 resistor element to ground. The user calculates the loop filter component values for the normal steady state considerations. The device configuration ensures that as long as a second identical damping resistor is wired in appropriately, the loop will lock faster without any additional stability considerations to account for. Once locked on the correct frequency, the user can return the PLL to standard low noise operation by sending a MICROWIRE instruction with the RF1 ICPo bit set low. This transition does not affect the charge on the loop filter capacitors and is enacted synchronous with the charge pump output. This creates a nearly seamless change between Fastlock and standard mode. (3) (4) T2 = R2 • C2 The 3rd order PLL Open Loop Gain can be calculated in terms of frequency, ω, the filter time contants T1 and T2, and the design constants Kφ, KVCO, and N. (5) From Equation (3) we can see that the phase term will be dependent on the single pole and zero such that the phase margin is determined in Equation (5). (6) φ(ω) = tan−1 (ω • T2) −tan−1 (ω • T1) + 180˚C 13 www.national.com Application Information (Continued) DS012332-15 FIGURE 4. Open Loop Response Bode Plot DS012332-18 FIGURE 5. Fastlock PLL Architecture www.national.com 14 Physical Dimensions inches (millimeters) unless otherwise noted JEDEC 16-Lead (0.150" Wide) Small Outline Molded Package (M) Order Number LMX2335M or LMX2337M *For Tape and Reel (2500 Units Per Reel) Order Number LMX2335MX or LMX2337MX NS Package Number M16A 15 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TM) Order Number LMX2335TM or LMX2337TM *For Tape and Reel (2500 Units Per Reel) Order Number LMX2335TMX or LMX2337TMX NS Package Number MTC16 www.national.com 16 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead (0.173" Wide) Thin Shrink Small Outline Package (TM) Order Number LMX2336TM *For Tape and Reel (2500 Units Per Reel) Order Number LMX2336TMX NS Package Number MTC20 17 www.national.com LMX2335/LMX2336/LMX2337 PLLatinum Dual Frequency Synthesizer for RF Personal Communications Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.