High Precision ±10 V Reference AD688 FUNCTIONAL BLOCK DIAGRAM FEATURES ±10 V tracking outputs Kelvin connections Low tracking error: 1.5 mV Low initial error: 2.0 mV Low drift: 1.5 ppm/°C Low noise: 6 μV p-p Flexible output force and sense terminals High impedance ground sense Wide body SOIC and CERDIP packages The AD688 is available in commercial version. Specified over the −40oC to +85oC temperature range, the AD688 is offered in wide body 16-lead SOIC and 16-lead CERDIP packages, A3 IN +10V OUT SENSE 7 6 4 3 A3 AD688 A1 R1 1 +10V OUT FORCE 14 –10V OUT SENSE R4 A4 R2 15 –10V OUT FORCE 2 +VS R5 R6 R3 A2 5 9 10 8 12 11 13 GAIN ADJ GND SENSE +IN NC VLOW BAL ADJ NC A4 IN NC = NO CONNECT Figure 1. PRODUCT HIGHLIGHTS 1. Precision Tracking. The AD688 offers precision tracking ±10 V Kelvin output connections with no external components. Tracking error is less than 1.5 mV and finetrim is available for applications requiring exact symmetry between the +10 V and −10 V outputs. 2. Accuracy. The AD688 offers 12-bit absolute accuracy without any user adjustments. Optional fine-trim connections are provided for applications requiring higher precision. The fine-trimming does not alter the operating conditions of the Zener or the buffer amplifiers and thus does not increase the temperature drift. 3. Low output noise. Output noise of the AD688 is low— typically 6 μV p-p. A pin is provided for broadband noise filtering using an external capacitor. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 00815-001 16 –VS The AD688 is a high precision ±10 V tracking reference. Low tracking error, low initial error, and low temperature drift give the AD688 reference absolute ±10 V accuracy performance previously unavailable in monolithic form. The AD688 uses a proprietary ion-implanted buried Zener diode, and laser wafer drift trimming of high stability thin-film resistors to provide outstanding performance. The low initial error allows the AD688 to be used as a system reference in precision measurement applications requiring 12-bit absolute accuracy. In such systems, the AD688 can provide a known voltage for system calibration; the cost of periodic recalibration can therefore be eliminated. Furthermore, the mechanical instability of a trimming potentiometer and the potential for improper calibration can be eliminated by using the AD688 and calibration software. VHIGH RB GENERAL DESCRIPTION The AD688 includes the basic reference cell and three additional amplifiers. The amplifiers are laser-trimmed for low offset and low drift and maintain the accuracy of the reference. The amplifiers are configured to allow Kelvin connections to the load and/or boosters for driving long lines or high current loads, delivering the full accuracy of the AD688 where it is required in the application circuit. NOISE REDUCTION One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD688 TABLE OF CONTENTS Specifications..................................................................................... 3 Turn On Time................................................................................8 Absolute Maximum Ratings............................................................ 4 Temperature Performance............................................................9 ESD Caution.................................................................................. 4 Kelvin Connections.......................................................................9 Pin Configuration and Function Descriptions............................. 5 Dynamic Performance............................................................... 11 Theory of Operation ........................................................................ 6 Bridge Driver Circuit ................................................................. 12 Applications....................................................................................... 7 Outline Dimensions ....................................................................... 13 Calibration..................................................................................... 7 Ordering Guide .......................................................................... 13 Noise Performance and Reduction ............................................ 8 REVISION HISTORY 3/05—Rev. A to Rev. B Updated Format..................................................................Universal Added AD688ARWZ .........................................................Universal Removed AD688SQ ...........................................................Universal Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 13 Rev. B | Page 2 of 16 AD688 SPECIFICATIONS Typical @ 25°C, +10 V output, VS = ±15 V unless otherwise noted.1 Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed. Table 1. Min OUTPUT VOLTAGE ERROR +10 V, −10 V Outputs ±10 V TRACKING ERROR OUTPUT VOLTAGE DRIFT +10 V, −10 V Outputs 0°C to +70°C (A, B) −40°C to +85°C (A, B) GAIN ADJ AND BAL ADJ2 Trim Range Input Resistance LINE REGULATION TMIN to TMAX 3 LOAD REGULATION TMIN to TMAX +10 V Output, 0<IOUT<10 mA −10 V Output, −10<IOUT<0 mA SUPPLY CURRENT TMIN to TMAX Power Dissipation OUTPUT NOISE (ANY OUTPUT) 0.1 Hz to 10 Hz Spectral Density, 100 Hz LONG-TERM STABILITY (@ 25°C) BUFFER AMPLIFIERS Offset Voltage Offset Voltage Drift Bias Current Open-Loop Gain Output Current A3, A4 Common-Mode Rejection (A3, A4) VCM = 1 V p-p Short-Circuit Current TEMPERATURE RANGE Specified Performance A, B Grades AD688AQ Typ Max −5 −3 Min AD688BQ Typ Max Min +5 +3 −2 −1.5 +2 +1.5 −4 −1.5 +4 +1.5 mV mV +3 –1.5 –3 +1.5 +3 –8 +8 ppm/°C ppm/°C ±2 −3 ±5 150 –200 ±5 150 +200 –200 9 270 12 360 Unit mV kΩ +200 µV/V ±50 ±50 ±50 ±50 µV/mA µV/mA 12 360 12 360 mA mW –200 6 140 15 6 140 15 6 140 15 µV p-p nV√Hz ppm/1000 hours 100 1 20 110 100 1 20 110 100 1 20 110 µV µV/°C nA dB mA −10 +10 −10 100 50 −40 ±5 150 +200 ±50 ±50 9 270 AD688ARWZ Typ Max +10 −10 100 50 +85 −40 1 100 50 +85 See Figure 4 for output configuration. Gain and balance adjustments guaranteed capable of trimming output voltage error and symmetry error to zero. 3 Test Conditions: +VS = +18 V, −VS = –18 V; +VS = +13.5 V, −VS = −13.5 V. 2 Rev. B | Page 3 of 16 +10 −40 dB mA +85 °C AD688 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter +VS to −VS Power Dissipation (25°C) Q Package Storage Temperature Lead Temperature (Soldering, 10 s) Package Thermal Resistance Q (θJA/θJC) Output Protection: All outputs safe if shorted to ground Rating 36 V 600 mW −65°C to +150°C +300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 120/35°C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 4 of 16 AD688 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS +10V OUT FORCE 1 16 –VS +VS 2 15 –10V OUT FORCE 14 –10V OUT SENSE +10V OUT SENSE 3 AD688 TOP VIEW 13 A4 IN GAIN ADJ 5 (Not to Scale) 12 BAL ADJ VHIGH 6 11 NC NOISE REDUCTION 7 10 NC VLOW 8 9 GND SENSE +IN NC = NO CONNECT 00815-002 A3 IN 4 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic +10 V OUT FORCE +VS +10 V OUT SENSE A3 IN GAIN ADJ VHIGH NOISE REDUCTION 8 9 10 11 12 13 14 15 16 VLOW GND SENSE +IN NC NC BAL ADJ A4 IN −10 V OUT SENSE −10 V OUT FORCE −VS Description +10 V Output with Kelvin Force. Connect to Pin 3. Positive Power Supply. +10 V Output with Kelvin Sense. Connect to Pin 1. + Input to A3. Connect to VHIGH, Pin 6. Reference Gain Adjustment for Calibration. See the Calibration section. Unbuffered Reference High Output. Noise Filtering Pin. Connect external 1 µF capacitor to ground to reduce output noise, see the Noise Performance and Reduction section. May be left open. Unbuffered Reference Low Output. Gound with Kelvin Sense. No Connection. Leave floating. No Connection. Leave floating. Reference Centering Adjustment for Calibration. See the Calibration section. + Input to A4. Connect to VLOW, Pin 8. −10 V Output with Kelvin Sense. Connect to Pin 15. −10 V Output with Kelvin Force. Connect to Pin 14. Negative Power Supply. Rev. B | Page 5 of 16 AD688 THEORY OF OPERATION Amplifier A1 performs several functions. A1 primarily acts to amplify the Zener voltage to the required 20 V. In addition, A1 also provides for external adjustment of the 20 V output through Pin 5 (GAIN ADJ). Using the bias compensation resistor between the Zener output and the noninverting input to A1, a capacitor can be added at the noise reduction pin (Pin 7) to form a low-pass filter and reduce the noise contribution of the Zener to the circuit. Two matched 12 kΩ nominal thin-film resistors (R4 and R5) divide the 20 V output in half. Amplifiers A3 and A4 are internally compensated and are used to buffer the voltages at Pin 6 and Pin 8 as well as to provide a full Kelvin output. Thus, the AD688 has a full Kelvin capability by providing the means to sense a system ground, and forced and sensed outputs referenced to that ground. NOISE REDUCTION VHIGH A3 IN +10V OUT SENSE 7 6 4 3 A3 1 +10V OUT FORCE 14 –10V OUT SENSE 15 –10V OUT FORCE 2 +VS 16 –VS RB AD688 A1 R1 R4 A4 R2 Ground sensing for the circuit is provided by amplifier A2. The noninverting input (Pin 9) senses the system ground and forces the midpoint of resistors R4 and R5 to be a virtual ground. Pin 12 (BAL ADJ) can be used for fine adjustment of this midpoint transfer. R5 R6 R3 A2 5 9 10 8 12 11 13 GAIN ADJ GND SENSE +IN NC VLOW BAL ADJ NC A4 IN NC = NO CONNECT Figure 3. Functional Block Diagram Rev. B | Page 6 of 16 00815-003 The AD688 consists of a buried Zener diode reference, amplifiers and associated thin-film resistors as shown in Figure 3. The temperature compensation circuitry provides the device with a temperature coefficient of 1.5 ppm/°C or less. AD688 APPLICATIONS voltage and the position of the center tap within the span. The gain adjustment should be performed first. Although the trims are not interactive within the device, the gain trim will move the balance trim point as it changes the magnitude of the span. The AD688 can be configured to provide ±10 V reference outputs as shown in Figure 4. The architecture of the AD688 provides ground sense and uncommitted output buffer amplifiers which offer the user a great deal of functional flexibility. The AD688 is specified and tested in the configuration shown in Figure 4. The user may choose to take advantage of other configuration options available with the AD688; however performance in these configurations is not guaranteed to meet the stringent data sheet specifications. Unbuffered outputs are available at Pin 6 and Pin 8. Loading of these unbuffered outputs will impair circuit performance. Amplifiers A3 and A4 can be used interchangeably. However, the AD688 is tested (and the specifications are guaranteed) with the amplifiers connected as indicated in Figure 4. When either A3 or A4 is unused, its output force and sense pins should be connected and the input tied to ground. Two outputs of the same voltage polarity may be obtained by connecting both A3 and A4 to the appropriate unbuffered output on Pin 6 or Pin 8. Performance in these dual output configurations will typically meet data sheet specifications. Trimming the AD688 introduces no additional errors over temperature, so precision potentiometers are not required. 3 A3 +10V 1 When balance adjustment is not necessary, Pin 12 should be left floating. If gain adjustment is not required, Pin 5 should also be left floating. RB AD688 A1 14 R1 R4 A4 R2 –10V 15 +15V SUPPLY 8 12 11 13 7 4 6 3 0.1µF A3 SYSTEM GROUND +10V 1 RB –15V SUPPLY 00815-004 10 1µF SYSTEM GROUND A2 16 +15V NOISE REDUCTION 0.1µF R6 R3 9 20kΩ R5 2 5 Input impedance on both the GAIN ADJ and the BAL ADJ pins is approximately 150 kΩ. The gain adjustment trim network effectively attenuates the 20 V across the trim potentiometer by a factor of about 1150 to provide a trim range of –5.8 mV to +12.0 mV with a resolution of approximately 900 µV/turn (20-turn potentiometer). The balance adjustment trim network attenuates the trim voltage by a factor of about 1250, providing a trim range of ±8 mV with a resolution of 800 µV/turn. AD688 A1 14 R1 Figure 4. +10 V and −10 V Outputs R4 A4 R2 –10V 15 R5 CALIBRATION +15V SUPPLY 2 Generally, the AD688 will meet the requirements of a precision system without additional adjustment. Initial output voltage error of 2 mV and output noise specs of 6 µV p-p allow for accuracies of 12 to 16 bits. However, in applications where an even greater level of accuracy is required, additional calibration may be called for. The provision for trimming has been made through the use of the GAIN ADJ and BAL ADJ pins (Pin 5 and Pin 12, respectively). The AD688 provides a precision 20 V span with a center tap which is used with the buffer and ground sense amplifiers to achieve the ±10 V output configuration. GAIN ADJ and BAL ADJ can be used to trim the magnitude of the 20 V span 0.1µF R6 R3 SYSTEM GROUND A2 16 5 10 9 8 12 11 13 0.1µF –15V SUPPLY SYSTEM GROUND 100kΩ 20T BALANCE ADJUST 100kΩ 20T GAIN ADJUST Rev. B | Page 7 of 16 Figure 5. Gain and Balance Adjustment with Noise Reduction 00815-005 4 6 7 Figure 5 shows the gain and balance trims of the AD688. A 100 kΩ 20-turn potentiometer is used for each trim. The potentiometer for the gain trim is connected between Pin 6 (VHIGH) and Pin 8 (VLOW) with the wiper connected to Pin 5 (GAIN ADJ). The potentiometer is adjusted to produce exactly 20 V between Pin 1 and Pin 15, the amplifier outputs. The balance potentiometer, also connected between Pin 6 and Pin 8 with the wiper to Pin 12 (BAL ADJ), is then adjusted to center the span from +10 V to −10 V. AD688 NOISE PERFORMANCE AND REDUCTION The noise generated by the AD688 is typically less than 6 µV p-p over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz bandwidth is approximately 840 µV p-p. The dominant source of this noise is the buried Zener which contributes approximately 140 nV/√Hz. In comparison, the op amp’s contribution is negligible. Figure 6 shows the 0.1 Hz to 10 Hz noise of a typical AD688. any thermal tails when the horizontal scale is expanded to 2 ms/cm in Figure 9. 10V 1mV 100µs +VS 100 90 –VS 1mV 5s +VOUT 10 100 00815-008 0% 90 10V 1µV Figure 8. Turn On Characteristics: Electrical Turn On 10V 10 0% 1mV 2ms +VS 00815-006 100 90 Figure 6. 0.1 Hz to 10 Hz Noise –VS If further noise reduction is desired, an optional capacitor can be added between the noise reduction pin and ground as shown in Figure 5. This will form a low-pass filter with the 5 kΩ RB on the output of the Zener cell. A 1 µF capacitor will have a 3 dB point at 32 Hz and will reduce the high frequency noise (to 1 MHz) to about 250 µV p-p. Figure 7 shows the 1 MHz noise of a typical AD688 both with and without a 1 µF capacitor. 200µV +VOUT 10 00815-009 0% 10V Figure 9. Turn On Characteristics: Extended Time Scale Output turn on time is modified when an external noise reduction capacitor is used. When present, this capacitor presents an additional load to the internal Zener diode’s current source, resulting in a somewhat longer turn on time. In the case of a 1 µF capacitor, the initial turn on time is approximately 100 ms (Figure 10). 50µs CN = 1µF When the noise reduction feature is used, a 20 kΩ resistor between Pin 6 and Pin 2 is required for proper startup. NO CN 00815-007 10V 1mV 20ms +VS 100 90 Figure 7. Effect of 1 µF Noise Reduction Capacitor on Broadband Noise TURN ON TIME Rev. B | Page 8 of 16 –VS +VOUT 10 0% 10V Figure 10. Turn On With 1 µF CN 00815-010 Upon application of power (cold start), the time required for the output voltage to reach its final value within a specified error is the turn on settling time. Two components normally associated with this are: time for active circuits to settle and time for thermal gradients on the chip to stabilize. Figure 8 and Figure 9 show the turn on characteristics of the AD688. They show the settling time to be about 600 µs. Note the absence of AD688 MAXIMUM OUTPUT CHANGE (mV) TEMPERATURE PERFORMANCE = EMAX – EMIN (TMAX – TMIN) × 10 × 10–6 2.2mV – –3.2mV (85°C – –40°C) × 10 × 10–6 = 3ppm/°C 6 –10V OUT 4 +10V EMAX SLOPE 2 1 0 –1 –2 3.75 AD688BQ 1.05 3.75 4.0 Duplication of these results requires a combination of high accuracy and stable temperature control in a test system. Evaluation of the AD688 will produce curves similar to those in Figure 11, but output readings may vary depending on the test methods and equipment utilized. KELVIN CONNECTIONS Force and sense connections, also referred to as Kelvin connections, offer a convenient method of eliminating the effects of voltage drops in circuit wires. As seen in Figure 13a, the load current and wire resistance produce an error (VERROR = R × IL) at the load. The Kelvin connection of Figure 13b overcomes the problem by including the wire resistance within the forcing loop of the amplifier and sensing the load voltage. The amplifier corrects for any errors in the load voltage. In the circuit shown, the output of the amplifier would actually be at 10 V + VERROR and the voltage at the load would be the desired 10 V. +10V OUT R –3 i=0 +10V EMIN –4 –5 –6 –60 –50 –40 –30 –20 –10 0 TMIN V = 10V – RIL R IL RLOAD i=0 + 10V 10 20 30 40 50 60 70 80 90 100 110 120 130 TEMPERATURE (°C) R – a. TMAX b. R V = 10V IL RLOAD V = 10V + RIL 00815-014 3 –40°C TO +85°C 1.40 (TYP) Figure 12. Maximum + 10 V or −10 V Output Change 00815-011 ERROR VOLTAGE FROM ±10V (mV) 5 0 TO +70°C AD688AQ AD688ARWZ Figure 11 shows the typical output voltage drift and illustrates the test methodology. The box in Figure 11 is bounded on the sides by the operating temperature extremes, and on top and bottom by the maximum and minimum +10 V output error voltages measured over the operating temperature range. The slopes of the diagonals drawn for both the +10 V and –10 V outputs determine the performance grade of the device. +10V OUTPUT SLOPE = T.C. = DEVICE GRADE 00815-012 The AD688 is designed for precision reference applications where temperature performance is critical. Extensive temperature testing ensures that the device’s high level of performance is maintained over the operating temperature range. Figure 11. Typical AD688AQ Temperature Drift Figure 13. Advantage of Kelvin Connection Each AD688A and B grade unit is tested at −40°C, −25°C, 0°C, +25°C, +50°C, +70°C, and +85°C. This approach ensures that the variations of output voltage that occur as the temperature changes within the specified range will be contained within a box whose diagonal has a slope equal to the maximum specified drift. The position of the box on the vertical scale will change from device to device as initial error and the shape of the curve vary. Maximum height of the box for the appropriate temperature range is shown in Figure 12. The AD688 has three amplifiers which can be used to implement Kelvin connections. Amplifier A2 is dedicated to the ground force-sense function while uncommitted amplifiers A3 and A4 are free for other force-sense chores. In some applications, one amplifier may be unused. In such cases, the unused amplifier should be connected as a unity-gain follower (force and sense pins tied together) and the input should be connected to ground. An unused amplifier may be used for other circuit functions as well. Figure 14 through Figure 19 show the typical performance of A3 and A4. Rev. B | Page 9 of 16 AD688 100 0 100 40 –90 PHASE 20 –120 0 –150 80 70 60 50 40 30 20 00815-018 –60 60 PHASE (Degrees) GAIN 1k 100 10k 100k FREQUENCY (Hz) –180 10M 1M 00815-015 10 –20 10 0 1 10 Figure 14. A3, A4 Open-Loop Frequency Response 100 FREQUENCY (Hz) 10k 1k Figure 17. Input Noise Voltage Spectral Density 110 VS = ±15V VCM = 1V p-p 25°C 100 5V CMRR (dB) 80 50µs 100 90 60 40 20 10 00815-016 100 1k 10k 100k 1M 0% 00815-019 0 10 10M FREQUENCY (Hz) Figure 15. A3, A4 CMR vs. Frequency Figure 18. Unity-Gain Follower Pulse Response (Large Signal) 110 VS = ±15V WITH 1V p-p SINE WAVE 100 50mV +SUPPLY 80 2µs 100 90 60 –SUPPLY 40 20 100 1k 10k 100k FREQUENCY (Hz) 1M 0% 00815-020 10 10 10 00815-017 POWER SUPPLY REJECTION (dB) OPEN-LOOP GAIN (dB) –30 NOISE SPECTRAL DENSITY (nV/ Hz) 90 80 10M Figure 16. A3, A4 PSR vs. Frequency Figure 19. Unity-Gain Follower Pulse Response (Small Signal) Rev. B | Page 10 of 16 AD688 DYNAMIC PERFORMANCE A3 OR A4 The output buffer amplifiers (A3 and A4) are designed to provide the AD688 with static and dynamic load regulation superior to less complete references. VOUT 10V VL – Many A/D and D/A converters present transient current loads to the reference, and poor reference response can degrade the converter’s performance. 2kΩ 10V 0V Figure 23. Transient and Constant Load Test Circuit 1mV Figure 20, Figure 21, and Figure 22 display the characteristic of the AD688 output amplifier driving a 0 mA to 10 mA load. 2kΩ 00815-024 IL + VOUT 1mV/CM 1µs 200mV 100 90 A3 OR A4 VOUT 10V VL VOUT 200mV/ CM 1kΩ 10V 0V 00815-021 IL 10 0% Figure 20. Transient Load Test Circuit 00815-025 VL 5V 200mV 5V 500ns Figure 24. Transient Response 5 mA to 10 mA Load 100 In some applications, a varying load may be both resistive and capacitive in nature, or may be connected to the AD688 by a long capacitive cable. Figure 25 and Figure 26 display the output amplifier characteristics driving a 1000 pF, 0 mA to 10 mA load. 90 VOUT 10 VOUT 10V Figure 21. Large-Scale Transient Response 1mV 5V 1kΩ VL 10V 0V 00815-026 00815-022 VL 1000pF CL Figure 25. Capacitive Load Transient Response Test Circuit 2µs 200mV 100 1µs 100 90 CL = 0 90 VOUT CL = 1000pF 10 10 0% VL Figure 22. Fine-Scale Settling for Transient Load 5V 00815-027 0% 00815-023 VL Figure 26. Output Response with Capacitive Load Figure 23 and Figure 24 display the output amplifier characteristic driving a 5 mA to 10 mA load, a common situation found when the reference is shared among multiple converters or is used to provide bipolar offset current. Figure 27 and Figure 28 display the crosstalk between output amplifiers. The top trace shows the output of A4, dc-coupled and offset by 10 V, while the output of A3 is subjected to a 0 mA to 10 mA load current step. The transient at A4 settles in about 1 µs, and the load-induced offset is about 100 µV. Rev. B | Page 11 of 16 AD688 VOUT A3 1kΩ 10V VL – + 10V 10V 0V – 100 VIN 90 VOUT 10 00815-028 A4 + Figure 27. Load Crosstalk Test Circuit 1mV 2µs 5V 0% 100 10V 00815-032 90 200µs 1V Figure 31. Output Amplifier Step Response Using Figure 30 Compensation VOUT BRIDGE DRIVER CIRCUIT The Wheatstone bridge is a common transducer. In its simplest form, a bridge consists of four 2-terminal elements connected to form a quadrilateral, a source of excitation connected along one of the diagonals and a detector comprising the other diagonal. 10 0% 00815-029 VL Figure 28. Load Crosstalk Attempts to drive a large capacitive load (in excess of 1000 pF) may result in ringing or oscillation, as shown in the step response photo (Figure 29). This is due to the additional pole formed by the load capacitance and the output impedance of the amplifier, which consumes phase margin. The recommended method of driving capacitive loads of this magnitude is shown in Figure 30. The 150 Ω resistor isolates the capacitive load from the output stage, while the 10 kΩ resistor provides a dc feedback path and preserves the output accuracy. The 1 µF capacitor provides a high frequency feedback loop. The performance of this circuit is shown in Figure 31. In this unipolar drive configuration, the output voltage of the bridge is riding on a common-mode voltage signal equal to approximately VIN/2. Further processing of this signal may necessarily be limited to high common-mode rejection techniques such as instrumentation or isolation amplifiers. However, if the bridge is driven from a pair of bipolar supplies, then the common-mode voltage is ideally eliminated and the restrictions on any processing elements that follow are relaxed. As shown in Figure 32, the AD688 is an excellent choice for the control element in a bipolar bridge driver scheme. Transistors Q1 and Q2 serve as series pass elements to boost the current drive capability to the 57 mA required by the typical 350 Ω bridge. A differential gain stage may still be required if the bridge balance is not perfect. 100 +15V 90 220Ω 7 3 A3 10 1 – RB 0% 200µs 1V A1 00815-030 10V + EO AD688 14 R1 R4 220Ω Figure 29. Output Amplifier Step Response, CL = 1 µF A4 R2 15 R5 Q2 = 2N3906 10kΩ –15V 1µF R6 R3 2 +VS 16 –VS A2 150Ω + VIN – VOUT CL 1µF 5 9 10 8 12 11 13 00815-031 VOUT 4 6 Q1 = 2N3904 Figure 32. Bipolar Bridge Drive Figure 30. Compensation for Capacitive Loads Rev. B | Page 12 of 16 00815-033 VIN AD688 OUTLINE DIMENSIONS 0.098 (2.49) MAX 0.005 (0.13) MIN 16 9 1 8 PIN 1 0.200 (5.08) MAX 0.310 (7.87) 0.220 (5.59) 0.840 (21.34) MAX 0.060 (1.52) 0.015 (0.38) 0.320 (8.13) 0.290 (7.37) 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) BSC 0.023 (0.58) 0.014 (0.36) 0.015 (0.38) 0.008 (0.20) 15° 0° 0.070 (1.78) SEATING PLANE 0.030 (0.76) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 33. 16-Lead Ceramic Dual In-Line Package [CERDIP] (Q-16) Dimensions shown in inches and (millimeters) 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1 1.27 (0.0500) BSC 0.75 (0.0295) × 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 8° 0.33 (0.0130) 0° 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 34. 16-Lead Standard Small Outline Package [SOIC] Wide Body (RW-16) Dimensions shown in millimeter and (inches) ORDERING GUIDE Model AD688AQ AD688BQ AD688ARWZ1 1 Initial Error 5 mV 2 mV 4 mV Temperature Coefficient 3 ppm/°C 3 ppm/°C 8 ppm/°C Temperature Range −40°C to + 85°C −40°C to + 85°C −40°C to + 85°C Z = Pb-free part. Rev. B | Page 13 of 16 Package Description 16-Lead CERDIP 16-Lead CERDIP 16-Lead SOIC Package Option Q-16 Q-16 RW-16 AD688 NOTES Rev. B | Page 14 of 16 AD688 NOTES Rev. B | Page 15 of 16 AD688 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00815-0-3/05(B) Rev. B | Page 16 of 16