a
FEATURES
610 V Tracking Outputs
Kelvin Connections
Low Tracking Error – 1.5 mV
Low Initial Error – 2.0 mV
Low Drift – 1.5 ppm/8C
Low Noise – 6 mV p-p
Flexible Output Force and Sense Terminals
High Impedance Ground Sense
Machine Insertable DIP Packaging
MIL-STD-883 Compliant Versions Available
PRODUCT DESCRIPTION
The AD688 is a high precision ± 10 V tracking reference. Low
tracking error, low initial error and low temperature drift give
the AD688 reference absolute ± 10 V accuracy performance
previously unavailable in monolithic form. The AD688 uses a
proprietary ion-implanted buried Zener diode, and laser-waferdrift-trimming of high stability thin-film resistors to provide
outstanding performance at low cost.
The AD688 includes the basic reference cell and three additional
amplifiers. The amplifiers are laser-trimmed for low offset and
low drift and maintain the accuracy of the reference. The
amplifiers are configured to allow Kelvin connections to the
load and/or boosters for driving long lines or high current loads,
delivering the full accuracy of the AD688 where it is required in
the application circuit.
The low initial error allows the AD688 to be used as a system
reference in precision measurement applications requiring
12-bit absolute accuracy. In such systems, the AD688 can
provide a known voltage for system calibration and the cost of
periodic recalibration can therefore be eliminated. Furthermore,
the mechanical instability of a trimming potentiometer and the
potential for improper calibration can be eliminated by using
the AD688 and calibration software.
High Precision
610 V Reference
AD688*
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. The AD688 offers precision tracking ± 10 V Kelvin output
connections with no external components. Tracking error is
less than 1.5 mV and a fine-trim is available for applications
requiring exact symmetry between the +10 V and –10 V
outputs.
2. The AD688 offers 12-bit absolute accuracy without any user
adjustments. Optional fine-trim connections are provided for
applications requiring higher precision. The fine-trimming
does not alter the operating conditions of the Zener or the
buffer amplifiers and thus does not increase the temperature
drift.
3. Output noise of the AD688 is low – typically 6 µV p-p. A pin
is provided for broadband noise filtering using an external
capacitor.
4. The AD688 is available in versions compliant with MILSTD-883. Refer to the Analog Devices Military Products
Databook or current AD688/883B data sheet for detailed
specifications.
The AD688 is available in three versions. The AD688AQ and
BQ grades are packaged in 16-pin cerdip (0.3") packages and
are specified for operation from –40°C to +85°C. The AD688SQ
grade is specified for operation from –55°C to +125°C.
*Covered by Patent Number 4,644,253.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD688–SPECIFICATIONS (typical @ +258C, +10 V output, V = 615 V unless otherwise noted )
1
S
Min
AD688AQ/SQ
Typ
Max
Min
AD688BQ
Typ
Max
Units
OUTPUT VOLTAGE ERROR
+10 V, –10 V Outputs
–5
+5
–2
+2
mV
± 10 V TRACKING ERROR
–3
+3
–1.5
+1.5
mV
OUTPUT VOLTAGE DRIFT
+10 V, –10 V Outputs
0°C to +70°C (A, B)
–40°C to +85°C (A, B)
–55°C to +125°C (S)
–3
–6
–1.5
–3
+1.5
+3
ppm/°C
ppm/°C
ppm/°C
±2
GAIN ADJ AND BAL ADJ2
Trim Range
Input Resistance
LINE REGULATION
TMIN to TMAX3
+3
+6
+5
150
+5
150
–200
+200
LOAD REGULATION
TMIN to TMAX
+10 V Output, 0<IOUT <10 mA
–10 V Output, –10<IOUT<0 mA
–200
650
650
mV
kΩ
+200
µV/V
650
650
µV/mA
µV/mA
12
360
mA
mW
SUPPLY CURRENT
TMIN to TMAX
Power Dissipation
9
270
OUTPUT NOISE (ANY OUTPUT)
0.1 Hz to 10 Hz
Spectral Density, 100 Hz
6
140
6
140
µV p-p
nV√Hz
LONG TERM STABILITY (@ +25°C)
15
15
ppm/1000 hours
100
1
20
110
100
1
20
110
µV
µV/°C
nA
dB
mA
BUFFER AMPLIFIERS
Offset Voltage
Offset Voltage Drift
Bias Current
Open Loop Gain
Output Current A3, A4
Common Mode Rejection (A3, A4)
VCM = 1 V p-p
Short-Circuit Current
TEMPERATURE RANGE
Specified Performance
A, B Grades
S Grade
9
270
12
360
–10
+10
–10
100
50
+10
100
50
–40
–55
+85
+125
–40
dB
mA
+85
°C
°C
NOTES
1
See Figure 2a for output configuration. Specifications tested using +10 V output unless otherwise indicated.
2
Gain and balance adjustments guaranteed capable of trimming output voltage error and symmetry error to zero.
3
Test Condition: +V S = +18 V, –V S = –18 V; +V S = +13.5 V, V S = –13 .5 V.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
+VS to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 V
Power Dissipation (+25°C)
Q Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600 mW
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . +300°C
Package Thermal Resistance
Q (θJA/θJC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120/35°C/W
Output Protection: All outputs safe if shorted to ground
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
–2–
REV. A
AD688
ORDERING GUIDE
Part
Number1
Initial
Error
Temperature
Coefficient
Temperature
Range - 8C
Package
Option2
AD688AQ
AD688BQ
AD688SQ
5 mV
2 mV
5 mV
3 ppm/°C
3 ppm/°C
6 ppm/°C
–40 to +85
–40 to +85*
–55 to +125
Q-16
Q-16
Q-16
NOTES
1
For details on grade and package offerings screened in accordance with MIL-STD-883,
refer to the Analog Devices Military Products Databook or current AD688/883B data
sheet.
2
Q = Cerdip.
*Temperature coefficient specified from 0 to +70°C.
PIN CONFIGURATION
Amplifiers A3 and A4 are internally compensated and are used
to buffer the voltages at Pins 6 and 8 as well as to provide a full
Kelvin output. Thus, the AD688 has a full Kelvin capability by
providing the means to sense a system ground and provide
forced and sensed outputs referenced to that ground.
THEORY OF OPERATION
The AD688 consists of a buried Zener diode reference, amplifiers and associated thin-film resistors as shown in the block
diagram of Figure 1. The temperature compensation circuitry
provides the device with a temperature coefficient of 1.5 ppm/°C
or less.
Amplifier A1 performs several functions. A1 primarily acts to
amplify the Zener voltage to the required 20 volts. In addition,
A1 also provides for external adjustment of the 20 V output
through Pin 5, the GAIN ADJUST. Using the bias compensation resistor between the Zener output and the noninverting
input to A1, a capacitor can be added at the NOISE
REDUCTION pin (Pin 7) to form a low pass filter and reduce
the noise contribution of the Zener to the circuit. Two matched
12 kΩ nominal thin-film resistors (R4 and R5) divide the 20 V
output in half.
Ground sensing for the circuit is provided by Amplifier A2. The
noninverting input (Pin 9) senses the system ground and forces
the midpoint of resistors R4 and R5 to be a virtual ground. Pin
12 (BALANCE ADJUST) can be used for fine adjustment of
this midpoint transfer.
REV. A
Figure 1. AD688 Functional Block Diagram
–3–
AD688
APPLYING THE AD688
The AD688 can be configured to provide ± 10 V reference outputs as shown in Figure 2a. The architecture of the AD688 provides ground sense and uncommitted output buffer amplifiers
which offer the user a great deal of functional flexibility. The
AD688 is specified and tested in the configuration shown in
Figure 2a. The user may choose to take advantage of other
configuration options available with the AD688; however
performance in these configurations is not guaranteed to meet
the stringent data sheet specifications.
Unbuffered outputs are available at Pins 6 and 8. Loading of
these unbuffered outputs will impair circuit performance.
Amplifiers A3 and A4 can be used interchangeably. However,
the AD688 is tested (and the specifications are guaranteed) with
the amplifiers connected as indicated in Figure 2a. When either
A3 or A4 is unused, its output force and sense pins should be
connected and the input tied to ground.
Two outputs of the same voltage polarity may be obtained by
connecting both A3 and A4 to the appropriate unbuffered output on Pin 6 or 8. Performance in these dual output configurations will typically meet data sheet specifications.
20 V between Pins 1 and 15, the amplifier outputs. The BALANCE potentiometer, also connected between Pins 6 and 8
with the wiper to Pin 12 (BAL ADJ), is then adjusted to center
the span from +10 V to –10 V.
Input impedance on both the GAIN ADJUST and the BALANCE ADJUST pins is approximately 150 kΩ. The GAIN
ADJUST trim network effectively attenuates the 20 V across the
trim potentiometer by a factor of about 1150 to provide a trim
range of –5.8 mV to + 12.0 mV with a resolution of approximately 900 µV/turn (20 turn potentiometer). The BALANCE
ADJUST trim network attenuates the trim voltage by a factor of
about 1250, providing a trim range of ± 8 mV with a resolution
of 800 µV/turn.
Trimming the AD688 introduces no additional errors over
temperature, so precision potentiometers are not required.
In cases when BALANCE ADJUST is not necessary, Pin 12
should be left floating. If GAIN ADJUST is not required, Pin 5
should also be left floating.
Figure 2a. +10 V and –10 V Outputs
CALIBRATION
Generally, the AD688 will meet the requirements of a precision
system without additional adjustment. Initial output voltage
error of 2 mV and output noise specs of 6 µV p-p allow for
accuracies of 12-16 bits. However, in applications where an
even greater level of accuracy is required, additional calibration
may be called for. The provision for trimming has been made
through the use of the GAIN ADJUST and BALANCE
ADJUST pins (Pins 5 and 12, respectively).
The AD688 provides a precision 20 V span with a center tap
which is used with the buffer and ground sense amplifiers to
achieve the ± 10 V output configuration. The GAIN ADJUST
and BALANCE ADJUST can be used to trim the magnitude of
the 20 V span voltage and the position of the center tap within
the span. The GAIN ADJUST should be performed first. Although the trims are not interactive within the device, the GAIN
trim will move the BALANCE trim point as it changes the
magnitude of the span.
Figure 2b. Gain and Balance Adjust with Noise Reduction
NOISE PERFORMANCE AND REDUCTION
The noise generated by the AD688 is typically less than 6 µV
p-p over the 0.1 Hz to 10 Hz band. Noise in a 1 MHz
bandwidth is approximately 840 µV p-p. The dominant source
of this noise is the buried Zener which contributes approximately 140 nV/√Hz. In comparison, the op amp’s contribution
is negligible. Figure 3 shows the 0.1 Hz to 10 Hz noise of a
typical AD688.
Figure 2b shows the GAIN and BALANCE trims of the
AD688. A 100 kΩ 20-turn potentiometer is used for each trim.
The potentiometer for the GAIN trim is connected between
Pins 6 (VHIGH) and 8 (VLOW) with the wiper connected to Pin 5
(GAIN ADJ). The potentiometer is adjusted to produce exactly
Figure 3. 0.1 Hz to 10 Hz Noise
–4–
REV. A
AD688
When the NOISE REDUCTION feature is used, a 20 kΩ
resistor between Pins 6 and 2 is required for proper startup.
If further noise reduction is desired, an optional capacitor may
be added between the NOISE REDUCTION pin and ground as
shown in Figure 2b. This will form a low pass filter with the
5 kΩ RB on the output of the Zener cell. A 1 µF capacitor will
have a 3 dB point at 32 Hz and will reduce the high frequency
noise (to 1 MHz) to about 250 µV p-p. Figure 4 shows the 1 MHz
noise of a typical AD688 both with and without a 1µF capacitor.
Figure 6. Turn-On With 1 µ F CN
TEMPERATURE PERFORMANCE
The AD688 is designed for precision reference applications
where temperature performance is critical. Extensive temperature testing ensures that the device’s high level of performance is
maintained over the operating temperature range.
Figure 4. Effect of 1 µ F Noise Reduction Capacitor on
Broadband Noise
Figure 7 shows the typical output voltage drift for the
AD688SQ and illustrates the test methodology. The box in Figure 7 is bounded on the sides by the operating temperature
extremes and on top and bottom by the maximum and
minimum +10 V output error voltages measured over the
operating temperature range. The slopes of the diagonals drawn
for both the +10 V and –10 V outputs determine the performance grade of the device.
TURN-ON TIME
Upon application of power (cold start), the time required for the
output voltage to reach its final value within a specified error is
the turn-on settling time. Two components normally associated
with this are: time for active circuits to settle and time for thermal gradients on the chip to stabilize. Figure 5 shows the turnon characteristics of the AD688. It shows the settling time to be
about 600 µs. Note the absence of any thermal tails when the
horizontal scale is expanded to 2 ms/cm in Figure 5b.
a. Electrical Turn-On
Figure 7. Typical AD688SQ Temperature Drift
Each AD688A and B grade unit is tested at –40°C, –25°C, 0°C,
+25°C, +50°C, +70°C and +85°C. Each AD688S grade unit is
tested at –55°C, –25°C, +25°C, +70°C and +125°C. This
approach ensures that the variations of output voltage that occur
as the temperature changes within the specified range will be
contained within a box whose diagonal has a slope equal to the
maximum specified drift. The position of the box on the vertical
scale will change from device to device as initial error and the
shape of the curve vary. Maximum height of the box for the
appropriate temperature range is shown in Figure 8.
b. Extended Time Scale
Figure 5. Turn-On Characteristics
Output turn-on time is modified when an external noise reduction capacitor is used. When present, this capacitor presents an
additional load to the internal Zener diode’s current source,
resulting in a somewhat longer turn-on time. In the case of a
1 µF capacitor, the initial turn-on time is approximately 100 ms
(see Figure 6).
Figure 8. Maximum +10 V or –10 V Output Change
REV. A
–5–
AD688
Duplication of these results requires a combination of high
accuracy and stable temperature control in a test system.
Evaluation of the AD688 will produce curves similar to those in
Figure 7, but output readings may vary depending on the test
methods and equipment utilized.
KELVIN CONNECTIONS
Force and sense connections, also referred to as Kelvin connections, offer a convenient method of eliminating the effects of
voltage drops in circuit wires. As seen in Figure 9a, the load
current and wire resistance produce an error (VERROR = R × IL )
at the load. The Kelvin connection of Figure 9b overcomes the
problem by including the wire resistance within the forcing loop
of the amplifier and sensing the load voltage. The amplifier
corrects for any errors in the load voltage. In the circuit shown,
the output of the amplifier would actually be at 10 volts + VERROR
and the voltage at the load would be the desired 10 volts.
The AD688 has three amplifiers which can be used to implement Kelvin connections. Amplifier A2 is dedicated to the
ground force-sense function while uncommitted amplifiers A3
and A4 are free for other force-sense chores.
In some applications, one amplifier may be unused. In such
cases, the unused amplifier should be connected as a unity-gain
follower (force and sense pins tied together) and the input
should be connected to ground.
An unused amplifier may be used for other circuit functions as
well. The curves on this page show the typical performance of
A3 and A4.
Figure 9. Advantage of Kelvin Connection
A3, A4 Open-Loop Frequency
Response
Input Noise Voltage Spectral
Density
A3, A4 CMR vs. Frequency
Unity-Gain Follower Pulse
Response (Large Signal)
A3, A4 PSR vs. Frequency
Unity-Gain Follower Pulse
Response {Small Signal)
DYNAMIC PERFORMANCE
The output buffer amplifiers (A3 and A4) are designed to provide the AD688 with static and dynamic load regulation
superior to less complete references.
Many A/D and D/A converters present transient current loads
to the reference, and poor reference response can degrade the
converter’s performance.
Figure 10 displays the characteristic of the AD688 output
amplifier driving a 0-to-10 mA load.
Figure 10a. Transient Load Test Circuit
–6–
REV. A
AD688
In some applications, a varying load may be both resistive and
capacitive in nature, or be connected to the AD688 by a long
capacitive cable. Figure 12 displays the output amplifier characteristics driving a 1,000 pF, 0-to-10 mA load.
Figure 10b. Large-Scale Transient Response
Figure 12a. Capacitive Load Transient Response Test
Circuit
Figure 10c. Fine-Scale Settling for Transient Load
Figure 11 displays the output amplifier characteristic driving a
5 mA-to-10 mA load, a common situation found when the
reference is shared among multiple converters or is used to
provide bipolar offset current.
Figure 12b. Output Response with Capacitive Load
Figure 13 displays the crosstalk between output amplifiers. The
top trace shows the output of A4, dc-coupled and offset by 10
volts, while the output of A3 is subjected to a 0-to-10 mA load
current step. The transient at A4 settles in about 1 µs, and the
load-induced offset is about 100 µV.
Figure 11a. Transient and Constant Load Test Circuit
Figure 13a. Load Crosstalk Test Circuit
Figure 11b. Transient Response 5–10 mA Load
REV. A
Figure 13b. Load Crosstalk
–7–
In this unipolar drive configuration, the output voltage of the
bridge is riding on a common-mode voltage signal equal to
approximately VIN/2. Further processing of this signal may
necessarily be limited to high common-mode rejection
techniques such as instrumentation or isolation amplifiers.
However, if the bridge is driven from a pair of bipolar supplies,
then the common-mode voltage is ideally eliminated and the
restrictions on any processing elements that follow are relaxed.
Attempts to drive a large capacitive load (in excess of 1,000 pF)
may result in ringing or oscillation, as shown in the step response photo (Figure 14a). This is due to the additional pole
formed by the load capacitance and the output impedance of the
amplifier, which consumes phase margin. The recommended
method of driving capacitive loads of this magnitude is shown in
Figure 14b. The 150 Ω resistor isolates the capacitive load from
the output stage, while the 10 kΩ resistor provides a dc feedback
path and preserves the output accuracy. The 1 µF capacitor
provides a high frequency feedback loop. The performance of
this circuit is shown in Figure 14c.
As shown in Figure 15, the AD688 is an excellent choice for the
control element in a bipolar bridge driver scheme. Transistors
Q1 and Q2 serve as series pass elements to boost the current
drive capability to the 57 mA required by the typical 350 Ω
bridge. A differential gain stage may still be required if the
bridge balance is not perfect.
C1397–12–7/90
AD688
Figure 14a. Output Amplifier Step Response, CL = 1 µ F
Figure 15. Bipolar Bridge Drive
Figure 14b. Compensation for Capacitive Loads
OUTLINE DIMENSIONS
PRINTED IN U.S.A.
Dimensions shown in inches and (mm).
Figure 14c. Output Amplifier Step Response Using Figure
14b Compensation
BRIDGE DRIVER CIRCUIT
The Wheatstone bridge is a common transducer. In its simplest
form, a bridge consists of 4 two-terminal elements connected to
form a quadrilateral, a source of excitation connected along one
of the diagonals and a detector comprising the other diagonal.
–8–
REV. A