ETC PEF2466-H

H ar d wa r e Re f er e n c e M a n u a l , D S 1 , F e b . 2 0 0 1
®
SICOFI 4-µC
Four Channel Codec
Filter with PCM and
Microcontroller Interface
PE B 2 4 6 6 V e r sio n 2 .2
PE F 2 4 6 6 V e rsio n 2 .2
Wired
C om mu n i ca t i o n s
N e v e r
s t o p
t h i n k i n g .
Edition 2001-02-20
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2001.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address
list).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
H ar d wa r e Ref er e n c e M a n u a l , D S 1 , F e b . 2 0 0 1
®
SICOFI 4-µC
Four Channel Codec
Filter with PCM and
Microcontroller Interface
PE B 2 4 6 6 V e r sio n 2 .2
PE F 2 4 6 6 V e rsio n 2 .2
Wired
C om mu n i ca t i o n s
N e v e r
s t o p
t h i n k i n g .
•
PEB 2466
PEF 2466
Revision History:
Previous Version:
Page
Current Version 2001-02-20
DS 1
Data Sheet 02.97 DS2 (V 1.2)
Delta Sheet 11.98 DS2 (V 1.4)
Errata Sheet 05.98 DS1 (V 1.4)
Subjects (major changes since last revision)
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S,
ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2,
IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A,
OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®-2, SICOFI®-4, SICOFI®-4µC,
SLICOFI® are registered trademarks of Infineon Technologies AG.
ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of
Infineon Technologies AG.
PEB 2466
PEF 2466
Table of Contents
Page
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1
1.1
1.2
1.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
2.1
2.2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DSP-based Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Programming and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
4.1
4.1.1
4.1.2
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.8.1
4.2.8.2
4.2.9
4.2.10
4.2.11
4.2.12
4.2.13
4.2.14
4.2.15
4.2.16
4.2.17
4.2.18
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmission Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0 dBm0-Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compressor Gain Relative to Coding Law . . . . . . . . . . . . . . . . . . . . . . .
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gain Tracking (Receive and Transmit) . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Group Delay, Absolute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Group Delay Distortion with Frequency . . . . . . . . . . . . . . . . . . . . . . .
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Harmonic and Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . .
Total Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Frequency Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crosstalk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Out-of-Band Discrimination in Transmit Direction . . . . . . . . . . . . . . . . .
Out-of-Band Discrimination in Receive Direction . . . . . . . . . . . . . . . . . .
Out-of-Band Idle Channel Noise at Analog Output . . . . . . . . . . . . . . . .
Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5.1
5.1.1
Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Coupling Capacitors at the Analog Interface . . . . . . . . . . . . . . . . . . . . . 27
Hardware Reference Manual
2
3
4
4
12
12
12
12
14
14
14
15
16
17
17
18
18
18
19
19
20
20
22
22
22
23
24
25
26
2001-02-20
PEB 2466
PEF 2466
Table of Contents
Page
5.1.2
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.3.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
Analog Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCM Receive and Transmit Example . . . . . . . . . . . . . . . . . . . . . . . . . .
Signaling Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signaling Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debouncing Functions and Interrupt Generation . . . . . . . . . . . . . . . . . .
Clock Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Microcontroller Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Three-Wire Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
30
30
30
32
33
34
34
35
36
36
36
38
6
6.1
6.1.1
6.1.2
6.1.3
6.2
Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRAM Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Types of Commands and Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
39
39
40
41
42
7
7.1
7.1.1
7.2
7.2.1
7.3
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Support Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Guidelines for Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Filter Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Proposal for SICOFI®4-µC Board Design . . . . . . . . . . . . . . . . . . . . . . . . .
43
43
43
44
44
45
8
8.1
8.2
8.3
8.4.1
8.5
8.4
8.6
8.6.1
8.6.2
8.7
8.8
8.8.1
8.8.2
Electrical Characteristics and Timing Diagrams . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Coupling Capacitors at the Analog Interface . . . . . . . . . . . . . . . . . . . . .
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCM-Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Double Clocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontroller Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signaling Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing from the µC Interface to the SO/SB-pins . . . . . . . . . . . . . . . . . .
Timing from the SI/SB-pins to the µC Interface . . . . . . . . . . . . . . . . . . .
46
46
47
47
48
48
48
49
49
50
51
52
52
52
Hardware Reference Manual
2001-02-20
PEB 2466
PEF 2466
Table of Contents
Page
9
9.1
9.2
9.3
Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Cut-Off’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Hardware Reference Manual
53
53
54
55
2001-02-20
PEB 2466
PEF 2466
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Page
SICOFI®4-µC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SICOFI®4-µC Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Configuration of SICOFI®4-µC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SICOFI®4-µC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SICOFI®4-µC State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Analog and PCM Signal Levels in A-Law Mode . . . . . . . . . . . . . . . . . 15
Analog and PCM Signal Levels in µ-Law Mode . . . . . . . . . . . . . . . . . . 15
Simplified Signal Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Total Distortion Measured with Sine-Wave, Receive and Transmit . . . 20
Total Distortion Receive (Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Total Distortion Transmit (Noise) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Overload Compression (µ-Law Coding, Transmit Direction) . . . . . . . . 22
Out-of-Band Discrimination in Transmit Direction . . . . . . . . . . . . . . . . 23
Analog Output: Out-of-Band Signals . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Analog Output: Out-of-Band Idle Channel Noise . . . . . . . . . . . . . . . . . 25
Analog Interface to Four Subscriber Line Interface Circuits (SLICs) . . 28
PCM Interface Example: Location of Time Slots . . . . . . . . . . . . . . . . . 31
PCM Interface Example: Detail A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Signaling Example: Four Subscriber Lines . . . . . . . . . . . . . . . . . . . . . 33
Serial Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Example for a Two-Byte Write Access. . . . . . . . . . . . . . . . . . . . . . . . . 36
Example for a One-Byte Read Access . . . . . . . . . . . . . . . . . . . . . . . . 37
Example for a Read Access with Byte-by-Byte Transfer . . . . . . . . . . . 37
Bi-Directional Data Signal: DIN and DOUT Strapped Together. . . . . . 38
Channel-Specific and Common Coefficients . . . . . . . . . . . . . . . . . . . . 41
Development System with STUT 2466 Evaluation Board . . . . . . . . . . 43
SICOFI®4-µC Test Circuit Configuration . . . . . . . . . . . . . . . . . . . . . . . 44
Proposal for a ground concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PCM Interface Timing in Single Clocking Mode. . . . . . . . . . . . . . . . . . 49
PCM Interface Timing in Double Clocking Mode . . . . . . . . . . . . . . . . . 50
Timing of the Microcontroller Interface. . . . . . . . . . . . . . . . . . . . . . . . . 51
Signaling Output Timing (data downstream) . . . . . . . . . . . . . . . . . . . . 52
Analog Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Digital Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Cut-Off’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Hardware Reference Manual
2001-02-20
PEB 2466
PEF 2466
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Page
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Register Values and Accessibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Input and Output Pin Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Maximum Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Analog Voltage Levels Corresponding to 0 dBm0-Level . . . . . . . . . . . 14
Gain Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Gain Deviations with Input Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Attenuation with Frequency in Transmit and Receive Direction. . . . . . 18
Group Delay, Absolute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Group Delay Distortion with Frequency . . . . . . . . . . . . . . . . . . . . . . . . 19
Idle Channel Noise in Transmit Direction. . . . . . . . . . . . . . . . . . . . . . . 19
Idle Channel Noise in Receive Direction . . . . . . . . . . . . . . . . . . . . . . . 19
Harmonic and Intermodulation Distortion. . . . . . . . . . . . . . . . . . . . . . . 20
Signal-to-Total Distortion Ratio Measured with Sine Wave . . . . . . . . . 20
Signal-to-Total Distortion Ratio Measured with Noise . . . . . . . . . . . . . 21
Crosstalk Between Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Out-of-Band Signals Applied to the Analog Inputs (VINx) . . . . . . . . . . 23
Out-of-Band Signals at the Analog Outputs (VOUTx) . . . . . . . . . . . . . 24
Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Analog Interface Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PCM Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PCM Register Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . 31
Signaling Interface: Pins and Functions for SLIC Interfaces . . . . . . . . 34
Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Serial Microcontroller Interface: Pins and Functions . . . . . . . . . . . . . . 36
Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Read Access to Common Configuration Register (XR) Map . . . . . . . . 40
Write Access to Common Configuration Register (XR) Map . . . . . . . . 40
Channel-Specific Configuration Register (CR) Map (Read & Write) . . 40
Coefficient RAM (CRAM) Structure per Channel . . . . . . . . . . . . . . . . . 41
Coefficient RAM (CRAM) Structure per Set . . . . . . . . . . . . . . . . . . . . . 42
Types of Commands and Data Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . 42
Analog Loop Programming in Register CR3, Bits 7 to 4 . . . . . . . . . . . 53
Digital Loop Programming in Register CR3, Bits 7 to 4 . . . . . . . . . . . . 54
Cut-Off Programming in Register CR2, Bits 7 to 5. . . . . . . . . . . . . . . . 55
Hardware Reference Manual
2001-02-20
PEB 2466
PEF 2466
Preface
This document provides detailed technical information about the SICOFI®4-µC. It is
intended for anyone considering or using the device for system design or board layout
for a broad range of analog telephony applications. All content applies to both the
standard PEB 2466 and the extended temperature version, PEF 2466, unless specified.
Organization of this Document
This Hardware Reference Manual is organized as follows:
• Chapter 1, Overview
Includes a general description of the architecture, feature list, and logic symbol.
• Chapter 2, Pin Descriptions
Illustrates the Pin Configuration and provides detailed functional descriptions.
• Chapter 3, Functional Description
Provides a block diagram and summarizes the major functional blocks.
• Chapter 4, Operational Description
Begins with a state diagram and description of the operating states of all four channels
and concludes with detailed transmission characteristics.
• Chapter 5, Interface Descriptions
Describes the Analog, PCM, Signaling, and Serial Microcontroller interfaces.
• Chapter 6, Programming Overview
Illustrates the register model and coefficient RAM structure, provides a register map
and summary, and identifies the programming command sequences.
• Chapter 7, Application Hints
Describes the development system available for the PEB 2466, and provides
guidelines and schematics for board layout.
• Chapter 8, Electrical Characteristics and Timing Diagrams
Provides detailed tables for the electrical characteristics and includes timing diagrams
for the Analog, PCM, Serial Microcontroller, and Signaling interfaces.
• Chapter 9, Test Configuration
Describes the test loops and cut-offs available for functional tests and diagnostics.
• Chapter 10, Package Outlines
Illustrates the P-MQFP-64 package in which the PEB 2466 is manufactured.
• The Appendix
Includes a glossary and an index.
Related Documentation
Other documentation for the PEB 2466 includes a Product Brief, a Product Overview, a
Programmer’s Reference Manual, and assorted Application Notes. Similar
documentation is also available for the other members of the SICOFI Codec family
including the PSB 2132, PSB 2134, and PEB 2266. Documentation is available by
accessing our website: http://www.infineon.com/sicofi
Hardware Reference Manual
1
2001-02-20
PEB 2466
PEF 2466
Overview
1
Overview
The four-channel codec filter PEB 2466 SICOFI®4-µC is built around a central DSP-core
which provides independent filter structures for all channels. Its analog I/O pins are used
to connect to external subscriber line interface circuits (SLICs). Their signals are
internally routed to the analog-to-digital and digital-to-analog converters (ADC, DAC).
The signaling pins carry line status and control information to and from the SLICs. Two
programmable clock outputs are available. The SICOFI®4-µC connects to the digital
switching and transmission system through two PCM Highways. The digitized voice
band signals are available as A-Law or µ-Law codes within selectable 8-bit time slots.
The SICOFI®4-µC modes, features, and filter characteristics are programmed through a
serial interface to a microcontroller. The access mechanism is very simple, and can be
implemented with as few as three I/O ports. The PEB 2466 is available for standard
temperature range applications (0 °C to +70 °C); the PEF 2466 is available for extended
temperature range applications (-40 °C to +85 °C).
PEB 2466
SICOFI4-µC
SLIC 1
t/r
SLIC 2
t/r
SLIC 3
t/r
SLIC 4
ADC - DAC
Digital Filters
Channel 1
Signaling
Digital Filters
Channel 2
ADC - DAC
Signaling
Digital Filters
Channel 3
ADC - DAC
Signaling
Highway A
Highway B
Digital Filters
Channel 4
ADC - DAC
Signaling
PLL,
Clocking
PCM Interface
t/r
DSP Core
Status and Control
Registers
CRAM
Serial Microcontroller Interface
2466_201
Figure 1
SICOFI®4-µC Architecture
Hardware Reference Manual
2
2001-02-20
Four Channel Codec Filter with PCM and
Microcontroller Interface
SICOFI®4-µC
Version 2.2
1.1
PEB 2466
PEF 2466
CMOS
Features
• Four-channel single chip codec with digital filters
• High analog driving capability (300 Ω, 50 pF) for
direct driving of transformers
• Digital Signal Processing (DSP) technique
• Programmable digital filters to adapt transmission
behavior, especially for:
– AC impedance matching
P-MQFP-64
– Transhybrid balancing
– Frequency response
– Signal levels
– A/µ-Law compression and expansion
• Fulfills international (e.g. ITU-T Q.552, G.712) and country-specific requirements
• High performance ADC and DAC for excellent linearity and dynamic gain
• Programmable Analog Interface to electronic SLICs or transformer solutions
• Seven SLIC-signaling I/O pins per channel with programmable debouncing
• Two PCM Highways accessible by on-chip PCM Interface with Programmable time
slot assignment and variable data rates from 128 kbit/s to 8 Mbit/s
• Easy to use 4-pin Serial Microcontroller Interface (SPI compatible) for read/write
access
• Single supply voltage (5 V)
• Advanced low-power mixed-signal CMOS technology
• Two programmable tone generators per channel (DTMF possible)
• Level metering function for system tests and for analog input signal testing
• Advanced on-chip functions for device and system diagnostics and manufacturing test
– Five digital loops
– Four analog loops
• Support tools include:
– Hardware development board — STUT 2466
– QSICOS Coefficient Calculation and Register Configuration Software
• Standard P-MQFP-64 package
Type
Package
PEB 2466 Version 2.2
P-MQFP-64
PEF 2466 Version 2.2
P-MQFP-64
Hardware Reference Manual
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PEB 2466
PEF 2466
Overview
1.2
Logic Symbol
Analog
Interface
Channel
1
VIN1
VOUT1
Channel
2
VOUT2
Channel
3
VIN3
VOUT3
Channel
4
VIN4
VIN2
VOUT4
CHCLK1
CHCLK2
DRA
DXA
TCA#
Highway
A
DRB
DXB
TCB#
Highway
B
FSC
PCLK
PCM
Clocks
MCLK
Master Clock
SICOFI®4-µC
Channel
1
SI1_0
SI1_1
SO1_0
SO1_1
SB1_0
SB1_1
SB1_2
Channel
2
SI2_0
SI2_1
SO2_0
SO2_1
SB2_0
SB2_1
SB2_2
SI4_0
SI4_1
SO4_0
SO4_1
SB4_0
SB4_1
SB4_2
INT12
INT34
Signaling
Interface
Ch. 1&2
RESET#
PEB 2466
SI3_0
SI3_1
SO3_0
SO3_1
SB3_0
SB3_1
SB3_2
Channel
3
Channel
4
1.3
Signaling
Interface
Ch. 3&4
DOUT DIN DCLK CS#
Microcontroller Interface
Figure 2
PCM
Interface
2466_203
SICOFI®4-µC Logic Symbol
Typical Applications
Many applications will benefit from the versatility of the SICOFI®4-µC codec and filter.
The inherent flexibility enables several products to be developed around one basic
architecture, thus affording potentially significant savings in time to market, inventory
costs, and support administration.
The following list represents some of the typical applications for which the SICOFI®4-µC
codec was designed: Analog linecards for Central Offices and PBXs, Small PBX or
Key Systems, Digital Loop Carrier (DLC) Systems, Digital Added Main Lines (DAML)
Systems, Fiber-to-the-Curb (FTTC) Systems, Radio-in-the-Loop (RITL) Systems, and
any Multi-channel, digital voice processing, storage, or communication applications.
Refer to the Product Overview, Chapter 5 Application Hints for more information.
Hardware Reference Manual
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PEB 2466
PEF 2466
Pin Descriptions
2
Pin Descriptions
2.1
Pin Diagram
(top view)
SI2_1
SI2_0
SB2_2
SB2_1
SB2_0
SO2_1
SO2_0
SO1_0
SO1_1
SB1_0
SB1_1
SB1_2
SI1_0
SI1_1
INT12
CHCLK1
P-MQFP-64
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GNDA1
VOUT1
VDDA12
VOUT2
GNDA2
VIN2
VREF
VDDREF
VIN3
GNDA3
VOUT3
VDDA34
VOUT4
GNDA4
VIN4
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
SICOFI®4-µC
PEB 2466-H
2 3
4
5
6
PCLK
FSC
DRB
DXB
TCB#
DRA
DXA
TCA#
VDDD
RESET#
MCLK
GNDD
DOUT
DIN
DCLK
CS#
7 8 9 10 11 12 13 14 15 16
SI3_1
SI3_0
SB3_2
SB3_1
SB3_0
SO3_1
SO3_0
SO4_0
SO4_1
SB4_0
SB4_1
SB4_2
SI4_0
1
Figure 3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SI4_1
INT34
CHCLK2
VIN1
2466_204
Pin Configuration of SICOFI®4-µC
Hardware Reference Manual
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2001-02-20
PEB 2466
PEF 2466
Pin Descriptions
2.2
Pin Definitions and Functions
Table 1
Pin Definitions and Functions
Pin Symbol Type Function
Ch.
1
SI3_1
I
Signaling Input, Channel 3 Pin 1
3
2
SI3_0
I
Signaling Input, Channel 3 Pin 0
3
3
SB3_2
I/O
Bi-directional Signaling, Channel 3 Pin 2
3
4
SB3_1
I/O
Bi-directional Signaling, Channel 3 Pin 1
3
5
SB3_0
I/O
Bi-directional Signaling, Channel 3 Pin 0
3
6
SO3_1
O
Signaling Output, Channel 3 Pin 1
3
7
SO3_0
O
Signaling Output, Channel 3 Pin 0
3
8
SO4_0
O
Signaling Output, Channel 4 Pin 0
4
9
SO4_1
O
Signaling Output, Channel 4 Pin 1
4
10
SB4_0
I/O
Bi-directional Signaling, Channel 4 Pin 0
4
11
SB4_1
I/O
Bi-directional Signaling, Channel 4 Pin 1
4
12
SB4_2
I/O
Bi-directional Signaling, Channel 4 Pin 2
4
13
SI4_0
I
Signaling Input, Channel 4 Pin 0
4
14
SI4_1
I
Signaling Input, Channel 4 Pin 1
4
15
INT34
O
Interrupt Output Channels 3 and 4
Active high.
O
Chopper Clock Output 2
Provides 256, 512, or 16384 kHz signal; sync. to MCLK.
all
I
Chip Select
Microcontroller Interface chip select, enable to read or
write; active low
all
I
Data Clock
Microcontroller Interface data clock, shifts data from or to
device; maximum clock rate 8192 kHz.
all
I
Data Input
Microcontroller Interface control data input pin; DCLK
determines data rate.
all
O
Data Output
Microcontroller Interface control data output pin; DCLK
determines data rate: DOUT is high impedance "Z" if no
data is transmitted from the SICOFI®4-µC.
all
16 CHCLK2
17
18
19
20
CS#
DCLK
DIN
DOUT
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PEB 2466
PEF 2466
Pin Descriptions
Pin Symbol Type Function
21
GNDD
Ch.
I
Digital Ground
Ground reference for all digital signals.
Internally isolated from GNDA1,2,3,4.
all
all
22
MCLK
I
Master Clock Input
1536, 2048, 4096 or 8192 kHz must be applied for any
operation (selected in Register XR5).
MCLK, PCLK, FSC must be synchronous.
23
RESET#
I
Reset Input
Forces the device to default setting mode; active low.
all
24
VDDD
I
Digital Supply Voltage
+5 V supply for digital circuits (use 100 nF blocking cap.).
all
O
Transmit Control Output A
PCM Interface: active if data is transmitted via DXA;
active low, open drain.
all
all
25
TCA#
26
DXA
O
Data Transmit to PCM-Highway A
PCM Interface: PCM data for each channel is transmitted
in 8-bit bursts every 125 µs.
27
DRA
I
Data Receive from PCM-Highway A
PCM Interface: PCM data for each channel is received in
8-bit bursts every 125 µs.
all
O
Transmit Control Output B
PCM Interface: active if data is transmitted via DXB;
active low, open drain.
all
O
Data Transmit to PCM-highway B
PCM Interface: data for each channel is transmitted in
8-bit bursts every 125 µs.
all
I
Data Receive from PCM-highway B
PCM Interface: data for each channel is received in 8-bit
bursts every 125 µs.
all
I
Frame Synchronization Clock
8 kHz; reference for individual time slots, indicates start of
PCM frame; MCLK, PCLK, FSC must be synchronous.
all
I
PCM Data Clock
128 to 8192 kHz; determines the rate at which PCM data
is shifted into or out of the PCM-ports.
MCLK, PCLK, FSC must be synchronous.
all
28
29
30
31
32
TCB#
DXB
DRB
FSC
PCLK
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2001-02-20
PEB 2466
PEF 2466
Pin Descriptions
Pin Symbol Type Function
Ch.
33 CHCLK1
O
Chopper Clock Output 1
Provides programmable (2 … 28 ms) output signal
(synchronous to MCLK).
34
INT12
O
Interrupt Output, Channels 1 and 2
Active high.
35
SI1_1
I
Signaling Input Channel 1, Pin 1
1
36
SI1_0
I
Signaling Input Channel 1, Pin 0
1
37
SB1_2
I/O
Bi-directional Signaling, Channel 1 Pin 2
1
38
SB1_1
I/O
Bi-directional Signaling, Channel 1 Pin 1
1
39
SB1_0
I/O
Bi-directional Signaling, Channel 1 Pin 0
1
40
SO1_1
O
Signaling Output, Channel 1, Pin 1
1
41
SO1_0
O
Signaling Output, Channel 1, Pin 0
1
42
SO2_0
O
Signaling Output, Channel 2, Pin 0
2
43
SO2_1
O
Signaling Output, Channel 2, Pin 1
2
44
SB2_0
I/O
Bi-directional Signaling, Channel 2 Pin 0
2
45
SB2_1
I/O
Bi-directional Signaling, Channel 2 Pin 1
2
46
SB2_2
I/O
Bi-directional Signaling, Channel 2 Pin 2
2
47
SI2_0
I
Signaling Input, Channel 2, Pin 0
2
48
SI2_1
I
Signaling Input, Channel 2, Pin 1
2
49
VIN1
I
Analog Voice (Voltage) Input, Channel 1
Requires a coupling capacitor >39 nF to the SLIC.
1
50
GNDA1
I
Analog Ground, Channel 1
Not internally connected to GNDD or GNDA2,3,4.
1
1
all
1, 2
51
VOUT1
O
Analog Voice (Voltage) Output, Channel 1
Requires a coupling capacitor to the SLIC. The capacitor
value depends on the SLIC’s input impedance.
(See Chapter 5.1 Analog Interface)
52
VDDA12
I
Analog Supply Voltage, Channels 1 and 2
+5 V (100 nF blocking capacitor required).
O
Analog Voice (Voltage) Output, Channel 2
Requires a coupling capacitor to the SLIC. The capacitor
value depends on the SLIC’s input impedance.
(See Chapter 5.1 Analog Interface)
53
VOUT2
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PEB 2466
PEF 2466
Pin Descriptions
Pin Symbol Type Function
Ch.
54
GNDA2
I
Analog Ground, Channel 2
Not internally connected to GNDD or GNDA 1,3,4.
2
55
VIN2
I
Analog Voice (Voltage) Input, Channel 2
Requires a coupling capacitor >39 nF to the SLIC.
2
56
VREF
I/O
Reference Voltage
Must connect to a 220 nF cap. to ground.
all
57
VDDREF
I
Analog Supply Reference Voltage
+5 V (100 nF blocking capacitor required).
all
58
VIN3
I
Analog Voice (Voltage) Input, Channel 3
Requires a coupling capacitor >39 nF to the SLIC.
3
59
GNDA3
I
Analog Ground, Channel 3
Not internally connected to GNDD or GNDA1,2,4.
3
3
60
VOUT3
O
Analog Voice (Voltage) Output, Channel 3
Requires a coupling capacitor to the SLIC. The capacitor
value depends on the SLIC’s input impedance.
(See Chapter 5.1 Analog Interface)
61
VDDA34
I
Analog Supply Voltage, Channels 3 and 4
+5 V (100 nF blocking capacitor required).
3
4
62
VOUT4
O
Analog Voice (Voltage) Output, Channel 4
Requires a coupling capacitor to the SLIC. The capacitor
value depends on the SLIC’s input impedance.
(See Chapter 5.1 Analog Interface)
63
GNDA4
I
Analog Ground, Channel 4
Not internally connected to GNDD or GNDA1,2,3.
4
64
VIN4
I
Analog Voice (Voltage) Input, Channel 4
Requires a coupling capacitor >39 nF to the SLIC.
4
Hardware Reference Manual
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PEB 2466
PEF 2466
Functional Description
3
Functional Description
The telephone subscriber loop is a bi-directional two-wire line. The Subscriber Line
Interface Circuit (SLIC) on the network side converts the two-wire interface to a four-wire
interface with separate receive and transmit signals, which connect to the SICOFI®4-µC.
The SLIC can be either a transformer or an electronic circuit with operational amplifiers.
It must have a defined input impedance towards the subscriber line for maximum signal
power transfer and return loss. The requirements for the input impedance vary from
country to country and demand impedance matching to the different environments.
Country-specific adaptations are also required for the transhybrid loss, which is a loss
between the transmit and the receive ports of the two-wire to four-wire hybrid.
3.1
DSP-based Architecture
The impedance matching and transhybrid balancing functions are performed by loop
filters between the transmit path (analog to PCM) and the receive path (PCM to analog).
The filter characteristics must be adjusted according to the local requirements of each
market. In the analog domain, filters must be optimized in hardware; this is generally
both tedious and time-consuming. This is not the case with the DSP-based SICOFI®4µC four-channel codec. Its integrated signal processor implements the impedance
matching and transhybrid balancing functions as digital, programmable filters. It also
performs frequency response corrections and level adjustments to enable the design of
a truly universal and internationally applicable telephone linecard. Transmission
characteristics and frequency behavior are enhanced by the accuracy of the digital
filters, which do not fluctuate over temperature or with age.
As an additional benefit of its DSP-based architecture, the PEB 2466 also provides two
tone generators per channel. An on-chip level-metering unit allows line-characterization
without extra hardware; it can also be used to detect specific tones, e.g., modem tones.
3.2
Programming and Control
A very simple Microcontroller Interface is used to program the SICOFI®4-µC functions.
The same port provides access to 28 general purpose I/O pins of the Signaling Interface.
This allows efficient and convenient monitoring and control of other linecard functions,
such as on-/off-hook detection, ground-key detection, switching of ring signals and test
relays. The Serial Microcontroller Interface provides a programming and control
interface and is generic and non-proprietary for use with any microcontroller. It can be
implemented with as few as three signal lines, since the data receive and data transmit
pins may be strapped together.
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PEB 2466
PEF 2466
Functional Description
PEB 2466, SICOFI4-µC
VIN1
ADC
VOUT1
DAC
VIN2
ADC
VOUT2
DAC
VIN3
ADC
VOUT3
DAC
VIN4
ADC
VOUT4
DAC
MCLK
CHCLK1
CHCLK2
Hardware
Filters
Programmable
Filters and Gain
A-Law
or
µ-Law
Hardware
Filters
Programmable
Filters and Gain
A-Law
or
µ-Law
Hardware
Filters
Programmable
Filters and Gain
A-Law
or
µ-Law
Hardware
Filters
Programmable
Filters and Gain
A-Law
or
µ-Law
Digital Signal Processing
Compander
Highway A
DXA
DRA
TCA#
PCMInterface
FSC
PCLK
with
Time Slot
Assignment
Highway B
DXB
DRB
TCB#
PLL,
Clocking
Registers and CRAM
SIx_y
SOx_y
Signaling Interface
Serial Microcontroller Interface
SBx_y
INT34
Figure 4
INT12
DCLK
CS#
DIN
DOUT
2466_205
SICOFI®4-µC Block Diagram
Figure 4 shows the functional blocks and the interface pins of the SICOFI®4-µC:
• Four independent bi-directional voice channels;
• Oversampling sigma-delta A/D and D/A converters with excellent resolution, dynamic
range, linearity, accuracy and signal-to-noise performance;
• Hardware filters for decimation and interpolation of the ADC and DAC bit stream, and
pre-processing of the voice data to reduce the load of the DSP;
• DSP core with programmable, channel-independent filter structures for impedance
matching, transhybrid balancing, frequency correction and level adjustments;
• Configurable A-Law or µ-Law compressor and expander units;
• Two PCM ports with data rates from 128 kbps to 8 Mbps per highway;
• Programmable time slot assignment for each channel;
• twenty-eight signaling input and output pins, accessible through registers;
• On-chip PLL for an internal 16.384 MHz clock;
• Two programmable versatile clock outputs;
• Eight common configuration registers (XR-Registers) affecting all four channels;
• Four sets of six channel-specific registers (CR-Registers); and
• Coefficient RAM (CRAM) for filter coefficients storage for each channel.
Hardware Reference Manual
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PEB 2466
PEF 2466
Operational Description
4
Operational Description
Each channel of the SICOFI®4-µC can be in one of two stable states: “Standby” and
“Operating”. These states can be switched by programming Bit 0 (PU) in the
channel-specific configuration register CR1. “Standby” is a power-saving state. Keeping
all unused channels in this state reduces the overall system power dissipation. The third
state, “Reset”, is transient and is reached after applying power to the device (Power On),
after asserting a logic low signal to the RESET#-pin (HW-Reset), or after issuing an XOP
command with Bit 7 (RST) set to ‘1’ (SW-Reset). All four channels would be affected in
any case.
Operating States
Operating
Ch.2
Standby
Ch.4
Operating
Ch.3
Power Down Ch.4
Power Up Ch.3
Power Up Ch.2
Power Up Ch.1
Operating
Ch.1
Standby
Ch.3
Power Up Ch.4
Standby
Ch.2
Power Down Ch.1
Standby
Ch.1
Reset
(all channels)
Power Down Ch.3
Power-On
HW-Reset
SW-Reset
Power Down Ch.2
4.1
Operating
Ch.4
2466_206
Figure 5
4.1.1
SICOFI®4-µC State Diagram
Power On
All input pins must be at GND level before applying VDD to the SICOFI®4-µC. Otherwise,
the device may not enter the Reset State. In this case, the SICOFI®4-µC can be reset by
HW- or SW-Reset, or can be initialized by setting all registers to zero.
4.1.2
Hardware Reset
Voltage levels lower than 1.2 V applied to pin 23 (RESET#) for more than 3 µs will reset
the SICOFI®4-µC. Spikes that are shorter than 1 µs will be ignored. When RESET# is
released the SICOFI®4-µC will enter Standby State.
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PEB 2466
PEF 2466
Operational Description
Table 2
Register Values and Accessibility
SICOFI®4-µC State
Register
Reset
Standby
Operating
CR0 ... CR4
00H
user configurable
user configurable
XR0 ... XR7
00H
user configurable
user configurable
CRAM
unchanged
user configurable
user configurable
Table 3
Input and Output Pin Behavior
SICOFI®4-µC State
Pin
Reset
Standby
Operating
DIN
ignored
serial input
serial input
DOUT
high impedance
serial output
serial output
DRA, DRB
ignored
ignored
active receive time slot
DXA, DXB
high impedance
high impedance
active transmit time slot
TCA#, TCB#
high
high
low during active
transmit time slot
VOUT1 , VOUT2
VOUT3 , VOUT4
high impedance
high impedance
analog output
VIN1 , VIN2
VIN3 , VIN4
ignored
ignored
analog input
SBx_y
configured as input
programmable as
input or output
programmable as input
or output
SOx_y
GNDD
digital output
digital output
SIx_y
ignored
digital input
digital input
CHCLK1
high
programmable
frequency
programmable
frequency
CHCLK2
high
programmable freq.
(not 16384 kHz)
programmable
frequency
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PEB 2466
PEF 2466
Operational Description
Table 4
Power Dissipation
No. of Channels Operating
Typical Power Dissipation
None
2.5 mW
1
70 mW
2
90 mW
3
110 mW
4
130 mW
4.2
Transmission Characteristics
4.2.1
Overload Point
The overload point of the SICOFI®4-µC A/D converters is at 2.223 V. This is the peak
amplitude of a sine wave level of 1.572 Vrms. Higher input signal levels will be distorted.
Theoretical load capacities for A-Law and µ-Law encoded signals are defined in ITU-T
Recommendation G.711. These values correspond to the SICOFI®4-µC overload point:
Table 5
Maximum Signal Levels
PCM Interface
Analog Interface
Encoding Law
Theoretical Load Capacity
(according to ITU-T G.711)
Max. Sine Wave Level
(SICOFI®4-µC Overload Point)
A-Law
3.14 dBm0
µ-Law
3.17 dBm0
4.2.2
1.572 Vrms
0 dBm0-Levels
The analog voltage levels corresponding to a 0 dBm0 sine wave signal can be calculated
from the maximum signal levels shown in Table 5.
Table 6
Analog Voltage Levels Corresponding to 0 dBm0-Level
Encoding Law
Analog Sine Wave Level
corresponding to 0 dBm0 PCM Level
A-Law
1.572 Vrms*10^(-3.14/20) = 1.095 V rms
µ-Law
1.572 Vrms*10^(-3.17/20) = 1.091 V rms
Note: Periodic PCM codes for a 1 kHz sine wave signal with 0 dBm0 level can be found
in ITU-T G.711.
Hardware Reference Manual
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PEB 2466
PEF 2466
Operational Description
4.2.3
Compressor Gain Relative to Coding Law
The µ-Law compressor unit of the SICOFI®4-µC automatically adds 1.94 dB gain, which
has to be considered for the total gain calculation. The accumulated gain of all
programmable transmit filters (AX1+AX2+FRX) must not exceed 7 dB if the device is set
to µ-Law operation. If the device is set to A-Law operation, then the accumulated gain
must not exceed 9 dB.
Transmit
1014 Hz
1.095 Vrms
VIN
VOUT
1.095 Vrms
A/D
0 dB
Gain
A-Law
Compressor
DXA/B
D/A
0 dB
Gain
A-Law
Expander
DXA/B
Receive
Figure 6
0 dBm0
1014 Hz
0 dBm0
2466_207
Analog and PCM Signal Levels in A-Law Mode
Transmit
1014 Hz
1.091 Vrms
VIN
VOUT
1.091 Vrms
A/D
0 dB
Gain
µ -Law
Compressor
[+1.94 dB]
D/A
0 dB
Gain
µ -Law
Expander
DXA/B
DXA/B
1.94 dBm0
1014 Hz
0 dBm0
Receive
2466_208
Figure 7
Analog and PCM Signal Levels in µ-Law Mode
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PEF 2466
Operational Description
4.2.4
Operating Conditions
The specifications to which the SICOFI®4-µC are tested are tighter than the ITU-T Q.552
Specification to guardband various SLIC implementations. The guaranteed transmission
characteristics of the SICOFI®4-µC under test conditions ensure that the final linecard
design will meet the ITU-T specification.
The figures in this document are based on the subscriber-line board requirements.
Proper
adjustment
of
the
programmable
filters
(transhybrid balancing,
impedance matching, frequency-response correction) requires a complete knowledge of
the analog environment in which the SICOFI®4-µC is to be used. Unless otherwise
stated, the transmission characteristics are guaranteed within the following operating
conditions:
•
•
•
•
•
•
•
•
•
TA = 0 °C to 70 °C (PEB 2466), TA = -40 °C to 85 °C (PEF 2466);
VDD = 5 V ± 5%;
GNDA1,2,3,4 = GNDD = 0 V;
Load on VOUT: RL > 300 Ω; CL < 50 pF;
H(IM) = H(TH) = 0;
H(R1) = H(FRX) = H(FRR) = 1;
HPR and HPX enabled;
AR = 0 to –9 dB (AR = AR1 + AR2 + FRR + R1);
AX = 0 to +9 dB for A-Law,
AX = 0 to +7 dB for µ-Law (AX = AX1 + AX2 + FRX);
• f = 1014 Hz; 0 dBm0; A-Law or µ-Law;
• AGX = 0 dB, +6.02 dB; and
• AGR = 0 dB, –6.02 dB.
Transmit Path
Analog
AGX
ADC
AX2
FRX
AX1
HPX
CMP
PCM
Output
FRR
AR1
HPR
EXP
PCM
Input
Input
IM
TH
Analog
AGR
DAC
R1
AR2
Output
Receive Path
2466_209
Figure 8
Simplified Signal Flow Diagram
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PEB 2466
PEF 2466
Operational Description
4.2.5
Gain Accuracy
Table 7
Gain Accuracy
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Test Conditions
TA = 25 °C,VDD = 5 V,
–0.20 ±0.10 +0.20
dB
Variation with
Temperature
±0.05
dB
TA = –40 °C to 85 °C
Variation with
Supply Voltage
±0.05
dB
VDD = 5 V ± 5%
Variation with
Analog Gain
±0.05
dB
AGX= +6.02 dB,
AGR= –6.02 dB
Absolute Gain
4.2.6
G
AGX = AGR = 0 dB
Gain Tracking (Receive and Transmit)
The gain deviation for a 1014 Hz sine-wave input signal will stay within limits shown in
Table 8. All values are relative to the gain of a 0 dBm0 input signal.
Table 8
Gain Deviations with Input Level
Input Level
Symbol
Gain Deviation
min.
typ.
max.
Unit
Test Conditions
1014 Hz sine-wave
test signal. Reference
level is at 0 dBm0.
-55 to -50 dBm0
∆G
±1.4
dB
-50 to -37 dBm0
∆G
±0.5
dB
-37 to 3 dBm0
∆G
±0.25
dB
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PEB 2466
PEF 2466
Operational Description
4.2.7
Frequency Response
Table 9
Attenuation with Frequency in Transmit and Receive Direction
Input Frequency
Receive Loss
min.
max.
Transmit Loss
min.
max.
Unit
Test Conditions
0 dBm0 input signal
level. 1014 Hz
reference frequency
0 Hz to 100 Hz
0
>2
dB
100 Hz to 200 Hz
0
0
dB
200 Hz to 300 Hz
-0.125
-0.125
300 Hz to 3.0 kHz
-0.125
3.0 kHz to 3.2 kHz
1
dB
0.125 -0.125
0.125
dB
-0.125
0.3
-0.125
0.3
dB
3.2 kHz to 3.4 kHz
-0.125
0.65
-0.125
0.65
dB
> 3.4 kHz
0
0
dB
4.2.8
Group Delay
4.2.8.1
Group Delay, Absolute Values
Table 10 shows the limit values for the Absolute Group Delay. The maximum delays are
valid when the SICOFI®4-µC is operating with H(TH) = H(IM) = 0, and H(FRR) = H(FRX)
= 1, and include the delay through the A/D and D/A converters. The typical delays are
the average of all different time slot delays during one PCM frame.
Table 10
Group Delay, Absolute Values
Parameter
Symbol
Transmit Delay
DXA
DRA
Receive Delay
Hardware Reference Manual
Limit Values
Unit
Test Conditions
450
µs
450
µs
0 dBm0 input signal
level, fTest at TGmin.
min.
typ.
max.
300
375
300
375
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PEB 2466
PEF 2466
Operational Description
4.2.8.2
Group Delay Distortion with Frequency
The Group Delay Distortion in transmit and receive direction will stay within the limits
shown in Table 11. Group Delay Distortion values are referenced to the minimum value
of Group Delay (TGmin).
Table 11
Group Delay Distortion with Frequency
Symbol
Frequency
Limit Values
min. typ.
Unit
Test Conditions
0 dBm0 input signal level,
reference point is at TGmin.
max.
500 Hz to 600 Hz
∆tG
300
µs
600 Hz to 1.0 kHz
∆tG
150
µs
1.0 kHz to 2.6 kHz
∆tG
100
µs
2.6 kHz to 3.0 kHz
∆tG
300
µs
4.2.9
Noise
Table 12
Idle Channel Noise in Transmit Direction
Parameter
Symbol
A-Law, psophometric (VIN = 0 V)
min.
typ.
NTP
NTC
NTC
µ-Law, C-message (VIN = 0 V)
µ-Law, C-message (VIN = 0 V)
Table 13
Limit Values
max.
Unit
–67.4
dBm0p
17.5
dBmc
17.5
dBrnC0
Idle Channel Noise in Receive Direction
Parameter
Symbol
NRP
NRC
NRC
A-Law, psophometric (idle code + 0)
µ-Law, C-message (idle code + 0)
µ-Law, C-message (idle code + 0)
Hardware Reference Manual
19
Limit Values
min.
typ.
max.
Unit
–85
–78.0
dBm0p
5
12.0
dBmc
5
12.0
dBrnC0
2001-02-20
PEB 2466
PEF 2466
Operational Description
4.2.10
Harmonic and Intermodulation Distortion
Table 14
Harmonic and Intermodulation Distortion
Parameter
Symbol
Harmonic Distortion
2nd, 3rd order
Limit Values
min.
typ.
max.
–50
HD
–44
Unit
dB
0 dBm0; f = 1014 Hz
dB
dB
Equal-level, 4-tone method
(EIA-464) at composite
level of -13 dBm0;
f = 300 Hz to 3400 Hz
Intermodulation
R2
R3
4.2.11
–46
–56
IMD
IMD
Test Conditions
Total Distortion
Table 15
Signal-to-Total Distortion Ratio Measured with Sine Wave
Input Level Symbol
Min. Values
A-Law
µ-Law
Unit
Test Conditions
sine wave f=1014 Hz, receive and
transmit,
µ-Law: C-message weighted,
A-Law: psophometrically weighted.
-45 dB
S/D
24.5
27
dB
-40 dB
S/D
29.5
31
dB
-30 dB
S/D
35.5
35.5
dB
> -28 dB
S/D
36.4
36.4
dB
40
dB
S/D
30
27
24.5
36.4
35.5
µ-Law
31
29.5
A-Law
20
10
0
-60
Figure 9
-50
-45
-40
-30
-28
-20
Input Level
-10 dBm0 0
2466_210
Total Distortion Measured with Sine-Wave, Receive and Transmit
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PEF 2466
Operational Description
Table 16
Signal-to-Total Distortion Ratio Measured with Noise
Input Level
Symbol
Min. Value, PEB 2466 Min. Value, PEF 2466
Receive
Transmit
Receive
Transmit
Unit
-55 dB
S/D
14.7
13.7
14.7
12
dB
-40 dB
S/D
29.7
28.7
29.7
27
dB
-34 dB
S/D
34.3
33.3
34.3
33.3
dB
-27 dB
S/D
36
35.4
36
35.4
dB
-24 to -6 dB
S/D
36.7
36.3
36.7
36.3
dB
-3 dB
S/D
28.4
27.4
28.4
27.4
dB
S/D
40
dB
36.7
34.3
36
30
29.7
28.4
20
14.7
10
0
-60
Figure 10
-55
-50
-40
-34 -30
-24 -20 dBm0 -10
0
-27
-6 -3
Input Level
2466_211
Total Distortion Receive (Noise)
40
dB
36.3
35.4
33.3
30
28.7
S/D
27.0
27.4
PEB 2466
20
PEF 2466
13.7
12
10
0
-60
-55
-50
-40
-34
-30 -27
-24
-20 dBm0 -10
Input Level
Figure 11
-6
-3
0
2466_212
Total Distortion Transmit (Noise)
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PEB 2466
PEF 2466
Operational Description
4.2.12
Single Frequency Distortion
Test Input Signal
Frequency Range
max. Input Level
Receive Direction
300 Hz to 3.4kHz
0 dBm0
Transmit Direction
0 Hz to 12 kHz
0 dBm0
Any resulting signal with a frequency different from the test input signal will stay at least
28 dB below the input signal level.
4.2.13
Overload Compression
This is measured with a 1014 Hz sine-wave signal. The overload point in µ-Law Mode is
at 3.17 dBm0.
Fundamental
Output Power
10
dBm0
8
7
6
5
4
3
2
1
0.25
0
-0.25
-1
0
1
2
3
4
5
6
7
dBm0
9
Fundamental Input Power
Figure 12
4.2.14
2466_213
Overload Compression (µ-Law Coding, Transmit Direction)
Crosstalk
Table 17
Crosstalk Between Channels
Parameter
Crosstalk, 0dBm0
Symbol
CT
Limit Values
min.
typ.
max.
– 85
– 80
Unit
dB
Test Conditions
f = 200 Hz to 3400 Hz,
any combination of
directions and channels
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PEF 2466
Operational Description
4.2.15
Out-of-Band Discrimination in Transmit Direction
With any 0 dBm0 sine-wave signal below 100 Hz and in the range from 3.4 kHz to 100
kHz (out-of-band signal) applied to an analog input (VINx), the level of any resulting
frequency component at the digital output will stay at least X dB (see Table 18) below
the output level of a 0 dBm0 1kHz sine-wave reference signal at the analog input.
Table 18
Out-of-Band Signals Applied to the Analog Inputs (VINx)
Min. Output Signal Rejection
X
Unit
Test Conditions
0 Hz to 60 Hz
25
dB
60 Hz to 100 Hz
10
dB
0 dBm0 sine-wave input
signal on VIN
3.4 kHz to 4 kHz
4000 – f
– 14  sin  π --------------------- – 1



1200 
Input Frequency
4 kHz
15
dB
dB
dB
4000 – f
7
– 18  sin  π ---------------------  – ---


1200  9
4 kHz to 4.6 kHz
4.6 kHz to 100 kHz
40
dB
The Hardware Filters behind the A/D Converters reject teletax pulses with their poles at
12 kHz ±150 Hz and 16 kHz ±150 Hz.
40
dB
Transmit Out-of-Band
Discrimination X
32
30
25
20
15
10
0
0
0.06 0.1
3.4
4
4.6
6
18 kHz 100
10
f
Figure 13
2466_214
Out-of-Band Discrimination in Transmit Direction
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PEB 2466
PEF 2466
Operational Description
4.2.16
Out-of-Band Discrimination in Receive Direction
With any 0 dBm0 sine-wave frequency in the range from 300 Hz to 3.99 kHz applied to
the digital input (PCM time slot), the level of any resulting out-of-band signal at the
analog output will stay at least X dB (see Table 19) below the output level of a 0 dBm0
1kHz sine-wave reference signal at the digital input.
Out-of-Band Signals at the Analog Outputs (VOUTx)
Table 19
Output Frequency
Min. Output Signal Rejection
X
3.4 kHz to 4.6 kHz
4000 – f
– 14  sin  π --------------------- – 1 



1200 
Unit
dB
Test Conditions
0 dBm0 sine-wave
input signal on digital
input (PCM time slot)
dB
4.6 kHz to 10.55 kHz
f – 4600
35 + 22 --------------------5950
4 kHz
15
dB
4.6 kHz
28
dB
>10.55 kHz
57
dB
Receive Out-of-Band
Discrimination X
60
dB
50
40
35
30
28
20
15
10
0
Figure 14
57
0
0.06 0.1
3.4
4
4.6
6
16 18 kHz 100
8 10
10.55
f
2466_215
Analog Output: Out-of-Band Signals
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PEB 2466
PEF 2466
Operational Description
4.2.17
Out-of-Band Idle Channel Noise at Analog Output
With an idle code (any sequence of constant PCM octets) applied to the digital input, the
level of any resulting out-of-band power spectral density at the analog output, measured
with 3 kHz bandwidth, will be not greater than the limit curve shown in Figure 15.
Out of Band Noise
-40
dBm0
-50
-55
-60
-70
-78
-80
-90
-100
1
10
2
3
10
10
kHz
f
Figure 15
4
10
2466_216
Analog Output: Out-of-Band Idle Channel Noise
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PEF 2466
Operational Description
4.2.18
Transhybrid Loss
The quality of Transhybrid-Balancing is very sensitive to deviations in gain, group delay,
and deviations inherent to the A/D- and D/A-converters, as well as to all external
components used on a linecard (SLIC, OP’s etc.).
Transhybrid loss test setup:
The SICOFI®4-µC test loop “DLB-ANA” is selected (see Figure 34), which connects the
analog output with the analog input. The programmable filters FRR, AR, FRX, AX are
by-passed. The IM-filter is disabled, (H(IM)=0). The balancing filter TH is enabled with
optimized coefficients for this configuration (VOUT = VIN).
A 0 dBm0 sine wave signal with a frequency in the range of 300 Hz to 3400 Hz is applied
to the digital input. The signal levels of the resulting echo at the digital output will stay
below the values shown in Table 20.
Table 20
Transhybrid Loss
Input Frequency
Symbol
300 Hz
THL300
THL500
THL2500
THL3000
THL3400
500 Hz
2500 Hz
3000 Hz
3400 Hz
Hardware Reference Manual
Transhybrid Loss
Unit
Test Condition
min.
typ.
27
40
dB
TA = 25 °C; VDD = 5 V
30
45
dB
29
40
dB
27
35
dB
AGX = AGR = 0 dB;
typical variation of
amplitude: ± 0.15 dB
delay: ± 0.5 µs.
27
35
dB
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Interface Description
5
Interface Description
The SICOFI®4-µC provides four interfaces:
•
•
•
•
Analog Interface,
PCM Interface,
Signaling Interface, and
Serial Microcontroller Interface.
A general description of these interface is given in the Product Overview, Chapter 4.
Refer to the Programmers Reference Manual for information on the configuration and
operation of the four interfaces.
The subsequent chapters in this manual explain how to connect the SICOFI®4-µC to
subscriber line interface circuits (SLICs), microcontrollers, and PCM highways.
5.1
Analog Interface
The Analog Interface in combination with a Subscriber Line Interface Circuit (SLIC)
forms a configurable tip & ring (t/r) telephone line. The AC transmission characteristic of
the SICOFI®4-µC—SLIC combination can be controlled by programming the digital filter
structures inside the SICOFI®4-µC. The correct filter coefficients are determined by the
targeted AC transmission behavior (e.g. Telco specification) and by the transfer
functions of the SLIC.
The SICOFI®4-µC can be interfaced directly to electronic SLICs or transformer solutions.
The high driving capability of up to 300 Ohms eliminates the need for an external
amplifier that is normally used with transformer SLICs.
The peak amplitude of the analog inputs and outputs is at 2.223 V (overload point).
Out-of-band signals applied to the analog inputs are suppressed by the on-chip digital
hardware filters. The poles of these filters are fixed at 12 kHz and 16 kHz which
suppresses the echo signal from teletax pulses very efficiently: As long as the amplitude
of the teletax echo stays below the overload threshold of 2.223 Vp (1.57 Vrms), the voice
signal in the transmit path will not be disturbed. Thus, the on-chip hardware filters can
eliminate the need for external teletax filters.
5.1.1
Coupling Capacitors at the Analog Interface
A coupling capacitor >39 nF must be used on the VIN-pins in the transmit direction. The
required value for the coupling capacitor on the VOUT-pins depends on the input
resistance of the SLIC-circuitry (RLoad). It has to be chosen to fulfil the frequency
response requirement in the receive direction. Figure 16 can be used to determine an
appropriate value for the coupling capacitor (CExt1).
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PEB 2466
PEF 2466
Interface Description
SICOFI4-µC
SLIC 1
Channel 1
> 39nF
t/r
49
51
RLoad
CExt1
100nF
SLIC 2
RLoad
t/r
VIN3
VIN1
50
GNDA1
52
VDDA12
54
> 39nF
55
53
CExt1
GNDA3
Channel 4
GNDA4 63
VIN2
VIN4
VREF
t/r
CExt1
RLoad
100nF
100nF
SLIC 4
> 39nF
RLoad
220nF
100nF
CExt1
57
1
fmin·RLoad
CExt1=
CExt1
1
10
0
fmin = 250 Hz
10 -1
10
-2
10
-3
10
2
10
3
10
4
10
5
Ω
RLoad
Figure 16
t/r
VDDREF
10 2
µF
10
64
VOUT4 62
VOUT2
> 39nF
59
VDDA34 61
GNDA2
56
58
VOUT3 60
VOUT1
Channel 2
100nF
SLIC 3
Channel 3
10
6
2466_217
Analog Interface to Four Subscriber Line Interface Circuits (SLICs)
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PEF 2466
Interface Description
5.1.2
Table 21
Analog Interface Pins
Analog Interface Pins
Symbol
Pin
Function
VIN1
49
VIN2
55
VIN3
58
VIN4
64
VOUT1
51
VOUT2
53
VOUT3
60
VOUT4
62
GNDA1
50
GNDA2
54
GNDA3
59
GNDA4
63
VDDA12
52
Analog Supply Voltage, Channels 1+2
+5 V (100 nF blocking capacitor required, see Figure 16).
VDDA34
61
Analog Supply Voltage, Channels 3+ 4
+5 V (100 nF blocking capacitor required, see Figure 16).
VDDREF
57
Analog Supply Reference Voltage,
+5 V (100 nF blocking capacitor required, see Figure 16).
VREF
56
Reference Voltage
Must connect to a 220 nF cap. to ground, see Figure 16.
Analog Input, Channel 1, 2
Requires a coupling capacitor >39 nF to the SLIC, see Figure 16.
Analog Input, Channel 3, 4
Requires a coupling capacitor >39 nF to the SLIC, see Figure 16.
Analog Output, Channel 1, 2
Requires a coupling capacitor to the SLIC. The capacitor’s value
depends on the input impedance of the SLIC, see Figure 16.
Analog Output, Channel 3, 4
Requires a coupling capacitor to the SLIC. The capacitor’s value
depends on the input impedance of the SLIC, see Figure 16.
Analog Ground, Channel 1, 2
Not internally connected to GNDD or the other GNDAx.
Analog Ground, Channel 3, 4
Not internally connected to GNDD or the other GNDAx.
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PEB 2466
PEF 2466
Interface Description
5.2
PCM Interface
The SICOFI®4-µC provides an industry–standard PCM Interface with access to two PCM
highways. The PCM Interface has the following features:
•
•
•
•
•
•
•
•
Data rate from 128 kbit/s to 8 Mbit/s per highway,
2 to 128 time slots per frame per highway,
PCM data format serialized 8 bits with MSB first,
Configurable A-Law or µ-Law coding,
Independently configurable time slot and highway for each channel and direction,
PCM clock speed of once or twice the bit rates,
Programmable sampling slopes, and
Programmable frame delay.
5.2.1
PCM Interface Pins
Table 22
PCM Interface Pins
Symbol
Pin
Function
PCLK
32
PCM-Clock, 128 kHz to 8192 kHz; shared for both highways.
FSC
31
Frame Synchronization Clock, 8 kHz; shared for both highways.
DRA
27
Receive Data input for PCM-highway A.
DRB
30
Receive Data input for PCM-highway B.
DXA
26
Transmit Data output for PCM-highway A, open drain.
DXB
29
Transmit Data output for PCM-highway B, open drain.
TCA#
25
Transmit Control output for highway A, low when DXA is active.
TCB#
28
Transmit Control output for highway B, low when DXB is active.
5.2.2
PCM Receive and Transmit Example
Figure 17 and Figure 18 illustrate the time slot and bit positions resulting from the
programming example below:
Hardware Reference Manual
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PEB 2466
PEF 2466
Interface Description
Table 23
PCM Register Configuration Example
Channel
CR4
Receive Setting
CR5
1
0000 0000
DRA, time slot 0
0000 0000
DXA, time slot 0
2
0000 1111
DRA, time slot 15
0001 0010
DXA, time slot 18
3
0000 1000
DRA, time slot 8
0001 0011
DXA, time slot 19
4
0001 1010
DRA, time slot 26
0000 0011
DXA, time slot 3
all
Transmit Setting
XR6=0000 0000; single clock mode, no PCM offset; PCLK=2048 kHz.
125 µs
FSC
PCLK
0 1 2 3
8
Time Slot
15
26
31
DRA
18 19
High 'Z'
DXA
High 'Z'
TCA#
Detail A
2466_218
Figure 17
PCM Interface Example: Location of Time Slots
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PEF 2466
Interface Description
FSC
Clock 0
1
2
3
4
5
6
7
1
0
PCLK
DRA
Voice Data
Bit 7
DXA
High 'Z'
6
5
4
3
2
Voice Data
High 'Z'
TCA#
2466_219
Figure 18
PCM Interface Example: Detail A
The pins DRA/B and DXA/B may be strapped together to form a multiplexed
bi-directional PCM port.
5.3
Signaling Interface
The SICOFI®4-µC Signaling Interface is used to monitor and control supervision and
signaling functions on up to four subscriber lines. The device generates interrupt signals
to indicate signaling status changes on any of the input pins.
The Signaling Interface consists of the following I/O pins and functions:
• 28 signaling pins (2 input pins, 2 output pins, and 3 user-configurable bi-directional
pins per channel),
• Debouncing functions,
• 2 interrupts (one for each channel-pair), and
• 2 clock output signals (user configurable).
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PEF 2466
Interface Description
5.3.1
Signaling Interface Pins
SICOFI4-µC
33
Channel 1
SLIC 1
t/r
Operating
Mode
39
38
37
Off-Hook Det.
Ground Key Det.
36
35
Ring Relay
41
Status LED
40
SLIC 2
t/r
Operating
Mode
44
45
46
47
48
Ring Relay
42
43
CHCLK2
16
Channel 3
SB1_0
SB1_1
SB1_2
SB3_0
SB3_1
SB3_2
SI1_0
SI1_1
SI3_0
SI3_1
SO1_0
SO1_1
SO3_0
SO3_1
Channel 2
Off-Hook Det.
Ground Key Det.
Status LED
CHCLK1
SLIC 3
5
4
3
2
1
SB4_0
SB4_1
SB4_2
SI2_0
SI2_1
SI4_0
SI4_1
SO2_0
SO2_1
SO4_0
SO4_1
INT 12
Off-Hook Det.
Ground Key Det.
7
Ring Relay
6
Status LED
SLIC 4
Channel 4
SB2_0
SB2_1
SB2_2
t/r
Operating
Mode
10
11
12
t/r
Operating
Mode
13
14
Off-Hook Det.
Ground Key Det.
8
Ring Relay
9
Status LED
INT 34
34
15
Microcontroller
2466_220
Figure 19
Signaling Example: Four Subscriber Lines
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PEB 2466
PEF 2466
Interface Description
Table 24
Signaling Interface: Pins and Functions for SLIC Interfaces
Symbol
Pin
Function
Ch1
Ch2
Ch3
Ch4
SIx_0
36
47
2
13
Signaling Input Channel x, Pin 0.
SIx_1
35
48
1
14
Signaling Input Channel x, Pin 1.
SOx_0
41
42
7
8
Signaling Output, Channel x, Pin 0.
SOx_1
40
43
6
9
Signaling Output, Channel x, Pin 1.
SBx_0
39
44
5
10
Bi-directional Signaling, Channel x, Pin 0.
SBx_1
38
45
4
11
Bi-directional Signaling, Channel x, Pin 1.
SBx_2
37
46
3
12
Bi-directional Signaling, Channel x, Pin 2.
INT12
34
-
Interrupt Output, Channels 1+2, active high.
INT34
-
15
Interrupt Output, Channels 3+4, active high.
5.3.2
Debouncing Functions and Interrupt Generation
All signaling inputs are sampled at programmable intervals (Field N in register XR4). If
all the inputs assigned to one channel-pair (1&2 or 3&4) have been stable for two
subsequent samples their values are stored in the signaling registers and the associated
interrupt output (INT12 or INT34) is set high. Refer to the Programmer’s Reference
Manual for further details on this function.
5.3.3
Clock Output Signals
Two programmable Chopper Clock Output signals are provided by the PEB 2466:
• CHCLK1 (Pin 33) is configured in register XR4.Field T (bits XR4.3 to XR4.0)
• CHCLK2 (Pin 16) is configured in register XR5.CHCLK2 (bits XR5.3 and XR5.2)
• Both Chopper Clock Output signals are only available if a valid Master Clock signal is
applied to pin MCLK.
• CHCLK2 = 16,384 kHz: Requires at least one channel in POWER-UP state.
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PEB 2466
PEF 2466
Interface Description
Table 25
Clock Programming
CHCLK1
CHCLK2
XR4.Field T
Output (Pin 33)
XR5.CHCLK2
Output (Pin 16)
0000
High level (+5V)
00
High level (+5V)
0001 to 1110
Clock period = T *2ms
(min. 2 ms, max. 28 ms)
01
512 kHz signal
10
256 kHz signal
1111
Low level (0V)
11
16384 kHz signal
5.4
Serial Microcontroller Interface
The Serial Microcontroller Interface is used to access the SICOFI®4-µC’s internal
registers and the Coefficient RAM (CRAM). The Serial Microcontroller Interface consists
of four pins: two data pins (DIN, DOUT), one clock pin (DCLK) and one pin for chip select
(CS#). If DIN and DOUT are strapped together, only three microcontroller I/O pins are
required to build this interface.
SICOFI4-µC
SICOFI4-µC
CS# DCLK DIN DOUT
CS# DCLK DIN DOUT
Out
Out
Out
Out
In
Out
I/O
Microcontroller
Microcontroller
Configuration A:
Separate DIN, DOUT
Configuration B:
Bi-Directional Data
2466_221
Figure 20
Serial Microcontroller Interface
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PEB 2466
PEF 2466
Interface Description
5.4.1
Table 26
Serial Microcontroller Interface Pins
Serial Microcontroller Interface: Pins and Functions
Symbol
Pin
Function
CS#
17
Chip Select, enable to read or write data, active low.
DCLK
18
Data Clock, shifts data from or to device; max. clock rate is 8192 kHz.
DIN
19
Control Data Input; sampled with rising edge of DCLK.
DOUT
20
Control Data Output; bits are shifted with the falling edge of DCLK;
DOUT is in high impedance state when no data is transmitted from
the SICOFI®4-µC.
5.4.2
Write Access
Following a falling edge of CS#, the first eight bits received on DIN specify the type of
command. The data bytes following a write command are stored in the selected
configuration registers or the selected part of the Coefficient RAM. The number of data
bytes depends on the type of command. After every command CS# must be set to ’1’.
.
CS#
DCLK
DIN
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Write Command
5.4.3
Data Byte 2
High 'Z'
DOUT
Figure 21
Data Byte 1
2466_222
Example for a Two-Byte Write Access
Read Access
If the first eight bits received via DIN represent a read command, the SICOFI®4-µC will
initiate its response via DOUT. An identification byte (81H) is followed by the requested
number of data bytes (contents of configuration registers or contents of the CRAM).
During execution of a read command, the device will ignore data on DIN. After every
command CS# must be set to ’1’.
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PEB 2466
PEF 2466
Interface Description
.
CS#
DCLK
DIN
7 6 5 4 3 2 1 0
Read Command
DOUT
High 'Z'
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Identification 81H
High 'Z'
Data Byte 1
2466_223
Figure 22
Example for a One-Byte Read Access
For byte-by-byte transfer, the high time of DCLK can be prolonged, resulting in a
user-defined ‘waiting time’ between bytes. This mechanism can be used for writing to
and reading from the device.
CS#
DCLK
DIN
7 6 5 4 3 2 1 0
Read Command
DOUT
High 'Z'
7 6 5 4 3 2 1
Identification 81H
0
7 6 5 4 3 2 1 0
High 'Z'
Data Byte 1
2466_224
Figure 23
Example for a Read Access with Byte-by-Byte Transfer
Read and write commands can be chained by leaving CS# low after the completion of
each command sequence.
For read or write access to individual registers, the command sequence may be
terminated by rising CS# after the transmission of any number of bytes.
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PEB 2466
PEF 2466
Interface Description
5.4.4
Three-Wire Access
DIN and DOUT may be strapped together and connected to a single I/O pin of the
microcontroller. The interface remains fully functional with only three wire connections.
After every command CS# must be set to ’1’.
CS#
DCLK
DATA
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Read Command
Identification 81H
High 'Z'
Data Byte 1
2466_225
Figure 24
Bi-Directional Data Signal: DIN and DOUT Strapped Together
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PEB 2466
PEF 2466
Programming Overview
6
Programming Overview
The transmission characteristics and interfaces of the PEB 2466 can be adapted to
various environments. Configuring the functional blocks and programming the digital
filter behavior is accomplished by loading values to the Configuration Registers and the
Coefficient RAM (CRAM). Software utilities are available to determine the appropriate
register and CRAM values (see Programmer’s Reference Manual).
6.1
Programming Overview
The SICOFI®4-µC has eight Common Configuration Registers (XR0 to XR7). Settings in
these registers affect all four channels.
Each of the four channels has six Channel-Specific Configuration Registers (CR0 to
CR5). Settings in these registers affect only the designated channel.
The filters of each channel are individually programmable through channel-specific
coefficients in CRAM. There are four global sets of TH Filter coefficients that can be
assigned to any channel.
6.1.1
Register Model
Channel-specific and Common Configuration Registers and coefficients are shown in
Table 27.
Table 27
Channel 1
Register Model
Channel 2
Channel 3
Channel 4
XR0 to XR7 (8 bytes)
Type
common
CR0 to CR5
(6 bytes)
CR0 to CR5
(6 bytes)
CR0 to CR5
(6 bytes)
CR0 to CR5
(6 bytes)
IM,
FRR, FRX,
AR, AX,
TG1, TG2
Coefficients
(48 bytes)
IM,
FRR, FRX,
AR, AX,
TG1, TG2
Coefficients
(48 bytes)
IM,
FRR, FRX,
AR, AX,
TG1, TG2
Coefficients
(48 bytes)
IM,
FRR, FRX,
AR, AX,
TG1, TG2
Coefficients
(48 bytes)
channel-specific
TH Coefficient Set 1 (24 bytes)
TH Coefficient Set 2 (24 bytes)
TH Coefficient Set 3 (24 bytes)
one coefficient set
per channel
TH Coefficient Set 4 (24 bytes)
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PEB 2466
PEF 2466
Programming Overview
6.1.2
Register Maps
Table 28
Read Access to Common Configuration Register (XR) Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XR0
SI4_1
SI4_0
SI3_1
SI3_0
SI2_1
SI2_0
SI1_1
SI1_0
XR1
SB4_1
SB4_0
SB3_1
SB3_0
SB2_1
SB2_0
SB1_1
SB1_0
XR2
PSB4_1
PSB4_0
PSB3_1
PSB3_0
PSB2_1
PSB2_0
PSB1_1
PSB1_0
XR3
SB4_2
SB3_2
SB2_2
SB1_2
PSB4_2
PSB3_2
PSB2_2
PSB1_2
XR4
Signal Debounce
XR5
MCLK-SEL
CHCLK1
CRSH-A
CRSH-B
CHCLK2
XR6
C-Mode
X-S
R-S
DRV_0
Shift
XR7
OF7
OF6
OF5
OF4
OF3
Table 29
Version
PCM-OFFSET
OF2
OF1
OF0
Write Access to Common Configuration Register (XR) Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XR0
SO4_1
SO4_0
SO3_1
SO3_0
SO2_1
SO2_0
SO1_1
SO1_0
XR1
SB4_1
SB4_0
SB3_1
SB3_0
SB2_1
SB2_0
SB1_1
SB1_0
XR2
PSB4_1
PSB4_0
PSB3_1
PSB3_0
PSB2_1
PSB2_0
PSB1_1
PSB1_0
XR3
SB4_2
SB3_2
SB2_2
SB1_2
PSB4_2
PSB3_2
PSB2_2
PSB1_2
XR4
Signal Debounce
XR5
MCLK-SEL
CHCLK1
CRSH-A
CRSH-B
CHCLK2
XR6
C-Mode
X-S
R-S
DRV_0
Shift
XR7
OF7
OF6
OF5
OF4
OF3
Table 30
Version
PCM-OFFSET
OF2
OF1
OF0
Channel-Specific Configuration Register (CR) Map (Read & Write)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CR0
TH
IM/R1
FRX
FRR
AX
AR
CR1
ETG2
ETG1
PTG2
PTG1
LAW
0
0
PU
0
IDR
LM
LMR
V+T
AGX
AGR
D-HPX
D-HPR
CR2
COT/R
CR3
TEST-Loops
Bit 1
Bit 0
TH-SEL
CR4
R-way
RS6
RS5
RS4
RS3
RS2
RS1
RS0
CR5
X-way
XS6
XS5
XS4
XS3
XS2
XS1
XS0
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PEB 2466
PEF 2466
Programming Overview
6.1.3
CRAM Structure
Coefficient RAM (CRAM) is used to store the individual coefficients calculated for each
channel. The coefficients can be written and read through the Microcontroller Interface.
The IM, FRX, FRR, AX, AR, TG1, TG2, and TH coefficients are accessed through the
Coefficient Operation (COP) Command Sequences which include the channel address
(see Programmer’s Reference Manual Chapter 6.5).
Channel-specific coefficients always belong to their designated channel. Common
coefficients (TH) can be assigned to any of the four channels through field TH-SEL in
CR0 (see Figure 25).
Channel 3
IM Part 1 & 2,
FRX, FRR,
AX, AR,
TG1, TG2
Set 1
Set 4
IM Part 1 & 2,
FRX, FRR,
AX, AR,
TG1, TG2
Channel 2
TH Part TH Part TH Part TH Part
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Channel 4
Common Coefficients
Set 2
Set 3
IM Part 1 & 2,
FRX, FRR,
AX, AR,
TG1, TG2
IM Part 1 & 2,
FRX, FRR,
AX, AR,
TG1, TG2
Channel Specific
Coefficients
Channel Specific
Coefficients
Channel 1
2466_226
Figure 25
Channel-Specific and Common Coefficients
Table 31
Coefficient RAM (CRAM) Structure per Channel
IM Part 1
8 Coefficient Bytes
IM Part 2
8 Coefficient Bytes
FRX
8 Coefficient Bytes
FRR
8 Coefficient Bytes
AX
4 Coefficient Bytes
AR
4 Coefficient Bytes
TG1
4 Coefficient Bytes
TG2
4 Coefficient Bytes
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PEB 2466
PEF 2466
Programming Overview
Table 32
Coefficient RAM (CRAM) Structure per Set
TH Part 1
8 Coefficient Bytes
TH Part 2
8 Coefficient Bytes
TH Part 3
8 Coefficient Bytes
6.2
Types of Commands and Data Bytes
Coefficients and register contents are programmed and accessed through command
sequences via the Microcontroller Interface. There are three types of command
sequences:
• Extended Operation (XOP) for access to the Common Configuration Registers (XR0
to XR7) including the Control Registers for the signaling interface.
• Status Operation (SOP) for access to the Channel-Specific Registers (CR0 to CR5),
e.g. enabling and disabling of filters, time slot assignment, and test loops.
• Coefficient Operation (COP) for access to the CRAM structures. Coefficients can be
written to the SICOFI®4-µC, and also read back.
Table 33
XOP
Types of Commands and Data Bytes.
7
6
5
4
3
RST
0
RW
1
1
LSEL
0
LSEL
SOP
AD
RW
1
COP
AD
RW
0
2
1
0
CODE
With the first byte received via DIN, a command type is selected through bits 3 and 4. A
two-bit address field (AD) in the COP and SOP commands allows access to the
channel-specific structures (CRAM and CR registers). Since the XR Registers are
common for all channels, no address field is required within the XOP command byte.
All three commands allow read and write access, which is indicated by bit 5 (RW). The
bit fields LSEL and CODE specify the type and the length of data that follows the
command.
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PEB 2466
PEF 2466
Application Hints
7
Application Hints
7.1
Support Tools
7.1.1
Development Board
The Evaluation Package EASY 2466 includes the following hardware:
• One SICOFI®4-µC Evaluation Board STUT 2466 with connectors for four optional
SLIC daughter cards and BNC connectors to a PCM backplane.
• One microcontroller board EVC50x with RS-232 interface that translates data from a
PC to SICOFI®4-µC format.
• Two SLIC Babyboards STUT 5502 with HARRIS SLIC HC 5502 mounted.
The QSICOS software enables the calculation of the coefficients and the download of
the setup file to the evaluation board.
This setup allows measurements and optimization of the actual behavior of a complete
transmission system. The EASY 2466 evaluation system connects directly to
industry-standard test equipment.
Power Supply
tip ring
COM 1
SLIC (STUT5502)
PC
SLC1
ST2
ST3
reset EVC
sw1
SICOFI2/4
-µC/-TE
Evaluation Board EVC50x
ST1
SLC3
SLC2
P4
SICOFIx -µC/-TE
Eval. Board V1.4
STUT 2466
PCM
out
SLC4
S1
in
PCLK FSC
in/
out
in/
out
FSC in
P C M in
PC M ou t
C lo ck ou t
4 wire in
2 w ire
4 w ire ou t
PCM-4
DC Loop-Holding
circuit
Figure 26
Development System with STUT 2466 Evaluation Board
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PEB 2466
PEF 2466
Application Hints
7.2
Guidelines for Board Design
7.2.1
Filter Capacitors
• For high frequency noise rejection, use 100 nF SMD ceramic capacitors on pins
VDDA12, VDDA34 and VDDREF and connect to GND. Additional 2.2 µF tantalum capacitors
are recommended.
• Use one 100 nF SMD ceramic capacitor on pin VDDD and connect to GNDD.
• Use a 1 µF – 10 µF tantalum capacitor from +5 V supply to GND (central blocking).
Note: All blocking capacitors MUST be placed as close as possible to the
SICOFI®4-µC pins.
.
Signaling Interface, Channels 1&2
5 x 680K
5 x 680K
33
SI2_1
SI2_0
SB2_2
SB2_1
SB2_0
SO2_1
SO2_0
SO1_0
SO1_1
SB1_0
SB1_1
SB1_2
SI1_0
SI1_1
INT12
CHCLK1
48
Analog Interface
49
1µF
2.2µF 100nF
10µ
F
5V
10µF
2.2µF 100nF
220nF
5V
1µF
2.2µF 100nF
2.2µF 100nF
GNDA2
VIN2
VREF
VDDREF
VIN3
SICOFI4-µC
PEB 2466-H
GNDA3
VOUT3
VDDA34
VOUT4
10µF
5V
10µF
2.2µF 100nF
1µF
GNDA1
VOUT1
VDDA12
VOUT2
64
GNDA4
VIN4
PCLK
4.7K
FSC
DRB
5V
DXB
4.7K
TCB#
DRA
DXA
5V
TCA#
100nF 1-10µF
VDDD
10K
RESET#
MCLK
GNDD
DOUT
DIN
DCLK
CS#
17
Microcontroller
Interface
16
SI3_1
SI3_0
SB3_2
SB3_1
SB3_0
SO3_1
SO3_0
SO4_0
SO4_1
SB4_0
SB4_1
SB4_2
SI4_0
SI4_1
INT34
CHCLK2
1µF
VIN1
PCM Interface
32
5V
1
5 x 680K
5 x 680K
Signaling Interface, Channels 3&4
2466_228
Figure 27
®
SICOFI 4-µC Test Circuit Configuration
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PEB 2466
PEF 2466
Application Hints
Proposal for SICOFI®4-µC Board Design
7.3
For a new layout design it is recommended to use a separate ground-layer which gives
the possibilty to connect all ground-pins of the SICOFI®4-µC (GNDA and GNDD) lowohmic together.
Furthermore, an optimum board layout should follow these recommendations
•
•
•
•
Separate all digital supply lines from analog supply lines as far as possible
Applying the standard practice regarding blocking capacitors is recommended
Place all SLIC circuits as close as possible to the Vinx/Voutx pins of the SICOFI
Separate all analog circuitry (especially SLIC and Vinx/Voutx) as far as possible from
any digital signal source (esp. clock signals)
The ground-plane should
be used for shielding
100 nF
Ceramic
100 nF
Ceramic
Figure 28
VDD
Connector
1-10 µF
Tantal
next to the
connector pins
GND
Connector
GNDA4
VDDA34
GNDD
GNDA3
V REF
VDDREF
GNDA2
VDDA12
GNDA1
VDDD
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
16
33
15
34
14
35
13
36
SICOFI4-µC V2.2
12
37
11
38
10
39
Ground9
40
plane
8
41
7
42
6
43
PEB 2466 H
5
44
4
45
3
46
2
47
1
48
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
100 nF
Ceramic
220 nF
100 nF
Ceramic
Proposal for a ground concept
VDD is the grey colored layer and the Ground-plane is the black colored layer. The
Ground-plane should be on both sides of the board on the top and on the ground layer.
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PEB 2466
PEF 2466
Electrical Characteristics and Timing Diagrams
8
Electrical Characteristics and Timing Diagrams
8.1
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
min.
max.
Unit
VDD referred to GNDD
–0.3
7.0
V
GNDA to GNDD
–0.6
0.6
V
Analog input and output voltage
Referred to VDD = 5 V;
Referred to GNDA = 0 V
–5.3
–0.3
0.3
5.3
V
V
All digital input voltages
Referred to GNDD = 0 V; (VDD = 5V)
Referred to VDD = 5 V; (GNDD = 0 V)
–0.3
–5.3
5.3
0.3
V
V
10
mA
–60
125
°C
–10
80
°C
1
W
DC input and output current at any input
or output pin (free from latch-up)
Storage temperature
Ambient temperature under bias
Power dissipation (package)
TSTG
TA
PD
Test
Condition
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
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PEB 2466
PEF 2466
Electrical Characteristics and Timing Diagrams
8.2
Operating Range
VDD = 5 V ±5%; GNDD = 0 V; GNDA = 0 V;
TA = 0 °C to +70 °C (PEF 2466: -40 °C to +85 °C)
Parameter
Symbol
VDD supply current:
Limit Values
min. typ. max.
Unit
IDD
Test Condition
FSC = 8 kHz,
Standby (PEB 2466)
0.5
1.0
mA PCLK = MCLK =
Standby (PEF 2466)
0.5
1.5
mA 2.048 MHz,
1 channel operating
14
25
mA no loads,
2 channels operating
18
30
mA PCM idle codes,
3 channels operating
22
35
mA VIN= 0V.
4 channels operating
26
40
mA
Power supply rejection
ratio (either direction)
8.3
PSRR
30
dB
Ripple: sine wave
1014 Hz, 70 mVrms,
on every supply pin,
AGX=AGR=AX=AR=0dB
(see Chapter 4.2.4)
Digital Interface
VDD = 5 V ± 5%; GNDD = 0 V; GNDA = 0 V
TA = 0 °C to +70 °C (PEF 2466: -40 °C to +85 °C);
Parameter
Symbol
Limit Values
min.
max.
–0.3
0.8
Unit
Test Condition
Input voltages:
Low level
High level
VIL
VIH
2.0
V
V
Output voltages:
Low level
Low level
High level
High level
High level
Input leakage current
Hardware Reference Manual
VOL
VOL
VOH
VOH
VOH
VIL
0.45
V
0.8
V
4.4
V
4.0
V
2.4
V
±1
47
µA
IOL = – 2 mA
IOL = – 5 mA
IOH = 0.4 mA
IOH = 2 mA
IOH = 5 mA
–0.3 ≤ VIN ≤ VDD
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Electrical Characteristics and Timing Diagrams
8.4
Analog Interface
VDD = 5 V ±5%; GNDD = 0 V; GNDA = 0 V;
TA = 0 °C to +70 °C (PEF 2466: -40 °C to +85 °C)
Parameter
Symbol
Input resistance
PEF 2466
PEB 2466
Ri
Output resistance
Output load
Input leakage current
Input offset voltage
Output offset voltage
Input voltage range (AC)
8.4.1
RO
RL
CL
IIL
VIO
VOO
VIN
Limit Values
Unit
min.
typ.
max.
160
160
270
270
500
380
kΩ
kΩ
0.25
Ω
50
Ω
pF
±1.0
µA
±50
mV
±50
mV
±2.223
V
300
±0.1
Test Condition
0 ≤ VIN ≤ VDD
0 ≤ VIN ≤ VDD
Coupling Capacitors at the Analog Interface
Coupling capacitors are required on pins VIN and VOUT.
The recommended value for VIN is >39 nF. The required value for the VOUT capacitor
depends on the input impedance of the SLIC (see Figure 16 in Chapter 5.1).
8.5
Reset Timing
To reset the SICOFI®4-µC to Reset State, logic low pulses applied to pin RESET# must
be below 1.2 V (TTL-Schmitt-Trigger Input) and must persist longer than 3 µs.
Note: Spikes shorter than 1 µs will be ignored.
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Electrical Characteristics and Timing Diagrams
8.6
PCM-Interface Timing
8.6.1
Single Clocking Mode
t PCLKh
t PCLK
PCLK 50%
t FSC
t FSC_S
t FSC_H
FSC
t DR_S t DR_H
DRA/B
t dDXhz
t dDX
High Imp.
DXA/B
tdTCon
t dTCoff
TCA#/TCB#
Figure 29
2466_229
PCM Interface Timing in Single Clocking Mode
Parameter
Symbol
Limit Values
min.
Period of PCLK
PCLK high time
Period FSC
FSC setup time
FSC hold time
DRA/B setup time
DRA/B hold time
DXA/B delay time 1)
DXA/B delay time to high Z
TCA#/TCB# delay time on
TCA#/TCB# delay time off
1)
tPCLK
tPCLKh
tFSC
tFSC_s
tFSC_h
tDR_s
tDR_h
tdDX
tdDXhz
tdTCon
tdTCoff
typ.
1/8192
0.4*tPCLK
tPCLK/2
Unit
max.
1/128
ms
0.6*tPCLK
µs
125
µs
10
50
ns
40
50
ns
10
50
ns
10
50
ns
25
tdDX_min + tC_Load
ns
25
50
ns
25
tdTCon_min + tC_Load
tdTCoff_min + tC*R
ns
25
ns
Min. delay times: intrinsic time, caused by internal processing. Max. delay times: min. time + delay caused by
external components CLoad and RPullup.:
tC_Load = 0.4ns*CLoad/pF
tC*R
= RPullup*CLoad; RPullup>1.5kΩ
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Electrical Characteristics and Timing Diagrams
8.6.2
Double Clocking Mode
t PCLK
t PCLKh
PCLK 50%
t FSC
t FSC_S
t FSC_H
FSC
t DR_S t DR_H
DRA/B
t dDX
t dDXhz
High Imp.
DXA/B
t dTCon
t dDTCoff
TCA#/TCB#
2466_230
Figure 30
PCM Interface Timing in Double Clocking Mode
Parameter
Symbol
Limit Values
min.
Period of PCLK
PCLK high time
Period FSC
FSC setup time
FSC hold time
DRA/B setup time
DRA/B hold time
DXA/B delay time 1)
DXA/B delay time to high Z
TCA#/TCB# delay time on
TCA#/TCB# delay time off
1)
tPCLK
tPCLKh
tFSC
tFSC_s
tFSC_h
tDR_s
tDR_h
tdDX
tdDXhz
tdTCon
tdTCoff
typ.
1/8192
0.4*tPCLK
tPCLK/2
Unit
max.
1/256
ms
0.6*tPCLK
µs
125
µs
10
50
ns
40
50
ns
10
50
ns
10
50
ns
25
tdDX_min + tC_Load
ns
25
50
ns
25
tdTCon_min + tC_Load
tdTCoff_min + tC*R
ns
25
ns
Min. delay times: intrinsic time, caused by internal processing. Max. delay times: min. time + delay caused by
external components CLoad and RPullup.:
tC_Load = 0.4ns*CLoad/pF,
tC*R
= RPullup*CLoad; RPullup>1.5kΩ
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Electrical Characteristics and Timing Diagrams
8.7
Microcontroller Interface Timing
t DCLKh
t DCLK
DCLK
50%
t CS_S
t CS_h
CS#
t DIN_S t DIN_H
DIN
t dDOUThz
t dDOUT
High Imp.
DOUT
2466_231
Figure 31
Timing of the Microcontroller Interface
Parameter
Symbol
Limit Values
min.
Period of DCLK
DCLK high time
CS# setup time
CS# hold time
DIN setup time
DIN hold time
DOUT delay time 1)
DOUT delay time to high Z
1)
tDCLK
tDCLKh
tCS_s
tCS_h
tDIN_s
tDIN_h
tdDOUT
tdDOUThz
typ.
Unit
max.
1/8192
ms
0.4*tDCLK tDCLK/2
0.6*tDCLK
µs
10
50
ns
30
50
ns
10
50
ns
10
50
ns
30
tdDOUT_min + tC_Load
ns
30
50
ns
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processing,
and a second component tC_Load = 0.4ns*CLoad/pF, caused by external circuitry (C-load).
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Electrical Characteristics and Timing Diagrams
8.8
Signaling Interface Timing
8.8.1
Timing from the µC Interface to the SO/SB-pins
DCLK
DIN
Bit 2
Bit 1
Bit 0
t dSout
SO/SB Output
Old Value
New Value
t dSBZ
High Imp.
SB
(Output
Input)
t dSBD
High Imp.
SB
(Input
Figure 32
Output)
2466_232
Signaling Output Timing (data downstream)
Parameter
Symbol
Limit Values
min.
SO/SB delay time 1)
SB to ‘Z’ - time
SB to ‘drive’-time
1)
tdSout
tdSBZ
tdSBD
typ.
Unit
max.
30
tdSout_min+ tC_Load
ns
40
100
ns
40
tdSBD_min+ tC_Load
ns
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processing,
and a second component tC_Load = 0.4ns*CLoad/pF, caused by external circuitry (C-load).
8.8.2
Timing from the SI/SB-pins to the µC Interface
The register update and interrupt behavior resulting from signaling input changes (data
upstream – pins SI and SB, if programmed as signaling inputs) depend on internal
sampling clocks, counters and register settings. See Chapter 5.3.2 for a functional
description.
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Test Modes
9
Test Modes
Each SICOFI®4-µC channel has four test loops that feed the analog input signal back to
the analog output (analog test loops), and five test loops that feed the PCM input signal
back to the PCM output.
Note: The signal path can also be cut off at two different points per receive and transmit
direction.
9.1
Analog Loops
The four analog loops feed signals from the transmit path back into the receive path.
Figure 33 shows the locations of the analog loops.
Transmit Path
Analog
AGX
ADC
Digital Gain 2
Input
AGR
DAC
Frequency
Response
Digital Gain 1
HPR
TH
Analog
Digital Gain 2
Output
CMP
PCM
Output
ALB-PCM
IM1
HPX
ALB-8K
ALB-4M
ALB-PFI
IM2
Frequency
Response
Digital Gain 1
EXP
PCM
Input
Receive Path
2466_233
Figure 33
Analog Loops
Table 34
Analog Loop Programming in Register CR3, Bits 7 to 4
Test-Loops Analog Loops (CR3.7 = 0)
0000
All loops are disabled (normal operation).
0001
ALB-PFI
Analog Loop Back via PREFI-POFI is selected.
0011
ALB-4M
Analog Loop Back via 4 MHz is selected.
0100
ALB-PCM
Analog Loop Back via 8 kHz (PCM) is selected and in all
channels active.
(required slope setting in XR6.6, XR6.5 = 00 or 11).
0101
ALB-8K
Analog Loop Back via 8 kHz (linear) is selected.
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Test Modes
9.2
Digital Loops
The digital loops feed signals from the receive path back to the transmit path. There are
five digital loops, which are shown in Figure 34.
Transmit Path
AGX
ADC
Digital Gain 2
IM1
DLB-64K
IM2
DLB-128K
DLB-4M
DLB-ANA
Input
DAC
HPX
CMP
PCM
Output
Frequency
Response
Digital Gain 1
HPR
EXP
PCM
Input
TH
Analog
AGR
Frequency
Response
Digital Gain 1
DLB-PCM
Analog
Digital Gain 2
Output
Receive Path
2466_234
Figure 34
Digital Loops
Table 35
Digital Loop Programming in Register CR3, Bits 7 to 4
Test-Loops Digital Loops (CR3.7 = 1)
1000
DLB-ANA
Digital Loop Back via analog port is selected.
1001
DLB-4M
Digital Loop Back via 4 MHz is selected.
1100
DLB-128K
Digital Loop Back via 128 kHz is selected.
1101
DLB-64K
Digital Loop Back via 64 kHz is selected.
1111
DLB-PCM
Digital Loop Back via PCM Registers is selected.
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Test Modes
9.3
Cut-Off’s
The transmit path and the receive path can be cut off at two locations each. Figure 35
shows the locations in the signal paths.
Transmit Path
COT16
Analog
AGX
ADC
Digital Gain 2
Input
IM2
COR4M
DAC
HPX
CMP
Frequency
Response
Digital Gain 1
HPR
EXP
PCM
Output
TH
COR64
Analog
AGR
IM1
COT8
Frequency
Response
Digital Gain 1
Digital Gain 2
Output
PCM
Input
Receive Path
2466_235
Figure 35
Cut-Off’s
Table 36
Cut-Off Programming in Register CR2, Bits 7 to 5.
COT/R
Cut-Off’s in the Transmit and the Receive Paths
000
All Cut-offs disabled (Normal Operation).
001
COT16
Cut Off Transmit path at 16 kHz (input of TH-Filter).
010
COT8
Cut Off Transmit path at 8 kHz (shortens the input of the
compressor unit to ground, resulting in PCM idle codes in the
transmit time slot).
101
COR4M
Cut Off Receive path at 4 MHz (POFI-output).
110
COR64
Cut Off Receive path at 64 kHz (IM-filter input).
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Package Outlines
10
Package Outlines
GPM05250
P-MQFP-64
(Plastic Metric Quad Flat Package)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
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Dimensions in mm
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Glossary
11
Glossary
•
AC
Alternating Current
ADC
Analog-to-Digital Converter
CMOS
Complementary Metal Oxide Semiconductor
CO
Central Office
COT
Central Office Terminal
CRAM
Coefficient RAM
DAC
Digital-to-Analog Converter
DC
Direct Current
DLC
Digital Loop Carrier
DSP
Digital Signal Processor
DTMF
Dual Tone Multi Frequency
FIR
Finite Impulse Response
FTTC
Fiber-To-The-Curb
IIR
Infinite Impulse Response
IOM-2
ISDN-Oriented Modular 2nd Generation
ITU
International Telecommunication Union
ITU-T
International Telecommunication Union-Telecommunication
Standardization Sector (formerly CCITT)
PBX
Private Branch Exchange
PCM
Pulse Code Modulation
PSTN
Public Switched Telephone Network
PTT
Post Telephone Telegraph
QSICOS
Quad SICOFI Coefficient Software
RITL
Radio-In-The-Loop
RT
Remote Terminal
SICOFI
Signal Processor Codec Filter
SLIC
Subscriber Line Interface Circuit
t/r
tip/ring
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Index
Architecture . . . . . . . . . . . . . . . . . . . . . . 2
Attenuation . . . . . . . . . . . . . . . . . . . . . 18
AX . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Symbols
µ-Law . . . . . . . . . . . . . . . 2, 11, 14, 19, 30
µ-Law mode . . . . . . . . . . . . . . . . . . 15, 22
B
Balancing filter . . . . . . . . . . . . . . . . . . . 26
Bi-directional signaling pins . . . . . 6, 8, 34
Blocking capacitors . . . . . . . . . . . . . . . 44
Board design . . . . . . . . . . . . . . . . . . . . 44
Byte-by-byte transfer . . . . . . . . . . . . . . 37
Numerics
0 dBm0-Levels . . . . . . . . . . . . . . . . . . . 14
2-wire to 4-wire conversion. . . . . . . . . . 10
8-bit time slots. . . . . . . . . . . . . . . . . . . . . 2
C
A
Ceramic capacitors . . . . . . . . . . . . . . . 44
Channel operating ranges . . . . . . . . . . 47
Channel-pair . . . . . . . . . . . . . . . . . . . . 34
Channels . . . . . . . . . . . . . . . 2, 22, 29, 39
Channel-specific coefficients . . . . . . . . 41
Channel-specific registers . 11, 12, 39, 40
Chip Select . . . . . . . . . . . . . . . . 6, 35, 36
Chopper Clock. . . . . . . . . . . . . . . 6, 8, 34
Clock . . . . . . . . . . . . . . . . . 11, 32, 34, 35
Clock output signals . . . . . . . . . . . . . . . 2
Clock programming . . . . . . . . . . . . . . . 35
C-message . . . . . . . . . . . . . . . . . . . . . 19
Codec filter . . . . . . . . . . . . . . . . . . . . . . 2
Coefficient calculation &
configuration software . . . . . . . . . . . . . . 3
Coefficient Operation (COP) command . . . 42
Coefficient operation commands . . . . . 41
Coefficient RAM. . . . . . 11, 35, 36, 39, 41
Command sequences . . . . . . . . . . 37, 42
Command type . . . . . . . . . . . . . . . . . . 42
Commands . . . . . . . . . . . . . . . . . . . . . 36
Common configuration registers . . 11, 39, 40
Compression . . . . . . . . . . . . . . . . . . . . . 3
Compressor . . . . . . . . . . . . . . . . . . . . . 11
Configuration of interfaces. . . . . . . . . . 27
Configuration registers . . . . . . . . . 36, 39
Control Data input/output pins . . . . . . . 36
Conversion utilities . . . . . . . . . . . . . . . 43
A/µ-Law compression/expansion . . . . . . 3
A/D and D/A converters . . . . . . 11, 18, 26
A/D converters . . . . . . . . . . . . . . . . 14, 23
Absolute gain . . . . . . . . . . . . . . . . . . . . 17
Absolute group delay . . . . . . . . . . . . . . 18
Absolute maximum ratings . . . . . . . . . . 46
AC transmission characteristics . . . . . . 27
Accuracy of digital filters . . . . . . . . . 10, 11
ADC . . . . . . . . . . . . . . . . . . . . . . . . . 2, 11
ADC and DAC. . . . . . . . . . . . . . . . . . . . . 3
A-Law . . . . . . . . . . . . . . . 2, 11, 14, 19, 30
A-Law mode . . . . . . . . . . . . . . . . . . . . . 15
Ambient temperature . . . . . . . . . . . . . . 46
Analog ground pins. . . . . . . . . . . . 8, 9, 29
Analog I/O. . . . . . . . . . . . . . . . . . . . . . . . 2
Analog input . . . . . . . . . . . . . . . . . . . . . 13
Analog input/output pins . . . . . . . . . . . . 29
Analog Interface . . . . . . . 3, 14, 27, 28, 48
Analog Interface pins . . . . . . . . . . . . . . 29
Analog loop programming. . . . . . . . . . . 53
Analog loops . . . . . . . . . . . . . . . . . . . 3, 53
Analog output . . . . . . . . . . . . . . . . . . . . 13
Analog supply . . . . . . . . . . . . . . . . . . . . 45
Analog voice input/output pins . . . . . . 8, 9
Analog voltage levels . . . . . . . . . . . . . . 14
Application hints . . . . . . . . . . . . . . . . . . 43
Application Notes . . . . . . . . . . . . . . . . . . 1
AR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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DOUT . . . . . . . . . . . . . . . . . . . . . . . . . 51
Driving capability . . . . . . . . . . . . . . . 3, 27
DSP core . . . . . . . . . . . . . . . . 2, 3, 10, 11
DTMF. . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Dynamic gain. . . . . . . . . . . . . . . . . . . . . 3
Dynamic range . . . . . . . . . . . . . . . . . . 11
COP . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
COP command sequences. . . . . . . . . . 41
Country-specific adaptations . . . . . . . . 10
Coupling capacitors . . . . . . . . . 27, 29, 48
CR0 to CR5 . . . . . . . . . . . . . . . . . . . . . 39
CR0 to CR7 . . . . . . . . . . . . . . . . . . . . . 40
CRAM . . . . . . . . . . . 11, 35, 36, 39, 41, 42
CRAM structure . . . . . . . . . . . . . . . . . . 41
Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . 22
CR-Registers . . . . . . . . . . . . . . . . . . . . 11
CS#. . . . . . . . . . . . . . . . . . . . . . . . . 35, 51
Cut-Off programming . . . . . . . . . . . . . . 55
Cut-Off’s . . . . . . . . . . . . . . . . . . . . . . . . 55
E
EASY 2466 . . . . . . . . . . . . . . . . . . . 3, 43
EASY 2466 evaluation system . . . . . . 43
Echo . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical characteristics . . . . . . . . . . . 46
Evaluation boards . . . . . . . . . . . . . . . . 43
EVC50x . . . . . . . . . . . . . . . . . . . . . . . . 43
Expander . . . . . . . . . . . . . . . . . . . . . . . 11
Expansion . . . . . . . . . . . . . . . . . . . . . . . 3
Extended Operation (XOP) command . . .42
Extended temperature range. . . . . . . . . 2
External amplifier. . . . . . . . . . . . . . . . . 27
External components. . . . . . . . . . . . . . 26
D
DAC . . . . . . . . . . . . . . . . . . . . . . . . . 2, 11
Data bytes. . . . . . . . . . . . . . . . . . . . . . . 36
Data Clock . . . . . . . . . . . . . . . . . . . . 6, 36
Data input pins . . . . . . . . . . . . . . . . . . . . 6
Data output pins . . . . . . . . . . . . . . . . . . . 7
Data pins. . . . . . . . . . . . . . . . . . . . . . . . 35
Data rates . . . . . . . . . . . . . . . . . . 3, 11, 30
Data receive pins . . . . . . . . . . . . . . . . . . 7
Data transmit pins. . . . . . . . . . . . . . . . . . 7
DCLK . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Debouncing functions . . . . . . . . . . . 32, 34
Decimation . . . . . . . . . . . . . . . . . . . . . . 11
Detect specific tones. . . . . . . . . . . . . . . 10
Development boards. . . . . . . . . . . . . 3, 43
Digital filters . . . . . . . . . . . . . . . . . . . . . . 3
Digital ground pins . . . . . . . . . . . . . . . . . 7
Digital input . . . . . . . . . . . . . . . . . . . . . . 13
Digital interface . . . . . . . . . . . . . . . . . . . 47
Digital loop programming . . . . . . . . . . . 54
Digital loops . . . . . . . . . . . . . . . . . . . 3, 54
Digital output. . . . . . . . . . . . . . . . . . . . . 13
Digital switching & transmission system . . . 2
Digital, programmable filters . . . . . . . . . 10
DIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DLC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Double clocking mode timing . . . . . . . . 50
Hardware Reference Manual
F
Fiber-to-the-Curb Systems . . . . . . . . . . 4
Filter capacitors . . . . . . . . . . . . . . . . . . 44
Filter characteristics. . . . . . . . . . . . . . . 10
Filter coefficients . . . . . . . . . . . . . . . . . 27
Filter coefficients storage. . . . . . . . . . . 11
Filter structures . . . . . . . . . . . . . . . . . . 11
Flow diagram . . . . . . . . . . . . . . . . . . . . 16
Fluctuation . . . . . . . . . . . . . . . . . . . . . . 10
Four-wire interface. . . . . . . . . . . . . . . . 10
Frame . . . . . . . . . . . . . . . . . . . . . . . . . 30
Frame delay. . . . . . . . . . . . . . . . . . . . . 30
Frame Synchronization Clock . . . . . 7, 30
Frequency correction. . . . . . . . . . . . . . 11
Frequency response . . . . . . . . . 3, 18, 27
Frequency response corrections . . 10, 16
FRR . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FRX . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FSC . . . . . . . . . . . . . . . . . . . . . . . . 49, 50
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PEB 2466
PEF 2466
Functional blocks . . . . . . . . . . . . . . . . . 39
Interfaces. . . . . . . . . . . . . . . . . . . . . . . 39
Intermodulation . . . . . . . . . . . . . . . . . . 20
Intermodulation distortion . . . . . . . . . . 20
Internal registers . . . . . . . . . . . . . . . . . 35
Interpolation. . . . . . . . . . . . . . . . . . . . . 11
Interrupt generation . . . . . . . . . . . . . . . 34
Interrupt output pin . . . . . . . . . . . . . . . . 8
Interrupt output pins. . . . . . . . . . . . . 6, 34
Interrupt pins . . . . . . . . . . . . . . . . . . . . 32
Inventory costs . . . . . . . . . . . . . . . . . . . 4
ITU-T . . . . . . . . . . . . . . . . . . . . . 3, 14, 16
G
Gain . . . . . . . . . . . . . . . . . . . . . . . . 15, 26
Gain accuracy. . . . . . . . . . . . . . . . . . . . 17
Gain deviations with input level . . . . . . 17
Gain tracking. . . . . . . . . . . . . . . . . . . . . 17
Ground pins . . . . . . . . . . . . . . . . . . . . . 45
Ground plane . . . . . . . . . . . . . . . . . . . . 45
Ground-key detection . . . . . . . . . . . . . . 10
Group delay . . . . . . . . . . . . . . . . . . 18, 26
Group delay absolute values . . . . . . . . 18
Group delay distortion. . . . . . . . . . . . . . 19
K
Key Systems . . . . . . . . . . . . . . . . . . . . . 4
H
L
Hardware filters. . . . . . . . . . . . . . . . 11, 23
Hardware reset . . . . . . . . . . . . . . . . . . . 12
Harmonic distortion. . . . . . . . . . . . . . . . 20
High impedance state . . . . . . . . . . . . . . 36
Highway . . . . . . . . . . . . . . . . . . . . . . . . 11
HW-Reset . . . . . . . . . . . . . . . . . . . . . . . 12
Level adjustments . . . . . . . . . . . . . 10, 11
Level metering . . . . . . . . . . . . . . . . . 3, 10
Line characterization . . . . . . . . . . . . . . 10
Linearity . . . . . . . . . . . . . . . . . . . . . . 3, 11
Linecard functions . . . . . . . . . . . . . . . . 10
Load capacities . . . . . . . . . . . . . . . . . . 14
Local requirements . . . . . . . . . . . . . . . 10
Loop filters . . . . . . . . . . . . . . . . . . . . . . 10
I
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . 32
Identification byte . . . . . . . . . . . . . . . . . 36
Idle channel noise. . . . . . . . . . . . . . . . . 19
IM-filter . . . . . . . . . . . . . . . . . . . . . . 26, 41
Impedance matching . . . . . . 3, 10, 11, 16
Independent filter structures . . . . . . . . . . 2
Industry–standard PCM Interface . . . . . 30
Input impedance . . . . . . . . . . . . 10, 29, 48
Input leakage current . . . . . . . . . . . 47, 48
Input offset voltage . . . . . . . . . . . . . . . . 48
Input pins . . . . . . . . . . . . . . . . . . . . 12, 32
Input resistance . . . . . . . . . . . . . . . 27, 48
Input voltage range (AC). . . . . . . . . . . . 48
Input voltages . . . . . . . . . . . . . . . . . . . . 47
INT12 . . . . . . . . . . . . . . . . . . . . . . . . . . 34
INT34 . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Interface description . . . . . . . . . . . . . . . 27
Hardware Reference Manual
M
Manufacturing test . . . . . . . . . . . . . . . . . 3
Master Clock . . . . . . . . . . . . . . . . . . 7, 34
Maximum signal levels . . . . . . . . . . . . 14
Measurements. . . . . . . . . . . . . . . . . . . 43
Microcontroller . . . . . . . . . . . . . . . . . . . 10
Microcontroller Interface . . 10, 35, 41, 42
Microcontroller Interface timing . . . . . . 51
Microcontrollers . . . . . . . . . . . . . . . . . . 27
N
Noise . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Noise rejection. . . . . . . . . . . . . . . . . . . 44
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PEF 2466
O
PEF 2466. . . . . . . . . . . . . . . . . . . . . . . . 1
Pin configuration . . . . . . . . . . . . . . . . . . 5
Pin definitions and functions . . . . . . . . . 6
Pin descriptions . . . . . . . . . . . . . . . . . . . 5
Pin diagram . . . . . . . . . . . . . . . . . . . . . . 5
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power dissipation . . . . . . . . . . . . . 12, 14
Power dissipation (package) . . . . . . . . 46
Power On. . . . . . . . . . . . . . . . . . . . . . . 12
Power spectral density . . . . . . . . . . . . 25
Power supply rejection ratio . . . . . . . . 47
Power-saving state . . . . . . . . . . . . . . . 12
POWER-UP state . . . . . . . . . . . . . . . . 34
Product Brief . . . . . . . . . . . . . . . . . . . . . 1
Product Overview . . . . . . . . . . . . . . . . . 1
Programmable debouncing . . . . . . . . . . 3
Programmable digital filters . . . . . . . . . . 3
Programmable filters . . . . . . . . . . . . . . 26
Programmable frequency . . . . . . . . . . 13
Programmable tone generators. . . . . . . 3
Programmer’s Reference Manual . . . . . 1
Programming overview . . . . . . . . . . . . 39
PSB 2132 . . . . . . . . . . . . . . . . . . . . . . . 1
PSB 2134 . . . . . . . . . . . . . . . . . . . . . . . 1
Psophometric. . . . . . . . . . . . . . . . . . . . 19
On-/off-hook detection . . . . . . . . . . . . . 10
Operating conditions. . . . . . . . . . . . . . . 16
Operating range . . . . . . . . . . . . . . . . . . 47
Operating state . . . . . . . . . . . . . . . . 12, 13
Operating states . . . . . . . . . . . . . . . . . . 12
Operation of interfaces . . . . . . . . . . . . . 27
Operational description. . . . . . . . . . . . . 12
Optimization . . . . . . . . . . . . . . . . . . . . . 43
Other SICOFI devices. . . . . . . . . . . . . . . 1
Out-of-band discrimination . . . . . . . 23, 24
Out-of-band idle channel noise. . . . . . . 25
Out-of-band signal . . . . . . . . . . . . . . . . 24
Out-of-band signals . . . . . . . . . . . . . . . 27
Output load . . . . . . . . . . . . . . . . . . . . . . 48
Output offset voltage. . . . . . . . . . . . . . . 48
Output resistance . . . . . . . . . . . . . . . . . 48
Output voltages. . . . . . . . . . . . . . . . . . . 47
Overload compression . . . . . . . . . . . . . 22
Overload point . . . . . . . . . . . . . 14, 22, 27
Oversampling . . . . . . . . . . . . . . . . . . . . 11
P
Package . . . . . . . . . . . . . . . . . . . . . . . . . 3
Package Outlines . . . . . . . . . . . . . . . . . 56
PCLK . . . . . . . . . . . . . . . . . . . . . . . 49, 50
PCM Clock . . . . . . . . . . . . . . . . . . . . . . 30
PCM clock. . . . . . . . . . . . . . . . . . . . . . . 30
PCM Data Clock . . . . . . . . . . . . . . . . . . . 8
PCM data format. . . . . . . . . . . . . . . . . . 30
PCM highway A . . . . . . . . . . . . . . . . . . . 7
PCM highway B . . . . . . . . . . . . . . . . . . . 7
PCM highways . . . . . . . . . . . . 2, 3, 27, 30
PCM Interface. . . . . . . . . . . . . . . 3, 14, 27
PCM Interface timing . . . . . . . . . . . . . . 50
PCM ports. . . . . . . . . . . . . . . . . . . . . . . 11
PCM-Interface timing . . . . . . . . . . . . . . 49
Peak amplitude . . . . . . . . . . . . . . . . 14, 27
PEB 2266 . . . . . . . . . . . . . . . . . . . . . . . . 1
PEB 2466 . . . . . . . . . . . . . . . . . . . . . . . . 1
Hardware Reference Manual
Q
QSICOS. . . . . . . . . . . . . . . . . . . . . . 3, 43
R
Radio-in-the-Loop Systems . . . . . . . . . . 4
Read access . . . . . . . . . . . . . . . . . 36, 40
Read commands . . . . . . . . . . . . . . 36, 37
Receive data input pins . . . . . . . . . . . . 30
Receive delay . . . . . . . . . . . . . . . . . . . 18
Receive path . . . . . . . . . . . 10, 53, 54, 55
Reference voltage pin . . . . . . . . . . . 9, 29
Register maps . . . . . . . . . . . . . . . . . . . 40
Register model . . . . . . . . . . . . . . . . . . 39
Register values . . . . . . . . . . . . . . . . . . 13
61
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PEF 2466
Registers. . . . . . . . . . . . . . . . . . . . . . . . 11
Reset input pin . . . . . . . . . . . . . . . . . . . . 7
Reset state . . . . . . . . . . . . . . . . 12, 13, 48
Reset timing . . . . . . . . . . . . . . . . . . . . . 48
RESET# . . . . . . . . . . . . . . . . . . . . . . . . 12
RESET# pin . . . . . . . . . . . . . . . . . . . . . 48
Resolution. . . . . . . . . . . . . . . . . . . . . . . 11
Return loss . . . . . . . . . . . . . . . . . . . . . . 10
Ring signals . . . . . . . . . . . . . . . . . . . . . 10
RITL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
RST. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Signal-to-total distortion ratio. . . . . . . . 20
Sine wave signal . . . . . . . . . . . . . . . . . 14
Single clocking mode timing . . . . . . . . 49
Single frequency distortion . . . . . . . . . 22
SLIC. . . . . . . . . . . . . . 2, 3, 10, 16, 26, 27
SLIC daughter cards . . . . . . . . . . . . . . 43
SLIC interfaces . . . . . . . . . . . . . . . . . . 34
SOP . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Specifications . . . . . . . . . . . . . . . . . . . 16
Spikes . . . . . . . . . . . . . . . . . . . . . . . . . 48
Standard temperature range . . . . . . . . . 2
Standby operating range . . . . . . . . . . . 47
Standby state. . . . . . . . . . . . . . . . . 12, 13
State diagram . . . . . . . . . . . . . . . . . . . 12
States . . . . . . . . . . . . . . . . . . . . . . 12, 13
Status Operation (SOP) command . . . 42
Storage temperature . . . . . . . . . . . . . . 46
Subscriber line interface circuits . . . 2, 10, 27
Subscriber lines . . . . . . . . . . . . . . . . . . 32
Supervision and signaling functions . . 32
Supply current . . . . . . . . . . . . . . . . . . . 47
Supply voltage . . . . . . . . . . . . . . . . . . . . 3
Supply voltage pins . . . . . . . . . . . 7, 8, 29
Support tools . . . . . . . . . . . . . . . . . . 3, 43
SW-Reset . . . . . . . . . . . . . . . . . . . . . . 12
System diagnostics . . . . . . . . . . . . . . . . 3
System tests . . . . . . . . . . . . . . . . . . . . . 3
S
Sampling. . . . . . . . . . . . . . . . . . . . . . . . 36
Sampling intervals . . . . . . . . . . . . . . . . 34
Sampling slopes . . . . . . . . . . . . . . . . . . 30
Schmitt-Trigger input . . . . . . . . . . . . . . 48
Serial input . . . . . . . . . . . . . . . . . . . . . . 13
Serial Interface . . . . . . . . . . . . . . . . . . . . 2
Serial Microcontroller Interface . . . 10, 27, 35
Serial output . . . . . . . . . . . . . . . . . . . . . 13
Sigma-delta. . . . . . . . . . . . . . . . . . . . . . 11
Signal levels . . . . . . . . . . . . . . . . . . . 3, 15
Signal paths . . . . . . . . . . . . . . . . . . . . . 55
Signal power transfer . . . . . . . . . . . . . . 10
Signal processor . . . . . . . . . . . . . . . . . . 10
Signal reflections . . . . . . . . . . . . . . . . . 10
Signal rejection . . . . . . . . . . . . . . . . . . . 23
Signaling example . . . . . . . . . . . . . . . . 33
Signaling input pins. . . . . . . . . . . . 6, 8, 34
Signaling input/output pins . . . . . . . . . . 11
Signaling Interface . . . . . . . . . . 10, 27, 32
Signaling Interface pins . . . . . . . . . . . . 34
Signaling Interface timing . . . . . . . . . . . 52
Signaling output pins . . . . . . . . . . 6, 8, 34
Signaling output timing . . . . . . . . . . . . . 52
Signaling pins . . . . . . . . . . . . . . . . . . 2, 32
Signaling registers . . . . . . . . . . . . . . . . 34
Signaling status changes . . . . . . . . . . . 32
Signal-to-noise performance. . . . . . . . . 11
Signal-to-total distortion . . . . . . . . . . . . 21
Hardware Reference Manual
T
Tantalum capacitors . . . . . . . . . . . . . . 44
Telco specification . . . . . . . . . . . . . . . . 27
Telephone line . . . . . . . . . . . . . . . . . . . 27
Telephone linecard . . . . . . . . . . . . . . . 10
Telephone subscriber loop . . . . . . . . . 10
Teletax filters . . . . . . . . . . . . . . . . . . . . 27
Teletax pulses . . . . . . . . . . . . . . . . 23, 27
Test circuit . . . . . . . . . . . . . . . . . . . . . . 44
Test conditions . . . . . . . . . . . . . . . . . . 16
Test loop . . . . . . . . . . . . . . . . . . . . . . . 26
Test loops . . . . . . . . . . . . . . . . . . . . . . 53
Test modes . . . . . . . . . . . . . . . . . . . . . 53
62
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PEF 2466
X
Test relays . . . . . . . . . . . . . . . . . . . . . . 10
TG1 and TG2 . . . . . . . . . . . . . . . . . . . . 41
TH-filter . . . . . . . . . . . . . . . . . . . . . . 39, 41
Three-Wire access . . . . . . . . . . . . . . . . 38
Time slot assignment . . . . . . . . . . . . 3, 11
Time slots . . . . . . . . . . . . . . . . . . . . . 2, 30
Time to market . . . . . . . . . . . . . . . . . . . . 4
Timing . . . . . . . . . . . . . . . . . . . . 49, 51, 52
Timing diagrams . . . . . . . . . . . . . . . . . . 46
Tip & ring . . . . . . . . . . . . . . . . . . . . . . . 27
Tone generators . . . . . . . . . . . . . . . . 3, 10
Tool package . . . . . . . . . . . . . . . . . . . . 43
Total distortion . . . . . . . . . . . . . . . . 20, 21
Total gain calculation . . . . . . . . . . . . . . 15
Transfer functions . . . . . . . . . . . . . . . . . 27
Transformer . . . . . . . . . . . . . . . . 3, 10, 27
Transformer SLIC . . . . . . . . . . . . . . . . . 27
Transhybrid balancing . . 3, 10, 11, 16, 26
Transhybrid loss . . . . . . . . . . . . . . . 10, 26
Transmission characteristics. . . 10, 14, 16, 39
Transmission system . . . . . . . . . . . . . . 43
Transmit control output pins . . . . . . . . . 30
Transmit data output pins . . . . . . . . . . . 30
Transmit delay . . . . . . . . . . . . . . . . . . . 18
Transmit path . . . . . . . . . . . 10, 53, 54, 55
Two-wire interface . . . . . . . . . . . . . . . . 10
Types of commands . . . . . . . . . . . . . . . 42
XOP . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
XR0 to XR7 . . . . . . . . . . . . . . . . . . . . . 40
XR-Registers . . . . . . . . . . . . . . . . . . . . 11
V
VIN-pins . . . . . . . . . . . . . . . . . . . . . . . . 27
Voice channels . . . . . . . . . . . . . . . . . . . 11
Voltage levels . . . . . . . . . . . . . . . . . . . . 12
VOUT-pins . . . . . . . . . . . . . . . . . . . . . . 27
W
Waiting time . . . . . . . . . . . . . . . . . . . . . 37
Website. . . . . . . . . . . . . . . . . . . . . . . . . . 1
Write access . . . . . . . . . . . . . . . . . . 36, 40
Write commands. . . . . . . . . . . . . . . 36, 37
Hardware Reference Manual
63
2001-02-20
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