Features • MPEGI/II-Layer 3 Hardwired Decoder • • • • • • • • • • • • • • • • • • • • – Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 KHz Sampling Frequency – Separated Digital Volume Control on Left and Right Channels (Software Control Using 31 Steps) – Bass, Medium, and Treble Control (31 Steps) – Bass Boost Sound Effect – Ancillary Data Extraction – “CRC Error” and “MPEG Frame Synchronization” Indicators Programmable Audio Output for Interfacing With Common Audio DAC – PCM Format Compatible – I2S Format Compatible 8-bit MCU C51 Core Based (FMAX = 20 MHz) 2304 bytes of Internal RAM 64 Kbytes of Code Memory – Flash: AT89C51SND1A, ROM: AT83C51SND1A 4 Kbytes of Boot Flash Memory (AT89C51SND1A) – ISP: Download from USB or UART to any External Memory Cards USB Rev 1.1 Controller – “Full Speed” Data Transmission Built-in PLL – MP3 Audio Clocks – USB Clock MultiMediaCard™ Interface Compatibility Atmel DataFlash™ SPI Interface Compatibility IDE/ATAPI Interface 2 Channels 10-bit ADC, 8 KHz (8 True Bit) – Battery Voltage Monitoring – Voice Recording Controlled by Software Up to 44 bits of General-purpose I/Os for: – 4-bit Interrupt Keyboard Port for a 4 x n Matrix – Smartmedia™ Software Interface Standard Two 16-bit Timers/Counters Hardware Watchdog Timer Standard Full Duplex UART with Baud Rate Generator 2-wire Master and Slave Modes Controller SPI Master and Slave Modes Controller Power Management – Power-on reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode Operating Conditions: – 3V, ±10%, 25 mA Typical Operating at 25°C – Temperature Range: -40°C to +85°C Packages – TQFP80, PLCC84 (Development Board) – Dice Single Chip Microcontroller with MP3 Decoder and Man Machine Interface AT8xC51SND1A Preliminary Description The AT8xC51SND1A is a fully integrated stand-alone hardwired MPEGI/II-Layer 3 decoder with a C51 microcontroller core handling data flow and MP3-player control. The AT89C51SND1A includes 64 Kbytes of Flash memory and allows In-System Programming through an embedded 4 Kbytes of Boot Flash Memory. Rev. 4106E–8051–03/02 1 The AT83C51SND1A includes 64 Kbytes of ROM memory. The AT8xC51SND1A includes 2304 bytes of RAM memory. The AT8xC51SND1A provides all necessary features for man machine interface like timers, keyboard port, serial or parallel interface (USB, 2-wire, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia). Typical Applications 2 • MP3 Player • PDA, Camera, Mobile Phone MP3 • Car Audio/Multimedia MP3 • Home Audio/Multimedia MP3 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Pin Description Pinouts 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS# P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 Figure 1. AT8xC51SND1A 80-pin TQFP Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 AT89C51SND1A-RO (Flash) AT83C51SND1A-RO (ROM) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/RD# AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ALE ISP# P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PVDD FILT PVSS VSS X2 X1 TST# UVDD UVSS 3 4106E–8051–03/02 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS# P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 Figure 2. AT8xC51SND1A 84-pin PLCC Package 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AT89C51SND1A-SR (Flash) 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0# P3.3/INT1# P3.4/T0 P3.5/T1 P3.6/WR# P3.7/RD# AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 NC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 ALE ISP# P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PAVDD FILT PAVSS VSS X2 NC X1 TST# UVDD UVSS Signals All AT8xC51SND1A signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description Signal Name 4 Type Alternate Function Description P0.7:0 I/O Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to V DD or VSS. P1.7:0 I/O Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups. AD7:0 KIN3:0 SCL SDA AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Table 1. Ports Signal Description (Continued) Signal Name Type P2.7:0 I/O Description Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Alternate Function A15:8 RXD TXD INT0# INT1# T0 T1 WR# RD# P3.7:0 I/O Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups. P4.7:0 I/O Port 4 P4 is an 8-bit bidirectional I/O port with internal pull-ups. MISO MOSI SCK SS# P5.3:0 I/O Port 5 P5 is a 4-bit bidirectional I/O port with internal pull-ups. - Table 2. Clock Signal Description Signal Name Type Description Alternate Function X1 I Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. X2 O Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected. - FILT I PLL Low Pass Filter input FILT receives the RC network of the PLL low pass filter. - - Table 3. Timer 0 and Timer 1 Signal Description Signal Name Type Description Alternate Function Timer 0 Gate Input INT0# serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0# I External Interrupt 0 INT0# input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0#. If bit IT0 is cleared, bit IE0 is set by a low level on INT0#. P3.2 Timer 1 Gate Input INT1# serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1# I External Interrupt 1 INT1# input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1#. If bit IT1 is cleared, bit IE1 is set by a low level on INT1#. P3.3 5 4106E–8051–03/02 Table 3. Timer 0 and Timer 1 Signal Description (Continued) Signal Name Type Alternate Function T0 I Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. P3.4 T1 I Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.5 Description Table 4. Audio Interface Signal Description Signal Name Type Alternate Function DCLK O DAC Data Bit Clock - DOUT O DAC Audio Data - DSEL O DAC Channel Select Signal DSEL is the sample rate clock output. - SCLK O DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). - Description Table 5. USB Controller Signal Description Signal Name Type Alternate Function D+ I/O USB Positive Data Upstream Port This pin requires an external 1.5 kΩ pull-up to VDD for full speed operation. - D- I/O USB Negative Data Upstream Port - Description Table 6. MutiMediaCard Interface Signal Description 6 Signal Name Type Alternate Function MCLK O MMC Clock output Data or command clock transfer. - MCMD I/O MMC Command line Bidirectional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. - MDAT I/O MMC Data line Bidirectional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to V DD or VSS. - Description AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Table 7. UART Signal Description Signal Name Type RXD I/O Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. P3.0 TXD O Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. P3.1 Description Alternate Function Table 8. SPI Controller Signal Description Signal Name Type MISO I/O SPI Master Input Slave Output Data Line When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. P4.0 MOSI I/O SPI Master Output Slave Input Data Line When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. P4.1 SCK I/O SPI Clock Line When in master mode, SCK outputs clock to the slave peripheral. When in slave mode, SCK receives clock from the master controller. P4.2 SS# I SPI Slave Select Line When in controlled slave mode, SS# enables the slave mode. P4.3 Description Alternate Function Table 9. Two-wire Controller Signal Description Signal Name Type Description SCL I/O 2-wire Serial Clock When 2-wire controller is in master mode, SCL outputs the serial clock to the slave peripherals. When 2-wire controller is in slave mode, SCL receives clock from the master controller. SDA I/O 2-wire Serial Data SDA is the bidirectional 2-wire data line. Alternate Function P1.6 P1.7 Table 10. A/D Converter Signal Description Signal Name Type AIN1:0 I A/D Converter Analog Inputs - AREFP I Analog Positive Voltage Reference Input - AREFN I Analog Negative Voltage Reference Input This pin is internally connected to AVSS. - Description Alternate Function 7 4106E–8051–03/02 Table 11. Keypad Interface Signal Description Signal Name Type KIN3:0 I Alternate Function Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. P1.3:0 Table 12. External Access Signal Description Signal Name Type Alternate Function A15:8 I/O Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. P2.7:0 AD7:0 I/O Address/Data Lines Multiplexed lower address and data lines for the external memory or the IDE interface. P0.7:0 ALE O Address Latch Enable Output ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus. - ISP# I/O ISP Enable Input This signal must be held to GND through a pull-down resistor at the falling reset to force execution of the internal bootloader. - RD# O Read Signal Read signal asserted during external data memory read operation. P3.7 WR# O Write Signal Write signal asserted during external data memory write operation. P3.6 Description Table 13. System Signal Description Signal Name 8 Type Alternate Function Description RST I Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than V IL is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-down mode returns the chip to normal operation. TST# I Test Input Test mode entry signal. This pin must be set to VDD. - - AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Table 14. Power Signal Description Signal Name Type Description Alternate Function VDD PWR Digital Supply Voltage Connect these pins to +3V supply voltage. - VSS GND Circuit Ground Connect these pins to ground. - AVDD PWR Analog Supply Voltage Connect this pin to +3V supply voltage. - AVSS GND Analog Ground Connect this pin to ground. - PVDD PWR PLL Supply voltage Connect this pin to +3V supply voltage. - PVSS GND PLL Circuit Ground Connect this pin to ground. - UVDD PWR USB Supply Voltage Connect this pin to +3V supply voltage. - UVSS GND USB Ground Connect this pin to ground. - 9 4106E–8051–03/02 Internal Pin Structure Table 15. Detailed Internal Pin Structure Circuit(1) Type Pins Input TST# Input/Output RST Input/Output P1(2) P2(3) P3 P4 P53:0 RTST VDD VDD P RRST Watchdog Output VSS 2 osc periods Latch Output VDD VDD VDD P1 P2 P3 N VSS VDD P Input/Output N P0 MCMD MDAT ISP# VSS ALE SCLK DCLK VDD P Output N DOUT DSEL MCLK VSS D+ Input/Output D+ D- D- Note: 1. For information on resistors value, input/output levels, and drive capability, refer to the Section “DC Characteristics”, page 32. 2. When the 2-wire controller is enabled, P1, P2, and P3 transistors are disabled allowing pseudo open-drain structure. 3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8). 10 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Block Diagram Figure 3. AT8xC51SND1A Block Diagram INT0# 3 INT1# VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 3 Interrupt Handler Unit RAM 2304 bytes C51 (X2 CORE) Clock and PLL Unit Flash ROM 64 Kbytes Flash Boot 4 Kbytes 10-bit A to D Converter or 10-bit ADC TXD RXD T0 3 3 3 UART and BRG T1 3 SS# MISO MOSI SCK SCL SDA 4 1 Timers 0/1 Watchdog 4 4 4 SPI/DataFlash Controller 1 2-wire Controller 8-BIT INTERNAL BUS MP3 Decoder Unit I2S / PCM Audio Interface USB Controller MMC Interface Keyboard Interface I/O Ports IDE Interface 1 FILT X1 X2 RST ISP# ALE DOUT DCLK DSEL SCLK D+ D- MCLK MDAT MCMD KIN3:0 P0-P5 1 Alternate function of Port 1 3 Alternate function of Port 3 4 Alternate function of Port 4 11 4106E–8051–03/02 Application Information Battery Figure 4. AT8xC51SND1A Typical Application with On-board Atmel DataFlash and 2-wire LCD RST VDD AVDD VREFP VREFN Ref. AIN0 P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P0.0 P0.1 P0.2 P0.3 AIN1 P1.6/SCL P1.7/SDA LCD MMC1 MCLK MDAT MCMD AT8xC51SND1A UVDD X1 D+ D- USB PORT AVSS VSS P1.4 DOUT DCLK DSEL SCLK P4.0/SI DataFlash Memories P1.5 UVSS P4.1/SO P4n FILT P4.2/SCK X2 PVSS MMC2 Audio DAC RST AVDD VDD VREFP Ref. VREFN P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P0.0 P0.1 P0.2 P0.3 AIN1 P1.3 P0.4 P0.5 P0.6 P0.7 P1.6/SCL P1.7/SDA LCD AIN0 Battery Figure 5. AT8xC51SND1A Typical Application with On-board Atmel DataFlash and LCD MCLK MDAT MCMD AT8xC51SND1A D+ D- X2 DataFlash Memories USB PORT AVSS VSS P1.5 P1.4 DOUT DCLK DSEL SCLK P4.0/SI P4.1/SO P4.n FILT P4.2/SCK UVSS 12 MMC2 UVDD X1 PVSS MMC1 Audio DAC AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Battery Figure 6. AT8xC51SND1A Typical Application with On-board SSFDC Flash RST VDD AVDD VREFP VREFN Ref. AIN0 P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P0.0 P0.1 P0.2 P0.3 AIN1 P4.0 P4.1 P4.2 P4.4 P4.5 P4.6 P4.7 LCD MMC1 MCLK MDAT MCMD AT8xC51SND1A MMC2 UVDD D+ D- X1 USB PORT X2 AVSS VSS P3.5 P3.4 DOUT DCLK DSEL SCLK PVSS P0 P2 FILT P3.7/RD# P3.6/WR# UVSS Audio DAC SSFDC Memories or SmartMedia Cards SmartMedia RST AVDD VDD VREFP Ref. VREFN P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P0.0 P0.1 P0.2 P0.3 AIN1 P4.0 P4.1 P4.2 P4.4 P4.5 P4.6 P4.7 P1.6/SCL P1.7/SDA LCD AIN0 Battery Figure 7. AT8xC51SND1A Typical Application with IDE CD-ROM Drive MCLK MDAT MCMD AT8xC51SND1A MMC2 UVDD X1 D+ D- USB PORT AVSS VSS P3.5 P3.4 UVSS DOUT DCLK DSEL SCLK P3.7/RD# P0 P2 FILT P3.6/WR# X2 PVSS MMC1 Audio DAC IDE CD-ROM 13 4106E–8051–03/02 Address Spaces Code Memory The AT8xC51SND1A derivatives implement four different address spaces: • Program/Code Memory • Boot Memory • Data Memory • Special Function Registers (SFRs) The AT89C51SND1A and AT83C51SND1A implement 64 Kbytes of on-chip program/code memory. The AT83C51SND1A product provides the internal program/code memory in ROM technology while the AT89C51SND1A product provides it in Flash technology. The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the AT89C51SND1A can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programming tool. Boot Memory The AT89C51SND1A implements 4 Kbytes of on-chip boot memory provided in Flash technology. This boot memory is delivered programmed with a standard boot loader software allowing in system programming commonly known as ISP. It also contains some Application Programming Interfaces routines commonly known as API allowing user to develop his own boot loader. Data Memory The T89C51CC01 derivatives implement 2304 bytes of on-chip data RAM. This memory is divided in two separate areas: 14 • 256 bytes of on-chip RAM memory (standard C51 memory). • 2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX instructions). AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Special Function Registers The Special Function Registers (SFRs) of the T89C51CC01 derivatives fall into the categories detailed in Table 16 to Table 32. The relative addresses of these SFRs are provided together with their reset values in Table 33. In this table, the bit-addressable registers are identified by Note 1. Table 16. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer DPL 82h Data Pointer Low byte DPH 83h Data Pointer High byte 7 6 5 4 3 2 1 0 CY AC F0 RS1 RS0 OV F1 P 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - - GF1 GF0 PD IDL Table 17. System Management SFRs Mnemonic Add Name PCON 87h Power Control AUXR 8Eh Auxiliary Register 0 - EXT16 M0 DPHDIS XRS1 XRS0 EXTRAM AO AUXR1 A2h Auxiliary Register 1 - - ENBOOT - GF3 0 - DPS NVERS FBh Version Number NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0 7 6 5 4 3 2 1 0 - - - - - - - X2 R1 R0 - - PLLRES - PLLEN PLOCK Table 18. PLL and System Clock SFRs Mnemonic Add Name CKCON 8Fh Clock Control PLLCON E9h PLL Control PLLNDIV EEh PLL N Divider - N6 N5 N4 N3 N2 N1 N0 PLLRDIV EFh PLL R Divider R9 R8 R7 R6 R5 R4 R3 R2 15 4106E–8051–03/02 Table 19. Interrupt SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 IEN0 A8h Interrupt Enable Control 0 EA EAUD EMP3 ES ET1 EX1 ET0 EX0 IEN1 B1h Interrupt Enable Control 1 - EUSB - EKB EADC ESPI EI2C EMMC IPH0 B7h Interrupt Priority Control High 0 - IPHAUD IPHMP3 IPHS IPHT1 IPHX1 IPHT0 IPHX0 IPL0 B8h Interrupt Priority Control Low 0 - IPLAUD IPLMP3 IPLS IPLT1 IPLX1 IPLT0 IPLX0 IPH1 B3h Interrupt Priority Control High 1 - IPHUSB - IPHKB IPHADC IPHSPI IPHI2C IPHMMC IPL1 B2h Interrupt Priority Control Low 1 - IPLUSB - IPLKB IPLADC IPLSPI IPLI2C IPLMMC 7 6 5 4 3 2 1 0 - - - - Table 20. Port SFRs Mnemonic Add Name P0 80h 8-bit Port 0 P1 90h 8-bit Port 1 P2 A0h 8-bit Port 2 P3 B0h 8-bit Port 3 P4 C0h 8-bit Port 4 P5 D8h 4-bit Port 5 Table 21. Flash Memory SFR Mnemonic Add Name 7 6 5 4 3 2 1 0 FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY 7 6 5 4 3 2 1 0 Table 22. Timer SFRs Mnemonic Add Name TCON 88h Timer/Counter 0 and 1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00 TL0 8Ah Timer/Counter 0 Low Byte TH0 8Ch Timer/Counter 0 High Byte TL1 8Bh Timer/Counter 1 Low Byte 16 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Table 22. Timer SFRs (Continued) Mnemonic Add Name TH1 8Dh Timer/Counter 1 High Byte WDTRST A6h WatchDog Timer Reset WDTPRG A7h WatchDog Timer Program 7 6 5 4 3 2 1 0 - - - - - WTO2 WTO1 WTO0 Table 23. MP3 Decoder SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 MP3CON AAh MP3 Control MPEN MPBBST CRCEN MSKANC MSKREQ MSKLAY MSKSYN MSKCRC MP3STA C8h MP3 Status MPANC MPREQ ERRLAY ERRSYN ERRCRC MPFS1 MPFS0 MPVER MP3STA1 AFh MP3 Status 1 - - - MPFREQ MPBREQ - - - MP3DAT ACh MP3 Data MPD7 MPD6 MPD5 MPD4 MPD3 MPD2 MPD1 MPD0 MP3ANC ADh MP3 Ancillary Data AND7 AND6 AND5 AND4 AND3 AND2 AND1 AND0 MP3VOL 9Eh MP3 Audio Volume Control Left - - - VOL4 VOL3 VOL2 VOL1 VOL0 MP3VOR 9Fh MP3 Audio Volume Control Right - - - VOR4 VOR3 VOR2 VOR1 VOR0 MP3BAS B4h MP3 Audio Bass Control - - - BAS4 BAS3 BAS2 BAS1 BAS0 MP3MED B5h MP3 Audio Medium Control - - - MED4 MED3 MED2 MED1 MED0 MP3TRE B6h MP3 Audio Treble Control - - - TRE4 TRE3 TRE2 TRE1 TRE0 MP3CLK EBh MP3 Clock Divider - - - MPCD4 MPCD3 MPCD2 MPCD1 MPCD0 7 6 5 4 3 2 1 0 Table 24. Audio Interface SFRs Mnemonic Add Name AUDCON0 9Ah Audio Control 0 JUST4 JUST3 JUST2 JUST1 JUST0 POL DSIZ HLR AUDCON1 9Bh Audio Control 1 SRC DRQEN MSREQ MUDRN - DUP1 DUP0 AUDEN AUDSTA 9Ch Audio Status SREQ UDRN AUBUSY - - - - - AUDDAT 9Dh Audio Data AUD7 AUD6 AUD5 AUD4 AUD3 AUD2 AUD1 AUD0 AUDCLK ECh Audio Clock Divider - - - AUCD4 AUCD3 AUCD2 AUCD1 AUCD0 7 6 5 4 3 2 1 0 USBE SUSPCLK SDRMWUP - UPRSM RMWUPE CONFG FADDEN Table 25. USB Controller SFRs Mnemonic Add Name USBCON BCh USB Global Control 17 4106E–8051–03/02 Table 25. USB Controller SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 USBADDR C6h USB Address FEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 USBINT BDh USB Global Interrupt - - WUPCPU EORINT SOFINT - - SPINT USBIEN BEh USB Global Interrupt Enable - - EWUPCPU EEORINT ESOFINT - - ESPINT UEPNUM C7h USB Endpoint Number - - - - - - EPNUM1 EPNUM0 UEPCONX D4h USB Endpoint X Control EPEN - - - DTGL EPDIR EPTYPE1 EPTYPE0 UEPSTAX CEh USB Endpoint X Status DIR - STALLRQ TXRDY STLCRC RXSETUP RXOUT TXCMP UEPRST D5h USB Endpoint Reset - - - - EP3RST EP2RST EP1RST EP0RST UEPINT F8h USB Endpoint Interrupt - - - - EP3INT EP2INT EP1INT EP0INT UEPIEN C2h USB Endpoint Interrupt Enable - - - - EP3INTE EP2INTE EP1INTE EP0INTE UEPDATX CFh USB Endpoint X Fifo Data FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0 UBYCTX E2h USB Endpoint X Byte Counter - BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0 UFNUML BAh USB Frame Number Low FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUM0 UFNUMH BBh USB Frame Number High - - CRCOK CRCERR - FNUM10 FNUM9 FNUM8 USBCLK EAh USB Clock Divider - - - - - - USBCD1 USBCD0 7 6 5 4 3 2 1 0 Table 26. MMC Controller SFRs Mnemonic Add MMCON0 E4h MMC Control 0 DRPTR DTPTR CRPTR CTPTR MBLOCK DFMT RFMT CRCDIS MMCON1 E5h MMC Control 1 BLEN3 BLEN2 BLEN1 BLEN0 DATDIR DATEN RESPEN CMDEN MMCON2 E6h MMC Control 2 MMCEN DCR CCR - - DATD1 DATD0 FLOWC MMSTA DEh - - CBUSY CRC16S DATFS CRC7S RESPFS CFLCK MMINT E7h MMC Interrupt MCBI EORI EOCI EOFI F2FI F1FI F2EI F1EI MMMSK DFh MMC Interrupt Mask MCBM EORM EOCM EOFM F2FM F1FM F2EM F1EM MMCMD DDh MMC Command MC7 MC6 MC5 MC4 MC3 MC2 MC1 MC0 MMDAT DCh MMC Data MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MMCLK EDh MMC Clock Divider MMCD7 MMCD6 MMCD5 MMCD4 MMCD3 MMCD2 MMCD1 MMCD0 18 Name MMC Control and Status AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Table 27. IDE Interface SFR Mnemonic DAT16H Add F9h Name High Order Data Byte 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 Table 28. Serial I/O Port SFRs Mnemonic Add Name SCON 98h Serial Control SBUF 99h Serial Data Buffer SADEN B9h Slave Address Mask SADDR A9h Slave Address BDRCON 92h Baud Rate Control BRL 91h Baud Rate Reload 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI BRR TBCK RBCK SPD SRC Table 29. SPI Controller SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 SPSTA C4h SPI Status SPIF WCOL - MODF - - - - SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 7 6 5 4 3 2 1 0 Table 30. 2-wire Controller SFRs Mnemonic Add Name SSCON 93h Synchronous Serial Control SSCR2 SSPE SSSTA SSSTO SSI SSAA SSCR1 SSCR0 SSSTA 94h Synchronous Serial Status SSC4 SSC3 SSC2 SSC1 SSC0 0 0 0 SSDAT 95h Synchronous Serial Data SSD7 SSD6 SSD5 SSD4 SSD3 SSD2 SSD1 SSD0 SSADR 96h Synchronous Serial Address SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSGC 7 6 5 4 3 2 1 0 Table 31. Keyboard Interface SFRs Mnemonic Add Name KBCON A3h Keyboard Control KINL3 KINL2 KINL1 KINL0 KINM3 KINM2 KINM1 KINM0 KBSTA A4h Keyboard Status KPDE - - - KINF3 KINF2 KINF1 KINF0 19 4106E–8051–03/02 Table 32. A/D Controller SFRs Mnemonic Add Name 7 6 5 4 3 2 1 0 ADCON F3h ADC Control - ADIDL ADEN ADEOC ADSST - - ADCS ADCLK F2h ADC Clock Divider - - - ADCD4 ADCD3 ADCD2 ADCD1 ADCD0 ADDL F4h ADC Data Low Byte - - - - - - ADAT1 ADAT0 ADDH F5h ADC Data High Byte ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 20 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Table 33. SFR Addresses and Reset Values 0/8 1/9 F8h UEPINT 0000 0000 DAT16H XXXX XXXX F0h B1 0000 0000 PLLCON 0000 1000 E8h E0h ACC 1 0000 0000 D8h P51 XXXX 1111 D0h PSW1 0000 0000 C8h MP3STA1 0000 0001 C0h P41 1111 1111 B8h IPL01 X000 0000 B0h 2/A 3/B 4/C 5/D 6/E 7/F NVERS2 1000 0010 FFh ADCLK 0000 0000 ADCON 0000 0000 ADDL 0000 0000 ADDH 0000 0000 USBCLK 0000 0000 MP3CLK 0000 0000 AUDCLK 0000 0000 MMCLK 0000 0000 PLLNDIV 0000 0000 PLLRDIV 0000 0000 EFh MMCON0 0000 0000 MMCON1 0000 0000 MMCON2 0000 0000 MMINT 0000 0011 E7h MMDAT 1111 1111 MMCMD 1111 1111 MMSTA 0000 0000 MMMSK 1111 1111 DFh UEPCONX 0000 0000 UEPRST 0000 0000 UBYCTLX 0000 0000 FCON 3 1111 00004 F7h D7h UEPSTAX 0000 0000 UEPDATX 0000 0000 CFh UEPNUM 0000 0000 C7h UEPIEN 0000 0000 SPCON 0001 0100 SPSTA 0000 0000 SPDAT XXXX XXXX USBADDR 1000 0000 SADEN 0000 0000 UFNUML 0000 0000 UFNUMH 0000 0000 USBCON 0000 0000 USBINT 0000 0000 USBIEN 0001 0000 P31 1111 1111 IEN1 0000 0000 IPL1 0000 0000 IPH1 0000 0000 MP3BAS 0000 0000 MP3MED 0000 0000 MP3TRE 0000 0000 A8h IEN01 0000 0000 SADDR 0000 0000 MP3CON 0011 1111 MP3DAT 0000 0000 MP3ANC 0000 0000 A0h P21 1111 1111 98h SCON 0000 0000 90h IPH0 X000 0000 B7h MP3STA1 0100 0001 AFh WDTRST 0000 1000 WDTPRG 0000 1000 A7h MP3VOR 0000 0000 9Fh AUXR1 XXXX 00X0 KBCON 0000 1111 KBSTA 0000 0000 SBUF XXXX XXXX AUDCON0 0000 1000 AUDCON1 1011 0010 AUDSTA 1100 0000 AUDDAT 1111 1111 MP3VOL 0000 0000 P11 1111 1111 BRL 0000 0000 BDRCON XXX0 0000 SSCON 0000 0000 SSSTA 1111 1000 SSDAT 1111 1111 SSADR 1111 1110 88h TCON 1 0000 0000 TMOD 0000 0000 TL0 0000 0000 TL1 0000 0000 TH0 0000 0000 TH1 0000 0000 AUXR X000 1101 80h P01 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 0/8 1/9 2/A 3/B 4/C 5/D BFh 6/E 97h CKCON 0000 000X5 8Fh PCON XXXX 0000 87h 7/F Reserved Notes: 1. 2. 3. 4. 5. SFR registers with least significant nibble address equal to 0 or 8 are bit-addressable. NVERS reset value depends on the silicon version. FCON register is only available in AT89C51SND1A product. FCON reset value is 00h in case of reset with hardware condition. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte. 21 4106E–8051–03/02 In-System and In-application Programming As described in the section “Program/Code Memory” of the AT8xC51SND1A design guide, The AT89C51SND1A implements a 4 Kbytes Flash boot memory. This boot memory is delivered programmed with a standard boot loader software allowing In-System Programming (ISP). It also contains some Application Programming Interface routines named API routines allowing In Application Programming (IAP) by using user’s own boot loader. In-System Programming The ISP boot process is divided in two different processes: the hardware and software boot process detailed in the following sections. Hardware Boot Process As detailed in Figure 8 there are two hardware conditions that allow the user to execute the boot loader: the hardware and the programmed conditions. Hardware Condition The hardware condition is based on the ISP# pin. When driving this pin to low level, the chip reset forces the execution of the boot loader software. The hardware condition takes precedence on the programmed condition and always allows in-system recovery when the user’s memory has been corrupted. Programmed Condition The programmed condition is based on the Boot Loader Jump Bit (BLJB) in the hardware security bytes (HSB). When this bit is programmed (by hardware or software programming mode), the chip reset forces the execution of the boot loader software. Software Boot Process Whatever the physical medium may be, the boot loader software always starts execution by testing FCON to know if execution comes from hardware or programmed condition. If it is from hardware condition, Atmel’s boot loader is executed. If it is from programmed condition, the Software Boot Vector (SBV) is used to build a 16-bit address, SBV content being the MSB and the LSB at 00h. If this address is valid (< F000h), a jump occurs at this address to execute the user’s boot loader. Otherwise, jump is performed to Atmel’s boot loader. This implies that the user’s boot loader does not execute any code mapped from F000h to FFFFh. 22 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Figure 8. Boot Process Algorithm RESET Hardware Process Hard Cond? ISP#= L? Prog Cond? BLJB= P? Standard Init ENBOOT= 0 PC= 0000h FCON= F0h Hard Cond Init ENBOOT= 1 PC= F000h FCON= 00h Prog Cond Init ENBOOT= 1 PC= F000h FCON= F0h Software Process Hard Cond? FCON= 00h? User Vector? SBV< F0h? User Init PCH= SBV PCL= 00h User’s Application User’s Boot Loader Atmel’s Boot Loader 23 4106E–8051–03/02 Serial Boot Loader Configuration The serial boot loader is based on the internal UART and needs only 3 pins: the TXD and RXD pins of the UART and the VSS pin. The data transmission format on the serial link must be set to 8 data bits with 1 stop bit. The baud rate is automatically recognized during the synchronization phase. Synchronization Phase Before any data may be sent to the boot loader, a synchronization must be achieved with the host so that both sides converse at the same baud rate. This is done by sending the “U” character (ASCII 35h) to the boot loader. The boot loader acknowledges the synchronization by responding the same “U” character. At this time, the boot loader is able to receive data, then all data received are echoed to the host. Command Protocol Definition The protocol is based on the INTEL‚ HEX type records. These records are composed of seven fields of ASCII characters as detailed in Table 34. All fields except SOR (Start Of Record) end EOR (End Of Record) are ASCII coded hexadecimal values. The SOR field is always a “:” character. The EOR field is always a Carriage Return (ASCII 13h) followed by a Line Feed (ASCII 0Ah). The SIZE field is the size of the DATA field. The ADDRESS field is the address where to store data contained in the DATA field. The TYPE field is the record type detailed in Table 35. The DATA field contains the data and must never exceed 128 data bytes (256 ASCII characters). The CKSUM field is the checksum computed on the SIZE, ADDRESS, TYPE, DATA fields. Table 34. Hex Record Format Error Handling SOR SIZE ADDRESS TYPE DATA CKSUM EOR : NN AAAA RR DD…DD CC CR LF All received records that present a checksum error, a data length greater than 128 bytes or a bad type record are immediately acknowledged to the host by sending an “X” character followed by a CRLF sequence. Command Description Table 35. Hex Record Commands TYPE 00h 01h 24 SIZE 01h to 80h 00h ADDRESS 0000h to FFFFh 0000h Description Program Data Program the data in the DATA field at the address contained in the ADDRESS field. Return “.”Done. “P”Not done. Part protected (secured by level 1 or 2). End of File No operation. Return “.” AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Table 35. Hex Record Commands (Continued) TYPE SIZE 02h ADDRESS XXXX Description Block Erase: DATA[0] = 01h DATA[1] = 00h Erase block 0 from address 0000h to 1FFFh. DATA[1] = 20h Erase block 1 from address 2000h to 3FFFh. DATA[1] = 40h Erase block 2 from address 4000h to 7FFFh. DATA[1] = 80h Erase block 3 from address 8000h to BFFFh. DATA[1] = C0h Erase block 4 from address C000h to FFFFh. Return “.”Done. “P”Not done. Part protected (secured by level 1 or 2). Reset Software Boot Vector and Boot Status Byte: DATA[0] = 04h Set SBV to F0h and BSB to FFh. 01h 02h XXXX XXXX Return “.”Done. “P”Not done. Part protected (secured by level 1 or 2). Program Software Security Bits: DATA[0] = 05h DATA[1] = 00h Program level 1. Disable Flash programming. DATA[1] = 01h Program level 2. Disable Flash programming and verifying. Return “.”Done. “P”Not done. Part protected (secured by level 1 or 2). 03h 03h XXXX Program Software Boot Vector or Boot Status Byte: DATA[0] = 06h DATA[1] = 00h Program BSB with DATA[2]. DATA[1] = 01h Program SBV with DATA[2]. Return “.”Done. “P”Not done. Part already protected (secured by level 2). 01h XXXX Full Chip Erase: DATA[0] = 07h Erase user memory from address 0000h to FFFFh. Set SBV to F0h and BSB to FFh. Program software security to level 0. Return “.” 03h XXXX Program Fuse bits: DATA[0] = 0Ah DATA[1] = 04h DATA[2] = 00h Program BLJB bit. DATA[2] = 01h Erase BLJB bit. DATA[1] = 08h DATA[2] = 00h Program X2 bit. DATA[2] = 01h Erase X2 bit. Return “.”Done. “P”Not done. Part protected (secured by level 1 or 2). 25 4106E–8051–03/02 Table 35. Hex Record Commands (Continued) TYPE SIZE 05h ADDRESS XXXX Description Read Data: DATA[4] = 00h Read data from address given by DATA[1:0] (start address) to address given by DATA[3:2] (end address). Return “AAAA=DD…DD” up to 16 data bytes by line. 04h 05h 02h XXXX XXXX Blank Check: DATA[4] = 01h Check blanked data from address given by DATA[1:0] (start address) to address given by DATA[3:2] (end address). Return “.”Done. “XXXX”First address not blanked. Read Id: DATA[0] = 00h DATA[1] = 00h Return manufacturer id. DATA[1] = 01h Return device id 1. DATA[1] = 02h Return device id 2. DATA[1] = 03h Return device id 3. Return “XX”Selected id value. 02h XXXX 05h Read Special Bytes: DATA[0] = 07h DATA[1] = 00h Return SSB. DATA[1] = 01h Return BSB. DATA[1] = 02h Return SBV. Return “XX”Selected byte value. 01h 02h XXXX XXXX Read HSB: DATA[0] = 0Bh Return HSB. Return “XX”HSB value. Read Boot Id: DATA[0] = 0Eh DATA[1] = 00h Return boot id 1. DATA[1] = 01h Return boot id 1. Return “XX”Selected id value. 01h 26 XXXX Read Boot Loader Version: DATA[0] = 0Fh Return boot loader version. Return “XX”Boot loader version. AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A In-application Programming The IAP is based on several Application Program Interface routines (APIs) that may be called by the user’s boot loader to allow programming of the Flash memory. The APIs are executed by calling the API_CALL function at address FFF0h and by passing the API routine number in R1 register. Some other parameters may also be passed in registers as detailed in Table 36. Table 36. API Routines and Parameters R1 Description PROGRAM DATA BYTE Program data in the Flash memory at a given address. 02h Parameters DPTRAddress of the byte to program. ACCData to program. Return None. PROGRAM DATA PAGE Program a page of data in the Flash memory at a given page address. 09h Parameters DPTR0Address of the page to program. DPTR1Address in ERAM of the first data to program. ACCNumber of bytes to program limited to 128. Return None. PROGRAM SOFTWARE SECURITY BYTE Program SSB. 05h Parameters DPL00hProgram level 1. Disable Flash programming. 01hProgram level 2. Disable Flash programming and verifying. Return None. PROGRAM BOOT STATUS BYTE Program BSB. 06h Parameters DPL00hSelect BSB programming. ACCData to program in BSB. Return None. PROGRAM SOFTWARE BOOT VECTOR Program SBV. 06h Parameters DPL01hSelect SBV programming. ACCData to program in SBV. Return None. PROGRAM BOOT LOADER JUMP BIT Program BLJB. 06h Parameters DPL04hSelect BLJB programming. ACC00hProgram BLJB. 01hErase BLJB. Return None. 27 4106E–8051–03/02 Table 36. API Routines and Parameters (Continued) R1 Description PROGRAM X2 BIT Program X2B. 06h Parameters DPL08hSelect X2B programming. ACC00hProgram X2B. 01hErase X2B. Return None. Erase BLOCK Erase one of the 5 available blocks. 01h Parameters DPH00hErase block 0 from address 0000h to 1FFFh. 20hErase block 1 from address 2000h to 3FFFh. 40hErase block 2 from address 4000h to 7FFFh. 80hErase block 3 from address 8000h to BFFFh. C0hErase block 4 from address C000h to FFFFh. Return None. ERASE SOFTWARE BOOT VECTOR and BOOT STATUS BYTE Erase SBV and BSB. 04h Parameters None. Return None. READ DATA BYTE Read data at a given address. 03h Parameters DPTRAddress of the byte to program. Return ACCData read. READ MANUFACTURER ID Read manufacturer Id. 00h Parameters DPL00hSelect manufacturer Id. Return ACCId value. READ DEVICE ID 1 Read device Id 1 00h Parameters DPL01hSelect device Id 1. Return ACCId value. READ DEVICE ID 2 Read device Id 2. 00h Parameters DPL02hSelect device Id 2. Return ACCId value. 28 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Table 36. API Routines and Parameters (Continued) R1 Description READ DEVICE ID 3 Read device Id 3. 00h Parameters DPL03hSelect device Id 3. Return ACCId value. READ SOFTWARE SECURITY BYTE Read SSB. 07h Parameters DPL00hSelect SSB. Return ACCSSB value. READ BOOT STATUS BYTE Read BSB. 07h Parameters DPL01hSelect BSB. Return ACCBSB value. READ SOFTWARE BOOT VECTOR Read SBV. 07h Parameters DPL02hSelect SBV. Return ACCSBV value. READ HARDWARE SECURITY BYTE Read HSB. 0Bh Parameters None. Return ACCHSB value. READ BOOT ID 1 Read boot Id 1. 0Eh Parameters DPL00hSelect boot Id 1. Return ACCId value. READ BOOT ID 2 Read boot Id 2. 0Eh Parameters DPL01hSelect boot Id 2. Return ACCId value. READ BOOT LOADER VERSION Read BLV. 0Fh Parameters None. Return ACCBLV value. 29 4106E–8051–03/02 Peripherals The AT8xC51SND1A peripherals are briefly described in the following sections. For further details on how to interface (hardware and software) to these peripherals, please refer to the AT8xC51SND1A design guide. Clock Generator System The AT8xC51SND1A internal clocks are extracted from an on-chip PLL fed by an onchip oscillator. Four clocks are generated respectively for the C51 core, the MP3 decoder, the audio interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscillator clock. The MP3 decoder clock is generated by dividing the PLL output clock. The audio interface sample rates are also obtained by dividing the PLL output clock. Ports The AT8xC51SND1A implements five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition to performing general-purpose I/O, some ports are capable of external data memory operations; others allow for alternate functions. All I/O Ports are bidirectional. Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose I/O and alternate functions. Timers/Counters The AT8xC51SND1A implements the two general-purpose, 16-bit Timers/Counters of a standard C51. They are identified as Timer 0, Timer 1, and can independently be configured each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. Watchdog Timer The AT8xC51SND1A implements a hardware Watchdog Timer that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. MP3 Decoder The AT8xC51SND1A implements a MPEG I/II audio layer 3 decoder (known as MP3 decoder). In MPEG I (ISO 11172-3) three layers of compression have been standardized supporting three sampling frequencies: 48, 44.1, and 32 KHz. Among these layers, layer 3 allows highest compression rate of about 12:1 while still maintaining CD audio quality. For example, 3 minutes of CD audio (16-bit PCM, 44.1 KHz) data, which needs about 32 MBytes of storage, can be encoded into only 2.7 MBytes of MPEG I audio layer 3 data. In MPEG II (ISO 13818-3), three additional sampling frequencies: 24, 22.05, and 16 KHz are supported for low bit rates applications. The AT8xC51SND1A can decode in real-time the MPEG I audio layer 3 encoded data into a PCM audio data, and also supports MPEG II audio layer 3 additional frequencies. Additional features are supported by the AT8xC51SND1A MP3 decoder such as volume, bass, medium, and treble controls, bass boost effect and ancillary data extraction. Audio Output Interface The AT8xC51SND1A implements an audio output interface allowing the decoded audio bitstream to be output in various formats. It is compatible with right and left justification PCM and I2S formats and the on-chip PLL (see Section ) allows connection of almost all of the commercial audio DAC families available on the market. Universal Serial Bus Interface The AT8xC51SND1A implements a full-speed Universal Serial Bus Interface. It can be used for the following purposes: 30 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A • Download of MP3 encoded audio files by supporting the USB mass storage class. • In-System Programming by supporting the USB firmware upgrade class. MultiMediaCard Interface The AT8xC51SND1A implements a MultiMediaCard (MMC) interface compliant to the V2.2 specification in MultiMediaCard Mode. The MMC allows storage of MP3 encoded audio files in removable flash memory cards that can be easily plugged or removed from the application. It can also be used for In-System Programming. IDE/ATAPI interface The AT8xC51SND1A provides an IDE/ATAPI interface allowing connexion of devices such as CD-ROM reader, CompactFlash™ cards, Hard Disk Drive, etc. It consists in a 16-bit bidirectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass storage interface but could be used for In-System Programming using CDROM. Serial I/O Interface The AT8xC51SND1A implements a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex Universal Asynchronous Receiver Transmitter (UART) communication modes. It is provided for the following purposes: Serial Peripheral Interface Two-wire Controller A/D Controller Keyboard Interface • In-System Programming. • Remote control of the AT8xC51SND1A by a host. The AT8xC51SND1A implements a Serial Peripheral Interface (SPI) supporting master and slave modes. It is provided for the following purposes: • Interfacing DataFlash memory for MP3 encoded audio files storage. • Remote control of the AT8xC51SND1A by a host. • In-System Programming. The AT8xC51SND1A implements a two-wire controller supporting the four standard master and slave modes with multimaster capability. It is provided for the following purposes: • Connection of slave devices like LCD controller, audio DAC… • Remote control of the AT8xC51SND1A by a host. • In-System Programming. The AT8xC51SND1A implements a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). It is provided for the following purposes: • Battery monitoring. • Voice recording. • Corded remote control. The AT8xC51SND1A implements a keyboard interface allowing connection of 4 x n matrix keyboard. It is based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and power down modes. 31 4106E–8051–03/02 Electrical Characterstics Absolute Maximum Rating and Operating Conditions Storage Temperature ......................................... -65 to +150°C Voltage on any other Pin to VSS *NOTICE: ...................................... -0.3 to +4.0V IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Ambient Temperature Under Bias........................ -40 to +85°C VDD ........................................................................................... 2.7 to 3.3V DC Characteristics Digital Logic Table 37. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C Symbol Parameter 32 VIL Input Low Voltage VIH1 Input High Voltage (except RST) VIH2 Input High Voltage (RST) Min Typ(1) Max Units Test Conditions -0.5 0.2·V DD - 0.1 V 0.2·VDD + 0.9 VDD V 0.7·VDD VDD + 0.5 V VOL1 Output Low Voltage (except P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) 0.45 V IOL = 1.6 mA VOL2 Output Low Voltage (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) 0.45 V IOL = 3.2 mA VOH1 Output High Voltage (P1, P2, P3, P4 and P5) V DD - 0.7 V IOH = -30 µA VOH2 Output High Voltage (P0, P2 address mode, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT, D+, D-) V DD - 0.7 V IOH = -3.2 mA IIL Logical 0 Input Current (P1, P2, P3, P4 and P5) µA Vin = 0.45V -50 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Table 37. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C Symbol Parameter Min ILI Input Leakage Current (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) ITL Logical 1 to 0 Transition Current (P1, P2, P3, P4 and P5) RRST Pull-Down Resistor C IO 50 Pin Capacitance VRET Typ(1) Max 90 Units Test Conditions 10 µA 0.45 < VIN < VDD -650 µA Vin = 2.0V 200 kΩ 10 pF VDD Data Retention Limit 1.8 V TA = 25°C IDD Operating Current TBD TBD mA 12 MHz, VDD < 3.3V 16 MHz, VDD < 3.3V 20 MHz, VDD < 3.3V IDL Idle Mode Current TBD TBD mA 12 MHz, VDD < 3.3V 16 MHz, VDD < 3.3V 20 MHz, VDD < 3.3V IPD Power-Down Current TBD TBD µA VRET < VDD < 3.3V Note: 1. Typical values are obtained using VDD = 3V and TA = 25°C. They are not tested and there is no guarantee on these values. Figure 9. IDD/IDL Versus XTAL Frequency; VDD = 2.7 to 3.3V IDD/IDL (mA) TBD TBD TBD 0 2 4 max Active mode (mA) typ Active mode (mA) max Idle mode (mA) typ Idle mode (mA) 6 8 10 12 14 16 18 20 Frequency at XTAL (MHz) 33 4106E–8051–03/02 IDD, IDL and IPD Test Conditions Figure 10. IDD Test Condition, Active Mode VDD VDD IDD VDD RST VDD P0 (NC) Clock Signal X2 X1 TST# VSS VSS All other pins are unconnected Figure 11. IDL Test Condition, Idle Mode VDD RST IDL VDD VSS VDD P0 (NC) Clock Signal X2 X1 TST# VSS VSS All other pins are unconnected Figure 12. IPD Test Condition, Power-Down Mode VDD RST VDD VSS IPD VDD P0 (NC) X2 X1 VSS MCMD MDAT TST# VSS All other pins are unconnected 34 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A A to D Converter Table 38. A to D Converter DC Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C Symbol Parameter Min Typ Max Units 3.3 V Test Conditions AVDD Analog Supply Voltage AIDD Analog Operating Supply Current 600 µA AVDD = 3.3V AIN1:0 = 0 to AVDD AIPD Analog Standby Current 2 µA AVDD = 3.3V ADEN = 0 or PD = 1 AVIN Analog Input Voltage AVSS AVDD V Reference Voltage AREFN AREFP AVSS 2.4 AVDD V V 10 30 kΩ TA = 25°C 10 pF TA = 25°C AVREF RREF 2.7 AREF Input Resistance C IA Analog Input capacitance Oscillator and Crystal Schematic Figure 13. Crystal Connection X1 C1 Q C2 VSS Note: Parameters X2 For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits. Table 39. Oscillator and Crystal Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C Symbol Parameter Min Typ Max Unit C X1 Internal Capacitance (X1 - VSS) 10 pF C X2 Internal Capacitance (X2 - VSS) 10 pF CL Equivalent Load Capacitance (X1 - X2) 5 pF DL Drive Level 50 µW Crystal Frequency 20 MHz RS Crystal Series Resistance 40 Ω CS Crystal Shunt Capacitance 6 pF F 35 4106E–8051–03/02 Phase Lock Loop Schematic Figure 14. PLL Filter Connection PFILT R C2 C1 VSS Parameters VSS Table 40. PLL Filter Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C Symbol Parameter Min Typ Max Unit Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2.2 nF R In-System Programming Schematic Figure 15. ISP Pull-down Connection ISP# RISP VSS Parameters Table 41. ISP Pull-Down Characteristics VDD = 2.7 to 3.3V , TA = -40° to +85°C Symbol RISP 36 Parameter ISP Pull-Down Resistor Min Typ 2.2 Max Unit kΩ AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A AC Characteristics External 8-bit Bus Cycles Definition of Symbols Table 42. External 8-bit Bus Cycles Timing Symbol Definitions Signals Timings Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD# Z Floating W WR# Test conditions: capacitive load on all pins = 50 pF. Table 43. External 8-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL -15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLRL ALE Low to RD# Low 3·TCLCL-30 1.5·TCLCL-30 ns TRLRH RD# Pulse Width 6·TCLCL-25 3·TCLCL -25 ns TRHLH RD# high to ALE High TAVDV Address Valid to Valid Data In TAVRL Address Valid to RD# Low TRLDV RD# Low to Valid Data TRLAZ RD# Low to Address Float TRHDX Data Hold After RD# High TRHDZ Instruction Float After RD# High TCLCL-20 TCLCL+20 0.5·TCLCL-20 9·TCLCL-65 4·TCLCL-30 0.5·TCLCL+20 ns 4.5·TCLCL-65 ns 2·TCLCL -30 ns 5·TCLCL-30 2.5·TCLCL-30 ns 0 0 ns 0 0 2·TCLCL-25 ns TCLCL-25 ns 37 4106E–8051–03/02 Table 44. External 8-bit Bus Cycle – Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol Waveforms Parameter Min TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLWL ALE Low to WR# Low 3·TCLCL-30 1.5·TCLCL-30 ns TWLWH WR# Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TWHLH WR# High to ALE High TCLCL-20 TAVWL Address Valid to WR# Low 4·TCLCL-30 2·TCLCL-30 ns TQVWH Data Valid to WR# High 7·TCLCL-20 3.5·TCLCL-20 ns TWHQX Data Hold after WR# High TCLCL-15 0.5·TCLCL-15 ns TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns Figure 16. External 8-bit Bus Cycle – Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD# TRLDV TRHDZ TRLAZ TAVLL P0 TLLAX TRHDX A7:0 D7:0 TAVRL Data In TAVDV P2 38 A15:8 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Figure 17. External 8-bit Bus Cycle – Data Write Waveforms ALE TLHLL TLLWL TWLWH TWHLH WR# TAVWL TAVLL P0 TLLAX TQVWH A7:0 TWHQX D7:0 Data Out P2 A15:8 External IDE 16-bit Bus Cycles Definition of Symbols Table 45. External IDE 16-bit Bus Cycles Timing Symbol Definitions Signals Timings Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD# Z Floating W WR# Test conditions: capacitive load on all pins = 50 pF. 39 4106E–8051–03/02 Table 46. External IDE 16-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLRL ALE Low to RD# Low 3·TCLCL-30 1.5·TCLCL-30 ns TRLRH RD# Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TRHLH RD# high to ALE High TAVDV Address Valid to Valid Data In TAVRL Address Valid to RD# Low TRLDV RD# Low to Valid Data TRLAZ RD# Low to Address Float TRHDX Data Hold After RD# High TRHDZ Instruction Float After RD# High TCLCL-20 TCLCL+20 0.5·TCLCL-20 9·TCLCL-65 4·TCLCL-30 0.5·TCLCL+20 ns 4.5·TCLCL -65 ns 2·TCLCL-30 ns 5·TCLCL-30 2.5·TCLCL -30 ns 0 0 ns 0 0 2·TCLCL-25 ns TCLCL-25 ns Table 47. External IDE 16-bit Bus Cycle – Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol Parameter 40 TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL -20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL -20 ns TLLWL ALE Low to WR# Low 3·TCLCL-30 1.5·TCLCL -30 ns TWLWH WR# Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TWHLH WR# High to ALE High TAVWL Address Valid to WR# Low 4·TCLCL-30 2·TCLCL-30 ns TQVWH Data Valid to WR# High 7·TCLCL-20 3.5·TCLCL -20 ns TWHQX Data Hold after WR# High TCLCL-15 0.5·TCLCL -15 ns TCLCL-20 TCLCL+20 0.5·TCLCL -20 0.5·TCLCL +20 ns AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Waveforms Figure 18. External IDE 16-bit Bus Cycle – Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD# TRLDV TRHDZ TRLAZ TAVLL P0 TLLAX TRHDX A7:0 D7:0 TAVRL Data In TAVDV P2 A15:8 D15:81 Data In Note: D15:8 is written in DAT16H SFR. Figure 19. External IDE 16-bit Bus Cycle – Data Write Waveforms ALE TLHLL TLLWL TWLWH TWHLH WR# TAVWL TAVLL P0 TLLAX TQVWH A7:0 TWHQX D7:0 Data Out P2 A15:8 D15:81 Data Out Note: D15:8 is the content of DAT16H SFR. SPI Interface Definition of Symbols Table 48. SPI Interface Timing Symbol Definitions Signals Conditions C Clock H High I Data In L Low O Data Out V Valid X No Longer Valid Z Floating 41 4106E–8051–03/02 Timings Test conditions: capacitive load on all pins = 100 pF Table 49. SPI Interface Master AC Timing VDD = 2.7 to 3.3V, TA = -40° to +85°C Symbol Parameter Min Max Unit Slave mode TCHCH Clock Period TCHCX 8 TOSC Clock High Time 3.2 TOSC TCLCX Clock Low Time 3.2 TOSC TSLCH, TSLCL SS# Low to Clock edge 200 ns TIVCL, TIVCH Input Data Valid to Clock Edge 100 ns TCLIX, TCHIX Input Data Hold after Clock Edge 100 ns TCLOV, TCHOV Output Data Valid after Clock Edge TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns TCLSH, TCHSH SS# High after Clock Edge 0 ns TIVCL, TIVCH Input Data Valid to Clock Edge 100 ns TCLIX, TCHIX Input Data Hold after Clock Edge 100 ns TSLOV SS# Low to Output Data Valid 130 ns TSHOX Output Data Hold after SS# High 130 ns TSHSL SS# High to SS# Low TILIH Input Rise Time 2 µs TIHIL Input Fall Time 2 µs TOLOH Output Rise time 100 ns TOHOL Output Fall Time 100 ns 100 ns (1) Master mode TCHCH Clock Period TCHCX 4 TOSC Clock High Time 1.6 TOSC TCLCX Clock Low Time 1.6 TOSC TIVCL, TIVCH Input Data Valid to Clock Edge 50 ns TCLIX, TCHIX Input Data Hold after Clock Edge 50 ns TCLOV, TCHOV Output Data Valid after Clock Edge TCLOX, TCHOX Output Data Hold Time after Clock Edge TILIH Input Data Rise Time 2 µs TIHIL Input Data Fall Time 2 µs TOLOH Output Data Rise time 50 ns TOHOL Output Data Fall Time 50 ns Note: 42 65 0 ns ns 1. Value of this parameter depends on software. AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Waveforms Figure 20. SPI Slave Waveforms (SSCPHA = 0) SS# (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) TCHCH TCHCX TCLCH TCLSH TCHSH TSHSL TCLCX TCHCL SCK (SSCPOL = 1) (input) TCLOV TCHOV TSLOV MISO (output) SLAVE MSB OUT BIT 6 TCLOX TCHOX TSHOX SLAVE LSB OUT 1 TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN Not Defined but generally the MSB of the character which has just been received. Figure 21. SPI Slave Waveforms (SSCPHA = 1) SS#1 (output) TCHCH SCK (SSCPOL = 0) (output) TCHCX TCLCH TCLCX TCHCL SCK (SSCPOL = 1) (output) TIVCH TCHIX TIVCL TCLIX SI (input) MSB IN BIT 6 LSB IN TCLOX TCLOV TCHOV SO (output) Note: Port Data MSB OUT BIT 6 TCHOX LSB OUT Port Data Not Defined but generally the LSB of the character which has just been received. 43 4106E–8051–03/02 Figure 22. SPI Master Waveforms (SSCPHA = 0) SS#1 (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) TCHCH TCHCX TCLCH TCLSH TCHSH TSHSL TCLCX TCHCL SCK (SSCPOL = 1) (input) TCHOV TCLOV TSLOV MISO (output) 1 SLAVE MSB OUT BIT 6 TCHOX TCLOX TSHOX SLAVE LSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN SS# handled by software using general purpose port pin. Figure 23. SPI Master Waveforms (SSCPHA = 1) SS#1 (output) TCHCH SCK (SSCPOL = 0) (output) TCHCX TCLCH TCLCX TCHCL SCK (SSCPOL = 1) (output) TIVCH TCHIX TIVCL TCLIX SI (input) MSB IN TCLOV SO (output) Note: 44 TCHOV Port Data MSB OUT BIT 6 LSB IN TCLOX TCHOX BIT 6 LSB OUT Port Data SS# handled by software using general purpose port pin. AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Two-wire Interface Timings Table 50. Two-wire Interface AC Timing VDD = 2.7 to 3.3V, TA = -40° to +85°C INPUT Min Max OUTPUT Min Max Symbol Parameter THD; STA Start condition hold time 14·TCLCL(4) 4.0 µs(1) TLOW SCL low time 16·TCLCL(4) 4.7 µs(1) THIGH SCL high time 14·TCLCL(4) 4.0 µs(1) TRC SCL rise time 1 µs -(2) TFC SCL fall time 0.3 µs 0.3 µs(3) TSU; DAT1 Data set-up time 250 ns 20·TCLCL(4)- TRD TSU; DAT2 SDA set-up time (before repeated START condition) 250 ns 1 µs(1) TSU; DAT3 SDA set-up time (before STOP condition) 250 ns 8·TCLCL(4) THD; DAT Data hold time 0 ns 8·TCLCL(4) - TFC TSU; STA Repeated START set-up time 14·TCLCL(4) 4.7 µs(1) TSU; STO STOP condition set-up time 14·TCLCL(4) 4.0 µs(1) TBUF Bus free time 14·TCLCL(4) 4.7 µs(1) TRD SDA rise time 1 µs -(2) TFD SDA fall time 0.3 µs 0.3 µs(3) Notes: 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 µs. 3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL = 400 pF. 4. TCLCL = TOSC = one oscillator clock period. Waveforms Figure 24. Two-wire Waveforms Repeated START condition START or Repeated START condition START condition STOP condition Trd Tsu;STA 0.7 VDD 0.3 VDD SDA (INPUT/OUTPUT) Tsu;STO Tfd Trc Tfc Tbuf Tsu;DAT3 0.7 VDD 0.3 VDD SCL (INPUT/OUTPUT) Thd;STA Tlow Thigh Tsu;DAT1 Thd;DAT Tsu;DAT2 45 4106E–8051–03/02 MMC Interface Definition of Symbols Table 51. MMC Interface Timing Symbol Definitions Signals Timings Conditions C Clock H High D Data In L Low O Data Out V Valid X No Longer Valid Table 52. MMC Interface AC timings VDD = 2.7 to 3.3V, TA = 0 to 70°C, CL ≤ 100pF (10 cards) Symbol Waveforms Parameter Min Max Unit TCHCH Clock Period 50 ns TCHCX Clock High Time 10 ns TCLCX Clock Low Time 10 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TDVCH Input Data Valid to Clock High 3 ns TCHDX Input Data Hold after Clock High 3 ns TCHOX Output Data Hold after Clock High 5 ns TOVCH Output Data Valid to Clock High 5 ns Figure 25. MMC Input-Output Waveforms TCHCH TCHCX TCLCX MCLK TCHCL TCHIX TCLCH TIVCH MCMD Input MDAT Input TCHOX TOVCH MCMD Output MDAT Output 46 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Audio Interface Definition of Symbols Table 53. Audio Interface Timing Symbol Definitions Signals Timings Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid Table 54. Audio Interface AC timings VDD = 2.7 to 3.3V, TA = 0 to 70°C, CL ≤ 30pF Symbol Min Max Unit (1) TCHCH Clock Period TCHCX Clock High Time 30 ns TCLCX Clock Low Time 30 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TCLSV Clock Low to Select Valid 10 ns TCLOV Clock Low to Data Valid 10 ns Note: Waveforms Parameter 325.5 ns 32-bit format with Fs = 48 KHz. Figure 26. Audio Interface Waveforms TCHCH TCHCX TCLCX DCLK TCHCL TCLCH TCLSV DSEL Right Left TCLOV DDAT 47 4106E–8051–03/02 Analog to Digital Converter Definition of Symbols Table 55. Analog to Digital Converter Timing Symbol Definitions Signals Characteristics Conditions C Clock H High E Enable (ADEN bit) L Low S Start Conversion (ADSST bit) Table 56. Analog to Digital Converter AC Characteristics VDD = 2.7 to 3.3V, TA = 0 to 70°C Symbol Parameter Min TCLCL Clock Period 1.43 TEHSH Start-up Time TSHSL Max Unit µs 4 µs Conversion Time 11·TCLCL µs DLe Differential nonlinearity error1, 2 TBD LSB ILe Integral nonlinearity error1, 3 TBD LSB OSe Offset error1, 4 TBD LSB TBD % 1, 5 Ge Note: Gain error 1. AVDD = AVREFP = 3.0 V, AVSS = AVREFN = 0 V. ADC is monotonic with no missing code. 2. The differential non-linearity is the difference between the actual step width and the ideal step width (see Figure 28). 3. The integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 28). 4. The offset error is the absolute difference between the straight line which fits the actual transfer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see Figure 28). 5. The gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), and the straight line which fits the ideal transfer curve (see Figure 28). Waveforms Figure 27. Analog to Digital Converter Internal Waveforms CLK TCLCL ADEN Bit TEHSH ADSST Bit TSHSL 48 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Figure 28. Analog to Digital Converter Characteristics Offset Gain Error Error Ge OSe Code Out 1023 1022 1021 1020 1019 1018 Ideal Transfer curve 7 Example of an actual transfer curve 6 5 Center of a step 4 Integral non-linearity (ILe) 3 Differential non-linearity (DLe) 2 1 0 0 1 LSB (ideal) AVIN (LSBideal) 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 Offset Error OSe Flash Memory Definition of Symbols Table 57. Flash Memory Timing Symbol Definitions Signals Timings Conditions S ISP# L Low R RST V Valid B FBUSY flag X No Longer Valid Table 58. Flash Memory AC Timing VDD = 2.7 to 3.3V, TA = -40° to +85°C Symbol Parameter Min Typ TSVRL Input ISP# Valid to RST Edge 50 ns TRLSX Input ISP# Hold after RST Edge 50 ns TBHBL Flash Internal Busy (Programming) Time 10 Max Unit ms 49 4106E–8051–03/02 Waveforms Figure 29. Flash Memory – ISP Waveforms RST TSVRL TRLSX ISP#1 Note: ISP# must be driven through a pull-down resistor (see Section “In-System Programming”, page 36). Figure 30. Flash Memory – Internal Busy Waveforms FBUSY bit TBHBL External Clock Drive and Logic Level References Definition of Symbols Table 59. External Clock Timing Symbol Definitions Signals C Timings Conditions Clock H High L Low X No Longer Valid Table 60. External Clock AC Timings VDD = 2.7 to 3.3V, TA= 0 to 70°C Symbol Parameter Unit Clock Period 50 ns TCHCX High Time 10 ns TCLCX Low Time 10 ns TCLCH Rise Time 3 ns TCHCL Fall Time 3 ns Cyclic Ratio in X2 mode 40 60 % Figure 31. External Clock Waveform TCLCH V DD - 0.5 0.45 V VIH1 TCHCX TCLCX VIL TCHCL 50 Max TCLCL TCR Waveforms Min TCLCL AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Figure 32. AC Testing Input/Output Waveforms INPUTS V DD - 0.5 0.45 V Note: OUTPUTS 0.7 VDD VIH min 0.3 VDD VIL max 1. During AC testing, all inputs are driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 33. Float Waveforms VLOAD VLOAD + 0.1 V VLOAD - 0.1 V Note: Timing Reference Points VOH - 0.1 V VOL + 0.1 V For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading V OH/VOL level occurs with IOL/IOH = ±20 mA. 51 4106E–8051–03/02 Ordering Information Table 61. Ordering Information Part Number Memory Size Supply Voltage Temperature Range Max Frequency Package AT89C51SND1A-ROTIL 64K Flash 3V Industrial 40 MHz TQFP80 Tray AT83SND1Axxx(1)-ROTIL 64K ROM 3V Industrial 40 MHz TQFP80 Tray Note: (1) Packing Refers to ROM code. PLCC84 package only available for development board. 52 AT8xC51SND1A 4106E–8051–03/02 AT8xC51SND1A Package Information TQFP80 53 4106E–8051–03/02 Package Information PLCC84 54 AT8xC51SND1A 4106E–8051–03/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 436-4270 FAX 1(408) 436-4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards Atmel Rousset Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 RF/Automotive Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Atmel Colorado Springs 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 e-mail [email protected] Web Site http://www.atmel.com © Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Atmel®, DataFlash ™ are trademarks and/or registered trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4106E–8051–03/02 /0M