Features • Programmable Audio Output for Interfacing with Common Audio DAC • • • • • • • • • • • • • • • • • • • – PCM Format Compatible – I2S Format Compatible 8-bit MCU C51 Core-based (FMAX = 20 MHz) 2304 Bytes of Internal RAM 64K Bytes of Code Memory – AT89C5132: Flash (100K Write/Erase Cycles) 4K Bytes of Boot Flash Memory (AT89C5132) – ISP: Download from USB (standard) or UART (option) USB Rev 1.1 Device Controller – “Full Speed” Data Transmission Built-in PLL MultiMedia Card® Interface Compatibility Atmel DataFlash® SPI Interface Compatibility IDE/ATAPI Interface 2 Channels 10-bit ADC, 8 kHz (8 True Bits) – Battery Voltage Monitoring – Voice Recording Controlled by Software Up to 44 Bits of General-purpose I/Os – 4-bit Interrupt Keyboard Port for a 4 x n Matrix – SmartMedia® Software Interface Two Standard 16-bit Timers/Counters Hardware Watchdog Timer Standard Full Duplex UART with Baud Rate Generator Two Wire Master and Slave Modes Controller SPI Master and Slave Modes Controller Power Management – Power-on Reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode Operating Conditions – 3V, ±10%, 25 mA Typical Operating at 25°C – Temperature Range: -40°C to +85°C Packages – TQFP80, PLCC84 (Development Board Only) – Dice USB Microcontroller with 64K Bytes Flash Memory AT89C5132 1. Description The AT89C5132 is a mass storage device controlling data exchange between various Flash modules, HDD and CD-ROM. The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Programming through an embedded 4K Bytes of Boot Flash Memory. The AT89C5132 include 2304 Bytes of RAM memory. The AT89C5132 provides all the necessary features for man-machine interface including, timers, keyboard port, serial or parallel interface (USB, SPI, IDE), ADC input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards). 2. Typical Applications • • • Flash Recorder/Writer PDA, Camera, Mobile Phone PC Add-on 4173ES–USB–09/07 3. Block Diagram Figure 3-1. AT89C5132 Block Diagram INT0 INT1 1 1 VDD VSS UVDD UVSS AVDD AVSS AREF AIN1:0 Interrupt Handler Unit TXD RXD T0 1 1 1 T1 1 SS MISO MOSI SCK SCL SDA 2 2 2 2 1 1 Flash RAM 2304 Bytes 64K Bytes Flash Boot 4K Bytes C51 (X2 CORE) 10-bit A-to-D Converter UART and BRG Timers 0/1 Watchdog SPI/DataFlash Controller TWI Controller 8-BIT INTERNAL BUS I2S/PCM Audio Interface Clock and PLL Unit USB Controller MMC Interface Keyboard Interface I/O Ports IDE Interface 3 FILT Notes: 2 X1 X2 RST DOUT DCLK DSEL SCLK D+ D- MCLK MDAT MCMD KIN3:0 P0 - P5 1. Alternate function of Port 3 2. Alternate function of Port 4 3. Alternate function of Port 1 AT89C5132 4173ES–USB–09/07 AT89C5132 4. Pin Description AT89C5132 80-pin TQFP Package 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 Figure 4-1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TQFP80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PVDD FILT PVSS VSS X2 X1 TST UVDD UVSS 3 4173ES–USB–09/07 AT89C5132 84-pin PLCC (1) 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 NC P5.1 P5.0 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO P2.0/A8 P2.1/A9 P4.7 P4.6 Figure 4-2. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PLCC84 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 NC P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD D+ DVDD VSS P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD AVDD AVSS AREFP AREFN AIN0 AIN1 P5.2 P5.3 NC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 ALE ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P1.4 P1.5 P1.6/SCL P1.7/SDA VDD PAVDD FILT PAVSS VSS X2 NC X1 TST UVDD UVSS Note: 4.1 1. For development board only. Signals All the AT89C5132 signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description Signal Name 4 Type Alternate Function Description P0.7:0 I/O Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to VDD or VSS. P1.7:0 I/O Port 1 P1 is an 8-bit bidirectional I/O port with internal pull-ups. AD7:0 KIN3:0 SCL SDA AT89C5132 4173ES–USB–09/07 AT89C5132 Signal Name Type P2.7:0 I/O Description Port 2 P2 is an 8-bit bidirectional I/O port with internal pull-ups. Alternate Function A15:8 RXD TXD INT0 INT1 T0 T1 WR RD I/O Port 3 P3 is an 8-bit bidirectional I/O port with internal pull-ups. P4.7:0 I/O Port 4 P4 is an 8-bit bidirectional I/O port with internal pull-ups. MISO MOSI SCK SS P5.3:0 I/O Port 5 P5 is a 4-bit bidirectional I/O port with internal pull-ups. - P3.7:0 Table 2. Clock Signal Description Signal Name Type Description Alternate Function X1 I Input to the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing. X2 O Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected. - FILT I PLL Low Pass Filter input FILT receives the RC network of the PLL low pass filter. - - Table 3. Timer 0 and Timer 1 Signal Description Signal Name Type Description Alternate Function Timer 0 Gate Input INT0 serves as external run control for timer 0, when selected by GATE0 bit in TCON register. INT0 I External Interrupt 0 INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0 is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set by a low level on INT0. P3.2 Timer 1 Gate Input INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. INT1 I External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level on INT1. P3.3 5 4173ES–USB–09/07 Signal Name Type Alternate Function T0 I Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. P3.4 T1 I Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments the count. P3.5 Description Table 4. Audio Interface Signal Description Signal Name Type Alternate Function DCLK O DAC Data Bit Clock - DOUT O DAC Audio Data - DSEL O DAC Channel Select Signal DSEL is the sample rate clock output. - SCLK O DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL). - Description Table 5. USB Controller Signal Description Signal Name Type Alternate Function D+ I/O USB Positive Data Upstream Port This pin requires an external 1.5 KΩ pull-up to VDD for full speed operation. - D- I/O USB Negative Data Upstream Port - Description Table 6. MutiMediaCard Interface Signal Description 6 Signal Name Type Alternate Function MCLK O MMC Clock output Data or command clock transfer. - MCMD I/O MMC Command line Bidirectional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to VDD or VSS. - MDAT I/O MMC Data line Bidirectional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to VDD or VSS. - Description AT89C5132 4173ES–USB–09/07 AT89C5132 Table 7. UART Signal Description Signal Name Type RXD I/O Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3. P3.0 TXD O Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3. P3.1 Description Alternate Function Table 8. SPI Controller Signal Description Signal Name Type MISO I/O SPI Master Input Slave Output Data Line When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller. P4.0 MOSI I/O SPI Master Output Slave Input Data Line When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller. P4.1 SCK I/O SPI Clock Line When in master mode, SCK outputs clock to the slave peripheral. When in slave mode, SCK receives clock from the master controller. P4.2 SS I SPI Slave Select Line When in controlled slave mode, SS enables the slave mode. P4.3 Description Alternate Function Table 9. TWI Controller Signal Description Signal Name Type Description SCL I/O TWI Serial Clock When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller. SDA I/O TWI Serial Data SDA is the bidirectional Two Wire data line. Alternate Function P1.6 P1.7 Table 10. A/D Converter Signal Description Signal Name Type AIN1:0 I A/D Converter Analog Inputs - AREFP I Analog Positive Voltage Reference Input - AREFN I Analog Negative Voltage Reference Input This pin is internally connected to AVSS. - Description Alternate Function 7 4173ES–USB–09/07 Table 11. Keypad Interface Signal Description Signal Name Type KIN3:0 I Alternate Function Description Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. P1.3:0 Table 12. External Access Signal Description Signal Name Type Alternate Function A15:8 I/O Address Lines Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. P2.7:0 AD7:0 I/O Address/Data Lines Multiplexed lower address and data lines for the external memory or the IDE interface. P0.7:0 ALE O Address Latch Enable Output ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus. - ISP I/O ISP Enable Input This signal must be held to GND through a pull-down resistor at the falling reset to force execution of the internal bootloader. - RD O Read Signal Read signal asserted during external data memory read operation. P3.7 WR O Write Signal Write signal asserted during external data memory write operation. P3.6 Description Table 13. System Signal Description Signal Name 8 Type Alternate Function Description RST I Reset Input Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than VIL is applied, whether or not the oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and VDD. Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation. TST I Test Input Test mode entry signal. This pin must be set to VDD. - - AT89C5132 4173ES–USB–09/07 AT89C5132 Table 14. Power Signal Description Signal Name Type Description Alternate Function VDD PWR Digital Supply Voltage Connect these pins to +3V supply voltage. - VSS GND Circuit Ground Connect these pins to ground. - AVDD PWR Analog Supply Voltage Connect this pin to +3V supply voltage. - AVSS GND Analog Ground Connect this pin to ground. - PVDD PWR PLL Supply voltage Connect this pin to +3V supply voltage. - PVSS GND PLL Circuit Ground Connect this pin to ground. - UVDD PWR USB Supply Voltage Connect this pin to +3V supply voltage. - UVSS GND USB Ground Connect this pin to ground. - 9 4173ES–USB–09/07 4.2 Internal Pin Structure Table 15. Detailed Internal Pin Structure Circuit(1) Type Pins Input TST Input/Output RST Input/Output P1(2) P2(3) P3 P4 P53:0 RTST VDD VDD P RRST Watchdog Output VSS 2 osc periods Latch Output VDD VDD VDD P1 P2 P3 N VSS VDD P Input/Output P0 MCMD MDAT ISP N PSEN VSS ALE SCLK DCLK VDD P Output DOUT DSEL MCLK N VSS D+ Input/Output D+ D- D- Notes: 10 1. For information on resistors value, input/output levels, and drive capability, refer to the Section “DC Characteristics”, page 183. 2. When the Two Wire controller is enabled, P1, P2, and P3 transistors are disabled allowing pseudo open-drain structure. 3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8). AT89C5132 4173ES–USB–09/07 AT89C5132 5. Address Spaces The AT8xC5132 derivatives implement four different address spaces: 5.0.1 • Program/Code Memory • Boot Memory • Data Memory • Special Function Registers (SFRs) Code Memory The AT89C5132 implements 64K Bytes of on-chip program/code memory in Flash technology. The Flash memory increases ROM functionality by enabling in-circuit electrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard VDD voltage. Thus, the AT89C5132 can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programming tools. 5.0.2 Boot Memory The AT89C5132 implements 4K Bytes of on-chip boot memory provided in Flash technology. This boot memory is delivered programmed with a standard bootloader software allowing in system programming commonly known as ISP. It also contains some Application Programming Interfaces routines commonly known as API allowing user to develop his own bootloader. 5.0.3 Data Memory The AT89C5132 derivatives implement 2304 bytes of on-chip data RAM. This memory is divided in two separate areas: • 256 bytes of on-chip RAM memory (standard C51 memory). • 2048 bytes of on-chip expanded RAM memory (ERAM accessible via MOVX instructions). 11 4173ES–USB–09/07 Peripherals The AT8xC5132 peripherals are briefly described in the following sections. For further details on how to interface (hardware and software) to these peripherals, please refer to the AT8xC5132 complete datasheet. Clock Generator System The AT8xC5132 internal clocks are extracted from an on-chip PLL fed by an on-chip oscillator. Four clocks are generated respectively for the C51 core, the audio interface, and the other peripherals. The C51 and peripheral clocks are derived from the oscillator clock. The audio interface sample rates are also obtained by dividing the PLL output clock. Ports The AT8xC5132 implement five 8-bit ports (P0 to P4) and one 4-bit port (P5). In addition to performing general-purpose I/Os, some ports are capable of external data memory operations; others allow for alternate functions. All I/O Ports are bidirectional. Each Port contains a latch, an output driver and an input buffer. Port 0 and Port 2 output drivers and input buffers facilitate external memory operations. Some Port 1, Port 3 and Port 4 pins serve for both general-purpose I/Os and alternate functions. Timers/Counters The AT8xC5132 implement the two general-purpose, 16-bit Timers/Counters of a standard C51. They are identified as Timer 0, Timer 1, and can independently be configured each to operate in a variety of modes as a Timer or as an event Counter. When operating as a Timer, a Timer/Counter runs for a programmed length of time, then issues an interrupt request. When operating as a Counter, a Timer/Counter counts negative transitions on an external pin. After a preset number of counts, the Counter issues an interrupt request. Watchdog Timer The AT8xC5132 implement a hardware Watchdog Timer that automatically resets the chip if it is allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. Audio Output Interface The AT8xC5132 implements an audio output interface allowing the decoded audio bitstream to be output in various formats. They are compatible with right and left justification PCM and I2S formats and the on-chip PLL allows connection of almost all commercial audio DAC families available on the market. Universal Serial Bus Interface The AT8xC5132 implements a full-speed Universal Serial Bus Interface. The USB interface can be used for the following purposes: • Download of files by supporting the USB mass storage class. • In-System Programming by supporting the USB firmware upgrade class. MultiMedia Card Interface The AT8xC5132 implements a MultiMedia Card (MMC) interface compliant to the V2.2 specification in MultiMedia Card mode. The MMC allows storage of files in removable Flash memory cards that can be easily plugged or removed from the application. It can also be used for In-System Programming. IDE/ATAPI Interface The AT8xC5132 provide an IDE/ATAPI interface allowing connection of devices such as CD-ROM reader, CompactFlash™ cards, Hard Disk Drive, etc. It consists of a 16-bit bidirectional bus part of the low-level ANSI ATA/ATAPI specification. It is provided for mass storage interface but could be used for In-System Programming using CD-ROM. 12 AT89C5132 4173ES–USB–09/07 AT89C5132 Serial I/O Interface Serial Peripheral Interface Two-wire Controller The AT89C5132 implements a serial port with its own baud rate generator providing one single synchronous communication mode and three full-duplex Universal Asynchronous Receiver Transmitter (UART) communication modes. It is provided for the following purposes: • In System Programming. • Remote control of the AT89C5132 by a host. The AT89C5132 implements a Serial Peripheral Interface (SPI) supporting master and slave modes. It is provided for the following purposes: • Remote control of the AT89C5132 by a host. • In System Programming. The AT89C5132 implements a 2-wire controller supporting the four standard master and slave modes with multimaster capability. It is provided for the following purposes: • A/D Controller Connection of slave devices like LCD controller, audio DAC… • Remote control of the AT89C5132 by a host. • In System Programming. The AT89C5132 implements a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). It is provided for the following purposes: • Battery monitoring. • Voice recording. • Corded remote control. 13 4173ES–USB–09/07 6. Electrical Characteristics 6.1 Absolute Maximum Ratings Storage Temperature ..................................... -65°C to +150°C Voltage on any other Pin to VSS *NOTICE: ..................................... -0.3 to +4.0V IOL per I/O Pin ................................................................. 5 mA Power Dissipation ............................................................. 1 W Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “operating conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Ambient Temperature Under Bias.................... -40°C to +85°C VDD ....................................................................................... 2.7V 6.2 to 3.3V DC Characteristics 6.2.1 Digital Logic Table 1. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol Parameter Min VIL Input Low Voltage VIH1 Input High Voltage (except RST, X1) VIH2 Input High Voltage (RST, X1) VOL1 Max Units -0.5 0.2·VDD - 0.1 V 0.2·VDD + 1.1 VDD V 0.7·VDD(2) VDD + 0.5 V Output Low Voltage (except P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) 0.45 V IOL= 1.6 mA VOL2 Output Low Voltage (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) 0.45 V IOL= 3.2 mA VOH1 Output High Voltage (P1, P2, P3, P4 and P5) VDD - 0.7 V IOH= -30 μA VOH2 Output High Voltage (P0, P2 address mode, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT, D+, D-) VDD - 0.7 V IOH= -3.2 mA μA Vin = 0.45 V IIL 14 Typ(1) Logical 0 Input Current (P1, P2, P3, P4 and P5) -50 Test Conditions AT89C5132 4173ES–USB–09/07 AT89C5132 Table 1. Digital DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol Parameter ILI Input Leakage Current (P0, ALE, MCMD, MDAT, MCLK, SCLK, DCLK, DSEL, DOUT) ITL Logical 1 to 0 Transition Current (P1, P2, P3, P4 and P5) RRST CIO VRET IDD Typ(1) Min Pull-Down Resistor 50 90 Pin Capacitance Max Units 10 μA 0.45< VIN< VDD -650 μA Vin = 2.0 V 200 kΩ 10 VDD Data Retention Limit pF 1.8 Operating Current mA μA Idle Mode Current (3) IPD Power-Down Mode Current 20 500 Notes: 6.2.2 VDD < 3.3 V X1 / X2 mode 6.5 / 10.5 8 / 13.5 9.5 / 17 IDL TA= 25°C V (3) X1 / X2 mode 5.3 / 8.1 6.4 / 10.3 7.5 / 13 Test Conditions mA 12 MHz 16 MHz 20 MHz VDD < 3.3 V 12 MHz 16 MHz 20 MHz VRET < VDD < 3.3 V 1. Typical values are obtained using VDD= 3 V and TA= 25°C. They are not tested and there is no guarantee on these values. 2. Flash retention is guaranteed with the same formula for VDD min down to 0V. 3. See Table 154 for typical consumption in player mode. IDD, IDL and IPD Test Conditions Figure 6-1. IDD Test Condition, Active Mode VDD VDD RST (NC) Clock Signal VDD PVDD UVDD AVDD X2 X1 IDD VDD P0 VSS PVSS UVSS AVSS VSS TST All other pins are unconnected 15 4173ES–USB–09/07 Figure 6-2. IDL Test Condition, Idle Mode VDD VDD PVDD UVDD AVDD RST VSS (NC) Clock Signal X2 X1 IDL VDD P0 VSS PVSS UVSS AVSS VSS Figure 6-3. TST All other pins are unconnected IPD Test Condition, Power-Down Mode VDD VDD PVDD UVDD AVDD RST VSS (NC) X2 X1 6.2.3 MCMD MDAT TST All other pins are unconnected A-to-D Converter Table 2. A-to-D Converter DC Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol Parameter Min AVDD Analog Supply Voltage 2.7 AIDD Analog Operating Supply Current AIPD Analog Standby Current AVIN Analog Input Voltage AVREF Reference Voltage AREFN AREFP RREF AREF Input Resistance CIA 16 VDD P0 VSS PVSS UVSS AVSS VSS IPD Analog Input capacitance Typ Max Units Test Conditions 3.3 V 600 μA AVDD = 3.3V AIN1:0 = 0 to AVDD 2 μA AVDD = 3.3V ADEN = 0 or PD = 1 AVSS AVDD V AVSS 2.4 AVDD V V 10 30 kΩ TA = 25°C 10 pF TA = 25°C AT89C5132 4173ES–USB–09/07 AT89C5132 6.2.4 6.2.4.1 Oscillator and Crystal Schematic Figure 6-4. Crystal Connection X1 C1 Q C2 VSS Note: 6.2.4.2 X2 For operation with most standard crystals, no external components are needed on X1 and X2. It may be necessary to add external capacitors on X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits. Parameters Table 3. Oscillator and Crystal Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol 6.2.5.1 Min Typ Max Unit CX1 Internal Capacitance (X1 - VSS) 10 pF CX2 Internal Capacitance (X2 - VSS) 10 pF CL Equivalent Load Capacitance (X1 - X2) 5 pF DL Drive Level 50 μW Crystal Frequency 20 MHz RS Crystal Series Resistance 40 Ω CS Crystal Shunt Capacitance 6 pF F 6.2.5 Parameter Phase Lock Loop Schematic Figure 6-5. PLL Filter Connection FILT R C2 C1 VSS VSS 17 4173ES–USB–09/07 6.2.5.2 Parameters Table 4. PLL Filter Characteristics VDD = 2.7 to 3.3V , TA = -40 to +85°C Symbol 6.2.6 6.2.6.1 Parameter Min Typ Max Unit R Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2.2 nF USB Connection Schematic Figure 6-6. USB Connection VDD To Power Supply VBUS D+ RFS D+ RUSB D- D- RUSB GND VSS 6.2.6.2 Parameters Table 16. USB Characteristics VDD = 3 to 3.3 V, TA = -40 to +85°C Symbol 6.2.7 6.2.7.1 Parameter Min Typ Max Unit RUSB USB Termination Resistor 27 Ω RFS USB Full Speed Resistor 1.5 KΩ In-system Programming Schematic Figure 6-7. ISP Pull-down Connection ISP RISP VSS 6.2.7.2 Parameters Table 5. ISP Pull-Down Characteristics VDD = 3 to 3.3V , TA = -40 to +85°C Symbol RISP 18 Parameter ISP Pull-Down Resistor Min Typ 2.2 Max Unit kΩ AT89C5132 4173ES–USB–09/07 AT89C5132 6.3 6.3.1 6.3.1.1 AC Characteristics External 8-bit Bus Cycles Definition of Symbols Table 6. External 8-bit Bus Cycles Timing Symbol Definitions Signals 6.3.1.2 Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD Z Floating W WR Timings Test conditions: capacitive load on all pins = 50 pF. Table 7. External 8-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLRL ALE Low to RD Low 3·TCLCL-30 1.5·TCLCL-30 ns TRLRH RD Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TRHLH RD high to ALE High TAVDV Address Valid to Valid Data In TAVRL Address Valid to RD Low TRLDV RD Low to Valid Data TRLAZ RD Low to Address Float TRHDX Data Hold After RD High TRHDZ Instruction Float After RD High TCLCL-20 TCLCL+20 0.5·TCLCL-20 9·TCLCL-65 4·TCLCL-30 0.5·TCLCL+20 ns 4.5·TCLCL-65 ns 2·TCLCL-30 ns 5·TCLCL-30 2.5·TCLCL-30 ns 0 0 ns 0 0 2·TCLCL-25 ns TCLCL-25 ns 19 4173ES–USB–09/07 Table 8. External 8-bit Bus Cycle – Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol 6.3.1.3 Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLWL ALE Low to WR Low 3·TCLCL-30 1.5·TCLCL-30 ns TWLWH WR Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TWHLH WR High to ALE High TAVWL Address Valid to WR Low 4·TCLCL-30 2·TCLCL-30 ns TQVWH Data Valid to WR High 7·TCLCL-20 3.5·TCLCL-20 ns TWHQX Data Hold after WR High TCLCL-15 0.5·TCLCL-15 ns TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns Waveforms Figure 6-8. External 8-bit Bus Cycle – Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRHDZ TRLAZ TAVLL P0 TLLAX TRHDX A7:0 D7:0 TAVRL Data In TAVDV P2 20 A15:8 AT89C5132 4173ES–USB–09/07 AT89C5132 Figure 6-9. External 8-bit Bus Cycle – Data Write Waveforms ALE TLHLL TLLWL TWHLH TWLWH WR TAVWL TAVLL P0 TLLAX TQVWH A7:0 TWHQX D7:0 Data Out P2 6.3.2 6.3.2.1 A15:8 External IDE 16-bit Bus Cycles Definition of Symbols Table 9. External IDE 16-bit Bus Cycles Timing Symbol Definitions Signals 6.3.2.2 Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD Z Floating W WR Timings Test conditions: capacitive load on all pins = 50 pF. 21 4173ES–USB–09/07 Table 10. External IDE 16-bit Bus Cycle – Data Read AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLRL ALE Low to RD Low 3·TCLCL-30 1.5·TCLCL-30 ns TRLRH RD Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TRHLH RD high to ALE High TAVDV Address Valid to Valid Data In TAVRL Address Valid to RD Low TRLDV RD Low to Valid Data TRLAZ RD Low to Address Float TRHDX Data Hold After RD High TRHDZ Instruction Float After RD High TCLCL-20 TCLCL+20 0.5·TCLCL-20 9·TCLCL-65 4·TCLCL-30 0.5·TCLCL+20 ns 4.5·TCLCL-65 ns 2·TCLCL-30 ns 5·TCLCL-30 2.5·TCLCL-30 ns 0 0 ns 0 0 ns 2·TCLCL-25 TCLCL-25 ns Table 11. External IDE 16-bit Bus Cycle – Data Write AC Timings VDD = 2.7 to 3.3V, TA = -40° to +85°C Variable Clock Standard Mode Symbol 22 Parameter TCLCL Clock Period TLHLL ALE Pulse Width TAVLL Min Max Variable Clock X2 Mode Min Max Unit 50 50 ns 2·TCLCL-15 TCLCL-15 ns Address Valid to ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLAX Address hold after ALE Low TCLCL-20 0.5·TCLCL-20 ns TLLWL ALE Low to WR Low 3·TCLCL-30 1.5·TCLCL-30 ns TWLWH WR Pulse Width 6·TCLCL-25 3·TCLCL-25 ns TWHLH WR High to ALE High TAVWL Address Valid to WR Low 4·TCLCL-30 2·TCLCL-30 ns TQVWH Data Valid to WR High 7·TCLCL-20 3.5·TCLCL-20 ns TWHQX Data Hold after WR High TCLCL-15 0.5·TCLCL-15 ns TCLCL-20 TCLCL+20 0.5·TCLCL-20 0.5·TCLCL+20 ns AT89C5132 4173ES–USB–09/07 AT89C5132 6.3.2.3 Waveforms Figure 6-10. External IDE 16-bit Bus Cycle – Data Read Waveforms ALE TLHLL TLLRL TRLRH TRHLH RD TRLDV TRHDZ TRLAZ TAVLL P0 TLLAX TRHDX A7:0 D7:0 TAVRL Data In TAVDV P2 A15:8 D15:81 Data In Note: D15:8 is written in DAT16H SFR. Figure 6-11. External IDE 16-bit Bus Cycle – Data Write Waveforms ALE TLHLL TLLWL TWHLH TWLWH WR TAVWL TAVLL P0 TLLAX A7:0 TQVWH TWHQX D7:0 Data Out P2 A15:8 D15:81 Data Out Note: 6.3.3 6.3.3.1 D15:8 is the content of DAT16H SFR. SPI Interface Definition of Symbols Table 12. SPI Interface Timing Symbol Definitions Signals Conditions C Clock H High I Data In L Low O Data Out V Valid X No Longer Valid Z Floating 23 4173ES–USB–09/07 6.3.3.2 Timings Table 13. SPI Interface Master AC Timing VDD = 2.7 to 3.3V, TA = -40° to +85°C Symbol Parameter Min Max Unit Slave Mode TCHCH Clock Period TCHCX 8 TOSC Clock High Time 3.2 TOSC TCLCX Clock Low Time 3.2 TOSC TSLCH, TSLCL SS Low to Clock edge 200 ns TIVCL, TIVCH Input Data Valid to Clock Edge 100 ns TCLIX, TCHIX Input Data Hold after Clock Edge 100 ns TCLOV, TCHOV Output Data Valid after Clock Edge TCLOX, TCHOX Output Data Hold Time after Clock Edge 0 ns TCLSH, TCHSH SS High after Clock Edge 0 ns TIVCL, TIVCH Input Data Valid to Clock Edge 100 ns TCLIX, TCHIX Input Data Hold after Clock Edge 100 ns TSLOV SS Low to Output Data Valid 130 ns TSHOX Output Data Hold after SS High 130 ns TSHSL SS High to SS Low TILIH Input Rise Time 2 μs TIHIL Input Fall Time 2 μs TOLOH Output Rise Time 100 ns TOHOL Output Fall Time 100 ns 100 ns (1) Master Mode TCHCH Clock Period TCHCX 4 TOSC Clock High Time 1.6 TOSC TCLCX Clock Low Time 1.6 TOSC TIVCL, TIVCH Input Data Valid to Clock Edge 50 ns TCLIX, TCHIX Input Data Hold after Clock Edge 50 ns TCLOV, TCHOV Output Data Valid after Clock Edge TCLOX, TCHOX Output Data Hold Time after Clock Edge TILIH Input Data Rise Time 2 μs TIHIL Input Data Fall Time 2 μs TOLOH Output Data Rise Time 50 ns TOHOL Output Data Fall Time 50 ns Notes: 24 65 0 ns ns 1. Value of this parameter depends on software. 2. Test conditions: capacitive load on all pins = 100 pF AT89C5132 4173ES–USB–09/07 AT89C5132 6.3.3.3 Waveforms Figure 6-12. SPI Slave Waveforms (SSCPHA = 0) SS (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) TCHCH TCHCX TCLCH TCLSH TCHSH TSHSL TCLCX TCHCL SCK (SSCPOL = 1) (input) TCLOV TCHOV TSLOV MISO (output) SLAVE MSB OUT BIT 6 TCLOX TCHOX TSHOX SLAVE LSB OUT 1 TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. Not Defined but generally the MSB of the character which has just been received. Figure 6-13. SPI Slave Waveforms (SSCPHA = 1) SS1 (output) TCHCH SCK (SSCPOL = 0) (output) TCHCX TCLCH TCLCX TCHCL SCK (SSCPOL = 1) (output) TIVCH TCHIX TIVCL TCLIX SI (input) MSB IN BIT 6 LSB IN TCLOX TCLOV TCHOV SO (output) Note: Port Data MSB OUT BIT 6 TCHOX LSB OUT Port Data 1. Not Defined but generally the LSB of the character which has just been received. 25 4173ES–USB–09/07 Figure 6-14. SPI Master Waveforms (SSCPHA = 0) SS1 (input) TSLCH TSLCL SCK (SSCPOL = 0) (input) TCHCH TCHCX TCLCH TCLSH TCHSH TSHSL TCLCX TCHCL SCK (SSCPOL = 1) (input) TCHOV TCLOV TSLOV MISO (output) 1 SLAVE MSB OUT BIT 6 TCHOX TCLOX TSHOX SLAVE LSB OUT TIVCH TCHIX TIVCL TCLIX MOSI (input) Note: MSB IN BIT 6 LSB IN 1. SS handled by software using general purpose port pin. Figure 6-15. SPI Master Waveforms (SSCPHA = 1) SS1 (output) TCHCH SCK (SSCPOL = 0) (output) TCHCX TCLCH TCLCX TCHCL SCK (SSCPOL = 1) (output) TIVCH TCHIX TIVCL TCLIX SI (input) SO (output) Note: 6.3.4 6.3.4.1 MSB IN BIT 6 TCLOV TCLOX TCHOX TCHOV Port Data MSB OUT BIT 6 LSB IN LSB OUT Port Data 1. SS handled by software using general purpose port pin. Two-wire Interface Timings Table 17. TWI Interface AC Timing 26 AT89C5132 4173ES–USB–09/07 AT89C5132 VDD = 2.7 to 3.3 V, TA = -40 to +85°C INPUT Min Max OUTPUT Min Max Start condition hold time 14·TCLCL(4) 4.0 μs(1) TLOW SCL low time 16·TCLCL(4) 4.7 μs(1) THIGH SCL high time 14·TCLCL(4) 4.0 μs(1) TRC SCL rise time 1 μs -(2) TFC SCL fall time 0.3 μs 0.3 μs(3) TSU; DAT1 Data set-up time 250 ns 20·TCLCL(4)- TRD TSU; DAT2 SDA set-up time (before repeated START condition) 250 ns 1 μs(1) TSU; DAT3 SDA set-up time (before STOP condition) 250 ns 8·TCLCL(4) THD; DAT Data hold time 0 ns 8·TCLCL(4) - TFC TSU; STA Repeated START set-up time 14·TCLCL(4) 4.7 μs(1) TSU; STO STOP condition set-up time 14·TCLCL(4) 4.0 μs(1) TBUF Bus free time 14·TCLCL(4) 4.7 μs(1) TRD SDA rise time 1 μs -(2) TFD SDA fall time 0.3 μs 0.3 μs(3) Symbol Parameter THD; STA Notes: 6.3.4.2 1. At 100 kbit/s. At other bit-rates this value is inversely proportional to the bit-rate of 100 kbit/s. 2. Determined by the external bus-line capacitance and the external bus-line pull-up resistor, this must be < 1 μs. 3. Spikes on the SDA and SCL lines with a duration of less than 3·TCLCL will be filtered out. Maximum capacitance on bus-lines SDA and SCL= 400 pF. 4. TCLCL= TOSC= one oscillator clock period. Waveforms Figure 6-16. Two Wire Waveforms Repeated START condition START or Repeated START condition START condition STOP condition Trd Tsu;STA 0.7 VDD 0.3 VDD SDA (INPUT/OUTPUT) Tsu;STO Tfd Trc Tfc Tbuf Tsu;DAT3 0.7 VDD 0.3 VDD SCL (INPUT/OUTPUT) Thd;STA Tlow Thigh Tsu;DAT1 Thd;DAT Tsu;DAT2 27 4173ES–USB–09/07 6.3.5 6.3.5.1 MMC Interface Definition of Symbols Table 14. MMC Interface Timing Symbol Definitions Signals 6.3.5.2 Conditions C Clock H High D Data In L Low O Data Out V Valid X No Longer Valid Min Max Timings Table 15. MMC Interface AC Timings VDD = 2.7 to 3.3 V, TA = -40 to +85°C, CL ≤ 100pF (10 cards) Symbol 6.3.5.3 Parameter Unit TCHCH Clock Period 50 ns TCHCX Clock High Time 10 ns TCLCX Clock Low Time 10 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TDVCH Input Data Valid to Clock High 3 ns TCHDX Input Data Hold after Clock High 3 ns TCHOX Output Data Hold after Clock High 5 ns TOVCH Output Data Valid to Clock High 5 ns Waveforms Figure 6-17. MMC Input Output Waveforms TCHCH TCHCX TCLCX MCLK TCHCL TCHIX TCLCH TIVCH MCMD Input MDAT Input TCHOX TOVCH MCMD Output MDAT Output 28 AT89C5132 4173ES–USB–09/07 AT89C5132 6.3.6 6.3.6.1 Audio Interface Definition of Symbols Table 16. Audio Interface Timing Symbol Definitions Signals 6.3.6.2 Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid Timings Table 17. Audio Interface AC timings VDD = 2.7 to 3.3V, TA = -40 to +85°C, CL ≤ 30pF Symbol Parameter TCHCH Clock Period TCHCX Clock High Time 30 ns TCLCX Clock Low Time 30 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TCLSV Clock Low to Select Valid 10 ns Clock Low to Data Valid 10 ns TCLOV Note: 6.3.6.3 Min Max Unit 325.5(1) ns 32-bit format with Fs = 48 kHz. Waveforms Figure 6-18. Audio Interface Waveforms TCHCH TCHCX TCLCX DCLK TCHCL TCLCH TCLSV DSEL Right Left TCLOV DDAT 29 4173ES–USB–09/07 6.3.7 6.3.7.1 Analog to Digital Converter Definition of Symbols Table 18. Analog to Digital Converter Timing Symbol Definitions Signals 6.3.7.2 Conditions C Clock H High E Enable (ADEN bit) L Low S Start Conversion (ADSST bit) Characteristics Table 18. Analog to Digital Converter AC Characteristics VDD = 2.7 to 3.3 V, TA = -40 to +85°C Symbol TCLCL Clock Period TEHSH Start-up Time TSHSL Min Max Unit μs 4 4 μs Conversion Time 11·TCLCL μs DLe Differential nonlinearity error(1)(2) 1 LSB ILe Integral non-linearity errorss(1)(3) 2 LSB OSe Offset error(1)(4) 4 LSB Ge Gain error(1)(5) 4 LSB Notes: 30 Parameter 1. AVDD= AVREFP= 3.0 V, AVSS= AVREFN= 0 V. ADC is monotonic with no missing code. 2. The differential non-linearity is the difference between the actual step width and the ideal step width (see Figure 6-20). 3. The integral non-linearity is the peak difference between the center of the actual step and the ideal transfer curve after appropriate adjustment of gain and offset errors (see Figure 6-20). 4. The offset error is the absolute difference between the straight line which fits the actual transfer curve (after removing of gain error), and the straight line which fits the ideal transfer curve (see Figure 6-20). 5. The gain error is the relative difference in percent between the straight line which fits the actual transfer curve (after removing of offset error), and the straight line which fits the ideal transfer curve (see Figure 6-20). AT89C5132 4173ES–USB–09/07 AT89C5132 6.3.7.3 Waveforms Figure 6-19. Analog-to-Digital Converter Internal Waveforms CLK TCLCL ADEN Bit TEHSH ADSST Bit TSHSL Figure 6-20. Analog-to-Digital Converter Characteristics Offset Gain Error Error OSe Ge Code Out 1023 1022 1021 1020 1019 1018 Ideal Transfer Curve 7 Example of an Actual Transfer Curve 6 5 Center of a Step 4 Integral Non-linearity (ILe) 3 Differential Non-linearity (DLe) 2 1 0 0 1 LSB (Ideal) AVIN (LSBideal) 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 Offset Error OSe 31 4173ES–USB–09/07 6.3.8 6.3.8.1 Flash Memory Definition of Symbols Table 19. Flash Memory Timing Symbol Definitions Signals 6.3.8.2 Conditions S ISP L Low R RST V Valid B FBUSY flag X No Longer Valid Timings Table 20. Flash Memory AC Timing VDD = 2.7 to 3.3V, TA = -40° to +85°C Symbol 6.3.8.3 Parameter Min Typ Max Unit TSVRL Input ISP Valid to RST Edge 50 ns TRLSX Input ISP Hold after RST Edge 50 ns TBHBL FLASH Internal Busy (Programming) Time NFCY Number of Flash Write Cycles TFDR Flash Data Retention Time 10 ms 100K Cycle 10 Year Waveforms Figure 6-21. Flash Memory – ISP Waveforms RST TSVRL TRLSX ISP(1) Note: 1. ISP must be driven through a pull-down resistor (see Section “In-system Programming”, page 18). Figure 6-22. Flash Memory – Internal Busy Waveforms FBUSY bit 6.3.9 6.3.9.1 TBHBL External Clock Drive and Logic Level References Definition of Symbols Table 21. External Clock Timing Symbol Definitions Signals C 32 Clock Conditions H High L Low X No Longer Valid AT89C5132 4173ES–USB–09/07 AT89C5132 6.3.9.2 Timings Table 22. External Clock AC Timings VDD = 2.7 to 3.3V, TA= -40 to +85°C Symbol Parameter Max Unit TCLCL Clock Period 50 ns TCHCX High Time 10 ns TCLCX Low Time 10 ns TCLCH Rise Time 3 ns TCHCL Fall Time 3 ns Cyclic Ratio in X2 Mode 40 TCR 6.3.9.3 Min 60 % Waveforms Figure 6-23. External Clock Waveform TCLCH VDD - 0.5 0.45 V VIH1 TCHCX TCLCX VIL TCHCL TCLCL Figure 6-24. AC Testing Input/Output Waveforms INPUTS VDD - 0.5 0.45 V Notes: OUTPUTS 0.7 VDD VIH min 0.3 VDD VIL max 1. During AC testing, all inputs are driven at VDD -0.5V for a logic 1 and 0.45V for a logic 0. 2. Timing measurements are made on all outputs at VIH min for a logic 1 and VIL max for a logic 0. Figure 6-25. Float Waveforms VLOAD VLOAD + 0.1V VLOAD - 0.1V Note: Timing Reference Points VOH - 0.1V VOL + 0.1V For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = ±20 mA. 33 4173ES–USB–09/07 7. Ordering Information Possible Order Entries(1) Max Frequency (MHz) 3V Industrial 40 TQFP80 Tray 895132-IL 3V Industrial & Green 40 TQFP80 Tray 895132-UL Part Number Supply Voltage AT89C5132-ROTIL 64K Flash AT89C5132-ROTUL Note: 34 Temperature Range Memory Size (Bytes) 64K Flash Package Packing Product Marking 1. PLCC84 package only available for development board. AT89C5132 4173ES–USB–09/07 AT89C5132 8. Package Information 8.1 TQFP80 35 4173ES–USB–09/07 8.2 36 PLCC84 AT89C5132 4173ES–USB–09/07 AT89C5132 9. Datasheet Revision History for AT89C5132 9.1 Changes from 4173A-08/02 to 4173B-03/04 1. Suppression of ROM product version. 2. Suppression of TQFP64 package. 9.2 Changes from 4173B-03/04 - 4173C - 07/04 1. Add USB connection schematic in USB section. 2. Add USB termination characteristics in DC Characteristics section. 3. Page access mode clarification in Data Memory section. 9.3 Changes from 4173C-07/04 - 4173D - 01/05 1. Interrupt priority number clarification to match number defined by development tools. 9.4 Changes from to 4317D - 01/05 to 4173E - 09/07 1. Added green product ordering information. 2. Removed ‘Preliminary’ status. Product now fully Industrialised. 37 4173ES–USB–09/07 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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