MAXIM DS4625P+125/156

19-4558; Rev 0; 4/09
3.3V Dual-Output LVPECL Clock Oscillator
The DS4625 is a dual-output, low-jitter clock oscillator
capable of producing frequency output pair combinations ranging from 100MHz to 625MHz. The device
combines an AT-cut crystal, an oscillator, and a lownoise phase-locked loop (PLL) in a 5.0mm x 3.2mm
surface-mount LCCC package. Standard frequency
options are listed in the Ordering Information/Selector
Guide table. For custom frequency options, contact the
factory at: [email protected]
The DS4625 provides dual, low-voltage, positive emitter-coupled logic (LVPECL) clock output drivers. The
output drivers can be enabled and disabled through
the OE pin, which is an active-high CMOS input that
has an internal pullup resistor. When high, both output
pairs are enabled.
Features
♦ Standard Clock Output Frequencies: 100MHz,
125MHz, 150MHz, 156.25MHz, and 200MHz
♦ Phase Jitter < 0.7ps RMS (typical) from 12kHz to
20MHz
♦ LVPECL Output
♦ +3.3V ±10% Operating Voltage
♦ -40°C to +70°C Temperature Range
♦ Excellent Power-Supply Noise Rejection
♦ 5.0mm x 3.2mm Ceramic LCCC Package
♦ Output Enable/Disable
The device operates from a single +3.3V ±10% supply.
The operating temperature range is -40°C to +70°C.
Applications
XGMII Clock Oscillator
InfiniBand™
SAS/SATA
PCIe®
1GbE/10GbE
Ordering Information/Selector Guide
TOP
MARK
PART
TEMP RANGE
FREQUENCY (OP1:ON1)
(MHz) (fC)*
FREQUENCY (OP2:ON2)
(MHz) (fC)*
DS4625P+100/150
-40°C to +70°C
100.000
150.000
10 LCCC
6AC
DS4625P+125/125
-40°C to +70°C
125.000
125.000
10 LCCC
6BB
DS4625P+125/156
-40°C to +70°C
125.000
156.250
10 LCCC
6BD
DS4625P+150/150
-40°C to +70°C
150.000
150.000
10 LCCC
6CC
DS4625P+150/200
-40°C to +70°C
150.000
200.000
10 LCCC
6CE
PIN-PACKAGE
+Denotes a lead(Pb)-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both
lead-based and lead-free soldering processes.
*Standard frequency options. Contact the factory at [email protected] for custom frequencies.
Pin Configuration and Typical Application Circuit appear at end of data sheet.
InfiniBand is a trademark and service mark of the InfiniBand Trade Association.
PCIe is a registered trademark of PCI-SIG Corp.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
DS4625
General Description
DS4625
3.3V Dual-Output LVPECL Clock Oscillator
ABSOLUTE MAXIMUM RATINGS
θJA ...................................................................+90°C/W (Note 1)
Storage Temperature Range ...............................-55°C to +85°C
Soldering Temperature (3 passes max of reflow)......Refer to the
IPC/JEDEC J-STD-020 Specification.
(All voltages referenced to ground unless otherwise noted.)
Voltage Range on Any Pin Relative to Ground......-0.3V to +4.0V
Operating Temperature Range ...........................-40°C to +70°C
Junction Temperature ......................................................+150°C
Note 1: Package thermal resistances were obtained using a two-layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage Range
PARAMETER
SYMBOL
VCC
CONDITIONS
2.97
3.3
3.63
V
Input-Voltage High (OE)
VIH
0.7 x
VCC
VCC
V
Input-Voltage Low (OE)
VIL
0
0.3 x
VCC
V
ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +3.63V, TA = -40°C to +70°C, typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 2, 3)
PARAMETER
Operating Current
SYMBOL
Startup Time
MIN
TYP
MAX
UNITS
ICC_PU
LVPECL, output unloaded
65
90
mA
ICC_PL
LVPECL, output loaded
120
140
mA
VOE = V IL
80
115
mA
VOE = V IH
fC
MHz
(Note 4)
1.0
ms
ICC_OEZ
Output Frequency
CONDITIONS
f OUT1
f OUT2
t START
Frequency Stability
fTOTAL/fC
Temperature, aging, load, supply, and
initial tolerance (Note 5)
-50
+50
ppm
Frequency Stability Over
Temperature with Initial
Tolerance
fTEMP/fC
VCC = +3.3V
-35
+35
ppm
+3
ppm/V
Initial Tolerance
f INITIAL/fC VCC = +3.3V, TA = +25°C
Frequency Change Due to VCC
f VCC
Frequency Change Due to Load
Variation
fLOAD/fC
Aging (15 Years)
fAGING/fC
OE Pullup Resistance
2
RPU
VCC = +3.3V ±10%, TA = +25°C
±20
-3
±10% variation in termination resistance
±1
-7
TA = +25°C
ppm
70
100
_______________________________________________________________________________________
ppm
+7
ppm
130
k
3.3V Dual-Output LVPECL Clock Oscillator
(VCC = +2.97V to +3.63V, TA = -40°C to +70°C, typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) (Notes 2, 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
VOH
Output connected to 50 at PECL_BIAS at
VCC - 2.0V
Output Low Voltage
VOL
|V OD |
Differential Output Voltage
TYP
MAX
UNITS
VCC 1.085
VCC 0.88
V
Output connected to 50 at PECL_BIAS at
VCC - 2.0V
VCC 1.825
VCC 1.62
V
Output connected to 50 at PECL_BIAS at
VCC - 2.0V
0.595
0.710
V
ps
Output Rise Time
tR
20% to 80%
200
Output Fall Time
tF
80% to 20%
200
Duty Cycle
DCYCLE
45
ps
55
%
Propagation Delay from OE
Going Low to Output High
Impedance
t PAZ
(See Figure 2)
100
ns
Propagation Delay from OE
Going High to Output Active
t PZA
(See Figure 2)
100
ns
Jitter
JRMS
Integrated phase RMS, 12kHz to 20MHz,
VCC = +3.3V, TA = +25°C
0.7
ps
125.00MHz output, VCC = +3.3V,
TA = +25°C
0.1
ps
10kHz
12.9
ps
100kHz
26.3
ps
200kHz
20.1
ps
1MHz
6.4
ps
Accumulated Deterministic
Jitter Due to Reference Spurs
Accumulated Deterministic
Jitter Due to Power-Supply Noise
(P-P) (Note 6)
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Limits at -40°C are guaranteed by design and are not production tested.
AC parameters are guaranteed by design and not production tested.
Startup time is from VCC = VCCMIN until PLL locks to the crystal oscillator output.
Frequency stability is calculated as: ΔfTOTAL = ΔfTEMP + ΔfVCC x (3.3 x 10%) + ΔfLOAD + ΔfAGING.
Supply-induced jitter is the deterministic jitter as measured on a LeCroy SDA11000 measured with a 50mVP-P sine wave
forced on VCC.
SINGLE-SIDEBAND PHASE NOISE
SSB PHASE NOISE (dBc/Hz) (TYPICAL, +25°C, +3.3V)
OFFSET
fC = 100MHz
fC = 125MHz
fC = 150MHz
fC = 156.25MHz
fC = 200MHz
100Hz
-71
-85
-84
-79
-85
1kHz
-116
-117
-116
-115
-113
-113
10kHz
-119
-118
-116
-117
100kHz
-126
-125
-122
-123
-120
1MHz
-143
-142
-141
-140
-139
10MHz
-151
-149
-149
-148
-149
20MHz
-151
-150
-149
-149
-150
UNITS
dBc/Hz
_______________________________________________________________________________________
3
DS4625
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
fC DEVIATION vs. VCC
30
140
DS4625 toc02
DS4625 toc01
40
ICC vs. VCC
3.0
2.5
130
ICC_PU
120
10
0
-10
-20
2.0
CURRENT (mA)
DEVIATION (ppm)
20
1.5
110
100
ONE OUTPUT LOADED
90
80
1.0
ICC_PL
70
-30
DS4625 toc03
fC DEVIATION vs. TEMPERATURE
50
DEVIATION (ppm)
DS4625
3.3V Dual-Output LVPECL Clock Oscillator
0.5
60
-40
50
0
-50
-40
-20
0
20
40
60
3.0
3.1
TEMPERATURE (°C)
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
VCC (V)
VCC (V)
Pin Description
PIN
4
NAME
FUNCTION
1
OE
2, 3
GND
Ground
Active-High Output Enable. Has an internal pullup resistor (RPU).
4
OP1
Positive Output 1 for LVPECL
5
ON1
Negative Output 1 for LVPECL
6
VCC
Supply Voltage Input
A1, A2
N.C.
No Internal Connection. Must be connected to ground.
A3
OP2
Positive Output 2 for LVPECL
A4
ON2
Negative Output 2 for LVPECL
—
EP
Exposed Pad. The exposed pad must be used for thermal relief. This pad must be connected to
ground.
_______________________________________________________________________________________
3.3V Dual-Output LVPECL Clock Oscillator
DS4625
VCC
VCC
RPU
X1
OE
X0
PLL
OP1
LC-VCO
PFD
X2
DIV M
LVPECL
LPF
ON1
DIV N
OP2
DIV P
DS4625
LVPECL
ON2
GND
Figure 1. Block Diagram
0.7 x VCC
OE
0.3 x VCC
tPZA
tPAZ
OP_
PECL_BIAS
PECL_BIAS
PECL_BIAS
PECL_BIAS
ON_
Figure 2. LVPECL Output Timing Diagram When OE is Enabled and Disabled
_______________________________________________________________________________________
5
DS4625
3.3V Dual-Output LVPECL Clock Oscillator
Pin Configuration
Detailed Description
The DS4625 is a dual-output, low-jitter clock oscillator
that produces frequency output pair combinations as
shown in the Ordering Information/Selector Guide table.
The phase relationship between the outputs is not guaranteed. The device combines an AT-cut, fundamentalmode crystal, an oscillator, and a low-noise PLL in a
5.0mm x 3.2mm surface-mount LCCC package.
The DS4625 provides dual LVPECL clock output drivers. The output drivers can be enabled and disabled
through the OE pin. The OE pin is an active-high CMOS
input that has an internal pullup resistor. When OE is
high, both output pairs are enabled.
TOP VIEW
+
OE
1
GND
2
GND
3
N.C.
N.C.
A1
A2
DS4625
*EP
A3
6
VCC
5
ON1
4
OP1
Chip Information
A4
PROCESS: Bipolar SiGe
OP2
ON2
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
(5.00mm × 3.20mm × 1.49mm)
*EXPOSED PAD
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
10 LCCC
L1053+H2
21-0389
Typical Application Circuit
VCC
0.1μF
OP1
0.01μF
50Ω
PECL_BIAS AT VCC - 2.0V
DS4625
50Ω
ON1
OE
OP2
50Ω
PECL_BIAS AT VCC - 2.0V
GND
50Ω
ON2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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