Rev 0; 10/08 DDR Clock Oscillator The DS4266 surface-mount ceramic crystal oscillator is part of Maxim’s DS4-XO crystal oscillator product family. The DS4266 is a 266MHz crystal oscillator designed to support high-performance DDR memory applications that require a stable, low-jitter, and tight duty-cycle clock source. The device provides an overall accuracy and stability better than ±50ppm, including aging. Jitter performance is better than 0.7psRMS typically over a 12kHz to 20MHz bandwidth, and duty-cycle performance is better than 48%/52%. The DS4266 has an output frequency of 266MHz, and it supports LVDS and LVPECL output types. The DS4266 is constructed using a fundamental crystal in conjunction with high-performance silicon germanium PLL technology, enabling very low phase noise and phase jitter performance. The device operates from a 3.3V ±5% power supply and consumes a maximum current of 100mA. The DS4266 is packaged in a miniature 5mm x 3.2mm x 1.49mm, 10-lead LCCC ceramic package, making it suitable for applications where board space is critical. Applications Features ♦ < 0.7psRMS (typ) from 12kHz to 20MHz Jitter ♦ LVDS or LVPECL Output Types ♦ 3.3V Operating Voltage ♦ 5.0mm x 3.2mm x 1.49mm, 10-Pin LCCC Ceramic Package ♦ -40°C to +85°C Operating Temperature Range ♦ Lead-Free/RoHS Compliant Ordering Information PART TEMP RANGE PIN-PACKAGE DS4266D+ -40°C to +85°C 10 LCCC DS4266P+ -40°C to +85°C 10 LCCC +Denotes a lead-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both lead-based and lead-free soldering processes. Pin Configuration and Selector Guide appear at end of data sheet. DDR Memory Clock Source Typical Operating Circuits VCC 0.1μF OUTP VCC 0.1μF 0.01μF DS4266 50Ω DS4266 100Ω OE OUTP 0.01μF PECL_BIAS VCC - 2.0V 50Ω OE GND OUTN LVDS OPTION GND OUTN LVPECL OPTION ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS4266 General Description DS4266 DDR Clock Oscillator ABSOLUTE MAXIMUM RATINGS Power-Supply Voltage (VCC) .......................................-0.3V, +4V Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range ...............................-55°C to +85°C Soldering Temperature Profile (3 passes max of reflow) ......................Refer to the IPC/JEDEC J-STD-020 Specification. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER Operating Voltage Range SYMBOL VCC ICC_D Operating Current Output Frequency CONDITIONS (Note 1) MIN TYP MAX UNITS 3.135 3.3 3.465 V 52 75 LVDS, output loaded or unloaded ICC_PU LVPECL, output unloaded 49 70 ICC_PI LVPECL, output load 50 at VCC - 2.0V 74 100 f OUT fNOM Oscillator Startup Time t STARTUP (Note 2) Frequency Stability fTOTAL Over temperature range, aging, load, supply, and initial tolerance (Note 3) -50 Frequency Stability Over Temperature with Initial Tolerance fTEMP VCC = 3.3V -35 Initial Tolerance f INITIAL Frequency Change Due to VCC f VCC Frequency Change Due to Load Variation fLOAD Aging (15 Years) fAGING Jitter JRMS VCC = 3.3V, TA = +25°C VCC = 3.3V ±5% fNOM MHz 50 ms +50 ppm +35 ppm ±20 -3 ±10% variation in termination resistance ppm +3 ±1 -7 0.7 Integrated phase RMS; 12kHz to 20MHz, VCC = 3.3V, TA = +25°C 0.7 Integrated phase RMS; 12kHz to 80MHz, VCC = 3.3V, TA = +25°C 1.0 ppm/V ppm +7 Integrated phase RMS; 12kHz to 5MHz, VCC = 3.3V, TA = +25°C mA ppm ps Input-Voltage High (OE) VIH (Note 1) 0.7 x VCC VCC V Input-Voltage Low (OE) VIL (Note 1) 0 0.3 x VCC V -50 +5.0 μA Input Leakage (OE) 2 ILEAK GND OE VCC _______________________________________________________________________________________ DDR Clock Oscillator (VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.475 V 425 mV LVDS Output High Voltage VOHLVDSO 100 differential load (Note 1) Output Low Voltage VOLLVDSO 100 differential load (Note 1) Differential Output Voltage |VODLVDSO| 100 differential load Output Common-Mode Voltage Variation VLVDSOCOM 100 differential load 150 mV Change in Differential Magnitude or Complementary Inputs |VODLVDSO| 100 differential load 25 mV Offset Output Voltage Differential Output Impedance VOFFLVDSO L VSSLVDSO Output Current Output Rise Time (Differential) Output Fall Time (Differential) Duty Cycle 100 differential load (Note 1) R OLVDSO 0.925 V 250 1.125 1.275 V 80 140 OUTN or OUTP shorted to ground and measure the current in the shorting path 40 LLVDSO OUTN or OUTP shorted together 6.5 tRLVDSO 20% to 80% 175 tFLVDSO 80% to 20% DCYCLE_LVDS ps 175 48 mA ps 52 % Propagation Delay from OE Going Low to Logical 1 at OUTP t PA1 200 ns Propagation Delay from OE Going High to Output Active t P1A 200 ns LVPECL Output High Voltage VOH Output connected to 50 at PECL_BIAS at VCC - 2.0V VCC 1.085 VCC 0.88 V Output Low Voltage VOL Output connected to 50 at PECL_BIAS at VCC - 2.0V VCC 1.825 VCC 1.62 V Differential Voltage VDIFF_PECL Output connected to 50 at PECL_BIAS at VCC - 2.0V 0.595 Rise Time tR-PECL Fall Time tF-PECL Duty Cycle DCYCLE_PECL 0.710 V 200 ps 200 48 ps 52 % Propagation Delay from OE Going Low to Output High Impedance t PAZ 200 ns Propagation Delay from OE Going High to Output Active t PZA 200 ns Note 1: All voltages referenced to ground. Note 2: AC parameters are guaranteed by design and not production tested. Note 3: Frequency stability is calculated as: ΔfTOTAL = ΔfTEMP + ΔfVCC x (3.3 x 5%) + ΔfLOAD + ΔfAGING. _______________________________________________________________________________________ 3 DS4266 ELECTRICAL CHARACTERISTICS (continued) Single-Sideband Phase Noise at fO = fNOM SINGLE-SIDEBAND PHASE NOISE AT fO = fNOM (dBc/Hz) fM = 266MHz 10Hz -65 100Hz -95 1kHz -113 10kHz -113 100kHz -118 1MHz -137 10MHz -149 20MHz -153 Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) 55 DS4266 toc01 15 13 10 8 5 3 0 -3 -5 -8 -10 -13 -15 -18 -20 +85°C +40°C +70°C +25°C DS4266 toc02 OPERATING CURRENT vs. OPERATING VOLTAGE FREQUENCY vs. TEMPERATURE 53 ICC (mA) fOUT DEVIATION (ppm) DS4266 DDR Clock Oscillator 50 0°C 48 -40°C -40 -20 0 20 40 60 80 45 3.135 3.185 3.235 3.285 3.335 3.385 3.435 TEMPERATURE (°C) VCC (V) Pin Description PIN 4 NAME FUNCTION 1 OE 2, 7–10 N.C. No Connection. Must be floated. Active-High Output Enable. Has an internal pullup 100k resistor. 3 GND Ground 4 OUTP Positive Output for LVPECL or LVDS 5 OUTN Negative Output for LVPECL or LVDS 6 VCC — EP Supply Voltage Exposed Paddle. Do not connect this pad or place exposed metal under the pad. _______________________________________________________________________________________ DDR Clock Oscillator DS4266 VCC OE X1 THREESTATE PHASE DET X2 LC-VCO FILTER OUTP /n OUTSELN OUTDRV OUTN /m DS4266 GND Figure 1. Functional Diagram Detailed Description The DS4266 consists of a fundamental-mode crystal and synthesizer IC packaged in a 5mm x 3.2mm x 1.49mm, 10-pin LCCC ceramic package. The device produces a frequency output of 266.00MHz. Two differential output types are available: LVDS and LVPECL. The device output can be enabled or disabled through the OE signal input. When the OE signal is low, LVPECL outputs go to the PECL_BAS level of VCC - 2.9V, while the LVDS outputs are a logical 1. See Figures 2 and 3 for LVDS and LVPECL output timing diagrams. Additional Information For more available frequencies in the DS4-XO family, refer to the DS4125 data sheet at www.maximic.com/DS4125. 0.7 x VCC OE 0.7 x VCC 0.3 x VCC tP1A tPA1 OE 0.3 x VCC tPZA tPAZ OUTP OUTP OUTN OUTN Figure 2. LVDS Output Timing Diagram When OE Is Enabled and Disabled PECL_BIAS PECL_BIAS PECL_BIAS PECL_BIAS Figure 3. LVPECL Output Timing Diagram When OE Is Enabled and Disabled _______________________________________________________________________________________ 5 DS4266 DDR Clock Oscillator Selector Guide OUTPUT TYPE TOP MARK ±50 LVDS 66D ±50 LVPECL 66P FREQUENCY (NOM) (MHz) FREQUENCY STABILITY (ppm) DS4266D+ 266 DS4266P+ 266 PART +Denotes a lead-free/RoHS-compliant package. The lead finish is JESD97 category e4 (Au over Ni) and is compatible with both leadbased and lead-free soldering processes. Pin Configuration SUBSTRATE CONNECTED TO GROUND PROCESS: BiPOLAR SiGe TOP VIEW N.C. Chip Information N.C. + OE 6 1 Thermal Information VCC THETA-JA (°C/W) N.C. 2 GND 3 DS4266 *EP 5 OUTN 4 OUTP 90 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. N.C. N.C. (5.00mm × 3.20mm × 1.49mm) PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10 LCCC — 56-G5032-002 *EXPOSED PAD Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.