512 Kbit / 1 Mbit / 2 Mbit (x8) Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet FEATURES: • Organized as 64K x8 / 128K x8 / 256K x8 • Single 5.0V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 10 mA (typical) – Standby Current: 30 µA (typical) • Sector-Erase Capability – Uniform 4 KByte sectors • Fast Read Access Time: – 45 and 70 ns • Latched Address and Data • Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 1 seconds (typical) for SST39SF512A 2 seconds (typical) for SST39SF010A 4 seconds (typical) for SST39SF020A • Automatic Write Timing - Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • TTL I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 32-Pin PDIP – 32-Pin PLCC – 32-Pin TSOP (8mm x 14mm) PRODUCT DESCRIPTION 2 3 4 5 6 7 8 The SST39SF512A/010A/020A are CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF512A/010A/ 020A devices write (Program or Erase) with a 5.0V power supply. The SST39SF512A/010A/020A device conforms to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39SF512A/010A/020A devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39SF512A/010A/020A devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time © 2000 Silicon Storage Technology, Inc. 509-3 10/00 S71164 1 of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/ Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST39SF512A/010A/020A are offered in 32-pin TSOP and 32-pin PLCC packages. A 600 mil, 32-pin PDIP is also available. See Figures 1, 2 and 3 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon storage Technology, Inc. These specifications are subject to change without notice. 1 9 10 11 12 13 14 15 16 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet Read The Read operation of the SST39SF512A/010A/020A is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to Figure 4 for the Read cycle timing diagram. The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing diagram, and Figure 18 for the flowchart. Any commands written during the ChipErase operation will be ignored. Byte-Program Operation The SST39SF512A/010A/020A are programmed on a byte-by-byte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 5 and 6 for WE# and CE# controlled Program operation timing diagrams and Figure 15 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Write Operation Status Detection The SST39SF512A/010A/020A provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-ofWrite detection mode is enabled after the rising edge of WE#, which initiates the program or erase cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated by executing a six-byte-command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse , while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 9 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Data# Polling (DQ7) When the SST39SF512A/010A/020A are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program Operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling timing diagram and Figure 16 for a flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0’s and 1’s, i.e., toggling between 0 and 1. The Toggle Bit will begin with “1”. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising Chip-Erase Operation The SST39SF512A/010A/020A provide Chip-Erase operation, which allows the user to erase the entire memory array to the “1’s” state. This is useful when the entire device must be quickly erased. © 2000 Silicon Storage Technology, Inc. 2 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet Product Identification The product identification mode identifies the device as the SST39SF512A, SST39SF010A and SST39SF020A and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SST39SF512A/010A/020A. Users may wish to use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 11 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Toggle Bit timing diagram and Figure 16 for a flowchart. Data Protection The SST39SF512A/010A/020A provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The write operation is inhibited when VDD is less than 2.5V. TABLE 1: PRODUCT IDENTIFICATION TABLE Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Data 0000H BF H SST39SF512A 0001H B4 H SST39SF010A 0001H B5 H SST39SF020A 0001H B6 H Device ID Software Data Protection (SDP) The SST39SF512A/010A/020A provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six byte load sequence. The SST39SF512A/010A/020A devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. 2 3 4 5 Address Manufacturer’s ID 1 509 PGM T1.0 Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 12 for timing waveform and Figure 17 for a flowchart. 6 7 8 9 10 11 12 FUNCTIONAL BLOCK DIAGRAM X-Decoder 13 SuperFlash Memory 14 Memory Address Address Buffers & Latches Y-Decoder 15 CE# OE# I/O Buffers and Data Latches Control Logic 16 WE# DQ7 - DQ0 509 ILL B1.1 © 2000 Silicon Storage Technology, Inc. 3 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet SST39SF020A SST39SF010A SST39SF512A A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC NC A15 A12 A7 A6 A5 A4 SST39SF512A SST39SF010A SST39SF020A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die Up OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 509 ILL F01.1 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP (8mm x 14mm) SST39SF020A SST39SF010A SST39SF512A NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS NC NC A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS SST39SF512A SST39SF010A SST39SF020A 1 2 3 4 5 32-Pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VDD WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 509 ILL F02a.1 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PDIP © 2000 Silicon Storage Technology, Inc. 4 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A A17 1 2 NC VDD WE# WE# VDD 4 3 2 1 32 31 30 29 3 NC VDD WE# NC NC NC A15 A16 A16 NC A15 A12 A12 A15 SST39SF020A SST39SF010A SST39SF512A A12 SST39SF512A SST39SF010A SST39SF020A Data Sheet SST39SF512A SST39SF010A SST39SF020A A7 5 A14 A14 A14 A6 A6 A6 6 28 A13 A13 A13 A5 A5 A5 7 27 A8 A8 A8 A4 A4 A4 8 26 A9 A9 A9 A3 A3 A3 9 25 A11 A11 A11 A2 A2 A2 10 24 OE# OE# OE# A1 A1 A1 11 23 A10 A10 A10 A0 A0 A0 12 22 CE# CE# CE# DQ0 DQ0 DQ0 13 21 14 15 16 17 18 19 20 DQ7 DQ7 DQ7 4 5 6 7 509 ILL F02b.1 DQ6 8 9 DQ6 DQ5 DQ4 DQ4 DQ5 DQ5 DQ4 DQ3 DQ3 DQ3 VSS DQ2 DQ2 VSS VSS DQ2 DQ1 DQ1 DQ1 32-Pin PLCC Top View DQ6 A7 SST39SF020A SST39SF010A SST39SF512A A7 10 FIGURE 3: PIN ASSIGNMENTS FOR 32-PIN PLCC 11 12 13 14 15 16 © 2000 Silicon Storage Technology, Inc. 5 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet TABLE 2: PIN DESCRIPTION Symbol Pin Name Address Inputs AMS-A0 DQ7-DQ0 Data Input/output CE# OE# WE# VDD VSS NC Chip Enable Output Enable Write Enable Power Supply Ground No Connection Functions To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide 5-volt supply (± 10%) Unconnected pins. 509 PGM T2.1 Note: AMS = Most significant address AMS = A15 for SST39SF512A, A16 for SST39SF010A and A17 for SST39SF020A TABLE 3: OPERATION MODES SELECTION Mode CE# Read VIL Program VIL Erase VIL Standby Write Inhibit Product Identification Hardware Mode Software Mode OE# VIL VIH VIH WE# VIH VIL VIL A9 AIN AIN X DQ DOUT DIN X VIH X X X VIL X X X VIH X X X High Z High Z/DOUT High Z/DOUT Address AIN AIN Sector address, XXH for Chip-Erase X X X VIL VIL VIH VH VIL VIL VIH AIN Manufacturer’s ID (BFH) Device ID1 ID Code AMS(2) - A1 = VIL, A0 = VIL AMS(2) - A1 = VIL, A0 = VIH See Table 4 509 PGM T3.1 Note: 1. Device Code = B4H for SST39SF512A, B5H for SST39SF010A and B6H for SST39SF020A 2. AMS = Most significant address AMS = A15 for SST39SF512A, A16 for SST39SF010A and A17 for SST39SF020A © 2000 Silicon Storage Technology, Inc. 6 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr1 Data Byte-Program 5555H AAH Sector-Erase 5555H AAH Chip-Erase 5555H AAH Software ID Entry 5555H AAH Software ID Exit XXH F0H Software ID Exit 5555H AAH 2nd Bus Write Cycle Addr1 Data 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H 3rd Bus Write Cycle Addr1 Data 5555H A0H 5555H 80H 5555H 80H 5555H 90H 2AAAH 5555H 4th Bus Write Cycle Addr1 Data BA3 Data 5555H AAH 5555H AAH 5th Bus Write Cycle Addr1 Data 6th Bus Write Cycle Addr1 Data 1 2AAAH 55H 2AAAH 55H SAx2 30H 5555H 10H 2 3 55H F0H 509 PGM T4.0 Notes: 1. Address format A14-A0 (Hex), Address A15 is a “Don’t Care” for the Command sequence for SST39SF512A. Address A16 and A15 are "Don't Care" for the Command sequence for SST39SF010A. Address A15, A16 and A17 are "Don't Care" for the Command sequence for SST39SF020A. 2. SAx for Sector-Erase; uses AMS-A12 address lines AMS = Most significant address AMS = A15 for SST39SF512A, A16 for SST39SF010A and A17 for SST39SF020A 3. BA = Program Byte address 4. Both Software ID Exit operations are equivalent 5. With AMS -A1 =0; SST Manufacturer’s ID = BFH, is read with A0 = 0, SST39SF512A Device ID = B4 H, is read with A0 = 1. SST39SF010A Device ID = B5 H, is read with A0 = 1. SST39SF020A Device ID = B6 H, is read with A0 = 1. 6. The device does not remain in Software Product ID Mode if powered down. 4 5 6 7 8 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55°C to +125°C Storage Temperature ........................................................................................................................ -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential .............................................................................. -0.5V to VDD+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential .......................................................... -1.0V to VDD+ 1.0V Voltage on A9 Pin to Ground Potential ................................................................................................. -0.5V to 13.2V Package Power Dissipation Capability (Ta = 25°C) ............................................................................................ 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .................................................................................. 300°C Surface Mount Lead Soldering Temperature (3 Seconds) .................................................................................. 240°C Output Short Circuit Current1 .................................................................................................................................................................... 50 mA Note: 1. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Ambient Temp Commercial 0 °C to +70 °C Industrial -40 °C to +85 °C 10 11 12 13 14 AC CONDITIONS OF TEST VDD 5V±10% 5V±10% 9 Input Rise/Fall Time ......... 5 ns 15 Output Load ..................... CL = 30 pF See Figures 13 and 14 16 © 2000 Silicon Storage Technology, Inc. 7 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet TABLE 5: DC OPERATING CHARACTERISTICS VDD = 5V±10% Limits Symbol Parameter Min Max IDD Units Test Conditions Power Supply Current Read Write Standby VDD Current (TTL input) Standby VDD Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Supervoltage for A9 pin Supervoltage Current for A9 pin I SB1 I SB2 I LI I LO VIL VIH VOL VOH VH IH 20 20 3 mA mA mA 100 µA 1 1 0.8 µA µA V V V V V µA 2.0 0.4 2.4 11.4 12.6 200 Address input = VIL/VIH, at f=1/TRC Min., VDD=VDD Max CE#=OE#=VIL,WE#=VIH , all I/Os open. CE#=WE#=VIL, OE#=VIH CE#=VIH, VDD =VDD Max. CE#=VIHC. VDD = VDD Max. VIN =GND to VDD, VDD = VDD Max. VOUT =GND to VDD, VDD = VDD Max. VDD = VDD Min. VDD = VDD Max. IOL = 2.1 mA, VDD = VDD Min. IOH = -400µA, VDD = VDD Min. CE# = OE# =VIL, WE# = VIH CE# = OE# = VIL, WE# = VIH, A9 = VH Max. 509 PGM T5.2 TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ1 TPU-WRITE1 Power-up to Read Operation Power-up to Write Operation Minimum Units 100 100 µs µs 509 PGM T6.0 TABLE 7: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open) Parameter Description Test Condition 1 CI/O CIN1 I/O Pin Capacitance Input Capacitance Maximum VI/O = 0V VIN = 0V 12 pF 6 pF 509 PGM T7.0 Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: RELIABILITY CHARACTERISTICS Symbol Parameter NEND1 TDR1 VZAP_HBM1 VZAP_MM1 ILTH1 Endurance Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up Minimum Specification Units Test Method 10,000 100 2000 Cycles Years Volts JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 200 Volts JEDEC Standard A115 100 + IDD mA JEDEC Standard 78 509 PGM T8.1 Note: 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. © 2000 Silicon Storage Technology, Inc. 8 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet AC CHARACTERISTICS TABLE 9: READ CYCLE TIMING PARAMETERS VDD = 4.5-5.5V SST39SF512A/010A/020A-45 SST39SF512A/010A/020A-70 Symbol Parameter Min Max Min Max Read Cycle Time 45 70 TRC TCE Chip Enable Access Time 45 70 TAA Address Access Time 45 70 TOE Output Enable Access Time 25 35 TCLZ1 CE# Low to Active Output 0 0 TOLZ1 OE# Low to Active Output 0 0 CE# High to High-Z Output 15 25 TCHZ1 1 TOHZ OE# High to High-Z Output 15 25 1 TOH Output Hold from Address Change 0 0 1 Units ns ns ns ns ns ns ns ns ns 509 PGM T9.2 TABLE 10: PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Byte-Program Time TAS Address Setup Time TAH Address Hold Time TCS WE# and CE# Setup Time TCH WE# and CE# Hold Time TOES OE# High Setup Time TOEH OE# High Hold Time TCP CE# Pulse Width TWP WE# Pulse Width TWPH1 WE# Pulse Width High 1 TCPH CE# Pulse Width High TDS Data Setup Time 1 TDH Data Hold Time 1 TIDA Software ID Access and Exit Time TSE Sector-Erase TSCE Chip-Erase 2 3 4 5 6 7 Min Max 20 0 30 0 0 0 0 40 40 30 30 30 0 150 25 100 Units µs ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 8 9 10 11 12 13 509 PGM T10.1 Note: 1. This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 14 15 16 © 2000 Silicon Storage Technology, Inc. 9 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet TAA TRC ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z DQ7-0 TCHZ TOH TCLZ HIGH-Z DATA VALID DATA VALID 509 ILL F03.0 Note: AMS = Most significant address AMS = A15 for SST39SF512A, A16 for SST39SF010A and A17 for SST39SF020A FIGURE 4: READ CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TWP WE# TAS TDS TWPH OE# TCH CE# TCS DQ7-0 AA SW0 55 SW1 A0 SW2 DATA BYTE (ADDR/DATA) 509 ILL F04.0 Note: AMS = Most significant address AMS = A15 for SST39SF512A, A16 for SST39SF010A and A17 for SST39SF020A FIGURE 5: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. 10 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet INTERNAL PROGRAM OPERATION STARTS 1 TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR 2 TDH TCP CE# TAS TDS TCPH 3 OE# 4 TCH WE# TCS DQ7-0 AA 55 SW0 SW1 5 A0 DATA SW2 6 BYTE (ADDR/DATA) 509 ILL F05.0 Note: AMS = Most significant address AMS = A15 for SST39SF512A, A16 for SST39SF010A and A17 for SST39SF020A 7 FIGURE 6: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM 8 9 10 ADDRESS AMS-0 TCE 11 CE# TOES TOEH 12 OE# TOE 13 WE# DQ7 D D# D# 14 D 509 ILL F06.0 Note: AMS = Most significant address AMS = A15 for SST39SF512A, A16 for SST39SF010A and A17 for SST39SF020A 16 FIGURE 7: DATA# POLLING TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. 15 11 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet ADDRESS AMS-0 TCE CE# TOES TOE TOEH OE# WE# DQ6 Note TWO READ CYCLES WITH SAME OUTPUTS Note: Toggle bit output is always high first. AMS = Most significant address AMS = A15 for SST39SF512A, A16 for SST39SF010A and A17 for SST39SF020A 509 ILL F07.0 FIGURE 8: TOGGLE BIT TIMING DIAGRAM TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 SW0 SW1 SW2 SW3 SW4 30 SW5 509 ILL F08.0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A15 for SST39SF512A, A16 for SST39SF010A and A17 for SST39SF020A FIGURE 9: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM © 2000 Silicon Storage Technology, Inc. 12 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet TSCE SIX-BYTE CODE FOR CHIP-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA 1 5555 CE# 2 OE# 3 TWP 4 WE# DQ7-0 AA 55 80 AA 55 SW0 SW1 SW2 SW3 SW4 5 10 SW5 509 ILL F17.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minimum timings are met. (See Table 10) SAX = Sector Address 6 7 AMS = Most significant address AMS = A15 for SST39SF512A, A16 for SST39SF010A and A17 for SST39SF020A 8 FIGURE 10: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM 9 Three-byte sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 10 5555 0000 0001 11 CE# 12 OE# 13 TIDA TWP WE# 14 TWPH DQ7-0 AA 55 SW0 SW1 TAA BF 90 Device ID 15 SW2 509 ILL F09.1 Device ID = B4H for SST39SF512A, B5H for SST39SF010A and B6H for SST39SF020A 16 FIGURE 11: SOFTWARE ID ENTRY AND READ © 2000 Silicon Storage Technology, Inc. 13 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 DQ7-0 5555 2AAA AA 5555 55 F0 TIDA CE# OE# TWP WE# T WHP SW0 SW1 SW2 509 ILL F10.0 FIGURE 12: SOFTWARE ID EXIT AND RESET © 2000 Silicon Storage Technology, Inc. 14 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet 1 VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT 2 VILT 509 ILL F11.0 3 AC test inputs are driven at VIHT (3.0 V) for a logic “1” and VILT (0 V) for a logic “0”. Measurement reference points for inputs and outputs are VIT (1.5 V) and VOT (1.5 V). Inputs rise and fall times (10% « 90%) are <5 ns. Note: VIT–VINPUT Test VOT–VOUTPUT Test VIHT–VINPUT HIGH Test VILT–VINPUT LOW Test 4 5 FIGURE 13: AC INPUT/OUTPUT REFERENCE WAVEFORMS 6 7 8 TEST LOAD EXAMPLE VDD 9 TO TESTER RL HIGH 10 11 TO DUT CL RL LOW 12 13 509 ILL F12.1 14 FIGURE 14: A TEST LOAD EXAMPLE 15 16 © 2000 Silicon Storage Technology, Inc. 15 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Byte Address/Byte Data Wait for end of Program (TBP' Data# Polling bit or Toggle bit operation) Program Completed 509 ILL F13.1 FIGURE 15: BYTE-PROGRAM ALGORITHM © 2000 Silicon Storage Technology, Inc. 16 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet 1 Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Byte-Program/ Sector Erase Initiated Byte-Program Initiated Read byte Read DQ7 Wait TBP, TSCE, or TSE 2 3 4 5 Read same byte Program/Erase Completed No 6 Is DQ7 = true data? Yes No Does DQ6 match? 7 Write Completed 8 Yes 9 Write Completed 10 509 ILL F14.0 11 12 13 FIGURE 16: WAIT OPTIONS 14 15 16 © 2000 Silicon Storage Technology, Inc. 17 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet Software Product ID Entry Command Sequence Software Product ID Exit & Reset Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: F0H Address: XXH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Wait TIDA Load data: 90H Address: 5555H Load data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 509 ILL F15.1 FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS © 2000 Silicon Storage Technology, Inc. 18 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence 1 Load data: AAH Address: 5555H Load data: AAH Address: 5555H 2 3 Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 80H Address: 5555H 4 5 6 Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH 7 8 9 Load data: 10H Address: 5555H Load data: 30H Address: SAX 10 11 Wait TSCE Wait TSE Chip-Erase to FFH Sector-Erase to FFH 12 13 14 509 ILL F16.1 15 FIGURE 18: ERASE COMMAND SEQUENCE 16 © 2000 Silicon Storage Technology, Inc. 19 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet Device SST39SFxxxA Speed Suffix1 Suffix2 - XXX XX XX Package Modifier H = 32 leads Numeric = Die modifier Package Type P = PDIP N = PLCC W = TSOP (die up) (8mm x 14mm) U = Unencapsulated die Temperature Range C = Commercial = 0° to 70°C I = Industrial = -40° to 85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 45 = 45 ns, 70 = 70 ns Version Device Density 512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit Voltage S = 4.5-5.5V SST39SF512A Valid combinations SST39SF512A-45-4C-WH SST39SF512A-70-4C-WH SST39SF512A-70-4C-U1 SST39SF512A-45-4I-WH SST39SF512A-70-4I-WH SST39SF512A-45-4I-NH SST39SF512A-70-4I-NH SST39SF010A Valid combinations SST39SF010A-45-4C-WH SST39SF010A-70-4C-WH SST39SF010A-45-4C-NH SST39SF010A-70-4C-NH SST39SF512A-45-4C-NH SST39SF512A-70-4C-NH SST39SF512A-70-4C-PH SST39SF010A-70-4C-PH SST39SF010A-70-4C-U1 SST39SF010A-45-4I-WH SST39SF010A-70-4I-WH SST39SF010A-45-4I-NH SST39SF010A-70-4I-NH SST39SF020A Valid combinations SST39SF020A-45-4C-WH SST39SF020A-70-4C-WH SST39SF020A-45-4C-NH SST39SF020A-70-4C-NH SST39SF020A-70-4C-PH SST39SF020A-70-4C-U1 SST39SF020A-45-4I-WH SST39SF020A-70-4I-WH SST39SF020A-45-4I-NH SST39SF020A-70-4I-NH Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. © 2000 Silicon Storage Technology, Inc. 20 S71164 509-3 10/00 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet PACKAGING DIAGRAMS 1 pin 1 index 1 2 CL 3 .600 .625 32 .530 .550 1.645 1.655 .065 .075 4 7˚ 4 PLCS. .170 .200 Base Plane Seating Plane 5 .015 .050 .070 .080 Note: .045 .065 .016 .022 .120 .150 .100 BSC 0˚ 15˚ .008 .012 6 .600 BSC 7 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32.pdipPH-ILL.1 8 32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH 9 TOP VIEW Optional Pin #1 Identifier SIDE VIEW .485 .495 .447 .453 .042 .048 2 1 BOTTOM VIEW 10 11 .106 .112 32 .020 R. MAX. .023 x 30˚ .029 .030 R. .040 12 .042 .048 .585 .595 .547 .553 .013 .021 .400 BSC .026 .032 13 .490 .530 .050 BSC. 14 .015 Min. .075 .095 .050 BSC. .125 .140 Note: 15 .026 .032 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 32.PLCC.NH-ILL.1 32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH © 2000 Silicon Storage Technology, Inc. 21 S71164 509-3 10/00 16 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash SST39SF512A / SST39SF010A / SST39SF020A Data Sheet 1.05 0.95 PIN # 1 IDENTIFIER .50 BSC 8.10 7.90 0.15 0.05 12.50 12.30 0.70 0.50 Note: .270 .170 14.20 13.80 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 32.TSOP-WH-ILL.3 32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM SST PACKAGE CODE: WH Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 2000 Silicon Storage Technology, Inc. 22 S71164 509-3 10/00