SST SST39WF400A-100-4I-C1QE

4 Mbit (x16) Multi-Purpose Flash
SST39WF400A
SST39WF400A1.8V 4Mb (x16) MPF memory
Data Sheet
FEATURES:
• Organized as 256K x16
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 1 µA (typical)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Fast Read Access Time
– 90 ns
– 100 ns
• Latched Address and Data
• Fast Erase and Word-Program
– Sector-Erase Time: 36 ms (typical)
– Block-Erase Time: 36 ms (typical)
– Chip-Erase Time: 140 ms (typical)
– Word-Program Time: 28 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm) Micro-Package
– 48-bump XFLGA (4mm x 6mm) Micro-Package
PRODUCT DESCRIPTION
The SST39WF400A device is a 256K x16 CMOS MultiPurpose Flash (MPF) manufactured with SST’s proprietary,
high performance CMOS SuperFlash technology. The
split-gate cell design and thick-oxide tunneling injector
attain better reliability and manufacturability compared with
alternate approaches. The SST39WF400A writes (Program or Erase) with a 1.65-1.95V power supply. This
device conforms to JEDEC standard pin assignments for
x16 memories.
Featuring
high-performance
Word-Program,
the
SST39WF400A device provides a typical Word-Program
time of 28 µsec. The device uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent writes, it has on-chip
hardware and software data protection schemes.
Designed, manufactured, and tested for a wide spectrum of
applications, this device is offered with a guaranteed typical
endurance of 100,000 cycles. Data retention is rated at
greater than 100 years.
The SST39WF400A device is suited for applications that
require convenient and economical updating of program,
configuration, or data memory. For all system applications,
it significantly improves performance and reliability, while
lowering power consumption. It inherently uses less energy
©2004 Silicon Storage Technology, Inc.
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1
during Erase and Program than alternative flash technologies. When programming a flash device, the total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash technologies. These devices also improve flexibility
while lowering the cost for program, data, and configuration
storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Program cycles.
To meet surface mount requirements, the SST39WF400A
is offered in both a 48-ball TFBGA package and 48-ball
Micro-Packages. See Figures 1 and 2 for pin assignments.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
Device Operation
operation is initiated by executing a six-byte command
sequence with Block-Erase command (50H) and block
address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (30H or 50H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data#
Polling or Toggle Bit methods. See Figures 9 and 10 for timing waveforms. Any commands issued during the Sectoror Block-Erase operation are ignored.
Commands are used to initiate the memory operation functions of the device. Commands are written to the device
using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39WF400A is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 3).
Chip-Erase Operation
The SST39WF400A provides a Chip-Erase operation,
which allows the user to erase the entire memory array to
the “1” state. This is useful when the entire device must be
quickly erased.
The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H)
at address 5555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid read is Toggle Bit or Data# Polling. See Table
4 for the command sequence, Figure 8 for timing diagram,
and Figure 19 for the flowchart. Any commands issued during the Chip-Erase operation are ignored.
Word-Program Operation
The SST39WF400A is programmed on a word-by-word
basis. Before programming, the sector where the word
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load word address and word data. During the
Word-Program operation, the addresses are latched on the
falling edge of either CE# or WE#, whichever occurs last.
The data is latched on the rising edge of either CE# or
WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of
the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 40
µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks.
Any commands issued during the internal Program operation are ignored.
Write Operation Status Detection
The SST39WF400A provides two software means to
detect the completion of a write (Program or Erase) cycle,
in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both Reads are valid, then the
device has completed the Write cycle, otherwise the rejection is valid.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system
to erase the device on a sector-by-sector (or block-byblock) basis. The SST39WF400A offers both Sector-Erase
and Block-Erase mode. The sector architecture is based
on uniform sector size of 2 KWord. The Block-Erase mode
is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The Block-Erase
©2004 Silicon Storage Technology, Inc.
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4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
Data# Polling (DQ7)
Software Data Protection (SDP)
When the SST39WF400A is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is
completed, DQ7 will produce true data. Note that even
though DQ7 may have valid data immediately following the
completion of an internal Write operation, the remaining
data outputs may still be invalid: valid data on the entire
data bus will appear in subsequent successive Read
cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the
internal Erase operation is completed, DQ7 will produce a
‘1’. The Data# Polling is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
Data# Polling timing diagram and Figure 17 for a flowchart.
The SST39WF400A provides the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation
requires the inclusion of the three-byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. This group of devices are shipped with
the Software Data Protection permanently enabled. See
Table 4 for the specific software command codes. During
SDP command sequence, invalid commands will abort the
device to Read mode within TRC. The contents of DQ15DQ8 can be VIL or VIH, but no other value, during any SDP
command sequence.
Common Flash Memory Interface (CFI)
Toggle Bit (DQ6)
The SST39WF400A also contains the CFI information to
describe the characteristics of the device. In order to enter
the CFI Query mode, the system must write three-byte
sequence, same as Software ID Entry command with 98H
(CFI Query command) to address 5555H in the last byte
sequence. Once the device enters the CFI Query mode,
the system can read CFI data at the addresses given in
Tables 5 through 7. The system must write the CFI Exit
command to return to Read mode from the CFI Query
mode.
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s
and 0s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector-,
Block- or Chip-Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diagram and Figure 17 for a flowchart.
Data Protection
The SST39WF400A provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.0V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
©2004 Silicon Storage Technology, Inc.
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4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
Product Identification
Product Identification Mode Exit/
CFI Mode Exit
The Product Identification mode identifies the devices as
the SST39WF400A and manufacturer as SST. This mode
may be accessed by software operations. Users may use
the Software Product Identification operation to identify the
part (i.e., using the device ID) when using multiple
manufacturers in the same socket. For details, see Table 4
for software operation, Figure 11 for the Software ID Entry
and Read timing diagram, and Figure 18 for the Software
ID Entry command sequence flowchart.
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/
CFI Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command
codes, Figure 13 for timing waveform, and Figure 18 for a
flowchart.
TABLE 1: PRODUCT IDENTIFICATION TABLE
Manufacturer’s ID
Address
Data
0000H
00BFH
0001H
272FH
Device ID
SST39WF400A
T1.0 1220
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
Memory Address
SuperFlash
Memory
Address Buffer & Latches
Y-Decoder
CE#
OE#
I/O Buffers and Data Latches
Control Logic
WE#
DQ15 - DQ0
1220 B1.0
©2004 Silicon Storage Technology, Inc.
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4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
TOP VIEW (balls facing down)
SST39WF400A
6
A13
A12 A14 A15 A16
A9
A8
A10 A11 DQ7 DQ14 DQ13 DQ6
WE#
NC
NC
NC DQ5 DQ12 VDD DQ4
NC
NC
NC
NC DQ2 DQ10 DQ11 DQ3
A7
A17
A6
A5
A3
A4
A2
A1
A0
CE# OE# VSS
A
B
C
D
E
F
5
NC DQ15 VSS
3
2
DQ0 DQ8 DQ9 DQ1
1
G
1220 48-tfbga P01.0
4
H
FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL TFBGA
TOP VIEW (balls facing down)
SST39WF400A
6
A2
A4
A6
A17
A1
A3
A7
NC
A0
A5
NC
NC
NC
WE#
NC
A9
A11
NC
A10
A13
A14
A8
A12
A15
5
3
CE#
DQ8 DQ10
VSS
OE# DQ9
DQ4 DQ11 A16
2
NC
NC
DQ5 DQ6 DQ7
1
DQ0 DQ1 DQ2 DQ3
A
B
C
D
E
VDD DQ12 DQ13 DQ14 DQ15 VSS
F
G
H
J
K
1220 48-wfbga-xflga P03_4.0
4
L
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL WFBGA AND 48-BUMP XFLGA
©2004 Silicon Storage Technology, Inc.
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4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the
sector. During Block-Erase AMS-A15 address lines will select the block.
DQ15-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD
Power Supply
To provide power supply voltage:
VSS
Ground
NC
No Connection
1.65-1.95V for SST39WF400A
Unconnected pins.
T2.0 1220
1. AMS = Most significant address
AMS = A17 for SST39WF400A
TABLE 3: OPERATION MODES SELECTION
Mode
CE#
OE#
WE#
Read
Program
DQ
Address
VIL
VIL
VIL
VIH
VIH
DOUT
AIN
VIL
DIN
AIN
X1
Sector or Block address,
XXH for Chip-Erase
Erase
VIL
VIH
VIL
Standby
VIH
X
X
High Z
X
X
VIL
X
High Z/ DOUT
X
X
X
VIH
High Z/ DOUT
X
VIL
VIL
VIH
Write Inhibit
Product Identification
Software Mode
See Table 4
T3.0 1220
1. X can be VIL or VIH, but no other value.
©2004 Silicon Storage Technology, Inc.
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4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
Addr1
Data2
2nd Bus
Write Cycle
Addr1
Data2
3rd Bus
Write Cycle
Addr1
4th Bus
Write Cycle
Data2
Addr1
Data2
Data
AAH
Word-Program
5555H
AAH
2AAAH
55H
5555H
A0H
WA3
Sector-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
Data2
Addr1
Data2
2AAAH
55H
SAX4
30H
4
Block-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
BAX
Chip-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
Software ID Entry5,6 5555H
AAH
2AAAH
55H
5555H
90H
CFI Query Entry5
5555H
AAH
2AAAH
55H
5555H
98H
XXH
F0H
5555H
AAH
2AAAH
55H
5555H
F0H
Software ID
CFI Exit
Exit7/
Software ID Exit7/
CFI Exit
50H
10H
T4.0 1220
1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.
AMS = Most significant address
AMS = A17 for SST39WF400A
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence
3. WA = Program word address
4. SAX for Sector-Erase; uses AMS-A11 address lines
BAX for Block-Erase; uses AMS-A15 address lines
5. The device does not remain in Software Product ID mode if powered down.
6. With AMS-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0,
SST39WF400A Device ID = 272FH, is read with A0 = 1.
7. Both Software ID Exit operations are equivalent
TABLE 5: CFI QUERY IDENTIFICATION STRING1 FOR SST39WF400A
Address
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Data
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T5.0 1220
1. Refer to CFI publication 100 for more details.
©2004 Silicon Storage Technology, Inc.
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4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
TABLE 6: SYSTEM INTERFACE INFORMATION FOR SST39WF400A
Address
Data
1BH
0016H
VDD Min (Program/Erase)
Data
1CH
0020H
VDD Max (Program/Erase)
1DH
0000H
VPP min (00H = no VPP pin)
1EH
0000H
VPP max (00H = no VPP pin)
1FH
0005H
Typical time out for Word-Program 2N µs (25 = 32 µs)
20H
0000H
Typical time out for min size buffer program 2N µs (00H = not supported)
21H
0005H
Typical time out for individual Sector/Block-Erase 2N ms (25 = 32 ms)
22H
0007H
Typical time out for Chip-Erase 2N ms (27 = 128 ms)
23H
0001H
Maximum time out for Word-Program 2N times typical (21 x 25 = 64 µs)
24H
0000H
Maximum time out for buffer program 2N times typical
25H
0001H
Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 25 = 64 ms)
26H
0001H
Maximum time out for Chip-Erase 2N times typical (21 x 27 = 256 ms)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
T6.0 1220
TABLE 7: DEVICE GEOMETRY INFORMATION FOR SST39WF400A
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Data
0013H
0001H
0000H
0000H
0000H
0002H
007FH
0000H
0010H
0000H
0007H
0000H
0000H
0001H
Data
Device size = 2N Byte (13H = 19; 219 = 512 KByte)
Flash Device Interface description; 0001H = x16-only asynchronous interface
Maximum number of byte in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 127 + 1 = 128 sectors (007FH = 127)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 7 + 1 = 8 blocks (0007H = 7)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T7.0 1220
©2004 Silicon Storage Technology, Inc.
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4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 11V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Ambient Temp
VDD
0°C to +70°C
1.65-1.95V
-40°C to +85°C
1.65-1.95V
Commercial
Industrial
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 14 and 15
©2004 Silicon Storage Technology, Inc.
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4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
TABLE 8: DC OPERATING CHARACTERISTICS VDD = 1.65-1.95V1
Limits
Symbol
Parameter
IDD
Power Supply Current
Min
Max
Units
Test Conditions
Address input=VILT/VIHT, at f=5 MHz,
VDD=VDD Max
Read
15
mA
CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase
20
mA
CE#=WE#=VIL, OE#=VIH
ISB
Standby VDD Current
52
µA
CE#=VDD, VDD=VDD Max
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
1
µA
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
0.2VDD
0.8VDD
0.1
VDD-0.1
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
V
VDD=VDD Max
V
IOL=100 µA, VDD=VDD Min
V
IOH=-100 µA, VDD=VDD Min
T8.2 1220
1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C
(room temperature), and VDD = 1.8V. Not 100% tested.
2. 5 µA is the maximum ISB for all 39WF400A commercial grade devices. 20 µA is the maximum ISB for all 39WF400A industrial grade
devices. For all 39WF400A commercial and industrial devices, ISB typical is 1 µA.
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
Power-up to Program/Erase Operation
100
µs
TPU-WRITE
1
T9.0 1220
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: CAPACITANCE (Ta = 25°C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
Maximum
CI/O1
I/O Pin Capacitance
VI/O = 0V
12 pF
Input Capacitance
VIN = 0V
6 pF
CIN
1
T10.0 1220
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol
NEND
1,2
Parameter
Minimum Specification
Units
Endurance
10,000
Cycles
JEDEC Standard A117
100
Years
JEDEC Standard A103
100 + IDD
mA
JEDEC Standard 78
TDR1
Data Retention
ILTH1
Latch Up
Test Method
T11.0 1220
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2004 Silicon Storage Technology, Inc.
S71220-05-000
10
6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
AC CHARACTERISTICS
TABLE 12: READ CYCLE TIMING PARAMETERS
VDD = 1.70-1.95V FOR 90 NS1
VDD = 1.65-1.95V FOR 100 NS
SST39WF400A-90
Min
SST39WF400A-100
Symbol
Parameter
TRC
Read Cycle Time
Max
Min
TCE
Chip Enable Access Time
90
100
ns
TAA
Address Access Time
90
100
ns
TOE
Output Enable Access Time
TCLZ2
CE# Low to Active Output
0
TOLZ2
OE# Low to Active Output
0
TCHZ2
CE# High to High-Z Output
TOHZ2
TOH2
OE# High to High-Z Output
90
Max
ns
50
50
ns
0
ns
0
ns
40
40
40
Output Hold from Address Change
Units
100
ns
40
0
ns
0
ns
T12.2 1220
1. 90 ns parts will ONLY support voltage range 1.70-1.95V.
2. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
Parameter
Min
Max
Units
TBP
Word-Program Time
TAS
Address Setup Time
0
TAH
Address Hold Time
50
ns
TCS
WE# and CE# Setup Time
0
ns
TCH
WE# and CE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TCP
CE# Pulse Width
50
ns
TWP
WE# Pulse Width
50
ns
TWPH1
WE# Pulse Width High
30
ns
TCPH1
CE# Pulse Width High
30
ns
TDS
Data Setup Time
50
ns
TDH1
Data Hold Time
0
TIDA1
Software ID Access and Exit Time
150
ns
TSE
Sector-Erase
50
ms
TBE
Block-Erase
50
ms
TSCE
Chip-Erase
200
ms
40
µs
ns
ns
T13.0 1220
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
TRC
TAA
ADDRESS AMS-0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
HIGH-Z
DQ15-0
TCHZ
TOH
TCLZ
HIGH-Z
DATA VALID
DATA VALID
1220 F03.1
Note: AMS = Most significant address
AMS = A17 for SST39WF400A
FIGURE 3: READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
TAH
ADDRESS AMS-0
2AAA
5555
ADDR
TDH
TWP
WE#
TAS
TDS
TWPH
OE#
TCH
CE#
TCS
DQ15-0
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
1220 F04.1
Note: AMS = Most significant address
AMS = A17 for SST39WF400A
X can be VIL or VIH, but no other value.
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71220-05-000
12
6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
TAH
ADDRESS AMS-0
2AAA
5555
ADDR
TDH
TCP
CE#
TAS
TDS
TCPH
OE#
TCH
WE#
TCS
DQ15-0
XXAA
XX55
XXA0
DATA
SW0
SW1
SW2
WORD
(ADDR/DATA)
1220 F05.1
Note: AMS = Most significant address
AMS = A17 for SST39WF400A
X can be VIL or VIH, but no other value.
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0
TCE
CE#
TOES
TOEH
OE#
TOE
WE#
DQ7
DATA
DATA#
DATA#
DATA
1220 F06.1
Note: AMS = Most significant address
AMS = A17 for SST39WF400A
FIGURE 6: DATA# POLLING TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
ADDRESS AMS-0
TCE
CE#
TOES
TOE
TOEH
OE#
WE#
DQ6
TWO READ CYCLES
WITH SAME OUTPUTS
1220 F07.1
Note: AMS = Most significant address
AMS = A17 for SST39WF400A
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
TSCE
SIX-BYTE CODE FOR CHIP-ERASE
5555
ADDRESS AMS-0
2AAA
5555
5555
2AAA
5555
CE#
OE#
TWP
WE#
DQ15-0
XXAA
SW0
XX55
SW1
XX80
XXAA
SW2
SW3
XX55
SW4
XX10
SW5
1220 F08.1
Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
AMS = Most significant address
AMS = A17 for SST39WF400A
X can be VIL or VIH, but no other value.
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
TBE
SIX-BYTE CODE FOR BLOCK-ERASE
5555
ADDRESS AMS-0
2AAA
5555
5555
2AAA
BAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
SW0
XX55
XX80
SW1
XXAA
SW2
XX55
SW3
SW4
XX50
SW5
1220 F09.1
Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
AMS = Most significant address
AMS = A17 for SST39WF400A
X can be VIL or VIH, but no other value.
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
TSE
SIX-BYTE CODE FOR SECTOR-ERASE
5555
ADDRESS AMS-0
2AAA
5555
5555
2AAA
SAX
CE#
OE#
TWP
WE#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
SW0
SW1
SW2
SW3
SW4
SW5
1220 F10.1
Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
AMS = Most significant address
AMS = A17 for SST39WF400A
X can be VIL or VIH, but no other value.
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A14-0
5555
2AAA
5555
0000
0001
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
XXAA
SW0
XX55
TAA
00BF
XX90
SW1
SW2
Device ID
1220 F11.1
Note: Device ID = 272FH for SST39WF400A
X can be VIL or VIH, but no other value.
FIGURE 11: SOFTWARE ID ENTRY AND READ
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
5555
ADDRESS A14-0
2AAA
5555
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
XXAA
SW0
XX55
SW1
TAA
XX98
1220 F12.1
SW2
Note: X can be VIL or VIH, but no other value.
FIGURE 12: CFI QUERY ENTRY AND READ
©2004 Silicon Storage Technology, Inc.
S71220-05-000
16
6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
ADDRESS A14-0
DQ15-0
XXAA
2AAA
5555
XX55
XXF0
TIDA
CE#
OE#
TWP
WE#
T WHP
SW0
SW1
1220 F13.1
SW2
Note: X can be VIL or VIH, but no other value.
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
VIHT
INPUT
VIT
VOT
REFERENCE POINTS
OUTPUT
VILT
1220 F14.0
AC test inputs are driven at VIHT (VDD) for a logic “1” and VILT (VSS) for a logic “0”. Measurement reference points for
inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times are (10% ↔ 90%) <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
VDD
TO TESTER
25KΩ
TO DUT
CL
25KΩ
1220 F15.1
FIGURE 15: A TEST LOAD EXAMPLE
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
Start
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XXA0H
Address: 5555H
Load Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
Note:
X can be VIL or VIH, but no other value.
1220 F16.0
FIGURE 16: WORD-PROGRAM ALGORITHM
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Wait TBP,
TSCE, TSE
or TBE
Read word
Read DQ7
Read same
word
Program/Erase
Completed
No
Is DQ7 =
true data?
Yes
No
Does DQ6
match?
Program/Erase
Completed
Yes
Program/Erase
Completed
1220 F17.0
FIGURE 17: WAIT OPTIONS
©2004 Silicon Storage Technology, Inc.
S71220-05-000
20
6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
CFI Query Entry
Command Sequence
Software ID Entry
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Wait TIDA
Load data: XX98H
Address: 5555H
Load data: XX90H
Address: 5555H
Load data: XXF0H
Address: 5555H
Return to normal
operation
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Software ID
Return to normal
operation
1220 F18.0
Note:
X can be VIL or VIH, but no other value.
FIGURE 18: SOFTWARE ID/CFI COMMAND FLOWCHARTS
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
Chip-Erase
Command Sequence
Sector-Erase
Command Sequence
Block-Erase
Command Sequence
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XX80H
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XXAAH
Address: 5555H
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX55H
Address: 2AAAH
Load data: XX10H
Address: 5555H
Load data: XX30H
Address: SAX
Load data: XX50H
Address: BAX
Wait TSCE
Wait TSE
Wait TBE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
Note:
X can be VIL or VIH, but no other value.
1220 F19.0
FIGURE 19: ERASE COMMAND SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
PRODUCT ORDERING INFORMATION
SST
39 WF 400A
XX XX XXXX
- 90
- XXX
-
4C
XX
- B3K
- XXX
E
X
Environmental Attribute
E = non-Pb
Package Modifier
K = 48 leads or balls
Q = 48 balls or bumps (66 possible positions)
Package Type
B3 = TFBGA (0.8mm pitch, 6mm x 8mm)
C1 = XFLGA (0.5mm pitch, 4mm x 6mm)
M1 = WFBGA (0.5mm pitch, 4mm x 6mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
90 = 90 ns
100 = 100 ns
Device Density
400 = 4 Mbit
Voltage
W = 1.65-1.95V
Product Series
39 = Multi-Purpose Flash
Valid combinations for SST39WF400A
SST39WF400A-90-4C-B3K
SST39WF400A-90-4C-B3KE
SST39WF400A-90-4C-C1Q
SST39WF400A-90-4C-C1QE
SST39WF400A-90-4C-M1Q
SST39WF400A-90-4C-M1QE
SST39WF400A-90-4I-B3K
SST39WF400A-90-4I-B3KE
SST39WF400A-100-4I-B3K
SST39WF400A-100-4I-B3KE
SST39WF400A-90-4I-C1Q
SST39WF400A-90-4I-C1QE
SST39WF400A-100-4I-C1Q
SST39WF400A-100-4I-C1QE
SST39WF400A-90-4I-M1Q
SST39WF400A-90-4I-M1QE
SST39WF400A-100-4I-M1Q
SST39WF400A-100-4I-M1QE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
BOTTOM VIEW
8.00 ± 0.20
5.60
0.45 ± 0.05
(48X)
0.80
6
6
5
5
4.00
4
4
6.00 ± 0.20
3
3
2
2
1
1
0.80
A B C D E F G H
A1 CORNER
SIDE VIEW
H G F E D C B A
A1 CORNER
1.10 ± 0.10
0.12
SEATING PLANE
1mm
0.35 ± 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
48-tfbga-B3K-6x8-450mic-4
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04
4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
TOP VIEW
BOTTOM VIEW
6.00 ± 0.08
5.00
0.50
6
5
4
3
2
1
4.00 ± 0.08
6
5
4
3
2
1
2.50
0.50
A B C D E F G H J K L
L K J H G F E D C B A
4
A1 CORNER
DETAIL
0.32 ± 0.05
(48X)
A1 INDICATOR
0.63 ± 0.10
SIDE VIEW
0.08
SEATING PLANE
0.20 ± 0.06
Note:
1mm
1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
4. No ball is present in position A1; a gold-colored indicator is present.
48-wfbga-M1Q-4x6-32mic-5
5. Ball opening size is 0.29 mm (± 0.05 mm)
48-BALL VERY-VERY-THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (WFBGA) 4MM X 6MM
SST PACKAGE CODE: M1Q
TOP VIEW
BOTTOM VIEW
6.00 ± 0.08
5.00
0.50
6
5
4
3
2
1
4.00 ± 0.08
6
5
4
3
2
1
2.50
0.50
A B C D E F G H J K L
L K J H G F E D C B A
4
A1 CORNER
DETAIL
0.29 ± 0.05
(48X)
A1 INDICATOR
0.52 max.
0.473 nom.
SIDE VIEW
0.08
SEATING PLANE
1mm
0.04 + 0.025/ - 0.015
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-222, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.08 mm
48-xflga-C1Q-4x6-29mic-5
4. No bump is present in position A1; a gold-colored indicator is present.
48-BUMP EXTREMELY-THIN-PROFILE, FINE-PITCH LAND GRID ARRAY (XFLGA) 4MM X 6MM
SST PACKAGE CODE: C1Q
©2004 Silicon Storage Technology, Inc.
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4 Mbit Multi-Purpose Flash
SST39WF400A
Data Sheet
TABLE 14: REVISION HISTORY
Number
Description
Date
00
•
Initial release
Mar 2003
01
•
•
Added 90 ns speed parts
Output leakage current changed from 10 µA to 1 µA in Table 8 on page 10
Apr 2003
02
•
Removed “Typical” column from Table 8 on page 10
Jun 2003
03
•
Added 90 ns commercial temperature range MPNs for all packages
Oct 2003
04
•
•
2004 Data Book
Updated the B3K, M1Q, and C1Q package diagrams
Nov 2003
05
•
Added footnote to max ISB parameter in Table 8 on page 10
Jun 2004
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2004 Silicon Storage Technology, Inc.
S71220-05-000
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6/04