a
Energy Metering IC
With On-Chip Fault Detection
AD7751*
FEATURES
High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036
Less than 0.1% Error Over a Dynamic Range of 500 to 1
Supplies Average Real Power on the Frequency
Outputs F1 and F2
High-Frequency Output CF Is Intended for Calibration
and Supplies Instantaneous Real Power
Continuous Monitoring of the Phase and Neutral
Current Allows Fault Detection in Two-Wire
Distribution Systems
AD7751 Uses the Larger of the Two Currents (Phase
or Neutral) to Bill—Even During a Fault Condition
Two Logic Outputs (FAULT and REVP) Can be Used to
Indicate a Potential Miswiring or Fault Condition
Direct Drive for Electromechanical Counters and
Two-Phase Stepper Motors (F1 and F2)
A PGA in the Current Channel Allows the Use of Small
Values of Shunt and Burden Resistance
Proprietary ADCs and DSP Provide High Accuracy Over
Large Variations in Environmental Conditions and Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V ⴞ 8% (30 ppm/ⴗC Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low-Cost CMOS Process
GENERAL DESCRIPTION
The AD7751 is a high-accuracy fault-tolerant electrical energy
measurement IC that is intended for use with 2-wire distribution
systems. The part specifications surpass the accuracy requirements as quoted in the IEC1036 standard.
The only analog circuitry used in the AD7751 is in the ADCs
and reference circuit. All other signal processing (e.g., multiplication and filtering) is carried out in the digital domain. This
approach provides superior stability and accuracy over extremes
in environmental conditions and over time.
The AD7751 incorporates a novel fault detection scheme that
warns of fault conditions and allows the AD7751 to continue
accurate billing during a fault event. The AD7751 does this
by continuously monitoring both the phase and neutral (return) currents. A fault is indicated when these currents differ by
more than 12.5%. Billing is continued using the larger of the
two currents.
The AD7751 supplies average real power information on the
low-frequency outputs F1 and F2. These logic outputs may be
used to directly drive an electromechanical counter or interface
to an MCU. The CF logic output gives instantaneous real power
information. This output is intended to be used for calibration
purposes.
The AD7751 includes a power supply monitoring circuit on the
AVDD supply pin. The AD7751 will remain in a reset condition
until the supply voltage on AVDD reaches 4 V. If the supply falls
below 4 V, the AD7751 will also be reset and no pulses will be
issued on F1, F2, and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are matched whether the HPF in Channel 1 is
on or off. The AD7751 also has anticreep protection.
The AD7751 is available in 24-lead DIP and SSOP packages.
FUNCTIONAL BLOCK DIAGRAM
G0 G1
FAULT
AVDD AGND
AC/DC
DVDD DGND
AD7751
POWER
SUPPLY MONITOR
V1A
V1N
V1B
ADC
PGA
ⴛ1, ⴛ2, ⴛ8, ⴛ16
ADC
PGA
ⴛ1, ⴛ2, ⴛ8, ⴛ16
V2P
ADC
V2N
...110101...
SIGNAL
PROCESSING
BLOCK
A<>B
A
A>B
...110101... B
B>A
HPF
⌽
PHASE
CORRECTION
MULTIPLIER
LPF
...11011001...
4k⍀
2.5V
REFERENCE
DIGITAL-TO-FREQUENCY
CONVERTER
REFIN/OUT CLKIN CLKOUT SCF S0 S1 REVP CF F1 F2 RESET
*US Patent 5,745,323; 5,760,617; 5,862,069; 5,872,469.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD7751–SPECIFICATIONS1, 2
Parameter
ACCURACY3
Measurement Error1 on Channels 1 and 2
Gain = 1
Gain = 2
Gain = 8
Gain = 16
Phase Error1 Between Channels
V1 Phase Lead 37°
(PF = 0.8 Capacitive)
V1 Phase Lag 60°
(PF = 0.5 Inductive)
AC Power Supply Rejection1
Output Frequency Variation (CF)
DC Power Supply Rejection1
Output Frequency Variation (CF)
FAULT DETECTION1, 4
Fault Detection Threshold
Inactive i/p <> Active i/p
Input Swap Threshold
Inactive i/p > Active i/p
Accuracy Fault Mode Operation
V1A Active, V1B = AGND
V1B Active, V1A = AGND
Fault Detection Delay
Swap Delay
ANALOG INPUTS
Maximum Signal Levels
Input Impedance (DC)
Bandwidth
ADC Offset Error1
Gain Error1
Gain Error Match1
REFERENCE INPUT
REFIN/OUT Input Voltage Range
Input Impedance
Input Capacitance
ON-CHIP REFERENCE
Reference Error
Temperature Coefficient
CLKIN
Input Clock Frequency
LOGIC INPUTS5
SCF, S0, S1, AC/DC,
RESET, G0 and G1
Input High Voltage, V INH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
(AVDD = DVDD = 5 V ⴞ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN =
3.58 MHz, TMIN to TMAX = –40ⴗC to +85ⴗC)
A Version
B Version
Unit
Test Conditions/Comments
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
% Reading typ
% Reading typ
% Reading typ
% Reading typ
One Channel with Full-Scale Signal (±660 mV)
Over a Dynamic Range 500 to 1
Over a Dynamic Range 500 to 1
Over a Dynamic Range 500 to 1
Over a Dynamic Range 500 to 1
Line Frequency = 45 Hz to 55 Hz
± 0.1
± 0.1
Degrees(°) max
AC/DC = 0 and AC/DC = 1
± 0.1
± 0.1
Degrees(°) max
0.2
0.2
% Reading typ
± 0.3
± 0.3
% Reading typ
AC/DC = 0 and AC/DC = 1
AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0
V1 = 100 mV rms, V2 = 100 mV rms @ 50 Hz
Ripple on AVDD of 200 mV rms @ 100 Hz
AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0
V1 = 100 mV rms, V2 = 100 mV rms,
AVDD = DVDD = 5 V ± 250 mV
See Fault Detection Section
12.5
12.5
% typ
(V1A or V1B Active)
14
14
% of Active typ
(V1A or V1B Active)
0.1
0.1
3
3
0.1
0.1
3
3
% Reading typ
% Reading typ
Second typ
Second typ
Over a Dynamic Range 500 to 1
Over a Dynamic Range 500 to 1
±1
390
14
± 20
±4
±1
390
14
± 20
±4
V max
kΩ min
kHz typ
mV max
% Ideal typ
± 0.2
± 0.2
% Ideal typ
2.7
2.3
3.2
10
2.7
2.3
3.2
10
V max
V min
kΩ min
pF max
± 200
± 30
± 200
± 30
± 60
mV max
ppm/°C typ
ppm/°C max
4
1
4
1
MHz max
MHz min
2.4
0.8
±3
2.4
0.8
±3
V min
V max
µA max
10
10
pF max
See Analog Inputs Section
V1A, V1B, V1N, V2N and V2P to AGND
CLKIN = 3.58 MHz
CLKIN/256, CLKIN = 3.58 MHz
See Terminology and Performance Graphs
External 2.5 V Reference, Gain = 1,
V1 = V2 = 660 mV dc
External 2.5 V Reference
2.5 V + 8%
2.5 V – 8%
Nominal 2.5 V
Note All Specifications for CLKIN of 3.58 MHz
–2–
DVDD = 5 V ± 5%
DVDD = 5 V ± 5%
Typically 10 nA, VIN = 0 V to DVDD
REV. A
AD7751
Parameter
A Version
B Version
Unit
Test Conditions/Comments
4.5
4.5
V min
0.5
0.5
V max
4
4
V min
0.5
0.5
V max
ISOURCE = 5 mA
DVDD = 5 V
ISINK = 5 mA
DVDD = 5 V
4.75
5.25
4.75
5.25
3
2.5
4.75
5.25
4.75
5.25
3
2.5
V min
V max
V min
V max
mA max
mA max
For Specified Performance
5 V – 5%
5 V + 5%
5 V – 5%
5 V + 5%
Typically 2 mA
Typically 1.5 mA
4
LOGIC OUTPUTS
F1 and F2
Output High Voltage, V OH
ISOURCE = 10 mA
DVDD = 5 V
ISINK = 10 mA
DVDD = 5 V
Output Low Voltage, V OL
CF, FAULT, and REVP
Output High Voltage, V OH
Output Low Voltage, V OL
POWER SUPPLY
AVDD
DVDD
AIDD
DIDD
NOTES
1
See Terminology section for explanation of specifications.
2
See plots in Typical Performance Characteristics graphs.
3
See Fault Detection section of data sheet for explanation of fault detection functionality.
4
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2
Parameter
3
t1
t2
t3
t4 3
t5
t6
(AVDD = DVDD = 5 V ⴞ 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 3.58 MHz,
TMIN to TMAX = –40ⴗC to +85ⴗC)
A, B Versions
Unit
Test Conditions/Comments
275
See Table III
1/2 t2
90
See Table IV
CLKIN/4
ms
sec
sec
ms
sec
sec
F1 and F2 Pulsewidth (Logic Low)
Output Pulse Period. See Transfer Function Section
Time Between F1 Falling Edge and F2 Falling Edge
CF Pulsewidth (Logic High)
CF Pulse Period. See Transfer Function Section
Minimum Time Between F1 and F2 Pulse
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
2
See Figure 1.
3
The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs section.
Specifications subject to change without notice.
ORDERING GUIDE
t1
F1
.t 6
.t2
F2
.t 3
t4
.t 5
CF
Model
Package Description
AD7751AAN
AD7751AARS
AD7751ABRS
EVAL-AD7751EB
AD7751AAN-REF
Plastic DIP
Shrink Small Outline Package
Shrink Small Outline Package
AD7751 Evaluation Board
AD7751 Reference Design
PCB (See AN-563)
Figure 1. Timing Diagram for Frequency Outputs
REV. A
–3–
Package
Option
N-24
RS-24
RS-24
AD7751
ABSOLUTE MAXIMUM RATINGS*
24-Lead Plastic DIP, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering 10 sec) . . . . . . . . . . . 260°C
24-Lead SSOP, Power Dissipation . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 112°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
(TA = 25°C unless otherwise noted)
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to AVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND
V1A, V1B, V1N, V2P, and V2N . . . . . . . . . . –6 V to +6 V
Reference Input Voltage to AGND . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7751 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
TERMINOLOGY
The error associated with the energy measurement made by the
AD7751 is defined by the following formula:
Percentage Error =
True Energy
ESD SENSITIVE DEVICE
For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading obtained under the same
input signal levels. Any error introduced is expressed as a percentage of reading—see Measurement Error definition.
MEASUREMENT ERROR
Energy Registered by the AD7751 – True Energy
WARNING!
For the dc PSR measurement a reading at nominal supplies
(5 V) is taken. The supplies are then varied ± 5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.
× 100%
PHASE ERROR BETWEEN CHANNELS
The HPF (High-Pass Filter) in Channel 1 has a phase lead
response. To offset this phase response and equalize the phase
response between channels a phase correction network is also
placed in Channel 1. The phase correction network matches the
phase to within ± 0.1° over a range of 45 Hz to 65 Hz and ± 0.2°
over a range 40 Hz to 1 kHz (see Figures 10 and 11).
GAIN ERROR
The gain error of the AD7751 is defined as the difference between
the measured output frequency (minus the offset) and the ideal
output frequency. It is measured with a gain of 1 in Channel
V1A. The difference is expressed as a percentage of the ideal
frequency. The ideal frequency is obtained from the transfer
function—see Transfer Function section.
ADC OFFSET ERROR
This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND the ADCs still see an analog input signal of 1 mV to
10 mV. However, when the HPF is switched on the offset is
removed from the current channel and the power calculation is
not affected by this offset.
GAIN ERROR MATCH
The gain error match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 and a gain
of 2, 8, or 16. It is expressed as a percentage of the output
frequency obtained under a gain of 1. This gives the gain
error observed when the gain selection is changed from
1 to 2, 8, or 16.
POWER SUPPLY REJECTION
This quantifies the AD7751 measurement error as a percentage
of reading when the power supplies are varied.
–4–
REV. A
AD7751
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
DVDD
2
AC/DC
3
AVDD
4, 5
V1A, V1B
6
V1N
7, 8
V2N, V2P
9
RESET
10
REFIN/OUT
11
AGND
12
SCF
13, 14
S1, S0
15, 16
G1, G0
17
CLKIN
18
CLKOUT
19
FAULT
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the AD7751.
The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
High-Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (the current
channel). A Logic 1 on this pin enables the HPF. The associated phase response of this filter has
been internally compensated over a frequency range of 45 Hz to 1 kHz. The HPF filter should be
enabled in energy metering applications.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the AD7751.
The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made
to minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin
should be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs
with a maximum signal level of ± 660 mV with respect to Pin V1N for specified operation. The
maximum signal level at these pins is ± 1 V with respect to AGND. Both inputs have internal ESD
protection circuitry and an overvoltage of ± 6 V can also be sustained on these inputs without risk of
permanent damage.
Negative Input Pin for Differential Voltage Inputs V1A and V1B. The maximum signal level at this
pin is ± 1 V with respect to AGND. The input has internal ESD protection circuitry and in addition,
an overvoltage of ± 6 V can be sustained without risk of permanent damage. This input should be
directly connected to the burden resistor and held at a fixed potential, i.e., AGND. See Analog
Input section.
Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differential input pair. The maximum differential input voltage is ± 660 mV for specified operation. The
maximum signal level at these pins is ± 1 V with respect to AGND. Both inputs have internal ESD
protection circuitry and an overvoltage of ± 6 V can also be sustained on these inputs without risk of
permanent damage.
Reset Pin for the AD7751. A logic low on this pin will hold the ADCs and digital circuitry in a reset
condition. Bringing this pin logic low will clear the AD7751 internal registers.
Provides Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of
2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may also
be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 µF ceramic
capacitor and 100 nF ceramic capacitor.
Provides the Ground Reference for the Analog Circuitry in the AD7751, i.e., ADCs and Reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the
ground reference for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, etc. For good noise suppression the analog ground plane should only be connected to the digital
ground plane at one point. A star ground configuration will help to keep noisy digital return currents
away from the analog circuits.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration
output CF. Table IV shows how the calibration frequencies are selected.
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency
conversion. This offers the designer greater flexibility when designing the energy meter. See Selecting a Frequency for an Energy Meter Application section.
These logic inputs are used to select one of four possible gains for the analog inputs V1A and V1B.
The possible gains are 1, 2, 8 and 16. See Analog Input section.
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can
be connected across CLKIN and CLKOUT to provide a clock source for the AD7751. The clock
frequency for specified operation is 3.579545 MHz. Crystal load capacitors of between 22 pF
and 33 pF (ceramic) should be used with the gate oscillator circuit.
A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the AD7751. The CLKOUT pin can drive one CMOS load when an external clock is supplied
at CLKIN or by gate oscillator circuit.
This logic output will go active high when a fault condition occurs. A fault is defined as a condition
under which the signals on V1A and V1B differ by more than 12.5%. The logic output will be reset
to zero when a fault condition is no longer detected. See Fault Detection section.
REV. A
–5–
AD7751
Pin No.
Mnemonic
Description
20
REVP
21
DGND
22
CF
23, 24
F2, F1
This logic output will go logic high when negative power is detected, i.e., when the phase angle
between the voltage and current signals is greater that 90°. This output is not latched and will be
reset when positive power is once again detected. The output will go high or low at the same time as
a pulse is issued on CF.
This provides the ground reference for the digital circuitry in the AD7751, i.e., multiplier, filters
and digital-to-frequency converter. This pin should be tied to the analog ground plane of the PCB.
The digital ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical
and digital), MCUs and indicator LEDs. For good noise suppression the analog ground plane
should only be connected to the digital ground plane at one point, e.g., a star ground.
Calibration Frequency Logic Output. The CF logic output gives instantaneous real power information. This output is intended to be used for calibration purposes. Also see SCF pin description.
Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs
can be used to directly drive electromechanical counters and two-phase stepper motors. See Transfer
Function section.
PIN CONFIGURATION
DIP and SSOP Packages
1
24
F1
AC/DC 2
23
F2
3
22
CF
V1A 4
21
DGND
V1B 5
20
REVP
DVDD
AVDD
AD7751
TOP VIEW 19 FAULT
V2N 7 (Not to Scale) 18 CLKOUT
V1N 6
V2P 8
17
CLKIN
RESET 9
16
G0
REFIN/OUT 10
15
G1
AGND 11
14
S0
SCF 12
13
S1
–6–
REV. A
Typical Performance Characteristics–AD7751
0.50
0.40
0.60
PF = 1
GAIN = 16
0.40 ON-CHIP REFERENCE
PF = 1
GAIN = 1
ON-CHIP REFERENCE
0.30
ⴙ85ⴗC
0.20
ERROR – %
ERROR – %
0.20
0.10
+85ⴗC PF = 1
–40ⴗC
0.00
–0.10
ⴙ25ⴗC
–0.20
+25ⴗC PF = 1
0.00
–0.20
–0.40
–40ⴗC PF = 1
–0.30
–0.60
–0.40
–0.50
0.01
–0.80
0.10
1.00
AMPS
10.0
0.01
100
1
0.1
10
TPC 1. Error as a % of Reading (Gain = 1)
TPC 4. Error as a % of Reading (Gain = 16)
0.25
0.40
0.20
100
AMPS
PF = 0.5
GAIN = 1
0.30 ON-CHIP REFERENCE
PF = 1
GAIN = 2
ON-CHIP REFERENCE
+85ⴗC
0.20
+25ⴗC PF = 0.5
ERROR – %
ERROR – %
0.15
0.10
–40ⴗC
0.05
+25ⴗC
0.10
–40ⴗC PF = 0.5
0.00
–0.10
0.00
+85ⴗC PF = 0.5
+25ⴗC PF = 1
–0.20
–0.30
–0.05
0.01
0.1
1
10
0.01
100
1
0.1
10
100
AMPS
AMPS
TPC 5. Error as a % of Reading (PF = 0.5, Gain = 1)
TPC 2. Error as a % of Reading (Gain = 2)
0.30
0.20
0.15
0.20
PF = 0.5
GAIN = 2
ON-CHIP REFERENCE
+85ⴗC PF = 0.5
+85ⴗC
0.10
0.05
ERROR – %
ERROR – %
0.10
+25ⴗC
0.00
+25ⴗC PF = 1
0.00
–0.10
+25ⴗC PF = 0.5
–0.05
–40ⴗC PF = 0.5
–40ⴗC
–0.10
–0.15
–0.20
PF = 1
GAIN = 8
ON-CHIP REFERENCE
0.01
0.1
–0.30
1
10
0.01
100
1
10
100
TPC 6. Error as a % of Reading (PF = 0.5, Gain = 2)
TPC 3. Error as a % of Reading (Gain = 8)
REV. A
0.1
AMPS
AMPS
–7–
AD7751
0.30
0.20
PF = 1
GAIN = 8
0.20 EXTERNAL REFERENCE
+25ⴗC PF=1
0.10
+85ⴗC PF=0.5
0.10
–0.10
ERROR – %
ERROR – %
0.00
–0.20
+25ⴗC PF=0.5
–0.30
+25ⴗC
0.00
+85ⴗC
–0.10
–0.20
–0.40
–0.30
–0.50 PF = 0.5
GAIN = 8
–0.60 ON-CHIP REFERENCE
0.01
–40ⴗC PF=0.5
1
0.1
–40ⴗC
–0.40
10
0.01
100
0.1
1
10
100
AMPS
AMPS
TPC 7. Error as a % of Reading (PF = 0.5, Gain = 8)
TPC 10. Error as a % of Reading Over Temperature With
an External Reference (Gain = 8)
0.60
0.60
PF = 0.5
GAIN = 16
0.40 ON-CHIP REFERENCE
PF = 1
GAIN = 16
0.40 EXTERNAL REFERENCE
+85ⴗC PF = 0.5
+85ⴗC PF = 0.5
0.20
+25ⴗC PF = 1
0.00
ERROR – %
ERROR – %
0.20
+25ⴗC PF = 0.5
–0.20
–0.40
+25ⴗC PF = 1
0.00
–0.20
–0.40
–0.60
–40ⴗC PF = 0.5
–0.60
–0.80
–1.00
–40ⴗC PF = 1
–0.80
0.01
0.1
1
0.01
100
10
0.1
1
10
100
AMPS
AMPS
TPC 8. Error as a % of Reading (PF = 0.5, Gain = 16)
TPC 11. Error as a % of Reading Over Temperature With
an External Reference (Gain = 16)
0.20
PF = 1
0.15 GAIN = 2
EXTERNAL REFERENCE
+85ⴗC
0.10
ERROR – %
0.05
0.00
–0.05
+25ⴗC
–0.10
–0.15
–40ⴗC
–0.20
–0.25
–0.30
0.01
0.1
1
10
100
AMPS
TPC 9. Error as a % of Reading Over Temperature With
an External Reference (Gain = 2)
–8–
REV. A
AD7751
DISTRIBUTION
CHARACTERISTICS
NUMBER OF PTS: 138
MINIMUM: –11.1367
MAXIMUM: 10.1775
MEAN: –1.44576
STD DEV: 4.6670
GAIN = 1
TEMP = 25ⴗC
16
14
12
DISTRIBUTION
CHARACTERISTICS
NUMBER OF PTS: 138
MINIMUM: 4.37379
MAXIMUM: –5.08496
MEAN: 0.47494
STD DEV: 1.71819
GAIN = 16
TEMP = 25ⴗ C
35
30
25
10
20
8
15
6
10
4
5
2
0
0
ⴚ15
ⴚ10
ⴚ5
5
0
10
–15
15
TPC 12. Channel 1 Offset Distribution (Gain = 1)
18
15
–5
100nF
RB
1k⍀
33nF
33nF
RB
9
1k⍀
33nF
6
931⍀ 33nF
930k⍀
3
220V
931⍀
33nF
100nF
10F
AVDD AC/DC AVDD
V1A
F1
U1
AD7751
V1B
V1N
F2
CF
REVP
PS2501-1
FAULT
CLKOUT
V2N
G0
G1
ⴚ10
ⴚ5
0
5
10
REFIN/OUT
15
10F
GAIN
1
2
8
16
22pF
GAIN
SELECT
VDD
10k⍀
30
25
20
15
10
5
ⴚ15
ⴚ10
ⴚ5
0
5
10
RB
18.2⍀
8.2⍀
2.2⍀
0.68⍀
S1
SCF
RESET AGND DGND
100nF
100nF
100nF
VDD
TPC 16. Test Circuit for Performance Curves
DISTRIBUTION
CHARACTERISTICS
NUMBER OF PTS: 138
MINIMUM: –5.36107
MAXIMUM: 4.30413
MEAN: 0.346894
STD DEV: 1.86651
GAIN = 8
TEMP = 25ⴗC
35
100nF
15
TPC 14. Channel 1 Offset Distribution (Gain = 8)
–9–
K10
Y1
22pF
3.58MHz
CLKIN
V2P
K9
U3
S0
ⴚ15
TPC 13. Channel 1 Offset Distribution (Gain = 2)
REV. A
15
10
10F
12
0
5
VDD
40A TO
40mA
1k⍀
0
0
TPC 15. Channel 1 Offset Distribution (Gain = 16)
DISTRIBUTION
CHARACTERISTICS
NUMBER OF PTS: 138
MINIMUM: –7.01774
MAXIMUM: 6.65068
MEAN: –0.421358
STD DEV: 2.974
GAIN = 2
TEMP = 25ⴗC
21
–10
AD7751
THEORY OF OPERATION
The two ADCs digitize the voltage and current signals from the
current and voltage transducers. These ADCs are 16-bit second
order sigma-delta converters with an oversampling rate of 900 kHz.
This analog input structure greatly simplifies transducer interfacing
by providing a wide dynamic range for direct connection to the
transducer and also simplifying the antialiasing filter design. A
programmable gain stage in the current channel further facilitates easy transducer interfacing. A high-pass filter in the current
channel removes any dc component from the current signal.
This eliminates any inaccuracies in the real-power calculation
due to offsets in the voltage or current signals—see HPF and
Offset Effects section.
are sinusoidal, the real-power component of the instantaneous
power signal (i.e., the dc term) is given by:
V × I
× cos (60°)
2
This is the correct real-power calculation.
INSTANTANEOUS
POWER SIGNAL
CH1
PGA
ADC
VⴛI
p(t) = i(t)ⴛv(t)
WHERE:
v(t) = Vⴛcos(t)
i(t) = Iⴛcos(t)
p(t) = VⴛI {1+cos(2t)}
2
VⴛI
2
INSTANTANEOUS
POWER SIGNAL
⌺
INSTANTANEOUS
REAL-POWER SIGNAL
VⴛI
ⴛcos(60ⴗ)
2
0V
CURRENT
60ⴗ
Figure 3. DC Component of Instantaneous Power Signal
Conveys Real-Power Information PF < 1
DIGITAL-TOFREQUENCY
ADC
INSTANTANEOUS
POWER SIGNAL – p(t)
CURRENT
VOLTAGE
VOLTAGE
F1
F2
⌺
MULTIPLIER
CH2
0V
DIGITAL-TOFREQUENCY
LPF
INSTANTANEOUS
REAL-POWER SIGNAL
VⴛI
2
The real-power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by
a direct multiplication of the current and voltage signals. In
order to extract the real-power component (i.e., the dc component) the instantaneous power signal is low-pass filtered. Figure
2 illustrates the instantaneous real-power signal and shows how
the real-power information can be extracted by low-pass filtering
the instantaneous power signal. This scheme correctly calculates
real-power for nonsinusoidal current and voltage waveforms at all
power factors. All signal processing is carried out in the digital
domain for superior stability over temperature and time.
HPF
(1)
Nonsinusoidal Voltage and Current
CF
The real-power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current
waveforms in practical applications will have some harmonic
content. Using the Fourier Transform, instantaneous voltage
and current waveforms can be expressed in terms of their
harmonic content.
INSTANTANEOUS REALPOWER SIGNAL
VⴛI
2
∞
v (t ) = VO + 2 × ∑ Vh × sin( hωt + α h )
h ≠0
(2)
where:
TIME
v(t)
VO
Vh
and
␣h
Figure 2. Signal Processing Block Diagram
The low frequency output of the AD7751 is generated by
accumulating this real-power information. This low frequency
inherently means a long accumulation time between output
pulses. The output frequency is therefore proportional to the
average real-power. This average real-power information can in
turn be accumulated (e.g., by a counter) to generate real-energy
information. Because of its high output frequency and hence
shorter integration time, the CF output is proportional to the
instantaneous real-power. This is useful for system calibration
purposes that would take place under steady load conditions.
is the phase angle of the voltage harmonic.
∞
i (t ) = IO + 2 × ∑ I h × sin( hωt + βh )
h ≠0
(3)
where:
Power Factor Considerations
The method used to extract the real-power information from the
instantaneous power signal (i.e., by low-pass filtering) is still
valid even when the voltage and current signals are not in phase.
Figure 3 displays the unity power factor condition and a DPF
(Displacement Power Factor) = 0.5, i.e., current signal lagging
the voltage by 60°. If we assume the voltage and current waveforms
is the instantaneous voltage
is the average value
is the rms value of voltage harmonic h
i(t)
IO
Ih
is the instantaneous current
is the dc component
is the rms value of current harmonic h
h
is the phase angle of the current harmonic.
and
–10–
REV. A
AD7751
Using Equations 2 and 3, the real-power P can be expressed in
terms of its fundamental real power (P1) and harmonic real
power (PH).
P = P1 + PH
where:
P1 = V1 × I1 cos( φ1 )
(4)
φ1 = α1 – β1
∞
and
(5)
PH = ∑ Vh × Ih × cos(φh )
The analog inputs V1A, V1B, and V1N have the same maximum
signal level restrictions as V2P and V2N. However, Channel 1
has a programmable gain amplifier (PGA) with user-selectable
gains of 1, 2, 8, or 16—see Table I. These gains facilitate easy
transducer interfacing.
Figure 5 illustrates the maximum signal levels on V1A, V1B,
and V1N. The maximum differential voltage is ±660 mV divided
by the gain selection. Again, the differential voltage signal on the
inputs must be referenced to a common mode, e.g., AGND. The
maximum common-mode signal is ±100 mV as shown in Figure 5.
h ≠1
φh = α h – βh
As can be seen from Equation 5 above, a harmonic real-power
component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms.
The power factor calculation has previously been shown to be
accurate in the case of a pure sinusoid, therefore the harmonic
real power must also correctly account for power factor since it
is made up of a series of pure sinusoids.
V1A
V1A, V1B
DIFFERENTIAL INPUT A
ⴞ660mV/GAIN MAX PEAK
+660mV
GAIN
COMMON-MODE
ⴞ100mV MAX
V1
V1N
VCM
AGND
VCM
DIFFERENTIAL INPUT B
ⴞ660mV/GAIN MAX PEAK
V1
V1B
–660mV
GAIN
Note that the input bandwidth of the analog inputs is 14 kHz
with a master clock frequency of 3.5795 MHz.
Figure 5. Maximum Signal Levels, Channel 1
Table I.
ANALOG INPUTS
Channel V2 (Voltage Channel)
The output of the line voltage transducer is connected to the
AD7751 at this analog input. Channel V2 is a fully differential
voltage input. The maximum peak differential signal on Channel 2 is ± 660 mV. Figure 4 illustrates the maximum signal levels
that can be connected to the AD7751 Channel 2.
G1
G0
Gain
Maximum
Differential Signal
0
0
1
1
0
1
0
1
1
2
8
16
± 660 mV
± 330 mV
± 82 mV
± 41 mV
V2
Typical Connection Diagrams
+600mV
V2P
DIFFERENTIAL INPUT
ⴞ600mV MAX PEAK
VCM
COMMON-MODE
ⴞ100mV MAX
–600mV
V2
V2N
VCM
AGND
Figure 4. Maximum Signal Levels, Channel 2
Channel 2 must be driven from a common-mode voltage, i.e.,
the differential voltage signal on the input must be referenced to
a common mode (usually AGND). The analog inputs of the
AD7751 can be driven with common-mode voltages of up to
100 mV with respect to AGND. However, best results are
achieved using a common mode equal to AGND.
Figure 6 shows a typical connection diagram for Channel V1.
Here the analog inputs are being used to monitor both the
phase and neutral currents. Because of the large potential
difference between the phase and neutral, two CTs (current
transformers) must be used to provide the isolation. Notice
both CTs are referenced to AGND (analog ground), hence
the common-mode voltage is 0 V. The CT turns ratio and
burden resistor (Rb) are selected to give a peak differential
voltage of ± 660 mV/Gain.
IP
IN
The voltage outputs from the current transducers are connected
to the AD7751 here. Channel V1 has two voltage inputs, namely
V1A and V1B. These inputs are fully differential with respect to
V1N. However, at any one time only one is selected to perform
the power calculation—see Fault Detection section.
V1A
Rb
ⴞ660mV
GAIN
Cf
Rb
ⴞ660mV
GAIN
Cf
AGND
V1N
Channel V1 (Current Channel)
REV. A
Rf
CT
CT
Rf
V1B
PHASE NEUTRAL
Figure 6. Typical Connection for Channel 1
–11–
AD7751
Figure 7 shows two typical connections for Channel V2. The
first option uses a PT (Potential Transformer) to provide complete isolation from the mains voltage. In the second option the
AD7751 is biased around the neutral wire and a resistor divider
is used to provide a voltage signal that is proportional to the line
voltage. Adjusting the ratio of Ra and Rb is also a convenient
way of carrying out a gain calibration on the meter.
Rf
CT
V2P
Cf
ⴞ660mV
V2N
Rf
HPF and Offset Effects
Figure 9 shows the effect of offsets on the real-power calculation.
As can be seen from Figure 9, an offset on Channel 1 and Channel
2 will contribute a dc component after multiplication. Since this
dc component is extracted by the LPF and used to generate the
real-power information, the offsets will have contributed a constant
error to the real power calculation. This problem is easily avoided
by enabling the HPF (i.e., pin AC/DC is set logic high) in Channel
1. By removing the offset from at least 1 channel no error component can be generated at dc by the multiplication. Error terms
at cos(ωt) are removed by the LPF and the digital-to-frequency
conversion—see Digital-to- Frequency Conversion section.
Cf
AGND
(V cos(ωt ) +VOS ) × (I × cos(ωt ) + IOS ) =
PHASE NEUTRAL
Rb
VR
ⴞ660mV
V2P
Rf
PHASE NEUTRAL
V ×I
+ VOS × IOS + VOS × I × cos(ωt )
2
V ×I
+V × IOS × cos(ωt ) +
× cos(2ωt )
2
Cf
Ra
NOTE:
Ra
R f;
Rb + VR = R f
V2N
Cf
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REALPOWER CALCULATION
VOS ⴛ I OS
Figure 7. Typical Connections for Channel 2
VⴛI
2
POWER SUPPLY MONITOR
The AD7751 contains an on-chip power supply monitor. The
analog supply (AVDD) is continuously monitored by the AD7751.
If the supply is less than 4 V ± 5%, the AD7751 will be reset.
This is useful to ensure correct device start-up at power-up and
power-down. The power supply monitor has built-in hysteresis
and filtering. This gives a high degree of immunity to false
triggering due to noisy supplies.
As can be seen from Figure 8 the trigger level is nominally set
at 4 V. The tolerance on this trigger level is about ± 5%. The
power supply and decoupling for the part should be such that
the ripple at AVDD does not exceed 5 V ± 5% as specified for
normal operation.
AVDD
5V
4V
IOS ⴛ V
VOS ⴛ I
0
2
FREQUENCY – RAD/S
Figure 9. Effect of Channel Offsets on the Real Power
Calculation
The HPF in Channel 1 has an associated phase response that is
compensated for on-chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figures 10 and 11 show the phase-error between channels with the compensation network activated. The AD7751 is
phase compensated up to 1 kHz as shown. This will ensure correct
active harmonic power calculation even at low power factors.
0.30
0.25
0V
TIME
ACTIVE
PHASE – Degrees
INTERNAL
RESET
RESET
0.20
RESET
Figure 8. On-Chip Power Supply Monitor
0.15
0.10
0.05
0
–0.05
–0.10
0
100
200
300
400 500 600 700
FREQUENCY – Hz
800
900 1000
Figure 10. Phase Error Between Channels (0 Hz to 1 kHz)
–12–
REV. A
AD7751
This will remove any ripple. If CF is being used to measure energy,
e.g., in a microprocessor-based application, the CF output should
also be averaged to calculate power. However, if an energy
measurement is being made by counting pulses, no averaging is
required. Because the outputs F1 and F2 operate at a much
lower frequency, a lot more averaging of the instantaneous realpower signal is carried out. The result is a greatly attenuated
sinusoidal content and a virtually ripple-free frequency output.
0.30
0.25
PHASE – Degrees
0.20
0.15
0.10
0.05
DIGITAL-TOFREQUENCY
–0.05
45
50
55
60
FREQUENCY – Hz
65
TIME
MULTIPLIER
2
FREQUENCY – RAD/S
INSTANTANEOUS REAL-POWER SIGNAL
(FREQUENCY DOMAIN)
(6)
Figure 12. Real-Power-to-Frequency Conversion
FAULT DETECTION
The AD7751 incorporates a novel fault detection scheme that
warns of fault conditions and allows the AD7751 to continue
accurate billing during a fault event. The fault detection function is
designed to work over a line frequency of 45 Hz to 55 Hz. The
AD7751 does this by continuously monitoring both the phase
and neutral (return) currents. A fault is indicated when these
currents differ by more than 12.5%. However, even during a
fault the output pulse rate on F1 and F2 is generated using the
larger of the two currents. Because the AD7751 looks for a
difference between the signals on V1A and V1B, it is important
that both current transducers are closely matched.
On power-up the output pulse rate of the AD7751 is proportional
to the product of the signals on Channel V1A and Channel 2. If
there is a difference of greater than 12.5% between V1A and
V1B on power-up, the fault indicator (FAULT) will go active
after about one second. In addition, if V1B is greater than V1A
the AD7751 will select V1B as the input. The fault detection is
automatically disabled when the voltage signal on Channel 1 is less
than 0.5% of the full-scale input range. This will eliminate false
detection of a fault due to noise at light loads.
in the application. Where CF is used for calibration purposes,
the frequency should be averaged by the frequency counter.
REV. A
CF
TIME
0
As can be seen in the diagram, the frequency output CF is seen
to vary over time, even under steady load conditions. This frequency variation is primarily due to the cos(2ωt) component in
the instantaneous real-power signal. The output frequency on CF
can be up to 128 times higher than the frequency on F1 and F2.
This higher output frequency is generated by accumulating the
instantaneous real-power signal over a much shorter time while
converting it to a frequency. This shorter accumulation period
means less averaging of the cos(2ωt) component. As a consequence, some of this instantaneous power signal passes through
the digital-to-frequency conversion. This will not be a problem
CF
cos(2t)
ATTENUATED BY LPF
The magnitude response of the filter is given by:
Figure 12 shows the instantaneous real-power signal output of
LPF which still contains a significant amount of instantaneous
power information, i.e., cos(2ωt). This signal is then passed to
the digital-to-frequency converter where it is integrated (accumulated) over time in order to produce an output frequency. This
accumulation of the signal will suppress or average out any nondc components in the instantaneous real-power signal. The average
value of a sinusoidal signal is zero. Hence the frequency generated
by the AD7751 is proportional to the average real power. Figure
12 shows the digital-to-frequency conversion for steady load
conditions, i.e., constant voltage and current.
⌺
LPF TO EXTRACT
REAL POWER
(DC TERM)
VⴛI
2
As previously described, the digital output of the low-pass filter
after multiplication contains the real-power information. However,
since this LPF is not an ideal “brick wall” filter implementation,
the output signal also contains attenuated components at
the line frequency and its harmonics, i.e., cos(hωt) where
h = 1, 2, 3, . . . etc.
For a line frequency of 50 Hz, this would give an attenuation of
the 2 ω (100 Hz) component of approximately –22 dBs. The
dominating harmonic will be at twice the line frequency, i.e.,
cos(2ωt) and this is due to the instantaneous power signal.
DIGITAL-TOFREQUENCY
I
DIGITAL-TO-FREQUENCY CONVERSION
1
1 + ( f / 8.9 Hz )
LPF
70
Figure 11. Phase Error Between Channels (40 Hz to 70 Hz)
|H ( f )| =
F1
F2
⌺
V
FREQUENCY
–0.10
40
FREQUENCY
F1
0
–13–
AD7751
Fault with Active Input Greater than Inactive Input
Calibration Concerns
If V1A is the active current input (i.e., is being used for billing),
and the signal on V1B (inactive input) falls by more than 12.5%
of V1A, the fault indicator will go active. Both analog inputs are
filtered and averaged to prevent false triggering of this logic
output. As a consequence of the filtering, there is a time delay of
approximately one second on the logic output FAULT after the
fault event. The FAULT logic output is independent of any activity on outputs F1 or F2. Figure 13 illustrates one condition under
which FAULT becomes active. Since V1A is the active input and it
is still greater than V1B, billing is maintained on VIA, i.e., no swap
to the V1B input will occur. V1A remains the active input.
Typically, when a meter is being calibrated, the voltage and current
circuits are separated as shown in Figure 15. This means that
current will only pass through the phase or neutral circuit. Figure
15 shows current being passed through the phase circuit. This is
the preferred option since the AD7751 starts billing on the input
V1A on power-up. The phase circuit CT is connected to V1A in
the diagram. Since there is no current in the neutral circuit the
FAULT indicator will come on under these conditions. However,
this does not affect the accuracy of the calibration and can be
used as a means to test the functionality of the fault detection.
Ib
V1A
V1A
V1B
V1A
AGND
0V
A
FILTER
FAULT
AND
COMPARE
Rb
PHASE
V1A
AGND
TEST
CURRENT
V1N
V1B
Rf
CT
B
TO
MULTIPLIER
V1A
Cf
V1N
Rb
Ib
0V
Cf
NEUTRAL
V1B
CT
Rf
V1B
Cf
Ra
V1B < 87.5% OF V1A
Rb
Figure 13. Fault Conditions for Inactive Input Less than
Active Input
Figure 14 illustrates another fault condition. If V1A is the active
input (i.e., is being used for billing), and the voltage signal on
V1B (inactive input) becomes greater than 114% of V1A, the
FAULT indicator goes active and there is also a swap over to
the V1B input. The analog input V1B has now become the
active input. Again there is a time delay of about 1.2 second
associated with this swap. V1A will not swap back to being the
active channel until V1A becomes greater than 114% of V1B.
However, the FAULT indicator will become inactive as soon as
V1A is within 12.5% of V1B. This threshold eliminates potential chatter between V1A and V1B.
V1A
V1A
V1A
V1N
AGND
0V
A
FILTER
FAULT
AND
COMPARE
V1B
B
TO
MULTIPLIER
V1B
V1A < 87.5% OF V1B
OR
V1B > 114% OF V1A
Figure 14. Fault Conditions for Inactive Input Greater than
Active Input
VR
240Vrms
Fault with V1B Greater than V1A
V1B
V2P
V
Rf
NOTE:
Rf;
Ra
Rb + VR = Rf
V2N
Cf
Figure 15. Fault Conditions for Inactive Input Greater than
Active Input
If the neutral circuit is chosen for the current circuit in the arrangement shown in Figure 15, it may have implications for the
calibration accuracy. The AD7751 will power up with the V1A
input active as normal. However, since there is no current in the
phase circuit, the signal on V1A is zero. This will cause a FAULT
to be flagged and the active input to be swapped to V1B (Neutral).
The meter may be calibrated in this mode but the phase and
neutral CTs may differ slightly. Since under no-fault conditions all billing is carried out using the phase CT, the meter
should be calibrated using the phase circuit. Of course, both
phase and neutral circuits may be calibrated.
TRANSFER FUNCTION
Frequency Outputs F1 and F2
The AD7751 calculates the product of two voltage signals (on
Channel 1 and Channel 2) and then low-pass filters this product
to extract real-power information. This real-power information
is then converted to a frequency. The frequency information is
output on F1 and F2 in the form of active low pulses. The pulse
rate at these outputs is relatively low, e.g., 0.34 Hz maximum for
ac signals with S0 = S1 = 0 (see Table III). This means that the
frequency at these outputs is generated from real-power information accumulated over a relatively long period of time. The result is
an output frequency that is proportional to the average real
power. The averaging of the real-power signal is implicit to the
digital-to-frequency conversion. The output frequency or pulse
rate is related to the input voltage signals by the following equation.
Freq =
5.74 × V 1 × V 2 × Gain × F1– 4
VREF
–14–
(7)
2
REV. A
AD7751
where,
Table III.
Freq
= Output frequency on F1 and F2 (Hz)
V1
= Differential rms voltage signal on Channel 1 (volts)
S1
S0
Max Frequency
for DC Inputs (Hz)
Max Frequency
for AC Inputs (Hz)
V2
= Differential rms voltage signal on Channel 2 (volts)
0
0
1
1
0
1
0
1
0.68
1.36
2.72
5.44
0.34
0.68
1.36
2.72
Gain = 1, 2, 8, or 16, depending on the PGA gain selection
made using logic inputs G0 and G1
VREF
= The reference voltage (2.5 V ± 8%) (volts)
F1–4
= One of four possible frequencies selected by using the
logic inputs S0 and S1 (see Table II)
Frequency Output CF
The pulse output CF (Calibration Frequency) is intended for
use during calibration. The output pulse rate on CF can be up
to 128 times the pulse rate on F1 and F2. The lower the F1–4
frequency selected the higher the CF scaling. Table IV shows
how the two frequencies are related depending on the states of
the logic inputs S0, S1, and SCF. Because of its relatively high
pulse rate, the frequency at this logic output is proportional to
the instantaneous real power. As is the case with F1 and F2,
the frequency is derived from the output of the low-pass filter
after multiplication. However, because the output frequency is
high, this real-power information is accumulated over a much
shorter time. Hence less averaging is carried out in the digitalto-frequency conversion. With much less averaging of the realpower signal, the CF output is much more responsive to power
fluctuations (see Signal Processing Block in Figure 2).
Table II.
S1
S0
F1–4 (Hz)
XTAL/CLKIN*
0
0
0
1
1.7
3.4
3.579 MHz/221
3.579 MHz/220
1
1
0
1
6.8
13.6
3.579 MHz/219
3.579 MHz/218
*F1–4 are a binary fraction of the master clock and will thus vary if the specified
CLKIN frequency is altered.
Example 1
If full-scale differential dc voltages of +660 mV and –660 mV are
applied to V1 and V2 respectively (660 mV is the maximum
differential voltage that can be connected to Channel 1 and
Channel 2), the expected output frequency is calculated as follows.
Gain
F1–4
V1
V2
VREF
=
=
=
=
=
Table IV.
1, G0 = G1 = 0
1.7 Hz, S0 = S1 = 0
+660 mV dc = 0.66 volts (rms of dc = dc)
–660 mV dc = 0.66 volts (rms of dc = |dc|)
2.5 V (nominal reference value).
NOTE: If the on-chip reference is used, actual output frequencies
may vary from device to device due to reference tolerance of ± 8%.
5.74 × 0.66 × 0.66 × 1 × 1.7 Hz
= 0.68 Hz
2.52
Freq =
(8)
Example 2
In this example, if ac voltages of ± 660 mV peak are applied to
V1 and V2, the expected output frequency is calculated as follows.
Gain
F1–4
V1
V2
VREF
=
=
=
=
=
1, G0 = G1 = 0
1.7 Hz, S0 = S1 = 0
rms of 660 mV peak ac = 0.66/√2 volts
rms of 660 mV peak ac = 0.66/√2 volts
2.5 V (nominal reference value).
NOTE: If the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance
of ± 8%.
Freq =
5.74 × 0.66 × 0.66 × 1 × 1.7 Hz
2 × 2 × 2.52
= 0.34 Hz
SCF
S1
S0
F1–4
(Hz)
CF Max for AC Signals
(Hz)
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1.7
1.7
3.4
3.4
6.8
6.8
13.6
13.6
128 × F1, F2 = 43.52
64 × F1, F2 = 21.76
64 × F1, F2 = 43.52
32 × F1, F2 = 21.76
32 × F1, F2 = 43.52
16 × F1, F2 = 21.76
16 × F1, F2 = 43.52
8 × F1, F2 = 21.76
SELECTING A FREQUENCY FOR AN ENERGY METER
APPLICATION
As shown in Table II, the user can select one of four frequencies.
This frequency selection determines the maximum frequency on
F1 and F2. These outputs are intended to be used to drive the
energy register (electromechanical or other). Since only four
different output frequencies can be selected, the available frequency selection has been optimized for a meter constant of
100 imp/kWhr with a maximum current of between 10 A and
120 A. Table V shows the output frequency for several maximum currents (IMAX) with a line voltage of 220 V. In all cases
the meter constant is 100 imp/kWhr.
(9)
Table V.
As can be seen from these two example calculations, the maximum output frequency for ac inputs is always half of that for dc
input signals. Table III shows a complete listing of all maximum
output frequencies.
REV. A
–15–
IMAX
F1 and F2 (Hz)
12.5 A
25 A
40 A
60 A
80 A
120 A
0.076
0.153
0.244
0.367
0.489
0.733
AD7751
Table VI.
S1
S0
F1–4
Frequency on F1 and F2 –
CH1 and CH2
Half-Scale AC Inputs
0
0
1
1
0
1
0
1
1.7
3.4
6.8
13.6
0.085 Hz
0.17 Hz
0.34 Hz
0.68 Hz
The high-frequency CF output is intended to be used for
communications and calibration purposes. CF produces a
90-ms-wide active high pulse (t4) at a frequency that is proportional to active power. The CF output frequencies are given in
Table IV. As in the case of F1 and F2, if the period of CF (t5)
falls below 180 ms, the CF pulsewidth is set to half the period.
For example, if the CF frequency is 20 Hz, the CF pulsewidth
is 25 ms.
NO LOAD THRESHOLD
When selecting a suitable F1–4 frequency for a meter design, the
frequency output at IMAX (maximum load) with a meter constant
of 100 imp/kWhr should be compared with Column 4 of Table
VI. The frequency that is closest in Table VI will determine the
best choice of frequency (F1–4). For example if a meter with a
maximum current of 25 A is being designed, the output frequency
on F1 and F2, with a meter constant of 100 imp/kWhr, is 0.153 Hz
at 25 A and 220 V (from Table V). Looking at Table VI, the
closest frequency to 0.153 Hz in column four is 0.17 Hz. Therefore F2 (3.4 Hz—see Table II) is selected for this design.
Frequency Outputs
alternating low going pulses. The pulsewidth (t1) is set at 275
ms and the time between the falling edges of F1 and F2 (t3) is
approximately half the period of F1 (t2). If, however, the period
of F1 and F2 falls below 550 ms (1.81 Hz), the pulsewidth of
F1 and F2 is set to half of their period. The maximum output
frequencies for F1 and F2 are shown in Table III.
C01194–2.5–7/00 (rev. A)
The F1–4 frequencies allow complete coverage of this range of
output frequencies on F1 and F2. When designing an energy
meter, the nominal design voltage on Channel 2 (voltage) should
be set to half-scale to allow for calibration of the meter constant.
The current channel should also be no more than half-scale when
the meter sees maximum load. This will allow over-current signals
and signals with high crest factors to be accommodated. Table
VI shows the output frequency on F1 and F2 when both analog
inputs are half-scale. The frequencies listed in Table VI align
very well with those listed in Table V for maximum load.
The AD7751 also includes a “no load threshold” and “start-up
current” feature that will eliminate any creep effects in the
meter. The AD7751 is designed to issue a minimum output
frequency. Any load generating a frequency lower than this
minimum frequency will not cause a pulse to be issued on F1,
F2, or CF. The minimum output frequency is given as 0.0014%
of the full-scale output frequency for each of the F1–4 frequency
selections (see Table II). For example, an energy meter with a
meter constant of 100 imp/kWhr on F1, F2 using F2 (3.4 Hz),
the maximum output frequency at F1 or F2 would be 0.0014%
of 3.4 Hz or 4.76 × 10–5 Hz. This would be 3.05 × 10–3 Hz at
CF (64 × F1 Hz). In this example the no load threshold would be
equivalent to 1.7 W of load or a start-up current of 8 mA at 220 V.
Comparing this value to the IEC1036 specification, which states
that the meter must start up with a load equal to or less than
0.4% Ib. For a 5 A(Ib) meter 0.4% of Ib is equivalent to 20 mA.
Figure 1 shows a timing diagram for the various frequency
outputs. The outputs F1 and F2 are the low frequency outputs
that can be used to directly drive a stepper motor or electromechanical impulse counter. The F1 and F2 outputs provide two
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Shrink Small Outline Package
(RS-24)
0.328 (8.33)
0.318 (8.08)
1.275 (32.30)
1.125 (28.60)
24
13
12
1
0.280 (7.11)
0.240 (6.10)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210
(5.33)
MAX
0.200 (5.05)
0.125 (3.18)
0.150
(3.81)
MIN
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
PRINTED IN U.S.A.
24-Lead Plastic DIP
(N-24)
0.070 (1.77) SEATING
0.045 (1.15) PLANE
24
0.325 (8.25)
0.300 (7.62)
13
0.311 (7.9)
0.301 (7.64)
0.195 (4.95)
0.115 (2.93)
0.212 (5.38)
0.205 (5.207)
1
0.015 (0.381)
0.008 (0.204)
0.078 (1.98) PIN 1
0.068 (1.73)
0.008 (0.203) 0.0256
(0.65)
0.002 (0.050) BSC
–16–
12
0.07 (1.78)
0.066 (1.67)
8°
0.015 (0.38)
0°
SEATING 0.009 (0.229)
0.010 (0.25) PLANE
0.005 (0.127)
0.037 (0.94)
0.022 (0.559)
REV. A