19-5159; Rev 0; 8/10 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor Features The MAX1358B smart data-acquisition system (DAS) is based on a 16-bit, sigma-delta analog-to-digital converter (ADC) and system-support functionality for a microprocessor (µP)-based system. This device integrates an ADC, DACs, operational amplifiers, internal selectable-voltage reference, temperature sensors, analog switches, a 32kHz oscillator, a real-time clock (RTC) with alarm, a high-frequency-locked loop (FLL) clock, four user-programmable I/Os, an interrupt generator, and 1.8V and 2.7V voltage monitors in a single chip. The MAX1358B has dual 10:1 differential input multiplexers (muxes) that accept signal levels from 0 to AVDD. An on-chip 1x to 8x programmable-gain amplifier (PGA) allows measuring low-level signals and reduces external circuitry required. o +1.8V to +3.6V Single-Supply Operation o Multichannel, 16-Bit, Sigma-Delta ADC 10sps to 477sps Programmable Conversion Rate Self- and System Offset and Gain Calibration PGA with Gains of 1, 2, 4, or 8 Unipolar and Bipolar Modes 10-Input Differential Multiplexer o 10-Bit Force-Sense DACs o Uncommitted Op Amps o Dual SPDT and SPST Analog Switches o Selectable References 1.25V, 2.048V, and 2.5V o Internal Charge Pump o System Support RTC and Alarm Register Internal/External Temperature Sensor Internal Oscillator with Clock Output User-Programmable I/O and Interrupt Generator VDD Monitors o SPI/QSPI/MICROWIRE, 4-Wire Serial Interface o Space-Saving (6mm x 6mm x 0.8mm), 40-Pin TQFN Package TEMP RANGE 0°C to +70°C -40°C to +85°C IN1- IN1+ AVDD SWB Industrial Control FBB OUTB TOP VIEW SWA Pin Configuration Electrochemical and Optical Sensors Medical Instruments PIN-PACKAGE 40 TQFN-EP* 40 TQFN-EP* +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. FBA Battery-Powered and Portable Devices PART MAX1358BCTL+ MAX1358BETL+ OUTA Applications Ordering Information AGND The MAX1358B operates from a single +1.8V to +3.6V supply and consumes only 1.15mA in normal mode and only 3µA in sleep mode. The MAX1358B has two DACs with one uncommitted op amp. The serial interface is compatible with either SPI™/QSPI™ or MICROWIRE™, and is used to power up, configure, and check the status of all functional blocks. The MAX1358B is available in a space-saving, 40-pin TQFN package and is specified over the commercial (0°C to +70°C) and the extended (-40°C to +85°C) temperature ranges. 30 29 28 27 26 25 24 23 22 21 Data-Acquisition Systems 31 20 32 19 SNC2 REF 33 18 SCM2 REG 34 17 SNO2 CF- 35 16 SNC1 CF+ 36 15 SCM1 CPOUT 37 14 SNO1 DVDD 38 13 32KIN DGND 39 12 32KOUT UPIO1 40 11 RESET *EXPOSED PAD. MAX1358B *EP UPIO3 UPIO4 6 7 8 9 10 CLK32K CLK 5 INT 4 CS 3 DIN 2 SCLK 1 UPIO2 + DOUT SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. OUT1 AIN2 AIN1 TQFN ________________________________________________________________ Maxim Integrated Products 1 For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX1358B General Description MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor ABSOLUTE MAXIMUM RATINGS Continuous Current Into Any Pin.........................................50mA Continuous Power Dissipation (TA = +70°C) 40-Pin TQFN (derate 25.6mW/°C above +70°C) ....2051.3mW Operating Temperature Range MAX1358BCTL+ .................................................0°C to +70°C MAX1358BETL+ ..............................................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Soldering Temperature (reflow) .......................................+260°C AVDD to AGND .........................................................-0.3V to +4V DVDD to DGND.........................................................-0.3V to +4V AVDD to DVDD ............................................................-4V to +4V AGND to DGND.....................................................-0.3V to +0.3V CLK32K to DGND ....................................-0.3V to (DVDD + 0.3V) UPIO_ to DGND........................................................-0.3V to +4V Digital Inputs to DGND ............................................-0.3V to +4V Analog Inputs to AGND ...........................-0.3V to (AVDD + 0.3V) Digital Output to DGND…........................-0.3V to (DVDD + 0.3V) Analog Outputs to AGND.........................-0.3V to (AVDD + 0.3V) CPOUT........................................................(DVDD - 0.3V) to +4V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, fCLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER ADC DC ACCURACY SYMBOL CONDITIONS MIN Noise-Free Resolution Data rate = 10sps, PGA gain = 2; data rate = 10sps to 60sps, PGA gain = 1; no missing codes, Table 1 (Note 2) 16 Conversion Rate No missing codes, Table 1 10 TYP 477 No missing codes Table 1 Integral Nonlinearity Unipolar mode, AVDD = 3V, PGA gain = 1, data rate = 40sps ±0.0046 Uncalibrated Unipolar Offset Error or Bipolar Zero Error (Note 3) %FSR ±0.003 Bipolar 1 Unipolar 1 %FSR µV/°C Uncalibrated Gain Error (Notes 3, 5) PGA = 1, calibrated, data rate = 10sps Gain-Error Temperature Coefficient DC Positive Power-Supply Rejection Ratio sps ±1.0 PGA gain = 1, calibrated, TA = +25°C, data rate = 10sps Unipolar Offset-Error or Bipolar Zero-Error Temperature Drift (Note 4) UNITS Bits Output Noise INL MAX ±0.6 ±0.003 %FSR (Notes 4, 6) 2 ppm/ °C PSRR PGA gain = 1, unipolar mode, measured by full-scale error with AVDD = 1.8V to 3.6V 85 dB CMRR PGA gain = 1, unipolar mode 85 dB ADC ANALOG INPUTS (AIN1, AIN2) DC Input Common-Mode Rejection Ratio 2 _______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor (AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, fCLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Normal-Mode 60Hz Rejection Ratio PGA gain = 1, unipolar mode, data rate = 40sps (Note 2) 100 dB Normal-Mode 50Hz Rejection Ratio Data rate = 10sps or 40sps, PGA gain = 1, unipolar mode (Note 2) 100 dB Absolute Input Range VAGND AVDD Unipolar mode -0.05/ Gain VREF/ Gain Bipolar mode -VREF/ Gain VREF/ Gain Differential Input Range ADC not in measurement mode, mux enabled, TA +55°C, inputs = +0.1V to (AVDD - 0.1V) DC Input Current (Note 7) ±1 Input Sampling Rate V nA ±5 TA = +85°C Input Sampling Capacitance V CIN 5 pF f SAMPLE 21.94 Table kHz External Source Impedance at Input FORCE-SENSE DAC (RL = 10k and CL = 200pF, FBA = OUTA, unless otherwise noted) Resolution Guaranteed monotonic 10 Bits Differential Nonlinearity DNL Code 3D hex to 3FF hex ±1 LSB Integral Nonlinearity INL Code 3D hex to 3FF hex ±4 LSB Offset Error ±20 Reference to code 52 hex Offset-Error Tempco 5 Gain Error ±5 Excludes offset and voltage reference error Gain-Error Tempco Excludes offset and reference drift Input Leakage Current at SWA/B Switches open (Notes 7, 8) Input Leakage Current at FBA/B VFBA = +0.3V to (AVDD - 0.3V) (Note 7) ppm/°C nA ±1 nA TA = 0°C to +70°C ±600 ±400 DAC buffer disabled (Note 7) Input Common-Mode Voltage At FBA Line Regulation AVDD = +1.8V to +3.6V, TA = +25°C Load Regulation I OUT = ±2mA, CL = 1000pF 0 40 VAGND LSB ±1 TA = 0°C to +50°C DAC Output Buffer Leakage Current Output Voltage Range 5.6 TA = -40°C to +85°C mV µV/°C pA ±75 nA AVDD 0.35 V 175 µV/V 0.5 µV/µA AVDD V _______________________________________________________________________________________ 3 MAX1358B ELECTRICAL CHARACTERISTICS (continued) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, fCLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Slew Rate 52 hex to 3FF hex code swing rising or falling, RL = 10k, CL = 100pF 50 V/ms Output-Voltage Settling Time 10% to 90% rising or falling to ±0.5 LSB 65 µs Input-Voltage Noise Referred to FBA, excludes reference noise Output Short-Circuit Current f = 0.1Hz to 10Hz 40 f = 10Hz to 10kHz 100 µVP-P OUTA shorted to AGND 20 OUTA shorted to AVDD 18 Input-Output SWA/SWB Switch Resistance Between SW_ and OUT_, HFCLK enabled SWA/SWB Switch Turn-On/Off Time HFCLK enabled Power-On Time Excluding reference mA 150 100 ns 12 µs EXTERNAL REFERENCE (REF) Input Voltage Range VAGND Input Resistance DAC on, internal REF and ADC off DC Input Leakage Current Internal REF, DAC, and ADC off (Note 7) AVDD 2.5 V M 100 nA INTERNAL VOLTAGE REFERENCE (CREF = 4.7µF) Reference Output Voltage VREF Output-Voltage Temperature Coefficient (Note 7) TC Output Short-Circuit Current IRSC AVDD +1.8V, TA = +25°C 1.213 1.25 1.288 AVDD +2.2V, TA = +25°C 1.987 2.048 2.109 AVDD +2.7V, TA = +25°C 2.425 2.5 2.575 TA = -40°C to +85°C 25 TA = 0°C to +70°C 13 REF shorted to AGND 65 mA REF shorted to AVDD 90 µA 25 µV/V Line Regulation Load Regulation 4 V TA = +25°C, VREF = 1.25V I SOURCE = 0 to 500µA I SINK = 0 to 50µA ppm/oC 1.2 1.7 _______________________________________________________________________________________ µV/µA 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor (AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, fCLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL Long-Term Stability CONDITIONS MIN (Note 9) TYP MAX UNITS ppm/ 1000hrs 150 f = 0.1Hz to 10Hz, AVDD = 3V 50 f = 10Hz to 10kHz, AVDD = 3V 200 Buffer only, settle to 0.1% of final value 100 µs Temperature Measurement Resolution 10sps 0.11 °C/LSB Internal Temperature-Sensor Measurement Error (Note 10) External voltage reference, twocurrent method Output Noise Voltage Turn-On Settling Time µVP-P TEMPERATURE SENSOR External Temperature-Sensor Measurement Error (Note 11) ±0.5 TA = 0°C to +50°C °C ±1 TA = -40oC to +85°C TA = +25°C ±0.5 TA = 0°C to +50°C ±0.5 °C ±1.0 TA = -40°C to +85°C Temperature Measurement Noise 0.18 °CRMS Temperature Measurement Power-Supply Rejection Ratio 0.2 °C/V OP AMP Input Offset Voltage VOS ±1 VCM = 0.5V Offset-Error Tempco IN1+ IBIAS ±1 TA = 0°C to +70°C 4 ±300 TA = 0°C to +50°C 2 ±200 0.025 ±1 20 ±600 TA = -40°C to +85°C IN1- TA = 0°C to +70°C ±400 TA = 0°C to +50°C Input Offset Current IOS Input Common-Mode Voltage Range VIN1_ = +0.3V to (AVDD - 0.3V) (Note 7) CMVR 0 0 ≤ VCM ≤ 75mV Common-Mode Rejection Ratio CMRR 75mV < VCM ≤ AVDD - 0.5V, TA = +25°C AVDD - 0.5V ≤ VCM ≤ AVDD - 0.35V mV µV/oC 0.006 TA = -40°C to +85°C Input Bias Current (Note 7) ±15 6.2 nA pA nA pA ±1 nA AVDD 0.35 V 60 60 75 dB 75 _______________________________________________________________________________________ 5 MAX1358B ELECTRICAL CHARACTERISTICS (continued) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, fCLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS Power-Supply Rejection Ratio PSRR AVDD = +1.8V to +3.6V, TA = +25°C Large-Signal Voltage Gain AVOL 100mV VOUT_ AVDD - 100mV (Note 12) Sourcing Output-Voltage Drop MIN TYP 76.5 100 90 116 Sinking GBW Phase Margin Output Slew Rate SR ISOURCE = 50µA 0.025 ISOURCE = 100µA 0.05 ISOURCE = 500µA 0.25 0.5 ISINK = 10µA 0.005 ISINK = 50µA 0.025 ISINK = 100µA 0.05 ISINK = 500µA 0.25 Output Short-Circuit Current V 0.5 Unity-gain configuration, CL = 1nF 80 kHz Unity-gain configuration, CL = 1nF (Note 12) 60 Degrees 0.05 V/µs CL = 200pF Unity-gain configuration Input-Voltage Noise dB 0.005 ISINK = 2mA Gain Bandwidth Product UNITS dB ISOURCE = 10µA ISOURCE = 2mA VOUT MAX f = 0.1Hz to 10Hz 50 f = 10Hz to 10kHz 100 VOUT_ shorted to AGND 20 VOUT_ shorted to AVDD 18 Power-On Time µVP-P mA 12 µs SPDT SWITCHES (SNO_, SNC_, SCM_, HFCLK enabled) On-Resistance SNO_, SNC_ Off-Leakage Current RON ISNO_(OFF) ISNC_(OFF) VSCM_ = 0V TA = 0°C to +50°C 45 VSCM_ = 0.5V TA = 0°C to +50°C 50 VSCM_ = 0.5V to AVDD TA = -40°C to +85°C 150 VSNO_, VSNC_ = +0.5V, TA = -40°C to +85°C +1.5V; VSCM_ = +1.5V, TA = 0°C to +70°C +0.5V (Note 7) TA = 0°C to +50°C ±600 SCM_ Off-Leakage Current VSNO_, VSNC_ = +0.5V, TA = -40°C to +85°C ISCM_(OFF) +1.5V; VSCM_ = +1.5V, TA = 0°C to +70°C +0.5V (Note 7) TA = 0°C to +50°C SCM_ On-Leakage Current VSNO_, VSNC_ = +0.5V, TA = -40°C to +85°C +1.5V, or unconnected; TA = 0°C to +70°C VSCM_ = +1.5V, +0.5V TA = 0°C to +50°C (Note 7) ISCM_(ON) Input Voltage Range Turn-On/Off Time 6 ±1 ±400 Break-before-make nA pA ±2 ±1.2 nA ±0.8 ±2 ±1.2 nA ±0.8 VAGND tON/tOFF AVDD 100 _______________________________________________________________________________________ V ns 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor (AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, fCLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN SNO_, SNC_, or SCM_ = AVDD or AGND; switch connected to enabled mux input Input Capacitance TYP MAX 2.5 UNITS pF CHARGE PUMP Maximum Output Current Output Voltage IOUT 10 No load 3.2 IOUT = 10mA 3.0 Output-Voltage Ripple IOUT = 10mA, excluding ESR of external capacitor Load Regulation IOUT = 10mA, excluding ESR of external capacitor REG Input Voltage Range Internal linear regulator disabled REG Input Current Linear regulator off, charge pump off CPOUT Input Voltage Range Charge pump disabled CPOUT Input Leakage Current Charge pump disabled mA 3.3 15 1.6 3.6 50 mVP-P 20 mV/mA 1.8 3 1.8 V V nA 3.6 2 V nA SIGNAL-DETECT COMPARATOR Differential Input-Detection Threshold Voltage TSEL[2:0] = 0 hex 0 TSEL[2:0] = 4 hex 50 TSEL[2:0] = 5 hex 100 TSEL[2:0] = 6 hex 150 TSEL[2:0] = 7 hex 200 Differential Input-Detection Threshold Error mV ±10 Common-Mode Input Voltage Range VAGND Turn-On Time mV AVDD 45 V µs VOLTAGE MONITORS DVDD Monitor Supply Voltage Range For valid reset Trip Threshold (DVDD Falling) 1.80 DVDD Monitor Timeout Reset Period DVDD Monitor Hysteresis 1.4 1.85 1.5 HYSE bit set to logic 1 225 HYSE bit set to logic 0 40 3.6 V 1.95 V s mV _______________________________________________________________________________________ 7 MAX1358B ELECTRICAL CHARACTERISTICS (continued) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, fCLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN DVDD Monitor Turn-On Time TYP MAX 5 CPOUT Monitor Supply Voltage Range 1.4 CPOUT Monitor Trip Threshold 2.7 ms 3.6 2.8 UNITS 2.9 V V CPOUT Monitor Hysteresis 35 mV CPOUT Monitor Turn-On Time 5 ms Internal Power-On Reset Voltage 1.7 V 32kHz OSCILLATOR (32KIN, 32KOUT) Clock Frequency DVDD = 2.7V Stability DVDD = 1.8V to 3.6V, excluding crystal Oscillator Startup Time Crystal Load Capacitance 32.768 kHz 25 ppm 1500 ms 6 pF 32.768 kHz LOW-FREQUENCY CLOCK INPUT/OUTPUT (CLK32K) Output Clock Frequency Absolute Input to Output Clock Jitter Cycle to cycle 5 ns Input to Output Rise/Fall Time 10% to 90%, 30pF load 5 ns Input Duty Cycle 40 Output Duty Cycle 60 54 % % HIGH-FREQUENCY CLOCK OUTPUT (CLK) FLL Output Clock Frequency Absolute Clock Jitter Rise and Fall Time tR/tF Duty Cycle Uncalibrated CLK Frequency Error fOUT = fFLL 4.8660 4.9152 4.9644 fOUT = fFLL/2, power-up default 2.4330 2.4576 2.4822 fOUT = fFLL/4 1.2165 1.2288 1.2411 fOUT = fFLL/8 608.25 614.4 620.54 Cycle to cycle, FLL off 0.1 Cycle to cycle, FLL on 0.5 10% to 90%, 30pF load kHz ns 10 fOUT = 4.9152MHz 40 60 fOUT = 2.4576MHz, 1.2288MHz, 614.4kHz 45 55 ±35 FLL calibration not performed MHz ns % % DIGITAL INPUTS (SCLK, DIN, CS, UPIO_, CLK32K) Input High Voltage VIH Input Low Voltage VIL 8 0.7 x DVDD _______________________________________________________________________________________ V 0.3 x DVDD V 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor (AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, fCLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS DVDD supply voltage UPIO_ Input High Voltage CPOUT supply voltage MIN TYP 0.7 x DVDD V 0.3 x DVDD UPIO_ Input Low Voltage VHYS IIN VCPOUT DVDD = 3.0V 200 ±0.01 VIN = VDGND or DVDD (Note 7) Input Capacitance VIN = VDGND or DVDD UPIO_ Input Current VIN = DVDD or VCPOUT or 0V, pullup disabled VIN = 0V, pullup enabled, unconnected UPIO_ inputs are pulled up to DVDD or CPOUT with pullup enabled mV ±100 4 ±0.01 VIN = DVDD or VCPOUT, pullup enabled UPIO_ Pullup Current V 0.3 x CPOUT supply voltage Input Current UNITS 0.7 x VCPOUT DVDD supply voltage Input Hysteresis MAX pF 1 1 0.1 2 nA µA 5 µA 0.4 V DIGITAL OUTPUTS (DOUT, RESET, UPIO_, CLK32K, INT, CLK) Output Low Voltage VOL ISINK = 1mA Output High Voltage VOH ISOURCE = 500µA DOUT Three-State Leakage Current DOUT Three-State Output Capacitance RESET Output Low Voltage UPIO_ Output High Voltage V IL ±0.01 COUT 4.5 VOL RESET Output Leakage Current UPIO_ Output Low Voltage 0.8 x DVDD VOL VOH ±1 µA pF ISINK = 1mA 0.4 V Open-drain output, RESET deasserted (Note 7) 0.1 µA ISINK = 1mA, UPIO_ referenced to DVDD 0.4 ISINK = 4mA, UPIO_ referenced to CPOUT 0.4 ISOURCE = 500µA, UPIO_ referenced to DVDD ISOURCE = 4mA, UPIO_ referenced to CPOUT 0.8 x DVDD V V VCPOUT - 0.4 POWER REQUIREMENT Analog Supply Voltage Range AVDD 1.8 3.6 V Digital Supply Voltage Range DVDD 1.8 3.6 V _______________________________________________________________________________________ 9 MAX1358B ELECTRICAL CHARACTERISTICS (continued) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +1.8V to +3.6V, VREF = +1.25V, external reference, fCLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS IMAX Everything on, charge pump unloaded, no digital AVDD = DVDD = 3.6V pins, sinking/sourcing current, e.g., RST, UPIO_, and CLK32K, max internal tempsensor current, clock AVDD = DVDD = 2.7V output buffers unloaded, ADC at 477sps Total Supply Current INORMAL Sleep-Mode Supply Current (IAVDD + IDVDD) Shutdown Supply Current (IAVDD + IDVDD) All on except charge pump and temp sensor, ADC at 477sps, CLK output buffer enabled, clock output buffers unloaded TA = -40°C to +85°C ISLEEP TA = +25°C ISHDN All off AVDD = DVDD = 2.7V MIN TYP MAX 1.2 2.0 1.15 1.4 1.15 1.5 3.0 5.2 mA AVDD = DVDD = 3.6V 6.7 AVDD = DVDD = 2.7V 3.0 AVDD = DVDD = 3.6V 4.5 TA = -40°C to +85°C TA = +25°C UNITS 2.5 1.2 µA µA Note 1: Devices are production tested at TA = room temperature. Specifications to TA = -40°C and TA = +85°C are guaranteed by design. Note 2: Guaranteed by design or characterization. Note 3: The offset and gain errors are corrected by self-calibration or system calibration. For accurate calibrations, perform calibration at the lowest rate. The calibration error is therefore in the order of peak-to-peak noise for the selected rate. Note 4: Eliminate drift errors by recalibration at the new temperature. Note 5: The gain error excludes reference error, offset error (unipolar), and zero error (bipolar). Note 6: Gain-error drift does not include unipolar-offset drift or bipolar zero-error drift. It is effectively the drift of the part if zeroscale error is removed. Note 7: These specifications are obtained from characterization during design or from initial product evaluation. Not production tested or guaranteed. Note 8: VOUTA = +0.5V or +1.5V, VSWA = +1.5V or +0.5V, TA = 0°C to +50°C. Note 9: Long-term stability is characterized using five to six parts. The bandgaps are turned on for 1000hrs at room temperature with the parts running continuously. Daily measurements are taken and any obvious outlying data points are discarded. Note 10: Temperature error is the difference in the calculated temperature using the internal circuit vs. measurements made using precision external voltage and current meters. The same diode and diode equation are used for both measurements. Note 11: All the stated temperature accuracies assume that 1) the external diode characteristic is precisely known (i.e., ideal) and 2) the ADC reference voltage is exactly equal to 1.25V. Any variations to this known reference characteristic and voltage caused by temperature, loading, or power supply results in errors in the temperature measurement. The actual temperature calculation is performed externally by the µC. Note 12: Values based on simulation results and are not production tested or guaranteed. 10 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX1358B Table 1. Output Noise (Notes 13 and 14) OUTPUT NOISE (µVRMS) RATE (sps) 10 GAIN = 1 1.75 GAIN = 2 1.75 GAIN = 4 1.75 GAIN = 8 1.75 40 2.92 2.92 2.92 2.92 50 3.23 3.23 3.23 3.23 60 3.60 3.60 3.60 3.60 200 56.06 56.06 56.06 56.06 240 102.36 102.36 102.36 102.36 400 587.06 587.06 587.06 587.06 477 951.07 951.07 951.07 951.07 Note 13: VREF = +1.25V, bipolar mode, VIN = 1.24912V, PGA gain = 1, TA = +25°C. Note 14: Assume ±3 sigma peak-to-peak variation; noise-free resolution means no code flicker at given bits’ LSB. Table 2. Peak-to-Peak Resolution PEAK-TO-PEAK RESOLUTION (BITS) RATE (sps) GAIN = 1 GAIN = 2 GAIN = 4 GAIN = 8 10 17.57 16.57 15.57 14.57 40 16.83 15.83 14.83 13.83 50 16.68 15.68 14.68 13.68 60 16.53 15.53 14.53 13.53 200 12.57 11.57 10.57 9.57 240 11.70 10.70 9.70 8.70 400 9.18 8.18 7.18 6.18 477 8.48 7.48 6.48 5.48 Table 3. Maximum External Source Impedance Without 16-Bit Gain Error PARAMETER Resistance (kΩ) EXTERNAL CAPACITANCE (pF) 0 (Note 15) 50 100 500 1000 5000 350 60 30 10 4 1 Note 15: 2pF parasitic capacitance is assumed, which represents pad and any other parasitic capacitance. ______________________________________________________________________________________ 11 MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor TIMING CHARACTERISTICS (Figures 1 and 19) (AVDD = DVDD = +1.8V to +3.6V, external VREF = +1.25V, fCLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 MHz SCLK Operating Frequency f SCLK 0 SCLK Cycle Time tCYC 100 ns SCLK Pulse-Width High tCH 40 ns SCLK Pulse-Width Low tCL 40 ns DIN to SCLK Setup tDS 30 ns DIN to SCLK Hold tDH 0 ns SCLK Fall to DOUT Valid tDO CL = 50pF, Figure 2 40 ns CS Fall to DOUT Enable tDV CL = 50pF, Figure 2 48 ns CS Rise to DOUT Disable tTR CL = 50pF, Figure 2 48 ns CS to SCLK Rise Setup tCSS 20 ns CS to SCLK Rise Hold tCSH 0 ns DVDD Monitor Timeout Period tDSLP (Note 16) 1.5 s Wake-Up (WU) Pulse Width tWU Minimum pulse width required to detect a wake-up event 1 µs Shutdown Delay tDPU The delay for SHDN to go high after a valid wake-up event 1 µs HFCLK Turn-On Time CRDY to INT Delay tDFON tDFI The turn-on time for the high-frequency clock and FLL (FLLE = 1) (Note 17) 10 ms If FLLE = 0, the turn-on time for the highfrequency clock (Notes 7, 18) 10 µs The delay for CRDY to go low after the HFCLK clock output has been enabled (Note 19) 7.82 ms HFCLK Disable Delay tDFOF The delay after a shutdown command has asserted and before HFCLK is disabled (Note 20) 1.95 ms SHDN Assertion Delay tDPD (Note 21) 2.93 ms Note 16: The delay for the sleep voltage monitor output, RESET, to go high after VDD rises above the reset threshold. This is largely driven by the startup of the 32kHz oscillator. Note 17: FLLE is gated by an AND function with three inputs—the external RESET signal, the internal DVDD monitor output, and the external SHDN signal. The time delay is timed from the internal LOVDD going high or the external RESET going high, whichever happens later. HFCLK always starts in the low state. Note 18: If FLLE = 0, the internal signal CRDY is not generated by the FLL block and INT or INT is deasserted. Note 19: CRDY is used as an interrupt signal to inform the µC that the high-frequency clock has started. Only valid if FLLE = 1. Note 20: tDFOF gives the µC time to clean up and go into sleep-override mode properly. Note 21: tDPD is greater than the HFCLK delay to clean up before losing power. 12 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX1358B CS tCSH tCH tCYC tCSH tCSS tCL SCLK tDS tDH DIN tDV tDO tTR DOUT Figure 1. Detailed Serial-Interface Timing DVDD 6kΩ DOUT DOUT 6kΩ CLOAD = 50pF a) FOR ENABLE, HIGH IMPEDANCE TO VOH AND VOL TO VOH FOR DISABLE, VOH TO HIGH IMPEDANCE CLOAD = 50pF b) FOR ENABLE, HIGH IMPEDANCE TO VOL AND VOH TO VOL FOR DISABLE, VOL TO HIGH IMPEDANCE Figure 2. DOUT Enable and Disable Time Load Circuits Typical Operating Characteristics (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) ALL ON WITH ADC AT 477sps AND MAXIMUM INTERNAL TEMP-SENSOR CURRENT SETTING 0.8 IDVDD 0.7 IAVDD 0.6 10.000 SUPPLY CURRENT (µA) SUPPLY CURRENT (mA) 0.9 MAX1358B toc01 1.0 MAX1358B toc02 DVDD SUPPLY CURRENT vs. DVDD SUPPLY VOLTAGE SUPPLY CURRENT vs. SUPPLY VOLTAGE SLEEP MODE 1.000 SLEEP MODE: ALL OFF EXCEPT 32kHz OSC, RTC, AND 1.8V MONITOR SHUTDOWN MODE: ALL OFF 0.100 0.010 0.5 SHUTDOWN MODE 0.001 0.4 1.8 2.1 2.4 2.7 3.0 AVDD, DVDD (V) 3.3 3.6 1.8 2.1 2.4 2.7 3.0 3.3 3.6 DVDD (V) ______________________________________________________________________________________ 13 Typical Operating Characteristics (continued) (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) 1.2 SLEEP MODE 0.8 SHUTDOWN MODE 0.8 DVDD = 3.0V 0.7 0.4 0.6 0 0.5 2.5 DVDD = 1.8V 2.0 DVDD = 3.0V 1.5 1.0 DVDD = 1.8V 2.4 2.7 3.0 3.3 3.6 -40 -15 10 35 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) DVDD SUPPLY CURRENT vs. TEMPERATURE AVDD SUPPLY CURRENT vs. TEMPERATURE AVDD SUPPLY CURRENT vs. TEMPERATURE 0.55 12 DVDD = 3.0V 8 4 0.53 SUPPLY CURRENT (mA) 16 ALL ON WITH ADC AT 512sps AND MAXIMUM INTERNAL TEMP-SENSOR CURRENT SETTING 0.51 DVDD = 3.0V 0.49 DVDD = 1.8V 0.47 DVDD = 1.8V -15 10 35 -15 10 35 1.3 85 60 DVDD = 1.8V -40 -15 0.45 0.40 DVDD = 3.0V 0.35 0.30 DVDD = 1.8V 0.20 2.60 OSCILLATOR FREQUENCY (MHz) ALL OFF 35 60 INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE MAX1358B toc09 0.50 10 TEMPERATURE (°C) AVDD SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (µA) DVDD = 3.0V 1.7 TEMPERATURE (°C) TEMPERATURE (°C) 0.25 2.1 2.55 FLL DISABLED FLL ENABLED 2.50 2.45 2.40 2.35 2.30 -40 -15 10 35 TEMPERATURE (°C) 60 85 0.5 -40 85 60 SLEEP MODE: ALL OFF EXCEPT 32kHz OSC, RTC, AND 1.8V MONITOR 0.9 0.45 0 2.5 MAX1358B toc10 ALL OFF SUPPLY CURRENT (mA) MAX1358B toc06 20 -40 -40 85 60 SUPPLY VOLTAGE (V) MAX1358B toc08 2.1 0.5 MAX1358B toc07 1.8 14 SLEEP MODE: ALL OFF EXCEPT 32kHz OSC, RTC, AND 1.8V MONITOR SUPPLY CURRENT (mA) ALL ON WITH ADC AT 512sps AND MAXIMUM INTERNAL TEMP-SENSOR CURRENT SETTING 0.9 3.0 MAX1358B toc04 SLEEP MODE: ALL OFF EXCEPT 32kHz OSC, RTC, AND 1.8V MONITOR SHUTDOWN MODE: ALL OFF SUPPLY CURRENT (mA) SUPPLY CURRENT (µA) 1.0 MAX1358B toc03 2.0 1.6 DVDD SUPPLY CURRENT vs. TEMPERATURE DVDD SUPPLY CURRENT vs. TEMPERATURE MAX1358B toc05 AVDD SUPPLY CURRENT vs. AVDD SUPPLY VOLTAGE SUPPLY CURRENT (nA) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor 85 -40 -15 10 35 TEMPERATURE (°C) ______________________________________________________________________________________ 60 85 85 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor 2.45 2.40 2.35 FLL DISABLED 1.5 MAX1358B toc13 1.2496 1.2494 VREF = 1.25V CLK = 2.4576MHz 1.2492 1.0 2.1 2.4 2.7 3.0 3.3 3.6 1.8 2.4 2.7 3.0 3.3 -50 3.6 50 150 250 350 450 SUPPLY VOLTAGE (V) OUTPUT CURRENT (µA) REFERENCE OUTPUT VOLTAGE vs. OUTPUT CURRENT REFERENCE OUTPUT VOLTAGE vs. OUTPUT CURRENT REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE 2.0492 2.0490 2.0488 2.4966 2.4964 2.4962 VREF = 2.048V 50 1.250 1.249 1.248 1.247 1.246 VREF = 2.5V 2.0486 150 250 350 450 550 VREF = 1.25V 2.4960 -50 50 150 250 350 450 OUTPUT CURRENT (µA) OUTPUT CURRENT (µA) REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE 2.046 2.044 -15 10 35 85 60 REFERENCE DRIFT (0˚C TO 50˚C) 2.497 VREF = 1.25V BOX METHOD OCCURRENCES 2.048 -40 MAX1358B toc18 2.050 550 1.245 TEMPERATURE (°C) 2.500 REFERENCE OUTPUT VOLTAGE (V) MAX1358B toc17 2.052 550 MAX1358B toc16 2.4968 1.251 REFERENCE OUTPUT VOLTAGE (V) 2.0494 2.4970 MAX1358B toc15 MAX1358B toc14 2.0496 -50 2.1 AVDD, DVDD SUPPLY VOLTAGE (V) REFERENCE OUTPUT VOLTAGE (V) 1.8 REFERENCE OUTPUT VOLTAGE (V) VREF = 2.048V VREF = 1.25V 1.2498 2.25 2.20 REFERENCE OUTPUT VOLTAGE (V) 2.0 1.2500 MAX1358B toc18b 2.30 2.5 1.2502 REFERENCE OUTPUT VOLTAGE (V) FLL ENABLED 2.50 VREF = 2.50V 50kI LOAD MAX1358B toc12 2.55 3.0 REFERENCE OUTPUT VOLTAGE (V) MAX1358B toc11 INTERNAL OSCILLATOR FREQUENCY (MHz) 2.60 REFERENCE OUTPUT VOLTAGE vs. OUTPUT CURRENT REFERENCE OUTPUT VOLTAGE vs. SUPPLY VOLTAGE INTERNAL OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE 2.494 2.491 2.488 VREF = 2.5V VREF = 2.048V 2.485 2.042 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 TEMPERATURE (°C) 60 85 6 11 16 21 26 ABSOLUTE DRIFT (ppm/NC) ______________________________________________________________________________________ 15 MAX1358B Typical Operating Characteristics (continued) (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) REFERENCE VOLTAGE OUTPUT NOISE (0.1Hz TO 10Hz) REFERENCE NOISE DENSITY vs. FREQUENCY ADC INL vs. OUTPUT CODE VREF = 1.25V 0 -0.002 100 INL (LSB) 50µV/div AC-COUPLED 0.002 MAX1358B toc21 1000 MAX1358B toc20 MAX1358B toc19 NOISE (nV/√Hz) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor -0.004 VREF = 2.048V UNIPOLAR MODE GAIN = 1 60sps -0.006 10 -0.008 -0.010 1 ADC INL vs. OUTPUT CODE -0.0044 0 -0.002 VREF = 2.048V UNIPOLAR MODE GAIN = 1 60sps -0.0024 -0.0021 20k 30k 40k 50k 60k 70k OUTPUT CODE -0.0020 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) ADC MAXIMUM INL vs. TEMPERATURE ADC MAXIMUM INL vs. TEMPERATURE -0.002 -0.003 -0.004 -0.005 0.0020 0.0015 0.0010 VREF = 1.25V BIPOLAR MODE GAIN = 1 60sps 0.0005 -0.006 0 -0.007 -40 -15 10 35 TEMPERATURE (NC) 16 0.0025 ADC MAXIMUM INL (%) VREF = 2.048V UNIPOLAR MODE GAIN = 1 60sps -0.001 0.0030 MAX1358B toc25 0 VREF = 1.25V BIPOLAR MODE GAIN = 1 60sps MAX1358B toc26 10k 60 85 70k -0.0022 -0.0060 0 60k -0.0023 -0.004 -0.005 50k -0.0025 -0.0056 -0.003 40k ADC MAXIMUM INL vs. SUPPLY VOLTAGE -0.0052 -0.001 30k ADC MAXIMUM INL vs. SUPPLY VOLTAGE -0.0048 0.001 ADC MAXIMUM INL (%) INL (LSB) 0.002 20k OUTPUT CODE ADC MAXIMUM INL (%) 0.003 10k FREQUENCY (Hz) MAX1358B toc23 0.004 ADC MAXIMUM INL (%) AVDD = DVDD = 1.8V VREF = 1.25V BIPOLAR MODE GAIN = 1 60sps 0 10,000 1000 -0.0040 MAX1358B toc22 0.005 100 MAX1358B toc24 10 1s/div -40 -15 10 35 TEMPERATURE (NC) ______________________________________________________________________________________ 60 85 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor ADC MAXIMUM vs. OUTPUT DATA RATE -0.0015 -0.0020 -0.0025 -0.0030 -0.0035 MAX1358B toc28 AVDD = DVDD = 1.8V VREF = 1.25V BIPOLAR MODE GAIN = 1 0.025 -0.0040 ADC MAXIMUM INL vs. PGA GAIN 0.010 0.020 0.015 0.010 AVDD = DVDD = 1.8V VREF = 1.25V BIPOLAR MODE 60sps 0.008 ADC MAXIMUM INL (%) ADC MAXIMUM INL (%) -0.0010 VREF = 1.25V BIPOLAR MODE GAIN = 1 60sps ADC MAXIMUM INL (%) -0.0005 0.030 MAX1358B toc27 0 MAX1358B toc29 ADC MAXIMUM INL vs. COMMON-MODE INPUT VOLTAGE 0.006 0.004 0.002 0.005 -0.0045 1.0 1.2 1.4 1.6 1.8 2.0 100 200 300 0 500 400 2 4 6 8 COMMON-MODE VOLTAGE (V) DATA RATE (sps) PGA GAIN ADC OFFSET ERROR vs. TEMPERATURE ADC GAIN ERROR vs. TEMPERATURE ADC OFFSET ERROR vs. SUPPLY VOLTAGE 0.005 0.0005 0 0.0035 0.004 0.003 0.002 VREF = 1.25V UNIPOLAR MODE GAIN = 1 60sps 0.0030 OFFSER ERROR (%FSR) 0.0010 VREF = 2.048V UNIPOLAR MODE GAIN = 1 60sps MAX1358B toc32 0.006 ADC GAIN ERROR (%) VREF = 2.048V UNIPOLAR MODE GAIN = 1 60sps 0.0015 0 2.2 MAX1358B toc31 0.0020 0.8 MAX1358B toc30 0.6 0.0025 0.0020 0.0015 0.0010 0.0005 0.001 -0.0005 0 0 -0.0010 -40 -15 10 35 60 -0.0005 -40 85 -15 10 35 85 60 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 TEMPERATURE (NC) TEMPERATURE (NC) SUPPLY VOLTAGE (V) ADC GAIN ERROR vs. SUPPLY VOLTAGE GAIN ERROR (%FSR) 0.0030 0.0025 0.0020 0.0015 1000.00 MAX1358B toc34 0.0035 VREF = 1.25V UNIPOLAR MODE GAIN = 1 60sps 100.00 INPUT CURRENT (nA) 0.0040 ADC MUX INPUT DC CURRENT vs. TEMPERATURE MAX1358B toc33 ADC OFFSET ERROR (%) 0 0 -0.0050 ADC CONVERTING 10.00 1.000 ADC OFF 0.100 0.0010 AIN1 = AVDD/2 MUX+ = AIN1 MUX- = AGND 0.010 0.0005 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) 0.001 -40 -15 10 35 60 85 TEMPERATURE (NC) ______________________________________________________________________________________ 17 MAX1358B Typical Operating Characteristics (continued) (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) SW_ LEAKAGE CURRENT vs. INPUT VOLTAGE 1.5 TA = +55°C TA = +25°C TA = +85°C 0.2 TA = +55°C 0.1 0 -0.1 TA = +25°C 0.5 -0.2 0 -0.5 0.5 1.0 1.5 2.0 2.5 3.0 0 -0.1 0 0.5 1.0 1.5 2.0 -0.3 3.0 2.5 0 0.5 1.0 1.5 2.0 2.5 SNO_ LEAKAGE CURRENT vs. INPUT VOLTAGE SNC_ LEAKAGE CURRENT vs. INPUT VOLTAGE SCM_ LEAKAGE CURRENT vs. INPUT VOLTAGE 0.05 0 TA = +85°C 0.10 TA = +55°C 0.05 0 0 TA = +25°C -0.10 -0.15 -0.15 -0.20 -0.20 1.5 2.0 2.5 0 3.0 0.5 1.0 1.5 2.0 0 3.0 2.5 0.5 IN1- LEAKAGE CURRENT vs. INPUT VOLTAGE 0.5 MAX1358B toc41 TA = +85NC 0.4 AVDD = 1.8V VREF = 1.25V 0.3 TA = +55NC 2.0 0.2 INL (LSB) 0.05 0 -0.05 1.5 DAC INL vs. OUTPUT CODE 0.20 0.15 1.0 VSCM_ (V) VSNC_ (V) VSNO_ (V) 0.10 TA = +25°C -0.10 -0.20 1.0 TA = +55°C 0.05 -0.15 0.5 TA = +85°C 0.10 MAX1358B toc42 -0.10 SN0_ = SNC_ = AVDD/2 0.15 TA = +25NC 0.1 0 -0.1 -0.2 -0.10 -0.3 -0.15 -0.4 -0.20 -0.5 0 0.5 1.0 1.5 VIN1- (V) 2.0 2.5 3.0 3.0 -0.05 -0.05 TA = +25°C 0.20 MAX1358B toc39 0.15 INPUT CURRENT (nA) TA = +55°C SCM_ = AVDD/2 INPUT CURRENT (nA) 0.10 0.20 MAX1358B toc38 TA = +85°C INPUT CURRENT (nA) TA = +25°C VFB (V) -0.05 18 0.1 VSW_ (V) SCM_ = AVDD/2 0 TA = +55°C VAIN_ (V) 0.20 0.15 0.2 -0.2 -0.3 0 TA = +85°C 0.3 MAX1358B toc40 2.0 1.0 0.3 INPUT CURRENT (nA) TA = +85°C 2.5 OUT_ = AVDD/2 INPUT CURRENT (nA) 3.0 0.4 MAX1358B toc36 3.5 INPUT CURRENT (nA) 0.4 MAX1358B toc35 4.0 FB LEAKAGE CURRENT vs. INPUT VOLTAGE MAX1358B toc37 AIN_ LEAKAGE CURRENT vs. INPUT VOLTAGE INPUT CURRENT (nA) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor 0 100 200 300 400 500 600 700 800 900 1000 1100 OUTPUT CODE ______________________________________________________________________________________ 2.5 3.0 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor DAC DNL vs. OUTPUT CODE 0.1 0 OUTPUT CODE OUTPUT CODE DAC OUTPUT VOLTAGE vs. ANALOG SUPPLY VOLTAGE DAC OUTPUT VOLTAGE vs. TEMPERATURE DAC FB_ INPUT BIAS CURRENT vs. TEMPERATURE 0.62405 0.62400 0.62395 VREF = 1.25V CODE = 0x200 RLOAD = 10kI 0.62390 0.62385 0.6242 0.6238 VREF = 1.25V EXTERNAL CODE = 0x200 RLOAD = 10kI AVDD = DVDD = 1.8V 0.6234 0.62380 0.6230 2.1 2.4 2.7 3.0 3.6 3.3 -40 AVDD (V) DAC GAIN ERROR vs.TEMPERATURE MAX1358B toc49 VREF = 1.25V EXTERNAL AVDD = DVDD = 1.8V 150 100 FB_ = AVDD 50 FB_ = 0 35 60 85 -50 -40 -15 10 35 60 85 TEMPERATURE (°C) DAC OUTPUT NOISE (0.1Hz TO 10Hz) 0.3 GAIN ERROR (LSB) 10 200 0 TEMPERATURE (°C) 0.5 0.4 -15 MAX1358B toc48 0.6246 INPUT CURRENT (pA) 0.62410 250 MAX1358B toc47 DAC OUTPUT VOLTAGE (V) MAX1358B toc46 0.6250 1100 900 1000 800 700 600 0 1100 900 1000 800 700 600 500 400 300 200 0 OUTPUT CODE 0.62415 1.8 100 1100 900 1000 800 -0.5 700 -0.5 600 -0.4 -0.5 500 -0.4 400 -0.3 -0.4 300 -0.2 -0.3 200 -0.2 -0.3 0 -0.2 500 -0.1 400 -0.1 300 -0.1 0 200 0 INL (LSB) 0.1 INL (LSB) 0.2 0.1 MAX1358B toc45 0.3 0.2 0.62420 DAC OUTPUT VOLTAGE (V) 0.3 VREF = 2.048V 0.4 0.2 100 INL (LSB) 0.3 AVDD = 1.8V VREF = 1.25V 0.4 0.5 100 MAX1358B toc43 VREF = 2.048V 0.4 DAC DNL vs. OUTPUT CODE 0.5 MAX1358B toc44 DAC INL vs. OUTPUT CODE 0.5 MAX1358B toc50 REF = 1.25V AVDD = DVDD = 1.8V CODE = 0x3FF 0.2 20µV/div AC-COUPLED 0.1 0 VREF = 2.5V EXTERNAL AVDD = DVDD = 3.0V -0.1 -0.2 OFFSET MEASURED AT CODE 0x52 -0.3 -40 -15 10 35 60 85 1s/div TEMPERATURE (°C) ______________________________________________________________________________________ 19 MAX1358B Typical Operating Characteristics (continued) (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) DAC OUTPUT-NOISE DENSITY vs. FREQUENCY NOISE (nV/√Hz) VREF = 1.25V AVDD = DVDD = 1.8V CODE = 3FF DAC LARGE-SIGNAL STEP RESPONSE (0x052 TO 0x3FF) MAX1358B toc52 MAX1358B toc51 1000 OUT_ = FB_ SCLK 2V/div 100 10 OUTA 500mV/div 0V 1 0.01 0.10 1.00 10.00 100.00 10µs/div FREQUENCY (kHz) DAC LARGE-SIGNAL STEP RESPONSE (0x3FF to 0x052) OP-AMP INPUT OFFSET VOLTAGE vs. TEMPERATURE -0.1 25 -0.2 -0.3 15 10 -0.4 0V 20 5 -0.5 0 -40 10µs/div -15 10 35 60 85 TEMPERATURE (°C) OFFSET (mV) OP-AMP OUTPUT VOLTAGE vs. LOAD CURRENT 0.89966 UNITY GAIN VIN = 0.9V AVDD = DVDD = 1.8V 0.89964 1.49970 1.49965 OP-AMP OUTPUT VOLTAGE (V) 0.89968 MAX1358B toc56 0.89970 OP-AMP OUTPUT VOLTAGE vs. LOAD CURRENT MAX1358B toc57 OUTA 500mV/div 30 OCCURRENCES OFFSET VOLTAGE (mV) SCLK MAX1358B toc55 VCM = 0.5V OUT_ = FB_ OP-AMP INPUT OFFSET HISTOGRAM 35 MAX1358B toc54 0 -2.92 -2.62 -2.32 -2.02 -1.72 -1.42 -1.12 -0.82 -0.52 -0.22 0.08 0.38 0.68 0.98 1.28 MAX1358B toc53 OP-AMP OUTPUT VOLTAGE (V) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor UNITY GAIN VIN = 1.5V AVDD = DVDD = 3.0V 1.49960 0.89962 0.89960 1.49955 0.89958 1.49950 0.89956 0.89954 1.49945 0.89952 0.89950 1.49940 -2.0 -1.5 -1.0 -0.5 0 0.5 LOAD CURRENT (mA) 20 1.0 1.5 2.0 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 LOAD CURRENT (mA) ______________________________________________________________________________________ 2.0 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor OP-AMP OUTPUT VOLTAGE vs. TEMPERATURE OP-AMP OUTPUT VOLTAGE vs. SUPPLY VOLTAGE 0.8984 0.8983 0.8982 0.49990 MAX1358B toc59 UNITY GAIN VIN1+ = 0.5V AVDD = DVDD = 1.8V 0.49985 20µV/div AC-COUPLED 0.49980 0.49975 0.49970 0.49965 0.8981 10 35 0.49960 85 60 SUPPLY VOLTAGE (V) OP-AMP OUTPUT-NOISE DENSITY vs. FREQUENCY OP-AMP UNITY-GAIN INPUT RANGE VIN+ = 0.5V AVDD = DVDD = 1.8V UNITY GAIN CLOSED-LOOP OP-AMP GAIN AND PHASE vs. FREQUENCY 10 MAX1358B toc61 1000 1s/div 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 TEMPERATURE (°C) AVDD = DVDD = 3.6V UNITY GAIN NO LOAD 8 6 GAIN 40 2 0 -2 10 20 45 0 0 -45 PHASE -90 -40 -6 -80 -10 1.00 10.00 0 100.00 0.6 1.2 1.8 2.4 10 3.6 3.0 100 -180 10k 100k 1M FREQUENCY (Hz) VIN (V) FREQUENCY (kHz) 1k -135 SPDT ON-RESISTANCE vs. SCM_ VOLTAGE SPST ON-RESISTANCE vs. SW_ VOLTAGE 70 MAX1358B toc64 45 ISCM_ = 1mA 40 MAX1358B toc65 0.10 CLOSED-LOOP GAIN = 1000 RLOAD = 10kI CLOAD = 200pF -60 -8 ISW_ = 1mA 65 60 35 RON (I) RON (I) 0.01 90 -20 -4 1 180 135 60 4 VOUT - VIN (mV) 100 MAX1358B toc63 80 30 AVDD = 3V 55 AVDD = 3V 50 45 25 AVDD = 1.8V 40 AVDD = 1.8V 20 0 0.5 35 1.0 1.5 VSCM_ (V) 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 VSW_ (V) ______________________________________________________________________________________ 21 PHASE (°) -15 MAX1358B toc62 -40 NOISE (nV/√Hz) MAX1358B toc60 GAIN (dB) OUTPUT VOLTAGE (V) 0.8985 OP-AMP OUTPUT NOISE (0.1Hz TO 10Hz) UNITY GAIN VIN = 0.5V RLOAD = 10kI 0.49995 OP-AMP OUTPUT VOLTAGE (V) UNITY GAIN AVDD = DVDD = 1.8V VIN+ = AVDD/2 RLOAD = 10kI 0.8986 0.50000 MAX1358B toc58 0.8987 MAX1358B Typical Operating Characteristics (continued) (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) SPDT ON-RESISTANCE vs. TEMPERATURE VSCM_ = AVDD ISCM_ = 1mA VSCM_ = AVDD ISCM_ = 1mA RON (I) 50 AVDD = DVDD = 3.0V 40 20 AVDD = DVDD = 1.8V -15 10 35 60 -40 85 -15 10 35 60 85 -40 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) SPDT SWITCHING TIME vs. SUPPLY VOLTAGE SPST SWITCHING TIME vs. SUPPLY VOLTAGE SPDT/SPST SWITCHING TIME vs. TEMPERATURE 40 30 50 40 30 2.1 2.4 2.7 20 3.0 3.3 3.6 20 tOFF 0 1.8 2.1 2.4 2.7 3.0 3.3 3.6 -15 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 10 35 TEMPERATURE (°C) 60 85 10 35 60 TEMPERATURE (°C) INTERNAL TEMPERATURE SENSOR ERROR vs. REFERENCE VOLTAGE 15 TA = +85°C TEMPERATURE SENSOR ERROR (°C) VREF = 1.250V MAX1358B toc72 2.0 -15 -40 AVDD, DVDD (V) INTERNAL TEMPERATURE SENSOR ERROR vs. AMBIENT TEMPERATURE TEMPERATURE SENSOR ERROR (°C) 30 10 AVDD, DVDD (V) -40 tON tOFF tOFF 20 RLOAD = 1kI CLOAD = 35pF 40 SWITCHING TIME (ns) tON tON 85 MAX1358B toc71 60 TIME (ns) 50 50 MAX1358B toc70 70 MAX1358B toc69 60 22 0.001 TEMPERATURE (°C) 70 1.8 0.010 AVDD = DVDD = 1.8V 30 10 -40 0.100 MAX1358B toc73 RON (I) AVDD = DVDD = 3.0V 30 VIN = AVDD LEAKAGE CURRENT (nA) 60 40 1.000 MAX1358B toc67 70 MAX1358B toc66 50 SPST LEAKAGE CURRENT vs. TEMPERATURE MAX1358B toc68 SPDT ON-RESISTANCE vs. TEMPERATURE TIME (ns) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor 10 TA = +27°C 5 0 TA = -40°C -5 -10 -15 1.21 1.23 1.25 1.27 REFERENCE VOLTAGE (V) ______________________________________________________________________________________ 1.29 85 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor CHARGE-PUMP OUTPUT VOLTAGE vs. OUTPUT CURRENT 1.8 3.4 3.1 35 3.0 0 85 60 AVDD = DVDD = 1.8V IOUT = 10mA 80 MAX1358B toc77 100 60 40 20 0 10 2 4 6 3.10 10 8 -40 -15 15 CAPACITANCE (µF) 20 10 35 60 85 TEMPERATURE (°C) CHARGE-PUMP OUTPUT-VOLTAGE RIPPLE vs. OUTPUT CURRENT CHARGE-PUMP OUTPUT RESISTANCE vs. CAPACITANCE 5 3.18 OUTPUT CURRENT (mA) TEMPERATURE (°C) 0 3.22 3.14 25 CHARGE-PUMP OUTPUT-VOLTAGE RIPPLE (mVP-P) 10 3.26 3.2 DVDD SUPERVISOR -15 AVDD = DVDD = 1.8V ILOAD = 10mA 3.3 1.5 -40 3.30 50 MAX1358B toc78 2.1 AVDD = DVDD = 1.8V OUTPUT VOLTAGE (V) CPOUT SUPERVISOR 2.4 3.5 MAX1358B toc75 2.7 OUTPUT RESISTANCE (I) VOLTAGE THRESHOLD (V) FALLING CHARGE-PUMP OUTPUT VOLTAGE (V) MAX1358B toc74 3.0 CHARGE-PUMP OUTPUT VOLTAGE vs. TEMPERATURE MAX1358B toc76 VOLTAGE SUPERVISOR THRESHOLD vs. TEMPERATURE AVDD = DVDD = 1.8V 40 30 20 10 0 0 2 4 6 8 10 OUTPUT CURRENT (mA) ______________________________________________________________________________________ 23 MAX1358B Typical Operating Characteristics (continued) (DVDD = AVDD = 1.8V, VREF = +1.25V, CCPOUT = 10µF, TA = +25°C, unless otherwise noted.) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor Pin Description PIN 24 NAME FUNCTION 1 CLK 2 UPIO2 User-Programmable Input/Output 2. See the UPIO2_CTRL Register section for functionality. Clock Output. Default is 2.457MHz output clock for the µC. 3 UPIO3 User-Programmable Input/Output 3. See the UPIO3_CTRL Register section for functionality. 4 UPIO4 User-Programmable Input/Output 4. See the UPIO4_CTRL Register section for functionality. 5 DOUT Serial-Data Output. Data is clocked out on SCLK’s falling edge. High impedance when CS is high, when UPIO/SPI pass-through mode is enabled, DOUT mirrors the state of UPIO1. 6 SCLK 7 DIN Serial-Data Input. Data is clocked in on SCLK’s rising edge. 8 CS Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. High impedance when CS is high; when UPIO/SPI pass-through mode is enabled, DOUT mirrors the state of UPIO1. 9 INT Programmable Active-High/Low Interrupt Output. ADC, UPIO wake-up, alarm, and voltage-monitor events. 10 CLK32K 32kHz Clock Input/Output. Outputs 32kHz clock for the µC. Can be programmed as an input by enabling the IO32E bit to accept an external 32kHz input clock. The RTC, PWM, and watchdog timer always use the internal 32kHz clock derived from the 32kHz crystal. 11 RESET 12 32KOUT 13 32KIN 32kHz Crystal Input. Connect an external 32kHz watch crystal between 32KIN and 32KOUT. 14 SNO1 Analog Switch 1 Normally Open Terminal. Analog input to mux. 15 SCM1 Analog Switch 1 Common Terminal. Analog input to mux. 16 SNC1 Analog Switch 1 Normally Closed Terminal. Analog input to mux (open on POR). 17 SNO2 Analog Switch 2 Normally Open Terminal. Analog input to mux. 18 SCM2 Analog Switch 2 Common Terminal. Analog input to mux (open on POR). 19 SNC2 Analog Switch 2 Normally Closed Terminal. Analog input to mux. 20 OUT1 21 IN1- Amplifier 1 Inverting Input. Analog input to mux. 22 IN1+ Amplifier 1 Noninverting Input Serial-Clock Input. Clocks data in and out of the serial interface. Active-Low, Open-Drain Reset Output. Remains low while DVDD is below the 1.8V voltage threshold and stays low for a timeout period (tDSLP) after DVDD rises above the 1.8V threshold. RESET also pulses low when the watchdog timer times out and holds low during POR until the 32kHz oscillator stabilizes. 32kHz Crystal Output. Connect an external 32kHz watch crystal between 32KIN and 32KOUT. Amplifier 1 Output. Analog input to mux. ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor PIN NAME FUNCTION 23 SWA DACA SPST Shunt Switch Input. Connects to OUTA through an SPST switch. 24 FBA DACA Force-Sense Feedback Input. Analog input to mux. 25 OUTA 26 AGND Analog Ground 27 AVDD Analog Supply Voltage. Also ADC reference voltage during AVDD measurement. Bypass to AGND with 10µF and 0.1µF capacitors in parallel as close to the pin as possible. 28 SWB DACB SPST Shunt Switch Input. Connects to OUTB through an SPST switch. 29 FBB DACB Force-Sense Feedback Input. Analog input to mux. 30 OUTB Force-Sense DACB Ouput. Analog input to mux. 31 AIN2 Analog Input 2. Analog input to mux. Inputs have internal programmable current source for external temperature measurement. 32 AIN1 Analog Input 1. Analog input to mux. Inputs have internal programmable current source for external temperature measurement. 33 REF Reference Input/Output. Output of the reference buffer amplifier or external reference input. Disabled at power-up to allow external reference. Reference voltage for ADC and DACs. 34 REG Linear Voltage-Regulator Output. Charge-pump-doubler input voltage. Bypass REG with a 10µF capacitor to DGND for charge-pump regulation. DACA Force-Sense Output. Analog input to mux. 35 CF- 36 CF+ 37 CPOUT 38 DVDD 39 DGND Digital Ground. Also ground for cascaded linear voltage regulator and charge-pump doubler. 40 UPIO1 User-Programmable Input/Output 1. See the UPIO1_CTRL Register for functionality. — EP Charge-Pump Flying Capacitor Terminals. Connect an external 10µF (typ) capacitor between CF+ and CF-. Charge-Pump Output. Connect an external 10µF (typ) reservoir capacitor between CPOUT and DGND. There is a low threshold diode between DVDD and CPOUT. When the charge pump is disabled, CPOUT is pulled up within 300mV (typ) of DVDD. Digital Supply Voltage. Bypass to DGND with 10µF and 0.1µF capacitors in parallel as close to the pin as possible. Exposed Pad. Leave unconnected or connect to AGND. ______________________________________________________________________________________ 25 MAX1358B Pin Description (continued) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor Detailed Description The MAX1358B DAS features a multiplexed differential 16-bit ADC, 10-bit force-sense DACs, an RTC with an alarm, a selectable bandgap voltage reference, a signaldetect comparator, 1.8V and 2.7V voltage monitors, and wake-up control circuitry, all controlled by a 4-wire serial interface (see Figure 3 for the functional diagram). CS SCLK DIN 32.768kHz OSCILLATOR The 16-bit ADC features programmable continuous conversion rates as shown in Table 4, and gains of 1, 2, 4, and 8 (Table 5) to suit applications with different power CLK INT 4.9152MHz HF OSCILLATOR AND FLL INTERRUPT CLK32K 32KOUT 32KIN DVDD The DAS directly interfaces to various sensor outputs and, once configured, provides the stimulus, signal conditioning, and data conversion, as well as µP support. See the Applications section for sample MAX1358B applications. CLK32K M32K INPUT/OUTPUT CONTROL SERIAL INTERFACE DOUT 32K UPIO2 CRDY UPR<4:1> UPF<4:1> STATUS ALD SDC ADD ADOU LDVD LCPD PWM RTC AND ALARM WATCHDOG TIMER AIN1 SNO1 FBA SCM1 FBB SNC1 IN1TEMP+ REF AGND AIN2 SNO1 SNC1 SCM1 SPDT1 SNC2 SPDT2 TEMPSNO2 OUTA SCM2 OUTB SNC2 OUT1 AIN2 REF AGND DGND UPIO4 DVDD (1.8V) VOLTAGE MONITOR CHARGEPUMP DOUBLER LINEAR 1.65V VOLTAGE REGULATOR M32K CF+ CFREG PROG. VOS PGA 1.25V BANDGAP 10:1 MUX POS REF CMP AV = 1, 1.6384, 2 V/V REF REF IN+ 16-BIT ADC IN- POLARITY FLIPPER 10-BIT DAC OUTA BUF HFCLK SWA AV = 1, 2, 4, 8 V/V FBA REF 10:1 MUX NEG 10-BIT DAC OUTB BUF SWB OP1 FBB IN1+ IN1- OUT1 AGND Figure 3. Functional Diagram 26 RESET CPOUT DVDD M32K MAX1358B PGA SNO2 SCM2 TEMP+ TEMP- UPIO3 4 4 CPOUT (2.7V) VOLTAGE MONITOR AIN2 TEMP SENSOR AIN1 UPIO WDTO AIN1 PROG CURRENT SOURCE UPIO1 16 HFCLK CONTROL LOGIC AVDD ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor ADC Modulator The MAX1358B performs analog-to-digital conversions using a single-bit, 3rd-order, switched-capacitor sigmadelta modulator. The sigma-delta modulation converts the input signal into a digital pulse train whose average duty cycle represents the digitized signal information. The pulse train is then processed by a digital decimation filter. The modulator provides 2nd-order frequency shaping of the quantization noise resulting from the single-bit quantizer. The modulator is fully differential for maximum signal-to-noise ratio and minimum susceptibility to power-supply noise. Analog-to-Digital Converter (ADC) INT asserts (and remains asserted) within 30µs when the differential voltage on the selected analog inputs exceeds the signal-detect comparator trip threshold. The signal-detect comparator’s differential input trip threshold (i.e., offset) is user selectable and can be programmed to the following values: 0mV, 50mV, 100mV, 150mV, or 200mV. The MAX1358B includes a sigma-delta ADC with programmable conversion rate, a PGA, and a dual 10:1 input mux. When performing continuous conversions at 10sps or single conversions at the 40sps setting (effectively 10sps due to four sample sigma-delta settling), the ADC has 16-bit noise-free resolution. The noise-free resolution drops to 10 bits at the maximum sampling rate of 477sps. Differential inputs support unipolar (between 0 and VREF) and bipolar (between ±VREF) modes of operation. Note: Avoid combinations of input signal and PGA gains that exceed the reference range at the ADC input. The ADOU bit in the STATUS register indicates if the ADC has overranged or underranged. Zero-scale and full-scale calibrations remove offset and gain errors. Direct access to gain and zero-scale calibration registers allows system-level offset and gain calibration. The zero-scale adjustment register allows intentional positive offset skewing to preserve unipolarmode resolution for signals that have a slight negative offset (i.e., unipolar clipping near zero can be removed). Perform ADC calibration whenever the ADC configuration, temperature, or AVDD changes. The ADC-done status can be programmed to provide an interrupt on INT or on any UPIO_. PGA Gain An integrated PGA provides four selectable gains (+1V/V, +2V/V, +4V/V, and +8V/V) to maximize the dynamic range of the ADC. Bits GAIN1 and GAIN0 set the gain (see the ADC Register for more information). The PGA gain is implemented in the digital filter of the ADC. Signal-Detect Comparator Analog Inputs The ADC provides two external analog inputs: AIN1 and AIN2. The rail-to-rail inputs accept differential or single-ended voltages, or external temperature-sensing diodes. The unused op amps, switches, or DAC inputs and output pins can also be used as rail-to-rail analog inputs if the associated function is disabled. Analog Input Protection Internal protection diodes clamp the analog inputs to AVDD and AGND and allow the channel input to swing from (AGND - 0.3V) to (AVDD + 0.3V). For accurate conversions near full scale, the inputs must not exceed AVDD by more than 50mV or be lower than AGND by 50mV. If the inputs exceed (AGND - 0.3V) to (AVDD + 0.3V), limit the current to 50mA. Analog Mux The MAX1358B includes a dual 10:1 mux for the positive and negative inputs of the ADC. Figure 3 illustrates which signals are present at the inputs of each mux for the MAX1358B. The MUXP[3:0] and MUXN[3:0] bits of the MUX register select the input to the ADC and the signaldetect comparator (Tables 8 and 9). See the MUX register description in the Register Definitions section for multiplexer functionality. The POL bit of the ADC register swaps the polarity of mux output signals to the ADC. ______________________________________________________________________________________ 27 MAX1358B and dynamic range constraints. The force-sense DAC provides 10-bit resolution for precise sensor applications. The ADC and DACs both utilize a low-drift 1.25V internal bandgap reference for conversions and fullscale range setting. The RTC has a 138-year range and provides an alarm function that can be used to wake up the system or cause an interrupt at a predefined time. The power-supply voltage monitor detects when DVDD falls below a trip threshold voltage of +1.8V and asserts RESET. The MAX1358B uses a 4-wire serial interface to communicate directly among SPI, QSPI, or MICROWIRE devices for system configuration and readback functions. Digital Filtering Force-Sense DAC The MAX1358B contains an on-chip digital lowpass filter that processes the data stream from the modulator using a sinc4 (sinx/x)4 response. The sinc4 filter has a settling time of four output data periods (4 x 200ms). The MAX1358B incorporates two 10-bit force-sensing DACs. The DACs’ reference voltage sets the full-scale range. Program the DACA_OP register using the serial interface to set the output voltages of the DAC at OUTA. Connecting resistors in a voltage-divider configuration between OUTA, FBA, and GND sets a different closedloop gain for the output amplifier (see the Applications Information section). The DAC output amplifier typically settles to ±0.5 LSB from a full-scale transition within 65µs (unity gain and loaded with 10kΩ in parallel with 200pF). Loads of less than 1kΩ could degrade performance. See the Typical Operating Characteristics for the source-and-sink capability of the DAC output. The MAX1358B features a software-programmable shutdown mode for the DAC. Power down DACA or DACB independently or simultaneously by clearing the DAE and DBE bits (see the DACA_OP Register and DACB_OP Register sections). DAC output OUTA and OUTB go high impedance when powered down. The DACs are normally powered down at power-on reset. The MAX1358B has 25% overrange capability built into the modulator and digital filter: 4 ⎡ ⎛ f ⎞⎤ ⎢ SIN⎜ Nπ ⎟ ⎥ fm ⎠ ⎥ ⎝ 1 H(f) = ⎢⎢ N ⎛ ⎞ ⎥ ⎢ SIN⎜ π f ⎟ ⎥ ⎢⎣ ⎝ fm ⎠ ⎥⎦ Figure 4 shows the filter frequency response. The sinc4 characteristic -3dB cutoff frequency is 0.228 times the first notch frequency. The output data rate for the digital filter corresponds with the positioning of the first notch of the filter’s frequency response. The notches of the sinc4 filter are repeated at multiples of the first notch frequency. The sinc4 filter provides an attenuation of better than 100dB at these notches. For example, 50Hz is equal to five times the first notch frequency and 60Hz is equal to six times the first notch frequency. 0 -40 GAIN (dB) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor -80 -120 Charge Pump The charge pump provides > 3V at CPOUT with a maximum 10mA load. Enable the charge pump through the PS_VMONS register. The charge pump is powered from DVDD. See Figures 5 and 6 for block diagrams of the charge pump and linear regulator. The charge pump is disabled at power-on reset. An internal clock drives the charge-pump clock and ADC clock. The charge pump delivers a maximum 10mA of current to external devices. The droop and the ripple depend on the clock frequency (f CLK = 32.768kHz/2), switch resistances (RSWITCH = 5Ω), and the external capacitors (10µF) along with their respective ESRs, as shown below. VDROOP = IOUTROUT -160 1 + 2RSWITCH + 4ESRCF + ESRCCPOUT fCLKCF IOUT VRIPPLE = + 2IOUTESRCCPOUT fCLKCCPOUT ROUT = -200 0 20 40 60 80 FREQUENCY (Hz) 100 120 Figure 4. Filter Frequency Response 28 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX1358B DVDD LDOE CPE CPOUT 1.22V OP M32K 1.65V NONOVERLAP CLOCK GENERATOR REG CF+ REG CF- LDOE CHARGE-PUMP DOUBLER LINEAR 1.65V VOLTAGE REGULATOR Figure 5. Linear-Regulator Block Diagram Voltage Supervisors The MAX1358B provides voltage supervisors to monitor DVDD and CPOUT. The first supervisor monitors the DVDD supply voltage. RESET asserts and sets the corresponding LDVD status bit when DVDD falls below the 1.8V threshold voltage. When the DVDD supply voltage rises above the threshold during power-up, RESET deasserts after a nominal 1.5s timeout period to give the crystal oscillator time to stabilize. Set the threshold hysteresis using the HYSE bit of the PS_VMONS register. See the PS_VMONS Register section for configuring hysteresis. There is no separate voltage monitor for AVDD, but the analog supply is covered by the DVDD monitor in many applications where DVDD and AVDD are externally connected together. Multiple supply applications where AVDD and DVDD are not connected together require a separate external voltage monitor for AVDD. See Figure 7 for a block diagram of the DVDD voltage supervisor. The second voltage monitor tracks the charge-pump output voltage, CPOUT. If CPOUT falls below the 2.7V threshold, a corresponding register status bit (LCPD) is Figure 6. Charge-Pump Block Diagram set to flag the condition. The CPOUT monitor output can also be mapped to the interrupt generator and output on INT. The CPOUT monitor can be used as a 3V AVDD monitor in applications where the charge pump is disabled and CPOUT is connected to AV DD . AV DD must be greater or equal to DVDD when CPOUT is used to monitor AVDD. See Figure 8 for a block diagram of the CPOUT voltage supervisor. Interrupt Generator (INT) The interrupt generator provides an interrupt to an external µC. The source of the interrupt is generated by the status register and can be masked and unmasked through the IMSK register. CRDY is unmasked by default, and INT is active-high at power-on reset. INT is programmable as active-high and active-low. Possible sources include a rising or falling edge of UPIO_, an RTC alarm, an ADC conversion completion, or the voltage-supervisor outputs. The interrupt causes INT to assert when configured as an interrupt output. ______________________________________________________________________________________ 29 MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor WDTO DVDD HYSE POR LSDE 1.8VTH ANALOG 2:1 MUX CMP 2.0VTH RSTE RESET CONTROL LOGIC 1.25V LDVD LSDE DVDD (1.8V) VOLTAGE MONITOR Figure 7. DVDD Voltage-Supervisor Block Diagram as the C-002RX32-E from Epson Crystal. Using a crystal with a CL that is larger than the load capacitance of the oscillator circuit causes the oscillator to run faster than the specified nominal frequency of the crystal or to not start up. See Figures 9 and 10 for block diagrams of the crystal oscillator and the CLK32K I/O. CPOUT CPDE 2.7VTH CMP LCPD Real-Time Clock (RTC) 1.25V CPDE CPOUT (2.7V) VOLTAGE MONITOR Figure 8. CPOUT Voltage-Supervisor Block Diagram Crystal Oscillator The on-chip oscillator requires an external crystal (or resonator) connected between 32KIN and 32KOUT with a 32.768kHz operating frequency. This oscillator is used for the RTC, alarm, PWM, watchdog, charge pump, and FLL. In any crystal-based oscillator circuit, the oscillator frequency is sensitive to the capacitive load (CL). CL is the capacitance that the crystal needs from the oscillator circuit and not the capacitance of the crystal. The input capacitance across 32KIN and 32KOUT is 6pF. Choose a crystal with a 32.768kHz oscillation frequency and a 6pF capacitive load such 30 The integrated RTC provides the current time information from a 32-bit counter and subsecond counts from an 8-bit ripple counter. An internally generated reference clock of 256Hz (derived from the 32.768kHz crystal) drives the 8-bit subsecond counter. An overflow of the 8-bit subsecond counter inputs a 1Hz clock to increment the 32-bit second counter. The RTC 32-bit second counter is translatable to calendar format with firmware. All 40 bits (32-bit second counter and 8-bit subsecond counter) must be clocked in or out for valid data. The RTC and the 32.768kHz crystal oscillator consume less than 1µA when the rest of the device is powered down. Time-of-Day Alarm Program the AL_DAY register with a 20-bit value, which corresponds to a time 1s to 12 days later than the current time with a 1s resolution. The alarm status bit, ALD, asserts when the 20 bits of the AL_DAY register matches the 20 LSBs of the 32-bit second counter. The ADE bit automatically clears when the time-of-day alarm trips. The time-of-day alarm causes the device to exit sleep mode. ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor High-Frequency Clock An internal oscillator and an FLL are used to generate a 4.9152MHz ±1% high-frequency clock. This clock and derivatives are used internally by the ADC, analog switches, and PWM. This clock signal outputs to CLK. When the FLL is enabled, the high- frequency clock is locked to the 32.768kHz reference. If the FLL is disabled, the high-frequency clock is free-running. At power-up, the CLK pin defaults to a 2.4576MHz clock output, which is compatible with most µCs. See Figure 12 for a block diagram of the high-frequency clock. User-Programmable I/Os The MAX1358B provides four digital programmable I/Os (UPIO1–UPIO4). Configure UPIOs as logic inputs or outputs using the UPIO control register. Configure the internal pullups using the UPIO setup register, if required. At power-up, the UPIOs are internally pulled up to DVDD. UPIO_ outputs can be referenced to DVDD or CPOUT. See the UPIO__CTRL Register and UPIO_SPI Register sections for more details on configuring the UPIO_ pins. OSCE 32K 32KOUT 32kHz OSCILLATOR OSCE CK32E IO32E 32K IO32E 0 IO32E 2:1 MUX 32KIN CLK32K M32K 1 32.768kHz OSCILLATOR CLK32K I/O CONTROL Figure 9. 32kHz Crystal-Oscillator Block Diagram Figure 10. CLK32K I/O Block Diagram POR PULSES HIGH DURING POWER-UP. WDW PULSES HIGH DURING WATCHDOG REGISTER WRITE. WDTO 32K WDE DIVIDEBY-8192 D Q CK Q 4Hz D Q CK R Q R POR WDW WATCHDOG TIMER Figure 11. Watchdog Timer Block Diagram ______________________________________________________________________________________ 31 MAX1358B Watchdog Enable the watchdog timer by writing a 1 to the WDE bit in the CLK_CTRL register. After enabling the watchdog timer, the device asserts RESET for 250ms, if the watchdog address register is not written every 500ms. Due to the asynchronous nature of the watchdog timer, the watchdog timeout period varies between 500ms and 750ms. Write a 0 to the WDE bit to disable the watchdog timer. See Figure 11 for a block diagram of the watchdog timer. MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor 32.768kHz CKSEL2 CKSEL<1:0> HFCE FLLE M32K FREQUENCY COMPARE FREQ ERROR FREQUENCY INTEGRATOR TUNE<8:0> DIGITALLY CONTROLLED OSCILLATOR CLKE 0 2:1 MUX 1, 2, 4, 8 DIVIDER CLK 1 4.9152MHz HFCLK CRDY 4.9152MHz HF OSCILLATOR AND FLL Figure 12. High-Frequency Clock and FLL Block Diagram Program each UPIO1–UPIO4 as one of the following: • General-purpose input PROGRAMMABLE CURRENT SOURCE • Power-mode control • Analog switch (SPST) and SPDT control input • ADC data-ready output IVAL<1:0> CURRENT SOURCE IMUX<1:0> 1:3 DEMUX • General-purpose output • PWM output • Alarm output AIN1 AIN1 AIN2 AIN2 • SPI pass-through Internal and External (Remote) Temperature Sensors An internal transistor or a remote transistor (or diode) is used with the ADC and a programmable current source to measure the ambient temperature. Depending on the method, either two or four currents are passed through the PN junction. The voltage across the PN junction is measured at each current. For each current, the voltage across a series resistor is also measured. Measuring the voltage across the resistor allows the user to determine the precise current ratios. A microcontroller can then use the diode equation to calculate the temperature. The four-current method eliminates errors caused by parasitic resistance in series with the diode, which increases the apparent voltage across the PN junction. When measuring temperature using the internal transistor for a sensor, the two-current method is usually adequate although the four-current method can also be used. Refer to Application Note 4296: Measuring Temperature with the MAX1358 Data Acquisition System for details on the measurement procedure. 32 TEMP+ TEMP- TEMP SENSOR Figure 13. Temperature-Sensor Measurement Block Diagram ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor Two-current method: T = q(VBE2 - VBE1)/(n k ln(VR2/VR1)) Four-current method: T = q(VBE2 + VBE3 - VBE1 - VBE4)/(n k ln((VR2 x VR3)/(VR1 x VR4)) where T is the temperature in degrees Kelvin, VBEX is the base to emitter voltage at current X, VRX is the voltage across the current-sensing resistor at current X, q is the charge on an electron, k is Boltzmann’s constant, and n is the ideality factor for the diode. From a practical standpoint, it is easiest to combine all the constants into one constant that also includes the voltage resolution of the ADC in unipolar mode. This requires introducing the term VREF, which is the reference voltage of the ADC. An N prefix on a term indicates that it is the integer value read directly from the ADC. Two-current method: T = 0.1771 x VREF(NVBE2 - NVBE1)/ln(NVR2/NVR1) Four-current method: T = 0.1771 x VREF((NVBE2 + NVBE3 - NVBE1 NVBE4)/ln(NVR2 x NVR3/NVR1/NVR4) The natural log function (ln) is eliminated from the calculation by using an approximation. Due to the small part-to-part variation in current ratios, this approximation is extremely accurate. Two-current method without an ln function: T = 0.1771 x VREF(NVBE2 – NVBE1)/(2.7081 + 2_(NVR2/NVR1 - 15)/(NVR2/NVR1 + 15) Four-current method without an ln function: T = 0.1771 x VREF(NVBE2 + NVBE3 - NVBE1 NVBE4)/(2.0794 + 2(NVR2 x NVR3/NVR1/NVR4 - 8)/ (NVR2 x NVR3/NVR1/NVR4 + 8) q = electron charge = 1.60219 x 10-19 coulombs n = diode ideality = 1.000 (typ) k = Boltzmann's constant = 1.3807 x 10-23 Joules/Kelvin I1 = Nominal current (4µA) I2 = Nominal current ng (60µA) I3 = Nominal current (64µA) I4 = Nominal current (120µA) To convert the measured temperature in Kelvin to degrees Celsius, the following formula is used: °C = K - 273.15 For the external temperature measurement, a transistor such as the 2N3904 is recommended. Voltage Reference and Buffer An internal 1.25V bandgap reference has a buffer with a selectable 1.0V/V, 1.638V/V, or 2.0V/V gain, resulting in nominally 1.25V, 2.048V, or 2.5V reference voltage at REF. The ADC and DACs use this reference voltage. The state of the internal voltage reference output buffer at POR is disabled so it can be driven, at REF, with an external reference between AGND and AVDD. The MAX1358B reference has an initial tolerance of ±1%. Program the reference buffer through the serial interface. Bypass REF with a 4.7µF capacitor to AGND. Uncommitted Operational Amplifiers (Op Amps) The MAX1358B includes one op amp. The op amp features rail-to-rail outputs, near rail-to-rail inputs, and has an 80kHz (1nF load) input bandwidth. The DACA_OP (DACB_OP) register controls the power state of the op amps. When powered down, the outputs of the op amps is high impedance. ______________________________________________________________________________________ 33 MAX1358B The temperature equations for the two-current and fourcurrent methods are as follows: MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor Single-Pole/Double-Throw (SPDT) Switches Serial Interface The MAX1358B provides two uncommitted SPDT switches. Each switch has a typical 35Ω on-resistance. Control the switches through the SW_CTRL register, the PWM output, and/or a UPIO port configured to control the switches (UPIO1–UPIO4_CTRL register). The MAX1358B features a 4-wire serial interface consisting of a chip select (CS), serial clock (SCLK), data in (DIN), and data out (DOUT). CS must be low to allow data to be clocked into or out of the device. DOUT is high impedance while CS is high. The data is clocked in at DIN on the rising edge of SCLK. Data is clocked out at DOUT on the falling edge of SCLK. The serial interface is compatible with SPI modes CPOL = 0, CPHA = 0 and CPOL = 1, CPHA = 1. A write operation to the MAX1358B takes effect on the last rising edge of SCLK. If CS goes high before the complete transfer, the write is ignored. Every data transfer is initiated by the command byte. The command byte consists of a start bit (MSB), R/W bit, and 6 address bits. The start bit must be 1 to perform data transfers to the device. Zeros clocked in are ignored. For SPI pass-through mode, see the UPIO_SPI Register section. An address byte identifies each register. Table 4 shows the complete register address map for this family of DAS. Figures 14, 15, and 16 provide timing diagrams for read and write commands. Pulse-Width Modulator (PWM) A single 8-bit PWM is available for various system tasks such as LCD bias control, sensor bias voltage trim, buzzer drive, and duty-cycled sleep-mode power-control schemes. PWM input clock sources include the 4.9512MHz FLL output, the 32kHz clock, and frequency-divided versions of each. Although most µCs have built-in PWM functions, the MAX1358B PWM is more flexible by allowing the UPIO outputs to be driven to DVDD or regulated CPOUT logic-high voltage levels. For duty-cycled power-control schemes, use the 32kHz-derived input clock. The PWM output is available independent of µC power state. The FLL is typically disabled in sleep-override mode. 34 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX1358B CS SCLK X DIN 1 0 A5 A4 A3 A2 A1 A0 DN DN -1 DN-2 DN-3 D2 D1 D0 X X DOUT X = DON’T CARE. Figure 14. Serial-Interface Register Write with 8-Bit Control Word, Followed by a Variable Length Data Write CS SCLK DIN X 1 1 A5 A4 A3 A2 A1 A0 DOUT X X X X X X X DN DN-1 DN-2 DN-3 D2 D1 D0 X = DON’T CARE. Figure 15. Serial-Interface Register Read with 8-Bit Control Word, Followed by a Variable Length Data Read CS SCLK DIN 1 DOUT 0 A4 A3 A2 A1 A0 X D7 D6 D5 D4 D3 D2 D1 D0 1 ADC CONV 1 A4 A3 A2 A1 A0 X D15D14 D13D12 D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CHANGES DRDY X = DON’T CARE. Figure 16. Performing an ADC Conversion (DRDY Function Can Be Accessed at UPIO Pins) ______________________________________________________________________________________ 35 MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor Register Definitions Table 4. Register Address Map REGISTER NAME START CTL (R/W) ADR<5:0> (ADDRESS) ADC 1 R/W 0 0 0 0 0 X MUX DATA OFFSET CAL GAIN CAL RESERVED 1 1 1 1 1 R/W R R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 S X X X X DACA_OP 1 R/W 0 0 1 1 0 X D<39:0>, D<23:0>, D<15:0> OR D<7:0> (DATA) ADCE STRT BIP POL CONT ADCREF GAIN<1:0> RATE<2:0> MODE<2:0> X X MUXP<3:0> MUXN<3:0> ADC<15:0> OFFSET<23:0> GAIN<23:0> Reserved. Do not use. DAE DBE OP1E X X X DACA<9:8> X DACB<9:8> DACA<7:0> DACB_OP 1 R/W 0 0 1 1 1 REF_SDC 1 R/W 0 1 0 0 0 AL_DAY 1 R/W 0 1 0 0 1 RESERVED 1 R/W 0 1 0 1 0 CLK_CTRL 1 R/W 0 1 0 1 1 RTC 1 R/W 0 1 1 0 0 PWM_CTRL 1 R/W 0 1 1 0 1 PWM_THTP 1 R/W 0 1 1 1 0 WATCHDOG NORM_MD SLEEP SLEEP_CFG UPIO4_CTRL UPIO3_CTRL UPIO2_CTRL UPIO1_CTRL UPIO_SPI SW_CTRL TEMP_CTRL RESERVED 1 1 1 1 1 1 1 1 1 1 1 1 W W W R/W R/W R/W R/W R/W R/W R/W R/W R 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 IMSK 1 R/W 1 1 0 1 1 RESERVED PS_VMONS RESERVED 1 1 1 R/W R/W R/W 1 1 1 1 1 1 1 1 1 0 0 1 0 1 0 STATUS 1 R 1 1 1 1 1 X DAE DBE OP1E X X DACB<7:0> AON SDCE TSEL<2:0> ASEC<19:4> X ASEC<3:0> X X X X X Reserved. Do not use. AWE ADE X RWE RTCE OSCE FLLE HFCE X CKSEL<2:0> IO32E CK32E CLKE INTP WDE SEC<31:0> X SUB<7:0> PWME FSEL<2:0> SWAH SWAL SWBH SWBL X SPD1 SPD2 X X X X X X PWMTH<7:0> X PWMTP<7:0> X X X X X X X X X X X X X X X X X X X X X X X X X X X SLP SOSCE SCK32E SPWME SHDN X X X X X UP4MD<3:0> PUP4 SV4 ALH4 LL4 X UP3MD<3:0> PUP3 SV3 ALH3 LL3 X UP2MD<3:0> PUP2 SV2 ALH2 LL2 X UP1MD<3:0> PUP1 SV1 ALH1 LL1 X UP4S UP3S UP2S UP1S X X X X X SWA SWB SPDT1<1:0> SPDT2<1:0> X X X IMUX<1:0> IVAL<1:0> X X X X X Reserved. Do not use. MLDVD MLCPD MADO MSDC MCRDY MADD MALD X X MUPR<4:1> MUPF<4:1> X Reserved. Do not use. X LDOE CPE LSDE CPDE HYSE RSTE X X X Reserved. Do not use. LDVD LCPD ADOU SDC CRDY ADD ALD X X UPR<4:1> UPF<4:1> X REFV<1:0> AOFF X = Don’t care. 36 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor ADC Register (Power-On State: 0000 0000 0000 00XX) MSB ADCE LSB STRT BIP RATE<2:0> The ADC register configures the ADC and starts a conversion. ADCE: ADC power-enable bit. ADCE = 1 powers up the ADC, and ADCE = 0 powers down the ADC. STRT: ADC start bit. STRT = 1 resets the registers inside the ADC filter and initiates a conversion or calibration. The conversion begins immediately after the 16th ADC control bit is clocked by the rising edge of SCLK. The initial conversion requires four conversion cycles for valid output data. If CONT = 0 when STRT is asserted, the ADC stops after a single conversion and holds the result in the DATA register. If CONT = 1 when STRT is asserted, the ADC performs continuous conversions at the rate specified by the RATE<2:0> bits until CONT is deasserted or ADCE is deasserted, powering down the ADC. The STRT bit is automatically deasserted after the initial conversion is complete (four conversion cycles; the ADC status bit ADD in the STATUS register asserts). The current ADC configurations are not affected if the ADC register is written with STRT = 0. This allows the ADC and mux configurations to be updated simultaneously with the S bit in the MUX register. BIP: Unipolar/bipolar bit. Set BIP = 0 for unipolar mode and BIP = 1 for bipolar mode. Unipolar-mode data is unsigned binary format and bipolar is two’s complement. See the ADC Transfer Functions section for more details. POL: Polarity flipper bit. POL = 1 flips the polarity of the differential signal to the ADC and the input to the signaldetect comparator (SDC). POL = 0 sets the positive mux output to the positive ADC and SDC inputs, and the negative mux output to the negative ADC and SDC inputs. POL = 1 sets the positive mux output to the negative ADC and SDC inputs, and the negative mux output to the positive ADC and SDC inputs. POL CONT ADCREF MODE<2:0> GAIN<1:0> X X CONT: Continuous conversion bit. CONT = 1 enables continuous conversions following completion of the first conversion or calibration(s) initiated by the STRT or S bit. Set CONT = 0 while asserting the STRT bit, or prior to asserting the S bit to perform a single conversion or to prevent conversions following a calibration. Set CONT = 0 to abort continuous conversions already in progress. When the ADC is stopped in this way, the last complete conversion result remains in the DATA register and the internal ADC state information is lost. Asserting the CONT bit does not restart the ADC, but results in continuous conversions once the ADC is restarted with the STRT or S bit. ADCREF: ADC reference source bit. Set ADCREF = 0 to select REF as the ADC reference. Set ADCREF = 1 to select AVDD as the ADC reference. To measure the AVDD voltage without having to attenuate the supply voltage, select REF and AGND as the differential inputs to the ADC, with POL = 0 and while ADCREF = 1. GAIN<1:0>: ADC gain-setting bits. These two bits select the gain of the ADC as shown in Table 5. Table 5. Setting the Gain of the ADC GAIN SETTING (V/V) GAIN1 GAIN0 1 0 0 2 0 1 4 1 0 8 1 1 ______________________________________________________________________________________ 37 MAX1358B Register Bit Descriptions MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor Table 6a. Setting the ADC Conversion Rate* CONTINUOUS CONVERSION RATE (sps) SINGLE CONVERSION RATE (sps) RATE2 RATE1 RATE0 10 2.5 0 0 0 40 10 0 0 1 50 12.5 0 1 0 60 15 0 1 1 200 50 1 0 0 240 60 1 0 1 400 100 1 1 0 477 128 1 1 1 Table 6b. Actual ADC Conversion Rates NOMINAL CONTINUOUS CONVERSION RATE (sps) DECIMATION RATIO ACTUAL CONTINUOUS CONVERSION RATE (sps) 10 1096 10.01 40 274 40.04 50 220 49.87 60 183 59.95 200 55 199.48 240 46 238.51 400 27 406.35 477 23 477.02 *Calculate the ADC sampling rate using the following equation: fHFCLK fS = 448 × decimation ratio where fHFCLK = 4.9152MHz nominally. 38 RATE<2:0>: ADC conversion-rate-setting bits. These three bits set the conversion rate of the ADC as shown in Table 6. The initial conversion requires four conversion cycles for valid data, and subsequent conversions require only one cycle (if CONT = 1). A full-scale input change can require up to five cycles for valid data if the digital filter is not reset with the STRT or S bit. MODE<2:0>: Conversion-mode bits. These three bits determine the type of conversion for the ADC as shown in Table 7. When the ADC finishes an offset calibration and/or gain calibration, the MODE<2:0> bits clear to 0 hex, the ADD bit in the STATUS register asserts, and an interrupt asserts on INT (or UPIO_ if programmed as DRDY) if MADD is unmasked. Perform a gain calibration after achieving the desired offset (calibrated or not). If an offset and gain calibration are performed together (MODE<2:0> = 7 hex), the offset calibration is performed first followed by the gain calibration, and the µC is interrupted by INT (or UPIO_ if programmed as DRDY) if MADD is unmasked only upon completion of both offset and gain calibration. After power-on or calibration, the ADC does not begin conversions until initiated by the user (see the ADCE and STRT bit descriptions in this section and see the S bit descriptions in the MUX Register section). See the GAIN CAL Register and OFFSET CAL Register sections for details on system calibration. Table 7. Setting the ADC Conversion Mode CONVERSION MODE MODE2 MODE1 MODE0 Normal 0 0 0 System Offset Calibration 0 0 1 System Gain Calibration 0 1 0 Normal 0 1 1 Normal 1 0 0 Self-Offset Calibration 1 0 1 Self-Gain Calibration 1 1 0 Self-Offset and Gain Calibration 1 1 1 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MSB S (ADR0) MUXP3 LSB MUXP2 MUXP1 MUXP0 The MUX register configures the positive and negative mux inputs and can start an ADC conversion. S (ADR0): Conversion start bit. The S bit is the LSB of the MUX register address byte. S = 1 resets the registers inside the ADC filter and initiates a conversion or calibration. The conversion begins immediately after the eighth MUX register data bit, when S = 1 and when writing to the MUX register. This allows the new MUX and ADC register settings to take effect simultaneously for a new conversion, if STRT = 0 during the last write to the ADC register. If the S bit is asserted and the command is a read from the MUX register, the conversion starts immediately after the S bit (ADR0) is clocked in by the rising edge of SCLK. Read the MUX register with S = 1 for the fastest method of initiating a conversion because only 8 bits are required. The subsequent MUX register read is valid, but can be aborted by raising CS with no harmful side effects. The initial conversion requires four conversion cycles for valid output data. If CONT = 0 and S = 1, the ADC stops after a single conversion and holds the result in the DATA register. If CONT = 1 and S = 1, the ADC performs continuous conversions at the rate Table 8. Selecting the Positive MUX Inputs MUXN3 MUXN2 MUXN1 MUXN0 specified by the RATE<2:0> bits until CONT deasserts or ADCE deasserts, powering down the ADC. When a conversion initiates using the S bit, the STRT bit asserts and deasserts automatically after the initial conversion completes. Writing to the MUX register with S = 0 causes the MUX settings to change immediately and the ADC continues in its prior state with its settings unaffected. When the ADC is powered down, MUX inputs are open. MUXP<3:0>: MUX positive input bits. These four bits select one of 10 inputs from the positive MUX to go to the positive output of the MUX as shown in Table 8. Any writes to the MUX register take effect immediately once the LSB (MUXN0) is clocked by the rising edge of SCLK. MUXN<3:0> MUX negative input bits. These four bits select one of 10 inputs from the negative MUX to go to the negative output of the MUX as shown in Table 9. Any writes to the MUX register take effect immediately once the LSB (MUXN0) is clocked by the rising edge of SCLK. The DATA register contains the data from the most recently completed conversion. The OFFSET CAL register contains the 24-bit data of the most recently completed offset calibration. Table 9. Selecting the Negative MUX Inputs POSITIVE MUX INPUT MUXP3 MUXP2 MUXP1 MUXP0 NEGATIVE MUX INPUT MUXN3 MUXN2 MUXN1 MUXN0 AIN1 0 0 0 0 TEMP- 0 0 0 0 SNO1 0 0 0 1 SNO2 0 0 0 1 FBA 0 0 1 0 OUTA 0 0 1 0 1 SCM1 0 0 1 1 SCM2 0 0 1 FBB 0 1 0 0 OUTB 0 1 0 0 SNC1 0 1 0 1 SNC2 0 1 0 1 0 IN1- 0 1 1 0 OUT1 0 1 1 TEMP+ 0 1 1 1 AIN2 0 1 1 1 REF 1 0 0 0 REF 1 0 0 0 AGND AGND Open X = Don’t care. 1 0 0 1 1 0 1 X 1 1 X X Open 1 0 0 1 1 0 1 X 1 1 X X X = Don’t care. ______________________________________________________________________________________ 39 MAX1358B MUX Register (Power-On State: 0000 0000) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor DATA Register (Power-On State: 0000 0000 0000 0000) MSB ADC15 ADC14 ADC13 ADC12 ADC11 ADC10 ADC9 ADC8 LSB ADC7 ADC6 ADC5 ADC4 ADC<15:0> Analog-to-digital conversion data bits. These 16 bits are the results from the most recently completed conversion. The data format is unsigned, ADC3 ADC2 ADC1 ADC0 binary for unipolar mode, and two’s complement for bipolar mode. OFFSET CAL Register (Power-On State: 0000 0000 0000 0000 0000 0000) MSB OFFSET23 OFFSET22 OFFSET21 OFFSET20 OFFSET19 OFFSET18 OFFSET17 OFFSET16 OFFSET15 OFFSET14 OFFSET13 OFFSET12 OFFSET11 OFFSET10 OFFSET9 OFFSET8 LSB OFFSET7 OFFSET6 OFFSET5 OFFSET4 OFFSET<23:0>: Offset-calibration bits. The data format is two’s complement and is subtracted from the ADC output before being written to the DATA register. The offset calibration allows input offset errors between VREF ±50% to be corrected in unipolar or bipolar mode. The MAX1358B can perform system offset calibration or self-offset calibration. Self-calibration performs a cal- OFFSET3 OFFSET2 OFFSET1 OFFSET0 ibration for the entire signal path. See the ADC Calibration section for more details. The ADC input voltage range specifications must always be obeyed, and the OFFSET CAL register effectively offsets the ADC digital scale to a “zero” value determined by the calibration. GAIN CAL Register (Power-On State: 1000 0000 0000 0000 0000 0000) MSB GAIN23 GAIN22 GAIN21 GAIN20 GAIN19 GAIN18 GAIN17 GAIN16 GAIN15 GAIN14 GAIN13 GAIN12 GAIN11 GAIN10 GAIN9 GAIN8 GAIN7 GAIN6 GAIN5 GAIN4 GAIN3 GAIN2 GAIN1 GAIN0 LSB GAIN<23:0>: Gain-calibration bits. The data format is unsigned binary with 23 bits to the right of the decimal point and scales the ADC output before being written to the DATA register. The gain calibration allows full-scale errors between -VREF/2 and +VREF/2 to be corrected in unipolar mode and full-scale errors between (+50% x VREF) and (+200% x VREF) in unipolar or bipolar mode. The MAX1358B can perform system gain calibration or self-gain calibration. Self-calibration performs a calibra- 40 tion for offsets in the ADC, and system calibration performs a calibration for the entire signal path. See the ADC Calibration section for more details. The ADC input voltage range specifications must always be obeyed, and the GAIN CAL register effectively scales the ADC digital output to a full-scale value determined by the calibration. The usable gain-calibration range is limited to less than the full GAIN CAL register digitalscaling range by the internal noise of the ADC. ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MSB DAE DBE OP1E X X X DACA9 DACA8 LSB DACA7 DACA6 DACA5 DACA4 Writing to the DACA_OP output register updates DACA on the rising SCLK edge of the LSB data bit. The output voltage can be calculated as follows: VOUTA = VREF x N/210 where VREF is the reference voltage for the DAC, and N is the integer value of the DACA<9:0> output register. The output buffer is in unity gain. The DACA data is 10 bits long and right justified. DACA3 DACA2 DACA1 DACA0 DAE: DACA enable bit. Set DAE = 1 to power up the DACA and the DACA output buffer in the MAX1358B. DBE: DACB enable bit. Set DBE = 1 to power up the DACB and the DACB output buffer in the MAX1358B. This bit is mirrored in the DACB_OP register. OP1E: OP1 power-enable bit. Set OP1E = 1 to power up OP1 in the MAX1358B. This bit is mirrored in the DACB_OP register. DACA<9:0>: DACA data bits. DACB_OP Register (Power-On State: 000X XX00 0000 0000) MSB DAE DBE OP1E X X X X X X X X X X X X LSB Writing to the DACB_OP output register updates DACB on the rising SCLK edge of the LSB. The output voltage can be calculated as follows: VOUTB = VREF x N/210 where VREF is the reference voltage for the DAC, and N is the integer value of DACB<9:0> output register. The output buffer is in unity gain. The DACB data is 10 bits long and right justified. X DAE: DACA enable bit. Set DAE = 1 to power up DACA and the DACA output buffer in the MAX1358B. This bit is mirrored in the DACA_OP register. DBE: DACB enable bit. Set DBE = 1 to power up DACB and the DACB output buffer in the MAX1358B. This bit is mirrored in the DACA_OP register. OP1E: OP1 power-enable bit. Set OP1E = 1 to power up OP1 in the MAX1358B. This bit is mirrored in the DACA_OP register. DACB<9:0>: DACB data bits. ______________________________________________________________________________________ 41 MAX1358B DACA_OP Register (Power-On State: 000X XX00 0000 0000) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor REF_SDC Register (Power-On State: 0000 0000) MSB REFV1 LSB REFV0 AOFF AON The REF_SDC register contains bits to control the reference voltage and signal-detect comparator. REFV<1:0>: Reference buffer voltage gain and enable bits. Enables the output buffer, and sets the gain and the voltage at the REF pin as shown in Table 10. Poweron state is off to enable an external reference to drive the REF pin without contention. AOFF: ADC and DAC/op-amp power-off bit. This bit provides a method for turning off several analog functions with a single write. Setting AOFF = 1 deasserts the ADCE in the ADC register and the DAE, DBE, and OP1E bits in the DACA_OP and DACB_OP registers, powering down these analog blocks. Setting AOFF = 0 has no effect. The AON bit has priority when both AON and AOFF bits are asserted. Most of the analog functions can be disabled with a single write to the REF_SDC register by using AOFF, REFV<1:0>, and SDCE. Table 10. Setting the Reference Output Voltage REFERENCE BUFFER GAIN (V/V) 42 REF OUTPUT VOLTAGE (V) REFV1 REFV0 Disabled Off (High Impedance at REF) 0 0 1.0 1.25 0 1 1.638 2.048 1 0 2.0 2.5 1 1 SDCE TSEL2 TSEL1 TSEL0 AON: ADC and DAC/op-amp power-on bit. This bit provides a method of turning on several analog functions with a single write. Setting AON = 1 asserts the ADCE bit in the ADC register and DAE, DBE, and OP1E bits in the DACA_OP and DACB_OP register, powering up these blocks. Setting AON = 0 has no effect. The AON bit has priority when both AON and AOFF bits are asserted. Most of the analog functions can be enabled with a single write to the REF_SDC register using AON, REFV<1:0>, and SDCE. SDCE: Signal-detect comparator power-enable bit. Set SDCE = 1 to power up the signal-detect comparator, and set SDCE = 0 to power down the signal-detect comparator. The ADCE bit in the ADC register must be set to 1 to use the signal-detect comparator. TSEL<2:0>: Threshold-select bits. These bits select the threshold for the signal-detect comparator as shown in Table 11. Table 11. Setting the Signal-Detect Comparator Threshold NOMINAL THRESHOLD (mV) TSEL2 TSEL1 TSEL0 0 0 X X 50 1 0 0 100 1 0 1 150 1 1 0 200 1 1 1 X = Don’t care. ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MSB ASEC19 ASEC18 ASEC17 ASEC16 ASEC15 ASEC14 ASEC13 ASEC12 ASEC11 ASEC10 ASEC9 ASEC8 ASEC7 ASEC6 ASEC5 ASEC4 LSB ASEC3 ASEC2 ASEC1 ASEC0 The AL_DAY register stores the second information of the time-of-day alarm. ASEC<19:0>: Alarm-second bits. These 20 bits store the time-of-day alarm, which corresponds to the lower 20 bits of the RTC second counter or SEC<19:0>. Program the time-of-day alarm trigger between 1s to just over 12 days beyond the current RTC second counter value in increments of 1s. Assert the AWE bit in the CLK_CTRL register (see the CLK_CTRL Register section) to enable writing to the AL_DAY register. Enabling the time-of-day alarm requires two writes to the CLK_CTRL register. Write the 20 alarmsecond bits in 3 bytes, MSB first. If CS is raised before the LSB is written, the alarm write is aborted, and the X X X X existing value remains. When the lower 20 bits in the RTC second counter match the contents of this register, the alarm triggers and asserts ALD in the STATUS register. It also asserts an interrupt on the INT pin unless masked by the MALD bit in the IMSK register. The part enters normal mode if an alarm triggers while in sleep mode. The timeof-day alarm is intended to trigger single events. Therefore, once it triggers, in the CLK_CTRL register, the ADE bit is automatically cleared, disabling the time-ofday alarm. Implement a recurring alarm with repeated software writes over the serial interface each time the time-of-day alarm triggers. The time-of-day alarm can also be programmed to output at the UPIO pins. When configured this way the MALD bit does not mask the UPIO alarm output. ______________________________________________________________________________________ 43 MAX1358B AL_DAY Register (Power-On State: 0000 0000 0000 0000 0000 XXXX) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor CLK_CTRL Register (Power-On State: 00X0 1111 0010 1110) MSB AWE ADE X RWE RTCE OSCE FLLE HFCE LSB CKSEL2 CKSEL1 CKSEL0 IO32E The CLK_CTR register contains the control bits for the RTC alarms and clocks. AWE: Alarm write-enable bit. Set AWE = 1 to write data to the AL_DAY register as well as the ADE bit in this register. When AWE = 0, all writes are prevented to the AL_DAY register and the ADE bit in this register. A second write to this register is required to change the value of the ADE bit. The power-on default state is 0. ADE: Alarm (time-of-day) enable bit. Set ADE = 1 to enable the time-of-day alarm, and set ADE = 0 to disable the time-of-day alarm. When enabled, the ALD bit in the STATUS register asserts when the RTC second counter time matches AL_DAY register. The device wakes up from sleep to normal mode if not already awake. The ADE bit can only be written if the AWE = 1 from a previous write. The power-on default state is 0. RWE: RTC write-enable bit. Set RWE = 1 prior to writing to the RTC register and the RTCE bit in this register. If RWE = 0, all writes are prevented to the RTC register as well as the RTCE bit in this register. The RWE signal takes effect after the rising edge of the 16th clock; 44 CK32E CLKE INTP WDE therefore, a second write to this register is required to change the value of the RTCE bit. The power-on default state is 0. RTCE: Real-time-clock enable bit. Set RTCE = 1 to enable the RTC, and set RTCE = 0 to disable the RTC. The RTC has a 32-bit second and an 8-bit subsecond counter. The power-on default state is 1. OSCE: 32kHz crystal-oscillator enable bit. Set OSCE = 1 to power up the 32kHz oscillator, and set OSCE = 0 to power down the oscillator. The power-on default state is 1. FLLE: Frequency-locked-loop enable bit. Set FLLE = 1 to enable the FLL, and set FLLE = 0 to disable the FLL. If HFCE = 1 and FLLE = 0, the internal high-frequency oscillator is enabled, but it is not frequency-locked to the 32kHz clock. When FLLE is asserted, it typically takes 3.5ms for the high-frequency clock to settle to within 1% of the 32kHz reference clock frequency. Switching the FLL on or off with this bit does not cause high-frequency clock glitching. The power-on default state is 1. ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor External clock frequencies applied to CLK32K are clock sources to the FLL, charge pump, and the signaldetect comparator. The default power-on state is 0. power in cases where the high-frequency clock is used internally but is not needed externally. If HFCE = 0, or if CLKE = 0, CLK remains low. The power-on default state is 1. INTP: Interrupt pin polarity bit. Set INTP = 1 to make INT an active-high output when asserted, and set INTP = 0 to make INT an active-low output when asserted. The power-on default state is 1. WDE: Watchdog-enable bit. Set WDE = 1 to enable the watchdog timer, which asserts RESET low within 500ms if the WATCHDOG register is not written. Set WDE = 0 to disable the watchdog timer. The power-on default state is 0. Table 12. Setting the CLK Frequency CLOCK FREQUENCY (kHz) CKSEL2 CKSEL1 CKSEL0 4915.2 0 0 0 2457.6 0 0 1 1228.8 0 1 0 614.4 0 1 1 32.768 1 0 0 16.384 1 0 1 8.192 1 1 0 4.096 1 1 1 CK32E: CLK32K output-buffer enable bit. Set CK32E = 1 to enable the CLK32K output buffer as long as OSCE = 1 and IO32E = 0; otherwise, the CK32E bit is not asserted. Set CK32E = 0 to disable the CLK32K output buffer. The power-on default state is 1. CLKE: CLK output-buffer enable bit. Set CLKE = 1 to enable the CLK output buffer. Set CLKE = 0 to disable the buffer. Disabling the buffer is useful for saving Table 13. Configuring the CLK32K as an Input or Output CLK32K CLK32K IO32E 32KIN, 32KOUT RTC, PWM, WDT CLOCK SOURCE FLL, C/P, SDC INPUT SOURCE ADC CLOCK SOURCE Output 1 0 XTAL attached XTAL XTAL FLL/HFCLK Input 0 1 XTAL attached XTAL CLK32K FLL/HFCLK ______________________________________________________________________________________ 45 MAX1358B HFCE: High-frequency-clock enable bit. Set HFCE = 1 to enable the internal high-frequency clock source, and set HFCE = 0 to disable the high-frequency clock source. If HFCE = 1 and CLKE = 1, the internal high-frequency oscillator is enabled and is present at CLK. The poweron default state is 1. CKSEL<2:0>: Clock selection bits. These bits select the FLL-based output clock frequency at the high-frequency CLK pin as shown in Table 12. The power-on default state is 001. IO32E: Input/output 32kHz clock select bit. Set IO32E = 0 to configure the CLK32K pin as an output, and set IO32E = 1 to configure the CLK32K pin as an input, regardless of the signal on the 32KIN pin as shown in Table 13. MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor RTC Register (Power-On State: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000) MSB SEC31 SEC30 SEC29 SEC28 SEC27 SEC26 SEC25 SEC24 SEC23 SEC22 SEC21 SEC20 SEC19 SEC18 SEC17 SEC16 SEC15 SEC14 SEC13 SEC12 SEC11 SEC10 SEC9 SEC8 SEC7 SEC6 SEC5 SEC4 SEC3 SEC2 SEC1 SEC0 LSB SUB7 SUB6 SUB5 SUB4 The RTC register stores the 40-bit second and subsecond count of the respective time-of-day and system clocks. SEC<31:0>: The second bits store the time-of-day clock settings. It is a 32-bit binary counter with 1s resolution that can keep time for a span of over 136 years. Firmware in the µC can translate this time count to units that are meaningful to the system (i.e., translate to calendar time or as an elapsed time from some predefined time = 0, such as January 1, 2000). The RTC runs continuously as long as RTCE = 1 (see the CLK_CNTL Register section) and does not stop for reads or writes. The counter increments when the subsecond counter overflows. Set RWE = 1 to enable writing to the RTC register. After writing to RWE, perform another write and set RTCE = 1 to enable the RTC. A 40-bit burst write operation, starting with SEC31 and finishing with SUB0 is required to set the RTC second and subsecond bits. If CS is brought high before the 40th rising SCLK edge, the write is aborted and the RTC contents are unchanged. The RTC register is loaded on the rising SCLK edge of the 40th bit (SUB0). A 40-bit burst read operation, starting with SEC31 and finishing with SUB0, is required to retrieve the current RTC second and subsecond counts. The read command can be aborted prior to receiving the 40th bit (SUB0) by raising CS and any RTC data read to that point is valid. When the read command is received, a snapshot of a valid RTC second count is latched to avoid reading an erroneous, transitioning RTC value. Due to the asynchronous nature of RTC reads, it is possible to have a maximum 1s error between the actual and reported times from the time-of-day clock. To prevent the data from changing during a read operation, complete reads 46 SUB3 SUB2 SUB1 SUB0 of the RTC register in less than 1ms. The power-on default state is 0000 0000 hex. SUB<7:0>: The subsecond bits store the system clock. This 8-bit binary counter has 3.9ms resolution (1/256Hz) and a span of 1s. The subsecond counter increments in single counts from 00 hex to FF hex before rolling over again to 00 hex, at which time the RTC second counter (SEC<31:0>) increments. The RTC runs continuously (as long as RTCE = 1) and does not stop for reads or writes. A 256Hz clock, derived from the 32kHz crystal, increments this counter. Set the RWE = 1 bit to enable writing to the RTC register. After writing to RWE, perform another write, setting RTCE = 1, to enable the RTC. A 40-bit burst write operation, starting with SEC31 and finishing with SUB0, is required to set the RTC second and subsecond bits. If CS is brought high before the 40th rising SCLK edge, the write is aborted and the RTC contents are unchanged. The RTC register is loaded on the rising SCLK edge of the 40th bit (SUB0). A 40-bit burst read operation, starting with SEC31 and finishing with SUB0, is required to retrieve the current RTC second and subsecond counts. The read command can be aborted prior to receiving the 40th bit (SUB0) by raising CS, and any RTC data read to that point is valid. When the read command is received, a snapshot of a valid RTC second count is latched to avoid reading an erroneous, transitioning RTC value. Due to the asynchronous nature of RTC reads, it is possible to have a maximum 1s error between the actual and reported times from the time-of-day clock. To prevent the data from changing during a read operation, complete reads of the RTC registers occur in less than 1ms. The poweron default state is 00 hex. ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MSB PWME FSEL2 FSEL1 FSEL0 SWAH SWAL SWBH SPD1 SPD2 X X X X X SWBL LSB The PWM_CTRL register contains control bits for the 8-bit PWM. PWME: PWM-enable bit. Set PWME = 1 to enable the internal PWM, and set PWME = 0 to disable the internal PWM. Enable the high-frequency clock before enabling the PWM when using input clock frequencies above 32.768kHz. The power-on default state is 0. FSEL<2:0>: Frequency selection bits. Selects the PWM input clock frequency as shown in Table 14. The power-on default is 000. Table 14. Setting the PWM Frequency PWM INPUT FREQUENCY* FSEL2 FSEL1 FSEL0 (kHz) 4915.2** 0 0 0 2457.6** 0 0 1 1228.8** 0 1 0 32.768 0 1 1 8.192 1 0 0 1.024 1 0 1 0.256 1 1 0 0.032 1 1 1 *The lower PWM frequencies are useful for power-supply duty cycling to conserve battery life and enable a single-battery cellpowered system. The higher frequencies allow reasonably small, external components for RC filtering when used as a DAC for bias adjustments. **When the part is in sleep mode, the HFCLK is shut down. In this case, PWM frequencies above 32kHz are not available (see SPWME in the SLEEP_CFG Register section). X SWAH: SWA-switch PWM-high control bit. Set SWAH = 1 to enable the PWM output to directly control the SWA switch. When SWAH = SWAL, the PWM output is disabled from controlling the SWA switch. When SWAH = 1, a PWM high output closes the SWA switch and a PWM low output opens the SWA switch. The PWM high output refers to the beginning of the period when the output is logic-high. See Table 17 for more details. The power-on default is 0. SWAL: SWA-switch PWM-low control bit. Set SWAL = 1 to enable the inverted PWM output to directly control the SWA switch. When SWAH = SWAL, the PWM output is disabled from controlling the SWA switch. When SWAL = 1, a PWM low output closes the SWA switch and a PWM high output opens the SWA switch. The PWM low output refers to the end of the period when the output is logic-low. See Table 17 for more details. The power-on default is 0. SPD1: SPDT1-switch PWM drive control bit. Set SPD1 = 1 to enable the PWM output to directly control the SPDT1 switch, and set SPD1 = 0 to disable the PWM output controlling the SPDT1 switch. The SPDT1<1:0> bits, the UPIO pins (if programmed), and the PWM output (if enabled), determine the SPDT1-switch state. See Table 18 for more details. The power-on default is 0. SPD2: SPDT2-switch PWM drive control bit. Set SPD2 = 1 to enable the PWM output to directly control the SPDT2 switch, and set SPD2 = 0 to disable the PWM output controlling the SPDT2 switch. The SPDT2<1:0> bits, the UPIO pins (if programmed), and the PWM output (if enabled), determine the SPDT2-switch state. See Table 19 for more details. The power-on default is 0. ______________________________________________________________________________________ 47 MAX1358B PWM_CTRL Register (Power-On State: 0000 0000 00XX XXXX) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor PWM_THTP Register (Power-On State: 0000 0000 0000 0000) MSB PWMTH7 PWMTH6 PWMTH5 PWMTH4 PWMTH3 PWMTH2 PWMTH1 PWMTH0 LSB PWMTP7 PWMTP6 PWMTP5 PWMTP4 The PWM_THTP register contains the bits that set the PWM on-time and period. PWMTH<7:0>: PWM time high bits. These bits define the PWM on (or high)-time and when combined with the PWMTP<7:0> bits, they determine the duty cycle and period. The on-time duty cycle is defined as: (PWMTH<7:0> + 1)/(PWMTP<7:0> + 1) To get 50% duty cycle, set PWMTH<7:0> to 126 decimal and PWMTP<7:0> to 253 decimal. Note that setting PWMTP<7:0> to 255 decimal is not valid as the denominator in the above formula becomes 0. A 100% duty cycle (i.e., always on) is possible with a value of PWMTH<7:0> ≥ PWMTP<7:0> > 0. A 0% duty cycle is possible by setting PWMTH<7:0> = 0 or PWME = 0 in the PWM_CTRL register. If the PWM is selected to drive the UPIO_ pin(s), the ALH_ bit(s) (UPIO_CTRL register) determine the on-time polarity at the beginning of the PWM cycle. If ALH_ = 1, the on-time at the start of the PWM period causes a logic-high level (DV DD or CPOUT) at the UPIO_ pin. When ALH_ = 0, it causes a logic-low level (DGND) during the on-time. When the PWM output drives the SWA/B switches, the SWA(B)H or SWA(B)L bits in the PWM_CTRL register determine which PWM phase closes these switches. The SPDT1 and SPDT2 switches do not have PWM polarity inversion bits (see the SPDT1<1:0> and SPDT2<1:0> bit descriptions in the SW_CTRL Register section), but their effective polarity is set by how the switches are connected externally. The power-on default is 00 hex. PWMTP<7:0>: PWM time period bits. These bits control the PWM output period defined. The PWM output period is defined as: PWMTP3 PWMTP2 PWMTP1 WATCHDOG Register (Power-On State: N/A) Writing to the WATCHDOG register address sets the watchdog timer to 0ms. If the watchdog is enabled (WDE = 1) and the WATCHDOG register is not written to before the 750ms expiration, RESET asserts low for 250ms and the watchdog timer restarts at 0ms when the watchdog timer is enabled. There are no data bits for this register, and the watchdog timer is reset on the rising edge of SCLK during the ADR0 bit in the WATCHDOG register address control byte. Figure 17 shows an example of watchdog timing. NORM_MD Register (Power-On State: N/A) Exit sleep mode and enter normal mode by writing to the NORM_MD register. The specific normal-mode state of all circuit blocks is set by the user, who must configure the individual power-enable bits before entering sleep mode (Table 15). There are no data bits for this register, and normal mode begins on the rising edge of SCLK during the ADR0 bit in the NORM_MD register address control byte. SLEEP Register (Power-On State: N/A) Enter sleep mode by writing to the SLEEP register. This low-power state overrides most of the normal powercontrol bits. Table 15 shows which functions are off, which functions are unaffected (ADE, RTCE, LSDE, and HYSE), and which functions are controlled by special sleep-mode bits (SOSCE, SCK32E, and SPWME) while in sleep mode. There are no data bits for this register, and sleep mode begins on the rising edge of SCLK during the ADR0 bit in the SLEEP register address control byte. (PWMTP<7:0> + 1)/(PWM input frequency) Set the PWM input frequency by selecting the FSEL<2:0> bits as described in Table 14. The poweron default is 00 hex. 48 PWMTP0 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX1358B Table 15. Normal-Mode and Sleep-Register Summary REGISTER NAME ADC DACA_OP, DACB_OP REF_SDC CLK_CTRL PWM_CTRL PS_VMONS TEMP_CTRL UPIO_CTRL CIRCUIT BLOCK DESCRIPTION POR DEFAULT NORMAL MODE SLEEP ADC ADCE = 0 ADCE OFF DACA DAE = 0 DAE OFF DACB DBE = 0 DBE OFF OP1 OP1E = 0 OP1E OFF Reference Buffer Gain and Enable REFV<1:0> = 00 REFV<1:0> OFF Signal-Detect Comparator SDCE = 0 SDCE OFF Time-of-Day Alarm Enable ADE = 0 ADE ADE RTC RTCE = 1 RTCE RTCE CK32 XTAL Oscillator OSCE = 1 OSCE SOSCE CK32 Output Buffer CK32E = 1 CK32E SCK32E High-Frequency Clock HFCE = 1 HFCE OFF High-Frequency Clock Output Buffer CLKE = 1 CLKE OFF FLL Enable FLLE = 1 FLLE OFF Watchdog Timer WDE = 0 WDE OFF PWM PWME = 0 PWME SPWME Linear Regulator LDOE = 0 LDOE OFF Charge-Pump Doubler CPE = 0 CPE OFF CPOUT Voltage Monitor CPDE = 0 CPDE OFF 1.8V DVDD Monitor LSDE = 1 LSDE LSDE 1.8V Monitor Hysteresis HYSE = 0 HYSE HYSE Temperature Sense Source IMUX<1:0> = 00 IMUX<1:0> OFF UPIO_ Function UP_MD<3:0> = 0 hex UP_MD<3:0> UP_MD<3:0> UPIO_ Pullup PUP_ = 1 PUP_ PUP_ UPIO_ Supply Voltage SV_ = 0 SV_ SV_ UPIO_ Assertion Level ALH_ = 0 ALH_ ALH_ ______________________________________________________________________________________ 49 MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor SLEEP_CFG Register (Power-On State: 1100 XXXX) MSB SLP (ADR0) LSB SOSCE SCK32E SPWME SHDN The SLEEP_CFG register allows users to program specific behavior for the 32kHz oscillator, buffer, and PWM in sleep mode. It also contains a sleep-control bit (SLP) to enable sleep mode. SLP (ADR0): Sleep bit. The SLP bit is the LSB in the SLEEP_CFG address control byte. Set SLP = 1 to assert the SHDN bit and enter sleep mode. Writing the register with SLP = 0 or reading with SLP = 0 or SLP = 1 has no effect on the SHDN bit. SOSCE: Sleep-mode 32kHz crystal oscillator enable bit. SOSCE = 1 enables the 32kHz oscillator in sleep mode, and SOSCE = 0 disables it in sleep mode, regardless of the state of the OSCE bit. The power-on default is 1. SCK32E: Sleep-mode CK32K-pin output-buffer enable bit. SCK32E = 1 enables the 32kHz output buffer in sleep mode, and SCK32E = 0 disables it in sleep mode, regardless of the state of the CK32E bit. The power-on default is 1. X X X X SPWME: Sleep-mode PWM enable bit. SPWME = 1 enables the internal PWM in sleep mode, and SPWME = 0 disables it in sleep mode, regardless of the state of the PWME bit. Input frequencies are limited to 32.768kHz or lower since the high-frequency clock is disabled in sleep mode. SOSCE must be asserted to have 32kHz available as an input to the PWM. The power-on default is 0. SHDN: Shutdown bit. This bit is read only. SHDN is asserted by writing to the SLEEP register address or by writing to the SLEEP_CFG register with SLP = 1. When SHDN is asserted, the device is in sleep mode even if the SLEEP or SLEEP function on the UPIO is deasserted. The SHDN bit is deasserted by writing to the NORM_MD register or by other defined events. Events that cause SHDN to be deasserted are a day alarm or an edge on the UPIO wake-up pin causing wake-up to be asserted. The power-on default is 0. RESET 32K DIVIDEBY-8192 WDE D Q CK Q Q D 4Hz CK Q R R POR WDW WATCHDOG TIMER 750ms 4Hz CLOCK 2-BIT COUNTER X 0 1 2 0 1 0 1 2 3 0 1 2 0 SPI WRITES RESET WDE = 1 WATCHDOG ADDRESS WATCHDOG ADDRESS WATCHDOG ADDRESS 250ms Figure 17. Watchdog Timer Architecture 50 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MSB UP4MD3 LSB UP4MD2 UP4MD1 UP4MD0 The UPIO4_CTRL register configures the UPIO4 pin functionality. UP4MD<3:0>: UPIO4-mode selection bits. These bits configure the mode for the UPIO4 pin. See Table 16 for a detailed description. The power-on default is 0 hex. PUP4: Pullup UPIO4 control bit. Set PUP4 = 1 to enable a weak pullup resistor on the UPIO4 pin, and set PUP4 = 0 to disable it. The pullup resistor is connected to either DVDD or CPOUT as programmed by the SV4 bit. The pullup is enabled only when UPIO4 is configured as an input. Open-drain behavior can be simulated at UPIO4 by setting the mode to GPO with LL4 = 0 and by changing the mode to GPI with PUP4 = 0, allowing external high pullup. The power-on default is 1. SV4: Supply-voltage UPIO4 selection bit. Set SV4 = 0 to select DVDD as the supply voltage for the UPIO4 pin, and set SV4 = 1 to select CPOUT as the supply voltage. The selected supply voltage applies to all modes for the UPIO4 pin. The power-on default is 0. PUP4 SV4 ALH4 LL4 ALH4: Active logic-level assertion high UPIO4 bit. Set ALH4 = 0 to define the input or output assertion level for UPIO4 as low except when in GPI and GPO modes. Set ALH4 = 1 to define the input or output assertion level as high. For example, asserting ALH4 defines the UPIO4 output signal as ALARM, while deasserting ALH4 defines it as ALARM. Similarly, asserting ALH4 defines the UPIO4 input signal as WU, while deasserting ALH4 defines it as WU. The power-on default is 0. LL4: Logic-level UPIO4 bit. When UPIO4 is configured as GPO, LL4 = 0 sets the output to a logic-low and LL4 = 1 sets the output to a logic-high. A read of LL4 returns the voltage level at the UPIO4 pin at the time of the read, regardless of how it is programmed. The power-on default is 0. UPIO3_CTRL Register (Power-On State: 0000 1000) MSB UP3MD3 LSB UP3MD2 UP3MD1 UP3MD0 The UPIO3_CTRL register configures the UPIO3 pin functionality. UP3MD<3:0>: UPIO3-mode selection bits. These bits configure the mode for the UPIO3 pin. See Table 16 for a detailed description. The power-on default is 0 hex. PUP3: Pullup UPIO3 control bit. Set PUP3 = 1 to enable a weak pullup resistor on the UPIO3 pin, and set PUP3 = 0 to disable it. The pullup resistor is connected to either DVDD or CPOUT as programmed by the SV3 bit. The pullup is enabled only when UPIO3 is configured as an input. Open-drain behavior can be simulated at UPIO3 by setting the mode to GPO with LL3 = 0 and by changing the mode to GPI with PUP3 = 0, allowing external high pullup. The power-on default is 1. SV3: Supply-voltage UPIO3 selection bit. Set SV3 = 0 to select DVDD as the supply voltage for the UPIO3 pin, and set SV3 = 1 to select CPOUT as the supply voltage. The selected supply voltage applies to all modes for the UPIO3 pin. The power-on default is 0. PUP3 SV3 ALH3 LL3 ALH3: Active logic-level assertion high UPIO3 bit. Set ALH3 = 0 to define the input or output assertion level for UPIO3 as low except when in GPI and GPO modes. Set ALH3 = 1 to define the input or output assertion level as high. For example, asserting ALH3 defines the UPIO3 output signal as ALARM, while deasserting ALH3 defines it as ALARM. Similarly, asserting ALH3 defines the UPIO3 input signal as WU, while deasserting ALH3 defines it as WU. The power-on default is 0. LL3: Logic-level UPIO3 bit. When UPIO3 is configured as GPO, LL3 = 0 sets the output to a logic-low and LL3 = 1 sets the output to a logic-high. A read of LL3 returns the voltage level at the UPIO3 pin at the time of the read, regardless of how it is programmed. The power-on default is 0. ______________________________________________________________________________________ 51 MAX1358B UPIO4_CTRL Register (Power-On State: 0000 1000) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor UPIO2_CTRL Register (Power-On State: 0000 1000) MSB UP2MD3 LSB UP2MD2 UP2MD1 UP2MD0 The UPIO2_CTRL register configures the UPIO2 pin functionality. UP2MD<3:0>: UPIO2-mode selection bits. These bits configure the mode for the UPIO2 pin. See Table 16 for a detailed description. The power-on default is 0 hex. PUP2: Pullup UPIO2 control bit. Set PUP2 = 1 to enable a weak pullup resistor on the UPIO2 pin, and set PUP2 = 0 to disable it. The pullup resistor is connected to either DVDD or CPOUT as programmed by the SV2 bit. The pullup is enabled only when UPIO2 is configured as an input. Open-drain behavior can be simulated at UPIO2 by setting the mode to GPO with LL2 = 0 and by changing the mode to GPI with PUP2 = 0, allowing external high pullup. The power-on default is 1. SV2: Supply-voltage UPIO2 selection bit. Set SV2 = 0 to select DVDD as the supply voltage for the UPIO2 pin, and set SV2 = 1 to select CPOUT as the supply voltage. The selected supply voltage applies to all modes for the UPIO2 pin. The power-on default is 0. PUP2 SV2 ALH2 LL2 ALH2: Active logic-level assertion high UPIO2 bit. Set ALH2 = 0 to define the input or output assertion level for UPIO2 as low except when in GPI and GPO modes. Set ALH2 = 1 to define the input or output assertion level as high. For example, asserting ALH2 defines the UPIO2 output signal as ALARM, while deasserting ALH2 defines it as ALARM. Similarly, asserting ALH2 defines the UPIO2 input signal as WU, while deasserting ALH2 defines it as WU. The power-on default is 0. LL2: Logic-level UPIO2 bit. When UPIO2 is configured as GPO, LL2 = 0 sets the output to a logic-low and LL2 = 1 sets the output to a logic-high. A read of LL2 returns the voltage level at the UPIO2 pin at the time of the read, regardless of how it is programmed. The power-on default is 0. UPIO1_CTRL Register (Power-On State: 0000 1000) MSB UP1MD3 LSB UP1MD2 UP1MD1 UP1MD0 The UPIO1_CTRL register configures the UPIO1 pin functionality. UP1MD<3:0>: UPIO1-mode selection bits. These bits configure the mode for the UPIO1 pin. See Table 16 for a detailed description. The power-on default is 0 hex. PUP1: Pullup UPIO1 control bit. Set PUP1 = 1 to enable a weak pullup resistor on the UPIO1 pin, and set PUP1 = 0 to disable it. The pullup resistor is connected to either DVDD or CPOUT as programmed by the SV1 bit. The pullup is enabled only when UPIO1 is configured as an input. Open-drain behavior can be simulated at UPIO1 by setting the mode to GPO with LL1 = 0 and by changing the mode to GPI with PUP1 = 0, allowing external high pullup. The power-on default is 1. SV1: Supply-voltage UPIO1 selection bit. Set SV1 = 0 to select DVDD as the supply voltage for the UPIO1 pin, and set SV1 = 1 to select CPOUT as the supply volt- 52 PUP1 SV1 ALH1 LL1 age. The selected supply voltage applies to all modes for the UPIO1 pin. The power-on default is 0. ALH1: Active logic-level assertion high UPIO1 bit. Set ALH1 = 0 to define the input or output assertion level for UPIO1 as low except when in GPI and GPO modes. Set ALH1 = 1 to define the input or output assertion level as high. For example, asserting ALH1 defines the UPIO1 output signal as ALARM, while deasserting ALH1 defines it as ALARM. Similarly, asserting ALH1 defines the UPIO1 input signal as WU, while deasserting ALH1 defines it as WU. The power-on default is 0. LL1: Logic-level UPIO1 bit. When UPIO1 is configured as GPO, LL1 = 0 sets the output to a logic-low and LL1 = 1 sets the output to a logic-high. A read of LL1 returns the voltage level at the UPIO1 pin at the time of the read, regardless of how it is programmed. The power-on default is 0. ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX1358B Table 16. UPIO Mode Configuration UP4MD<3:0>, UP3MD<3:0>, UP2MD<3:0>, UP1MD<3:0> MODE DESCRIPTION 0 0 0 0 GPI General-purpose digital input. Active edges detected by UPR_ or UPF_ status register bits. ALH_ has no effect with this setting. 0 0 0 1 GPO General-purpose digital output. Logic level set by LL_ bit. ALH_ has no effect with this setting. 0 0 1 0 SWA or SWA Digital input. DAC A buffer switch control. See the SWA bit description in the SW_CTRL Register section. 0 0 1 1 SWB or SWB Digital input. DAC B buffer switch control. See the SWB bit description in the SW_CTRL Register section. 0 1 0 0 SPDT1 or SPDT1 Digital input. SPDT1 switch control. See the SPDT1<1:0> bit description in the SW_CTRL Register section. 0 1 0 1 SPDT2 or SPDT2 Digital input. SPDT2 switch control. See the SPDT2<1:0> bit description in the SW_CTRL Register section. 0 SLEEP or SLEEP Sleep-mode digital input. Overrides power-control register and puts the part into sleep mode when asserted. The clock buffers must be powered down separately. When deasserted, power mode is determined by the SHDN bit. WU or WU Wake-up digital input. Asserted edge clears SHDN bit. Reserved Reserved. Do not use these settings. 0 1 1 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 PWM digital output. Signal defined by the PWM_CTRL register. PWM on (or high or “1”); assertion level defined by the ALH_ bit. When PWM is disabled (PWME = 0), the UPIO pin idles high (DVDD or CPOUT) if ALH = 1, and low (DGND) if ALH = 0. 1 0 1 1 PWM or PWM 1 1 0 0 SHDN or SHDN Power-supply shutdown digital output. Equivalent to SHDN bit. Power-on default of GPI with pullup ensures initial power-supply turn-on when UPIO is connected to a power supply with a SHDN input. 1 1 0 1 AL_DAY or AL_DAY RTC alarm digital output. Asserts for time-of-day alarm events; equivalent to ALD in STATUS register. 1 1 1 0 Reserved 1 1 1 1 DRDY or DRDY Reserved. Do not use these settings. ADC data-ready digital output. Asserts when analog-to-digital conversion or calibration completes. Not masked by MADD bit. Note: When multiple UPIO inputs are configured for the same input function, the inputs are ORed together. ______________________________________________________________________________________ 53 MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor UPIO_SPI Register (Power-On State: 0000 XXXX) MSB LSB UP4S UP3S UP2S UP1S X The UPIO_SPI pass-through control register bits map the serial interface signals to the UPIO pins, allowing the DAS to drive other devices at CPOUT or DVDD voltage levels, depending on the SV_ bit setting found in the UPIO_CTRL register. Individual bits are provided to set only the desired UPIO inputs to the SPI passthrough mode. This mode becomes active when CS is driven high to complete the write to this register, and remains active as long as CS stays high (i.e., multiple pass-through writes are possible). The SPI passthrough mode is deactivated immediately when CS is pulled low for the next DAS write. WRITE TO DAS TO ENABLE SPI MODE X X UP4S: UPIO4 SPI pass-through-mode enable bit. A logic 1 maps the inverted CS signal to the UPIO4 pin. Therefore, UPIO4 is low (near DGND) when SPI passthrough mode is active, and is high (near DV DD or CPOUT) when the mode is inactive. A logic 0 disables the UPIO4 SPI pass-through mode. The power-on default is 0. UP3S: UPIO3 SPI pass-through-mode enable bit. A logic 1 maps the SCLK signal to UPIO3 (directly with no inversion), while a logic 0 disables the UPIO3 SPI passthrough mode. The power-on default is 0. UP2S: UPIO2 SPI pass-through-mode enable bit. A logic 1 maps the DIN signal to UPIO2 (directly with no inversion), while a logic 0 disables the UPIO2 SPI passthrough mode. The power-on default is 0. UP1S: UPIO1 SPI pass-through-mode enable bit. A logic 1 maps the UPIO1 input signal to DOUT (directly with no inversion), while a logic 0 disables the UPIO1 SPI pass-through mode. The power-on default is 0. The UPIO_ state (both before and after the SPI passthrough mode) is set by the UP_MD<3:0> and LL_ bits. When a UPIO is configured for SPI pass-through mode and the CS is high, UPR_, UPF_, and LL_ continue to detect UPIO_ edges, which can still generate interrupts. See Figure 18 for an SPI pass-through timing diagram. CS X NORMAL WRITE TO DAS WRITE THROUGH DAS TO UPIO DEVICE SCLK DIN DN DN-1 DN-2 DN-3 D3 D2 D1 D0 EN EN-1 EN-2 EN-3 DOUT X X X X E3 E2 E1 E0 D7 D6 D5 D4 D3 UPIO4 SET BY UPIO4_CTRL REGISTER SET BY UPIO4_CTRL REGISTER UPIO3 SET BY UPIO3_CTRL REGISTER SET BY UPIO3_CTRL REGISTER UPIO2 SET BY UPIO2_CTRL REGISTER UPIO1 SET BY UPIO1_CTRL REGISTER EN EN-1 EN-2 EN-3 X X X X SET BY UPIO2_CTRL REGISTER E3 E2 E1 E0 SET BY UPIO1_CTRL REGISTER Figure 18. SPI Pass-Through Timing Diagram 54 D2 ______________________________________________________________________________________ D1 D0 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MSB SWA LSB SWB SPDT11 SPDT10 The switch-control register controls the two SPDT switches (SPDT1 and SPDT2) and the DACA output buffer SPST switch (SWA). Control this switch by the serial bits in this register, by any of the UPIO pins that are enabled for that function, or by the PWM. SWA: DACA output buffer SPST-switch A control bit. The SWA bit, the UPIO inputs (if configured), and the PWM (if configured) control the state of the SWA switch as shown in Table 17. The UPIO_ states of 0 and 1 in the table correspond to respective deasserted and asserted logic states as defined by the ALH_ bit of the UPIO_CTRL register. If a UPIO is not configured for this mode, its value applied to the table is 0. The PWM states of 0 and 1 in the table correspond to the respective PWM off (or low) and on (or high) states defined by the SWAH and SWAL bits (see the PWM_CTRL Register section). If the PWM is not configured for this mode, its value applied to the table is 0. The power-on default is 0. SWB: DACB output buffer SPST-switch B control bit. The SWB bit, the UPIO inputs (if configured), and the PWM (if configured) control the state of the SWB switch as shown in Table 18. The UPIO_ states of 0 and 1 in the table correspond to respective deasserted and asserted logic states as defined by the ALH_ bit (see the UPIO_CTRL Register section). If a UPIO is not configured for this mode, its value applied to the table is 0. The PWM states of 0 and 1 in the table correspond to the respective PWM off (or low) and on (or high) states defined by the SWBH and SWBL bits (see the PWM_CTRL Register section). If the PWM is not configured for this mode, its value applied to the table is 0. The power-on default is 0. SPDT1<1:0>: Single-pole double-throw switch 1 control bits. The SPDT1<1:0> bits, the UPIO pins (if configured), and the PWM (if configured) control the state of the switch as shown in Table 18. The UPIO_ states of 0 and 1 in the table correspond to respective deasserted and asserted logic states as defined by the ALH_ bit of the UPIO_CTRL register. If a UPIO is not configured for this mode, its value applied to Table 18 is 0. The PWM states of 0 and 1 in Table 18 correspond to the respective PWM off (low) and on (high) states defined by the SPD1 bit in the PWM_CTRL register. If the PWM is not configured for this mode, its value applied to Table 18 is 0. The power-on default is 00. SPDT21 SPDT20 X X Table 17. SWA States SW_ BIT* UPIO_* PWM* SW_ SWITCH STATE 0 0 0 X X 1 Switch open Switch closed X 1 X Switch closed 1 X X Switch closed X = Don’t care. *Switch SW_ control is effectively an OR of the SW_ bit, UPIO_ pins, and PWM. Table 18. SPDT Switch 1 States SPDT1<1:0> UPIO_* PWM* SPDT1 SWITCH STATE 0 0 0 0 SNO1 open, SNC1 open 0 X 0 X X 1 SNO1 closed, SNC1 closed 1 X 0 1 SNO1 closed, SNC1 closed X X SNO1 closed, SNC1 closed 1 0 0 0 SNC1 closed, SNO1 open 1 X X 1 SNC1 open, SNO1 closed 1 X 1 X SNC1 open, SNO1 closed 1 1 X X SNC1 open, SNO1 closed X = Don’t care. *Switch SPDT1 control is effectively an OR of the SPDT10 bit, the UPIO_ pins, and the PWM output. The SPDT11 bit determines if the switches open and close together or if they toggle. Table 19. SPDT Switch 2 States SPDT2<1:0> UPIO_* PWM* SPDT2 SWITCH STATE 0 0 0 0 SNO2 open, SNC2 open 0 X X 1 SNO2 closed, SNC2 closed 0 X 1 X SNO2 closed, SNC2 closed 0 1 X X SNO2 closed, SNC2 closed 1 0 0 0 SNC2 closed, SNO2 open 1 X X 1 SNC2 open, SNO2 closed 1 X 1 X SNC2 open, SNO2 closed 1 1 X X SNC2 open, SNO2 closed X = Don’t care. *Switch SPDT2 control is effectively an OR of the SPDT20 bit, the UPIO_ pins, and the PWM output. The SPDT21 bit determines if the switches open and close together or if they toggle. ______________________________________________________________________________________ 55 MAX1358B SW_CTRL Register (Power-On State: 0000 00XX) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor SPDT2<1:0>: Single-pole double-throw switch 2 control bits. The SPDT2<1:0> bits, the UPIO pins (if configured), and the PWM (if configured) control the state of the switch as shown in Table 19. The UPIO_ states of 0 and 1 in the table correspond to respective deasserted and asserted logic states as defined by the ALH_ bit in the UPIO_CTRL register. If a UPIO is not configured for this mode, its value applied to Table 19 is 0. The PWM states of 0 and 1 in Table 19 correspond to the respective PWM off (low) and on (high) states defined by the SPD2 bit in the PWM_CTRL register. If the PWM is not configured for this mode, its value applied to Table 19 is 0. The power-on default is 00. TEMP_CTRL Register (Power-On State: 0000 XXXX) MSB IMUX1 LSB IMUX0 IVAL1 IVAL0 X X X X The temperature-sensor control register controls the internal and external temperature measurement. IMUX<1:0>: Internal current-source MUX bits. Selects the pin to be driven by the internal current sources as shown in Table 20. The power-on default is 00. IVAL<1:0>: Internal current-source value bits. Selects the value of the internal current source as shown in Table 21. The power-on default is 00. Table 20. Selecting Internal Current Source Table 21. Setting the Current Level CURRENT SOURCE Disabled Internal temperature sensor AIN1 AIN2 56 IMUX1 0 0 1 1 IMUX0 0 1 0 1 CURRENT TYPICAL CURRENT (µA) IVAL1 IVAL0 I1 I2 I3 I4 4 60 64 120 0 0 1 1 0 1 0 1 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MSB MLDVD MLCPD MADO MSDC MCRDY MADD MALD X LSB MUPR4 MUPR3 MUPR2 MUPR1 The IMSK register determines which bits of the STATUS register generate an interrupt on INT. The bits in this register do not mask output signals routed to UPIO since the output signals are masked by disabling that UPIO function. MLDVD: LDVD status bit mask. Set MLDVD = 0 to enable the LDVD status bit interrupt to INT, and set MLDVD = 1 to mask the LDVD status bit interrupt. The power-on default value is 1. MLCPD: LCP status bit mask. Set MLCPD = 0 to enable the LCP status bit interrupt to INT, and set MLCPD = 1 to mask the LCP status bit interrupt. The power-on default value is 1. MADO: ADO status bit mask. Set MADO = 0 to enable the ADO status bit interrupt to INT, and set MADO = 1 to mask the ADO status bit interrupt. The power-on default value is 1. MSDC: SDC status bit mask. Set MSDC = 0 to enable the SDC status bit interrupt to INT, and set MSDC = 1 to mask the SDC status bit interrupt. The power-on default value is 1. MCRDY: CRD status bit mask. Set MCRDY = 0 to enable the CRDY status bit interrupt to INT, and set MUPF4 MUPF3 MUPF2 MUPF1 MCRDY = 1 to mask the CRDY status bit interrupt. The power-on default value is 0. MADD: ADD status bit mask. Set MADD = 0 to enable the ADD status bit interrupt to INT, and set MADD = 1 to mask the ADD status bit interrupt. The power-on default value is 1. MALD: ALD status bit mask. Set MALD = 0 to enable the ALD status bit interrupt to INT, and set MALD = 1 to mask the ALD status bit interrupt. The power-on default value is 1. MUPR<4:1>: UPR<4:1> status bits mask. Set MUPR_ = 0 to enable the UPR_ status bit interrupt to INT, and set MUPR_ = 1 to mask the UPR_ status bit interrupt. (_ = 1, 2, 3, or 4 and corresponds to the UPIO1, UPIO2, UPIO3, or UPIO4 pins, respectively.) The power-on default value is F hex. MUPF<4:1>: UPF<4:1> status bits mask. Set MUPF_ = 0 to enable the UPF_ status bit interrupt to INT, and set MUPF_ = 1 to mask the UPF_ status bit interrupt. (_ = 1, 2, 3, or 4 and corresponds to the UPIO1, UPIO2, UPIO3, or UPIO4 pins, respectively.) The power-on default value is F hex. PS_VMONS Register (Power-On State: 0010 01XX) MSB LDOE LSB CPE LSDE CPDE HYSE RSTE X X This register is the power-supply and voltage monitors control register. disable the DV DD low-supply-voltage detector. The power-on default value is 1. LDOE: Low-dropout linear-regulator enable bit. Set LDOE = 1 to enable the low-dropout linear regulator to provide the internal source voltage for the charge pump. Set LDOE = 0 to disable the LDO, allowing an external drive to the charge-pump input through REG. The power-on default value is 0. CPE: Charge-pump enable bit. Set CPE = 1 to enable the charge-pump doubler, and set CPE = 0 to disable the charge-pump doubler. The power-on default value is 0. LSDE: DV DD low-supply voltage-detector powerenable bit. Set LSDE = 1 to enable the +1.8V (DVDD) low-supply-voltage detector, and set LSDE = 0 to CPDE: CPOUT low-supply voltage-detector powerenable bit. Set CPDE = 1 to enable the +2.7V CPOUT low-supply voltage-detector comparator, and set CPDE = 0 to disable the CPOUT low-supply voltage-detector comparator. The power-on default value is 0. HYSE: DVDD low-supply voltage-detector hysteresisenable bit. Set HYSE = 1 to set the hysteresis for the +1.8V (DVDD) low-supply-voltage detector to +200mV, and set HYSE = 0 to set the hysteresis to +20mV. On initial power-up, the hysteresis is +20mV and can be programmed to 200mV once RESET goes high. Once programmed to +200mV, the DVDD falling threshold is +1.8V nominally and the rising threshold is +2.0V nominally. The ______________________________________________________________________________________ 57 MAX1358B IMSK Register (Power-On State: 1111 011X 1111 1111) MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor hysteresis helps eliminate chatter when running directly off unregulated batteries. If DVDD falls below +1.3V (typ), the power-on reset circuitry is enabled and the HYSE bit is deasserted setting the hysteresis back to +20mV. The power-on default is 0. RSTE: RESET output enable bit. Set RSTE = 1 to enable RESET to be controlled by the +1.8V DVDD lowsupply-voltage detector, and set RSTE = 0 to disable this control. The power-on default is 1. STATUS Register (Power-On State: 0000 000X 0000 0000) MSB LDVD LCPD ADOU SDC CRDY ADD ALD X UPR4 UPR3 UPR2 UPR1 UPF4 UPF3 UPF2 UPF1 LSB The STATUS register contains the status bits of events in various system blocks. Any status bits not masked in the IMSK register cause an interrupt on INT. Some of the status bit setting events (GPI, WAKEUP, ALARM, DRDY) can be directed to UPIO_ to provide multiple µC interrupt inputs. There are no specific mask bits for the UPIO interrupt signals since the bits are effectively masked by selecting a different function for UPIO. The STATUS bits always record the triggering event(s), even for masked bits, which do not generate an interrupt on INT. It is possible to set multiple STATUS bits during a single INT interrupt event. Clear all STATUS bits except for ADD and ADOU by reading the STATUS register. During a STATUS register read, INT deasserts when the first STATUS data bit (LDVD) reads out (9th rising SCLK) and remains deasserted until shortly after the last STATUS data bit (~15ns). At this point, INT reasserts if any STATUS bit is set during the STATUS register read. If the STATUS register is partially read (i.e., the read is aborted midway), none of the STATUS bits are cleared. New events occurring during a STATUS register read, or events that persist after reading the STATUS bits result in another interrupt immediately after the STATUS register read finishes. This is a read-only register. LDVD: Low DVDD voltage-detector status bit. LDVD = 1 indicates DVDD is below the +1.8V threshold; otherwise LDVD = 0. LDVD clears during the STATUS register read as long as the condition does not persist. Otherwise, the LDVD bit reasserts immediately. If the DVDD low voltage detector is disabled, LDVD = 0. The power-on default is 0. LCPD: Low CPOUT voltage-detector status bit. LCPD = 1 indicates CPOUT is below the +2.7V threshold; otherwise LCPD = 0. LCPD clears during the STATUS register read as long as the condition does not persist. Otherwise the LCPD bit reasserts immediately. LCPD = 0 when the CPOUT low voltage detector is disabled. The power-on default is 0. 58 ADOU: ADC overflow/underflow status bit. ADOU = 1 indicates an ADC underflow or overflow condition in the current ADC result. New conversions that are valid clear the ADOU bit. ADOU = 0 when the ADC data is valid or the ADC is disabled (ADCE = 0). An underflow condition occurs when the ADC data is theoretically less than 0000 hex in unipolar mode and less than 8000 hex in bipolar mode. An overflow condition occurs when the ADC data is theoretically greater than FFFF hex in unipolar mode and greater than 7FFF hex in bipolar mode. Use this bit to determine the validity of an ADC result at the maximum or minimum code values (i.e., 0000 hex or FFFF hex for unipolar mode and 8000 hex and 7FFF hex for bipolar mode). The power-on default is 0. Reading the STATUS register does not clear the ADOU bit. SDC: Signal-detect comparator status bit. When SDC = 1, the positive input to the signal-detect comparator exceeds the negative input plus the programmed threshold voltage. The SDC bit clears during the STATUS register read unless the condition remains true. The SDC bit also deasserts when the signal-detect comparator powers down (SDCE = 0). The power-on default is 0. CRDY: High-frequency-clock ready status bit. CRDY = 1 indicates a locked high-frequency clock to the 32kHz reference frequency by the FLL. The CRDY bit clears during the STATUS register read. This bit only asserts after power-up or after enabling the FLL using the FLLE bit. The power-on default is 0. ADD: ADC-done status bit. ADD = 1 indicates a completed ADC conversion or calibration. Clear the ADD bit by reading the appropriate ADC data, offset, or gain-calibration registers. The ADC status bit also clears when a new ADC result updates to the data or calibration registers (i.e., it follows the assertion level of the UPIO = DRDY signal). Reading the STATUS register does not clear this bit. This bit is equivalent to the DRDY signal available through UPIO_. The power-on default is 0. ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor Applications Information Analog Filtering The internal digital filter does not provide rejection close to the harmonics of the modulator sample frequency. However, due to high oversampling ratios in the MAX1358B, these bands typically occupy a small fraction of the spectrum and most broadband noise is filtered. Therefore, the analog filtering requirements in front of the MAX1358B are considerably reduced compared to a conventional converter with no on-chip filtering. In addition, because the device’s common-mode rejection (60dB) extends out to several kHz, the common-mode noise susceptibility in this frequency range is substantially reduced. Depending on the application, provide filtering prior to the MAX1358B to eliminate unwanted frequencies the digital filter does not reject. Providing additional filtering in some applications ensures that differential noise signals outside the frequency band of interest do not saturate the analog modulator. When placing passive components in front of the MAX1358B, ensure a low enough source impedance to prevent introducing gain errors to the system. This configuration significantly limits the amount of passive antialiasing filtering that can be applied in front of the MAX1358B. See Table 3 for acceptable source impedances. Power-On Reset or Power-Up After a power-on reset, the DVDD voltage supervisor is enabled and all UPIOs are configured as inputs with pullups enabled. The internal oscillators are enabled and are output at CLK and CLK32K once the DVDD voltage supervisor is cleared and the subsequent timeout period has expired. All interrupts are masked except CRDY. Figure 19 illustrates the timing of various signals during initial power-up, sleep mode, and wake-up events. The ADC, charge pump, internal reference, op amp(s), DAC, and switches are disabled after power-up. Power Modes Two power modes are available for the MAX1358B: sleep and normal mode. In sleep mode, all functional blocks are powered down except the serial interface, data registers, internal bandgap, wake-up circuitry (if enabled), DVDD voltage supervisor (if enabled), and the 32kHz oscillator (if enabled), which remain active. See Table 15 for details of the sleep-mode and normalmode power states of the various internal blocks. Each analog block can be shut down individually through its respective control register with the exception of the bandgap reference. Sleep Mode Sleep mode is entered one of three ways: • Writing to the SLEEP register address. The result is the SHDN bit is set to 1. • Asserting the SLEEP or SLEEP function on a UPIO (SLEEP takes precedence over software writes or wake-up events). The SHDN bit is unaffected. • Asserting the SHDN bit by writing SLP = 1 in the SLEEP_CFG register. Entering sleep mode is an OR function of the UPIO or SHDN bit. Before entering sleep mode, configure the normal mode conditions. Exit sleep mode and enter normal mode by one of the following methods: • With the SHDN bit = 0, deassert the SLEEP or SLEEP function on UPIO, only if SLEEP or SLEEP function is used for entering sleep mode. ______________________________________________________________________________________ 59 MAX1358B ALD: Alarm (day) status bit. ALD = 1 when the value programmed in ASEC<19:0> in the AL_DAY register matches SEC<19:0> in the RTC register. Clear the ALD bit by reading the STATUS register or by disabling the day alarm (ADE = 0). The power-on default is 0. UPR<4:1>: User-programmable I/O rising-edge status bits. UPR_ = 1 indicates a rising edge on the respective UPIO_ pin has occurred. Clear UPR_ by reading the STATUS register. Rising edges are detected independent of UPIO_ configuration, providing the ability to capture and record rising input (e.g., WU) or output (e.g., PWM) edge events on the UPIO_. Set the appropriate mask to determine if the edge will generate an interrupt on INT. If the UPIO_ is configured as an output, INT provides confirmation that an intended rising edge output occurred and has reached the desired DVDD or CPOUT level (i.e., was not loaded down externally). The power-on default is 0. UPF<4:1>: User-programmable I/O falling-edge status bit. UPF_ = 1 indicates a falling edge on the respective UPIO_ has occurred. Clear UPF_ by reading the STATUS register. Falling edges are detected independent of UPIO_ configuration, providing the ability to capture and record falling input (e.g., WU) or output (e.g., PWM) edge events on the UPIO_. Set the appropriate mask to determine if that edge should generate an interrupt on the INT pin. If the UPIO is configured as an output, INT provides confirmation that an intended falling edge output occurred at the pin and it reached the desired DGND level. The power-on default is 0. MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor 2 AVDD INITIAL POWER, WAKE-UP, AND SLEEP XTAL BETWEEN 32KIN AND 32KOUT PIN 1.8V 1 0V 2 DVDD 1.8V 1 0V POR HI LO OSCE = 1 SOSCE = 1 OSCE = 1 XIN, XOUT HI (32kHz) LO CK32E = 1 RESET HI (OPEN DRAIN) LO INTERNAL EXTERNAL OUTPUT DISABLED, BUT PULLED LOW HI INTERNAL LOW DVDD DETECTOR LO CK32E = 1 SCK32E = 0 BUFFER DISABLED HI CK32K (32kHz) LO OUTPUT ENABLED UPIO (WU) HI (INT. PULLUP) LO tWU tDPU HI UPIO (SHDN) INTERNAL LO tDPD CLK HI INTERNAL LO tDFON INTERNAL HI CRDY HFCE = 1, FLLE = 1 LO tDFON tDFOF IF FLLE = 0, CRDY WILL STAY LOW, DFON = 0 tDFI INT tDFI HI LO PWME = 0 UPIO (PWM) HI CONNECTED TO POWER SUPPLY SHDN PIN LO INTERNAL DRDY DOUT SPWME = 1 POWER SUPPLY OFF HI LO HI LO HI CS LO THREE-STATED SLEEP WRITE HI SCLK, DIN LO Figure 19. Initial Power-Up, Sleep Mode, and Wake-Up Timing Diagram with AVDD > 1.8V 60 PWME = 0 POWER SUPPLY OFF ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor VREF/GAIN VREF/GAIN BINARY OUTPUT CODE VREF (GAIN x 65,536) 1 LSB = VREF/GAIN 0111 1111 1111 1101 BINARY OUTPUT CODE 0111 1111 1111 1110 1111 1111 1111 1101 VREF x2 (GAIN x 65,536) 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 VREF/GAIN FULL-SCALE TRANSITION 1 LSB = VREF/GAIN 0111 1111 1111 1111 1111 1111 1111 1110 1111 1111 1111 1100 0000 0000 0000 0011 0000 0000 0000 0010 1000 0000 0000 0010 0000 0000 0000 0001 1000 0000 0000 0001 0000 0000 0000 0000 0 1 2 65,533 3 MAX1358B VREF/GAIN 1111 1111 1111 1111 65,535 1000 0000 0000 0000 -32,768 -32,766 INPUT VOLTAGE (LSB) -1 0 +1 +32,765 +32,767 INPUT VOLTAGE (LSB) Figure 20. ADC Unipolar Transfer Function Figure 21. ADC Bipolar Transfer Function • With the SLEEP or SLEEP function deasserted on UPIO, clear the SHDN bit by writing to the normalmode register address control byte. • With the SLEEP or SLEEP function deasserted, assert WU or WU (wake-up) function on UPIO. • With the SLEEP or SLEEP function deasserted, the day alarm triggers. MAX1358B FBA OUTA DAC A REF FBB Wake-Up A wake-up event, such as an assertion of a UPIO configured as WU or a time-of-day alarm causes the MAX1358B to exit sleep mode, if in sleep mode. A wake-up event in normal mode results only in a wake-up event being recorded in the STATUS register. RESET The RESET output pulls low for any one of the following cases: power-on reset, DV DD monitor trips and RSTE = 0, watchdog timer expires, crystal oscillator is attached, and 32kHz clock not ready. The RESET output can be turned off through the RSTE bit in the PS_VMONS register, causing DVDD low supply voltage events to issue an interrupt or poll through the LDVD status bit. This allows brownout detection µCs that operate with DVDD < 1.8V. Driving UPIO Outputs to AVDD Levels UPIO outputs can be driven to AVDD levels in systems with separate AVDD and DVDD supplies. Disable the charge-pump doubler by setting CPE = 0 in the PS_VMONS register, and connect the system’s analog supply to AVDD and CPOUT. Setting UPIO outputs to drive to CPOUT results in AVDD-referenced logic levels. DAC B OUTB Figure 22. DAC Unipolar Output Circuit Supply Voltage Measurement The AVDD supply voltage can be measured with the ADC by reversing the normal input and reference signals. The REF voltage is applied to one multiplexer input, and AGND is selected in the other. The AVDD signal is then switched in as the ADC reference voltage and a conversion is performed. The AVDD value can then be calculated directly as: VAVDD = (VREF x Gain x 65,536)/N where VREF is the reference voltage for the ADC, Gain is the PGA gain before the ADC, and N is the ADC result. Note the AVDD voltage must be greater than the gained-up REF voltage (AVDD > VREF x Gain). This measurement must be done in unipolar mode. ______________________________________________________________________________________ 61 MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor VREF FBA MAX1358B R1 R2 10kΩ +3.3V FB_ 10kΩ VOUT OUTA DAC A DAC_ OUT_ REF FBB -3.3V 10kΩ MAX1358B 10kΩ DAC B R2 = R1 VREF = 1.25V OUTB VREF = 1.25V Figure 23. DAC Unipolar Rail-to-Rail Output Circuit Figure 24. DAC Bipolar Output Circuit In unipolar mode, the output code ranges from 0 to 65,535 for inputs from zero to full-scale. In bipolar mode, the output code ranges from -32,768 to +32,767 for inputs from negative full-scale to positive full-scale. Power Supplies AVDD and DVDD provide power to the MAX1358B. The AVDD powers up the analog section, while the DVDD powers up the digital section. The power supply for both AVDD and DVDD ranges from +1.8V to +3.6V. Both AVDD and DVDD must be greater than +1.8V for device operation. AVDD and DVDD can connect to the same power supply. Bypass AVDD to AGND with a 10µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor, and bypass DVDD to DGND with a 10µF electrolytic capacitor in parallel with a 0.1µF ceramic capacitor. For improved performance, place the bypass capacitors as close to the device as possible. ADC Transfer Functions Figures 20 and 21 provide the ADC transfer functions for unipolar and bipolar mode. The digital output code format is binary for unipolar mode and two’s complement for bipolar mode. Calculate 1 LSB using the following equations: 1 LSB (Unipolar Mode) = VREF/(Gain x 65,536) 1 LSB (Bipolar Mode) = ±2VREF/(Gain x 65,536) DAC Unipolar Output For a unipolar output, the output voltages and the reference have the same polarity. Figure 22 shows the unipolar output circuit of the MAX1358B, which is also the typical operating circuit for the DAC. Table 22 lists some unipolar input codes and their corresponding output voltages. For larger output swing, see Figure 23. This circuit shows the output amplifiers configured with a closedloop gain of +2V/V to provide 0 to 2.5V full-scale range with the 1.25V reference. DAC Bipolar Output The MAX1358B DAC output can be configured for bipolar operation using the application circuit in Figure 24: ⎡⎛ 2N ⎞ ⎤ VOUT = VREF ⎢⎜ ⎟ − 1⎥ ⎝ ⎠ 1024 ⎣ ⎦ where VREF equals the reference voltage at REF and Gain equals the PGA gain. where N is the decimal value of the DAC’s binary input code. Table 23 shows digital codes (offset binary) and corresponding output voltages for Figure 24 assuming R1 = R2. Table 22. Unipolar Code Table 23. Bipolar Code DAC CONTENTS MSB LSB 1111 1111 11 1000 0000 01 1000 0000 00 0111 1111 11 0000 0000 01 0000 0000 00 62 ANALOG OUTPUT +VREF (1023/1024) +VREF (513/1024) +VREF (512/1024) = +VREF/2 +VREF (511/1024) +VREF (1/1024) 0 DAC CONTENTS MSB LSB 1111 1111 11 1000 0000 01 1000 0000 00 0111 1111 11 0000 0000 01 0000 0000 00 ANALOG OUTPUT +VREF (511/512) +VREF (1/512) 0 -VREF (1/512) -VREF (511/512) -VREF (512/512) = -VREF ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor Input Multiplexer The mux inputs can range between AGND and AVDD. However, when the internal temperature sensor is enabled, AIN1 and AIN2 cannot exceed 0.7V. This necessitates additional circuitry to divide down the input signal. See Figure 26 for an example circuit that divides down backlight VDD to work properly with the AIN1 pin. Optical Reflectometry Application with Dual LED and Single Photodiode Figure 27 illustrates the MAX1358B in a complete optical reflectometry application with two transmitting LEDs and one receiving photodiode. The LEDs transmit light at a specific wavelength onto the sample strip, and the photodiode receives the reflections from the strip. Set the DAC to provide appropriate bias currents for the LEDs. Always keep the photodiodes reverse-biased or zero-biased. SPDT1 and SPDT2 switch between the two LEDs. Electrochemical Sensor Operation The MAX1358B family interface with electrochemical sensors. The 10-bit DAC with the force-sense buffers have the flexibility to connect to many different types of sensors. An external precision resistor completes the transimpedance amplifier configuration to convert the current generated by the sensor to a voltage measurement using the ADC. The induced error from this source is negligible due to FBA’s extremely low input bias current. Internally, the ADC can differentially measure directly across the external transimpedance resistor, RF, eliminating any errors due to voltages drifting over time, temperature, or supply voltage. Temperature Measurement with Two Remote Sensors Use two diode-connected 2N3904 transistors for external temperature sensing in Figure 29. Select AIN1 and AIN2 through the positive and negative mux, respectively. For internal temperature sensor measurements, set MUXP<3:0> to 0111, and set MUXN<3:0> to 0000. The analog input signals feed through a PGA to the ADC for conversion. The MAX1358B integrated PWM is available for LCD bias control, sensor-bias voltage trimming, buzzer drive, and duty-cycled sleep-mode power-control schemes. Figure 30 shows the MAX1358B performing LCD bias control. A sensor-bias voltage trimming application is shown in Figure 31. Figures 33 and 34 show the PWM circuitry being used in a single-ended and differential piezoelectric buzzer-driving application. ADC Calibration Internal to the MAX1358B, the ADC is 24 bits and is always in bipolar mode. The OFFSET CAL and GAIN CAL data is also 24 bits. The conversion to unipolar and the gain are performed digitally. The default values for the OFFSET CAL and GAIN CAL registers in the MAX1358B are 00 0000h and 80 0000h, respectively. The calibration works as follows: ADC = (RAW - OFFSET) x Gain x PGA where ADC is the conversion result in the DATA register, RAW is the output of the decimation filter internal to the MAX1358B, OFFSET is the value stored in the OFFSET CAL register, Gain is the value stored in the GAIN CAL register, and PGA is the selected PGA gain found in the ADC register as GAIN<1:0>. In unipolar mode, all negative values return a zero result and an additional gain of 2 is added. BACKLIGHT VDD VBATT2 CMOS CLOCK (0 TO DVDD) 100kΩ VBATT1 32KIN UPIO1 GPIOn 100kΩ MAX1358B MAX1358B BATTVCHECK x2 < 0.6125V NOTE: GPIOn IS LOW = LED ON, HIGH-Z = LED OFF AIN1 VREF = 1.25V µP Figure 25. Clocking with a CMOS Signal Figure 26. Input Multiplexer ______________________________________________________________________________________ 63 MAX1358B Clocking with a CMOS Signal A CMOS signal can be used to drive 32KIN if it is divided down. Figure 25 is an example circuit, which works well. MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor VCP SERIAL-PORT INTERFACE TXD RXD VSS VSS µC VBAT EEPROM VSS MOSI SI MISO SO SCK SCK CS1 CS VCC GND VSS MAX1358B VCP BDOUT UPIO2 DIN LCD MODULE BDIN UPIO1 BSCLK UPIO3 DOUT BCS2 UPIO4 SCLK CS2 MEM UP DOWN INPUT RESET INPUT INPUT INPUT X2IN 32KIN CS2 VSS CS RESET INT HIGH-FREQUENCY MICRO CLOCK 32kHz MICRO CLOCK CLK IN1- CLK32K VSS IN1+ AVDD VBAT OUT1 DVDD VDD 2 AAA OR 1 LITHIUM COIN CELL VSS VSS 1nF SNO2 ADC TEST STRIP SCM2 VSS AGND SNC2 VSS DGND PWM VSS AMBIENT LIGHT AIN1 AIN2 DACA LED SOURCES VCP OUTA 32KIN LED SWA FBA SNO1 32.768kHz VCP LED SCM1 32KOUT DVDD SNC1 LINEAR REG REG CF+ VSS CF- CHARGEPUMP DOUBLER REF BG CPOUT VCP VSS VSS VSS Figure 27. Optical Reflectometry Application with Dual LED and Single Photodiode 64 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX1358B µC VCP LCD GLASS COM<3:0> SEG<23:0> LCDBIAS RX_WAKEUP SERIAL-PORT INTERFACE RXD VSS LCD DRIVERS VSS BUZ_HI PIEZO ALARM BUZ_LO VBAT EEPROM VSS MOSI SI MISO SO SCK SCK CS1 CS VCC GND VSS MAX1358B CPOUT UPIO2 DIN TXD DOUT SCLK CS2 MEM UP DOWN CS2 CPOUT PWM CS UPIO4 INPUT RESET RESET OUTA INPUT INPUT INT SWA CLK FBA INPUT X2IN 32KIN HIGH-FREQUENCY MICRO CLOCK 32kHz MICRO CLOCK LCDBIAS STRIP INSERTED VSS TEST STRIP CLK32K VSS AVDD VBAT DVDD VDD RX_WAKEUP UPIO1 UPIO3 VSS DACA OUTB 2 AAA OR 1 LITHIUM COIN CELL SWB FBB VSS AGND VSS ADC DGND DACB SNO1 SCM1 SNC1 32KIN OUT1 32.768kHz IN132KOUT DVDD IN1+ LINEAR REG BG REF REG CF+ VSS CFCPOUT VCP VSS CHARGEPUMP DOUBLER SNO2 SCM2 SNC2 AIN1 REMOTE TEMPERATUREMEASUREMENT DIODE VSS AIN2 VSS Figure 28. Electrochemical Meter Application Circuit (Traditional and Counter Configuration) ______________________________________________________________________________________ 65 MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor For self-calibration, the offset value is the RAW result when the inputs are shorted internally and the gain value is 1/(RAW - OFFSET) with the reference connected to the input. This is done automatically when these modes are selected. The self-offset and gain calibration corrects for errors internal to the ADC and the results are stored and used automatically in the OFFSET CAL and GAIN CAL registers. For best results, use the ADC in the same configuration as the calibration. This pertains to conversion rate only because the PGA gain and unipolar/bipolar modes are performed digitally. For system calibration, the offset and gain values correct for errors in the whole signal path including the internal ADC and any external circuits in the signal path. For the system calibration, a user-provided zeroinput condition is required for the offset calibration and a user-provided full-scale input is required for the gain calibration. These values are automatically written to the OFFSET CAL and GAIN CAL registers. The order of the calibrations should be offset followed by gain. The offset correction value is in two’s complement. The default value is 000000h, 00...00b, or 0 decimal. The gain correction value is an unsigned binary number with 23 bits to the right of the decimal point. The largest number is therefore 1.1111...1b = 2 - 2-23 and the smallest is 0.000...0b = 0, although it does not make sense to use a number smaller than 0.1000...0b = 0.5. The default value is 800000h, 1.000...0b or 1 decimal. Changing the offset or gain calibration values does not affect the value in the DATA register until a new conversion has completed. This applies to all the mode bits for PGA gain, unipolar/bipolar, etc. Grounding and Layout For best performance, use a PCB with separate analog and digital ground planes. Design the PCB so that the analog and digital sections are separated and confined to different areas of the board. Join the digital and analog ground planes at one point. If the DAS is the only device requiring an AGND-toDGND connection, connect planes to the AGND pin of the DAS. In systems where multiple devices require AGND-toDGND connections, the connection should still be made at only one point. Make the star ground as close as possible to the MAX1358B. Avoid running digital lines under the device because these may couple noise onto the device. Run the ana- 66 log ground plane under the MAX1358B to minimize coupling of digital noise. Make the power-supply lines to the MAX1358B as wide as possible to provide lowimpedance paths and reduce the effects of glitches on the power-supply line. Shield fast-switching signals such as clocks with digital ground to avoid radiating noise to other sections of the board. Avoid running clock signals near the analog inputs. Avoid crossover of digital and analog signals. Good decoupling is important when using high-resolution ADCs. Decouple all analog supplies with 10µF capacitors in parallel with 0.1µF HF ceramic capacitors to AGND. Place these components as close to the device as possible to achieve the best decoupling. Crystal Layout Follow basic layout guidelines when placing a crystal on a PCB with a DAS to avoid coupled noise: 1) Place the crystal as close as possible to 32KIN and 32KOUT. Keeping the trace lengths between the crystal and inputs as short as possible reduces the probability of noise coupling by reducing the length of the “antennae”. Keep the 32KIN and 32KOUT lines close to each other to minimize the loop area of the clock lines. Keeping the trace lengths short also decreases the amount of stray capacitance. 2) Keep the crystal solder pads and trace width to 32KIN and 32KOUT as small as possible. The larger these bond pads and traces are, the more likely it is that noise will couple from adjacent signals. 3) Place a guard ring (connect to ground) around the crystal to isolate the crystal from noise coupled from adjacent signals. 4) Ensure that no signals on other PCB layers run directly below the crystal or below the traces to 32KIN and 32KOUT. The more the crystal is isolated from other signals on the board, the less likely it is that noise will be coupled into the crystal. Maintain a minimum distance of 5mm between any digital signal and any trace connected to 32KIN or 32KOUT. 5) Place a local ground plane on the PCB layer immediately below the crystal guard ring. This helps to isolate the crystal from noise coupling from signals on other PCB layers. Note: The ground plane must be in the vicinity of the crystal only and not on the entire board. ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX1358B AIN1 MUX 16-BIT ADC PGA REF AGND 2N3904 AV = 1, 2, 4, 8 AIN2 MAX1358B MUX AGND AV = 1, 1.638, 2 2N3904 TEMP SENSOR 1.25V REF CREF REF Figure 29. Temperature Measurement with Two Remote Sensors Parameter Definitions INL Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line is either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nulled. INL for the MAX1358B is measured using the end-point method. DNL Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of greater than -1 LSB guarantees no missing codes and a monotonic transfer function. Gain Error Gain error is the amount of deviation between the measured full-scale transition point and the ideal full-scale transition point. Common-Mode Rejection Common-mode rejection (CMR) is the ability of a device to reject a signal that is common to both input terminals. The common-mode signal can be either an AC or a DC signal or a combination of the two. CMR is often expressed in decibels. Power-Supply Rejection Ratio (PSRR) Power-supply rejection ratio (PSRR) is the ratio of the input supply change (in volts) to the change in the converter output (in volts). It is typically measured in decibels. ______________________________________________________________________________________ 67 MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX1358B DVDD CPOUT SV_ CPOUT MUX 100kΩ 200kΩ UPIO_ PWM 0.01µF µC (1.8V TO 2.6V) 100kΩ EN_ SEG ALH_ LCD DRIVERS 100kΩ n LCD COM m 100kΩ Figure 30. LCD Contrast-Adjustment Application ~1.25V REF ~19kHz VOLTAGE RIPPLE < 1mV 350kΩ MAX1358B SNO1 SCM1 PWM 240kΩ ~0.3V SNC1 SPDT1 0.1µF 60kΩ AGND IN1+ OUT1 IN1IT TRANSDUCER 0.300V (±1mV) Figure 31. Sensor-Bias Voltage Trim Application 68 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor MAX1358B VDD AVDD DVDD MAX1358B DVDD < 10µA CPOUT MUX VBATT 10MΩ VDD VOUT VIN SV_ 100µF POWER SUPPLY µC UPIO_ PWM SHDN PSCTL ON-TIME <100ms TYP 10s PERIOD TYP PSCTL EN_ +3.3V VDD +2.3V ALH_ Figure 32. Power-Supply Sleep-Mode Duty-Cycle Control DVDD MAX1358B SV_ CPOUT MUX CPOUT(+3.2V) 0V UPIO_ 1kHz TO 8kHz TYP 1kΩ PWM ~10,000pF ALH_ Figure 33. Single-Ended Piezoelectric Buzzer Drive ______________________________________________________________________________________ 69 MAX1358B 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor DVDD CPOUT MAX1358B CPOUT(+3.2V) MUX SV_ 0V UPIO_ PWM 1kHz TO 8kHz TYP 1kΩ ~10,000pF ALH_ DVDD CPOUT SV_ CPOUT + 6.4V DIFF -CPOUT MUX UPIO_ 1kΩ CPOUT(~+3.2V) 0V 1kHz TO 8kHz TYP ALH_ Figure 34. Differential Piezoelectric Buzzer Drive Chip Information PROCESS: BiCMOS 70 Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 40 TQFN-EP T4066+5 21-0141 90-0055 ______________________________________________________________________________________ 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 0 8/10 Initial release of data sheet. The MAX1358B previously appeared on a different data sheet. 1–70 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 71 © 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX1358B Revision History