19-0584; Rev 0; 8/06 KIT ATION EVALU E L B A IL AVA Low-Voltage DDR Linear Regulator Features The MAX8794 DDR linear regulator sources and sinks up to 3A peak (typ) using internal n-channel MOSFETs. This linear regulator delivers an accurate 0.5V to 1.5V output from a low-voltage power input (VIN = 1.1V to 3.6V). The MAX8794 uses a separate 3.3V bias supply to power the control circuitry and drive the internal n-channel MOSFETs. The MAX8794 provides current and thermal limits to prevent damage to the linear regulator. Additionally, the MAX8794 generates a power-good (PGOOD) signal to indicate that the output is in regulation. During startup, PGOOD remains low until the output is in regulation for 2ms (typ). The internal soft-start limits the input surge current. The MAX8794 powers the active-DDR termination bus that requires a tracking input reference. The MAX8794 can also be used in low-power chipsets and graphics processor cores that require dynamically adjustable output voltages. The MAX8794 is available in a 10-pin, 3mm x 3mm, TDFN package. ♦ Internal Power MOSFETs with Current Limit (3A typ) Applications Ordering Information ♦ Fast Load-Transient Response ♦ External Reference Input with Reference Output Buffer ♦ 1.1V to 3.6V Power Input ♦ ±15mV (max) Load-Regulation Error ♦ Thermal-Fault Protection ♦ Shutdown Input ♦ Power-Good Window Comparator with 2ms (typ) Delay ♦ Small, Low-Profile, 10-Pin, 3mm x 3mm TDFN Package ♦ Ceramic or Polymer Output Capacitors Notebook/Desktop Computers DDR Memory Termination Active Termination Buses PART TEMP RANGE PINPACKAGE MAX8794ETB+ -40°C to +85°C 10 TDFN (3mm x 3mm) Graphics Processor Core Supplies Chipset/RAM Supplies as Low as 0.5V TOP MARK PKG CODE ABD T1033-1 +Denotes lead-free package. Typical Operating Circuit Pin Configuration VIN (1.1V TO 3.6V) IN OUT TOP VIEW VOUT = VTT OUTS + REFOUT 1 10 IN VCC 2 AGND 3 VBIAS (2.7V TO 3.6V) 9 OUT MAX8794 8 PGND REFIN 4 7 SHDN PGOOD 5 6 OUTS TDFN 3mm x 3mm MAX8794 VCC PGND SHDN AGND PGOOD VDDQ (2.5V OR 1.8V) VREFOUT = VTTR REFIN REFOUT ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX8794 General Description MAX8794 Low-Voltage DDR Linear Regulator ABSOLUTE MAXIMUM RATINGS IN to PGND............................................................-0.3V to +4.3V OUT to PGND ..............................................-0.3V to (VIN + 0.3V) OUTS to AGND ............................................-0.3V to (VIN + 0.3V) VCC to AGND.........................................................-0.3V to +4.3V REFIN, REFOUT, SHDN, PGOOD to AGND...-0.3V to (VCC + 0.3V) PGND to AGND .....................................................-0.3V to +0.3V REFOUT Short Circuit to AGND .................................Continuous OUT Continuous RMS Current 100s ................................................................................±1.6A 1s ....................................................................................±2.5A Continuous Power Dissipation (TA = +70°C) 10-Pin 3mm x 3mm TDFN (derated 24.4mW/°C above +70°C)...........................1951mW Operating Temperature Range MAX8794ETB...................................................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VIN Power input 1.1 3.6 VCC Bias supply 2.7 3.6 Quiescent Supply Current (VCC) ICC Load = 0, VREFIN > 0.45V 0.7 Shutdown Supply Current (VCC) ICC(SHDN) SHDN = GND, VREFIN > 0.45V 350 600 SHDN = GND, REFIN = GND 50 100 Quiescent Supply Current (VIN) IIN Load = 0 0.4 10 mA Shutdown Supply Current (VIN) IIN(SHDN) 0.1 10 µA 0 +4 Input Voltage Range Feedback-Voltage Error VOUTS SHDN = GND REFIN to OUTS, IOUT = ±200mA TA = +25°C -4 TA = -40°C to +85°C -6 Load-Regulation Error -1A ≤ IOUT ≤ +1A Line-Regulation Error 1.4V ≤ VIN ≤ 3.3V, IOUT = ±100mA OUTS Input Bias Current IOUTS 1.3 +6 -15 +15 1 V mA µA mV mV mV -1 +1 µA 0.5 1.5 V OUTPUT Output Adjust Range OUT On-Resistance Output Current Slew Rate OUT Power-Supply Rejection Ratio PSRR OUT to OUTS Resistance ROUTS Discharge MOSFET OnResistance 2 High-side MOSFET (source) (IOUT = 0.1A) 0.10 0.169 Low-side MOSFET (sink) (IOUT = -0.1A) 0.10 0.20 Ω COUT = 100µF, IOUT = 0.1A to 2A 3 A/µs 10Hz < f < 10kHz, IOUT = 200mA, COUT = 100µF 80 dB 12 kΩ 8 Ω RDISCHARGE SHDN = GND _______________________________________________________________________________________ Low-Voltage DDR Linear Regulator (VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE REFIN Voltage Range VREFIN 0.5 1.5 V REFIN Input Bias Current IREFIN -1 +1 µA 0.35 0.45 V VREFIN VREFIN + 0.01 V +20 mV REFIN Undervoltage-Lockout Voltage REFOUT Voltage Rising edge, hysteresis = 75mV VREFOUT REFOUT Load Regulation ∆VREFOUT VCC = 3.3V, IREFOUT = 0 IREFOUT = ±5mA VREFIN - 0.01 -20 FAULT DETECTION Thermal-Shutdown Threshold TSHDN Rising edge, hysteresis = 15°C VCC Undervoltage-Lockout Threshold VUVLO Rising edge, hysteresis = 100mV IN Undervoltage-Lockout Threshold Current-Limit Threshold Soft-Start Current-Limit Time +165 2.45 Rising edge, hysteresis = 55mV ILIMIT 1.8 tSS °C 2.55 2.65 V 0.9 1.1 V 3 4.2 200 A µs INPUTS AND OUTPUTS PGOOD Lower Trip Threshold With respect to feedback threshold, hysteresis = 12mV -200 -150 -100 mV PGOOD Upper Trip Threshold With respect to feedback threshold, hysteresis = 12mV 100 150 200 mV 5 10 35 µs 2 3.5 ms 0.3 V 1 µA PGOOD Propagation Delay tPGOOD OUTS forced 25mV beyond PGOOD trip threshold Startup rising edge, OUTS within ±100mV of the feedback threshold PGOOD Startup Delay PGOOD Output Low Voltage ISINK = 4mA PGOOD Leakage Current OUTS = REFIN (PGOOD high impedance), PGOOD = VCC + 0.3V SHDN Logic Input Threshold SHDN Logic Input Current IPGOOD Logic high 2.0 Logic low 0.8 SHDN = VCC or GND -1 +1 V µA Note 1: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed through correlation using statistical-quality-control (SQC) methods. _______________________________________________________________________________________ 3 MAX8794 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (Circuit of Figure 1. TA = +25°C, unless otherwise noted.) VIN = 1.25V VOUT (V) 0.90 VIN = 1.5V 1.26 1.24 0.88 VIN = 1.8V VIN = 1.5V 0.86 1.22 0.84 -2 -1 0 1 2 3 -2 -1 0 1 2 1.5 2.0 2.5 3.0 BIAS CURRENT (ICC) vs. LOAD CURRENT (IOUT) 0.9 0.8 VOUT = 1.25V 1.0 ICC (mA) 0.6 0.5 0.3 0.4 INPUT UVLO 0 2.0 2.5 3.0 0 3.5 ENTERING DROPOUT 0.2 0.1 0 VOUT = 0.90V 0.6 DROPOUT VOUT = 1.25V 0.8 0.4 0.2 1.5 VIN = 1.5V 1.2 0.7 50 1.0 1.4 MAX8794 toc05 MAX8794 toc04 1.0 100 0.5 1.0 1.5 0 2.0 2.5 3.0 3.5 -2 -1 0 VIN (V) IOUT (A) POWER GROUND CURRENT (IPGND) vs. SOURCE LOAD CURRENT (IOUT) INPUT CURRENT (IIN) vs. SINK LOAD CURRENT (IOUT) DROPOUT VOLTAGE vs. OUTPUT CURRENT VIN = 1.5V 6 IIN (mA) ENTERING DROPOUT VOUT = 1.25V 4 VOUT = 0.90V 3 VOUT = 1.25V 2 VOUT = 0.90V 0 0.5 1.0 IOUT (A) 1.5 2.0 VOUT = 1.25V 0.20 0.15 VOUT = 0.9V 0.10 0.05 1 0 0.25 DROPOUT VOLTAGE (V) 5 0.15 0.30 MAX8794 toc09 0.20 7 MAX8794 toc07 VIN = 1.5V 2 1 VIN (V) 0.25 4 1.0 3 BIAS CURRENT (ICC) vs. INPUT VOLTAGE (VIN) ICC (mA) IIN (µA) -3 VOUT = 0.90V 0 DROPOUT VOLTAGE LIMITED 0.5 INPUT CURRENT (IIN) vs. INPUT VOLTAGE (VIN) 150 0.05 THERMALLY LIMITED 1.0 INPUT VOLTAGE (V) 200 0.10 1.5 IOUT (A) VOUT = 1.25V 0.5 2.0 IOUT (A) 250 0 VOUT = 1.25V 2.5 0 1.20 -3 MAX8794 toc08 VOUT (V) 0.92 VOUT = 0.9V MAX8794 toc03 1.28 3.0 MAX8794 toc06 0.94 VREFIN = 1.25V MAXIMUM OUTPUT CURRENT (A) VREFIN = 0.9V MAX8794 toc02 1.30 MAX8794 toc01 0.96 MAXIMUM OUTPUT CURRENT vs. INPUT VOLTAGE OUTPUT LOAD REGULATION OUTPUT LOAD REGULATION IPGND (mA) MAX8794 Low-Voltage DDR Linear Regulator 0 -2.0 -1.5 -1.0 IOUT (A) -0.5 0 0 0.5 1.0 1.5 2.0 OUTPUT CURRENT (A) _______________________________________________________________________________________ 2.5 3.0 Low-Voltage DDR Linear Regulator REFOUT VOLTAGE ERROR vs. REFOUT LOAD CURRENT STARTUP WAVEFORM 15 REFOUT VOLTAGE ERROR (mV) MAX8794 toc11 MAX8794 toc10 20 5V SHDN 0V 10 1.25V 5 VOUT 0V 0 -5 4V -10 PGOOD -15 0V -20 -10 -5 0 5 10 500µs/div REFOUT LOAD CURRENT (mA) SHUTDOWN WAVEFORM MAX8794 toc12 RLOAD = 100Ω SOURCE LOAD TRANSIENT MAX8794 toc13 5V SHDN 0V 2V VOUT AC-COUPLED 1mV/div 1V VOUT 0V 4V PGOOD 1A 0V IOUT 0A 100µs/div 20.0µs/div LINE TRANSIENT SOURCE/SINK LOAD TRANSIENT MAX8794 toc15 MAX8794 toc14 3.3V VIN (1V/div) VOUT AC-COUPLED 5mV/div 1.5V +1.5A IOUT VOUT (10mV/div) AC-COUPLED 0.9V -1.5A IOUT = 100mA 4.00µs/div 40µs/div _______________________________________________________________________________________ 5 MAX8794 Typical Operating Characteristics (continued) (Circuit of Figure 1. TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (Circuit of Figure 1. TA = +25°C, unless otherwise noted.) DYNAMIC OUTPUT-VOLTAGE TRANSIENT DYNAMIC OUTPUT-VOLTAGE TRANSIENT MAX8794 toc16 MAX8794 toc17 VDDQ 1.8V 1.2V VREFOUT 1.2V VREFOUT 0.9V 1.2V 0.9V 1.2V VOUT VOUT 0.9V 0.9V 20.0µs/div SINK CURRENT-LIMIT DISTRIBUTION SOURCE CURRENT-LIMIT DISTRIBUTION +25°C +85°C SAMPLE SIZE = 200 SAMPLE PERCENTAGE (%) 40 50 MAX8794 toc18 SAMPLE SIZE = 200 30 20 2.5V VDDQ 1.8V 20.0µs/div 50 +25°C +85°C 40 30 20 10 10 0 0 -4.0 -3.5 -3.0 -2.5 SINK CURRENT LIMIT (A) 6 VIN = 1.8V 2.5V MAX8794 toc19 VIN = 1.5V SAMPLE PERCENTAGE (%) MAX8794 Low-Voltage DDR Linear Regulator -2.0 2.0 2.5 3.0 3.5 4.0 SOURCE CURRENT LIMIT (A) _______________________________________________________________________________________ Low-Voltage DDR Linear Regulator PIN NAME FUNCTION 1 REFOUT 2 VCC 3 AGND Analog Ground. Connect the backside pad to AGND. 4 REFIN External Reference Input. REFIN sets the output regulation voltage (VOUTS = VREFIN). 5 PGOOD 6 OUTS Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12kΩ resistor. 7 SHDN Shutdown Control Input. Connect to VCC for normal operation. Connect to analog ground to shut down the linear regulator. The reference buffer remains active in shutdown. 8 PGND Power Ground. Internally connected to the output sink MOSFET. 9 OUT 10 IN Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over 5mA. Bypass REFOUT to AGND with a 0.33µF or greater ceramic capacitor. Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass VCC to AGND with a 1µF or greater ceramic capacitor. Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the regulation voltage during startup, PGOOD becomes high impedance. Output of the Linear Regulator Power Input. Internally connected to the output source MOSFET. _______________________________________________________________________________________ 7 MAX8794 Pin Description MAX8794 Low-Voltage DDR Linear Regulator Detailed Description The MAX8794 is a low-voltage, low-dropout DDR termination linear regulator with an external bias supply input and a buffered reference output (see Figures 1 and 2). VCC is powered by a 2.7V to 3.6V supply that is commonly available in laptop and desktop computers. The 3.3V bias supply drives the gate of the internal pass transistor, while a lower voltage input at the drain of the transistor (IN) is regulated to provide VOUT. By using separate bias and power inputs, the MAX8794 can drive an n-channel high-side MOSFET and use a lower input voltage to provide better efficiency. The MAX8794 regulates its output voltage to the voltage at REFIN. When used in DDR applications as a termination supply, the MAX8794 delivers 1.25V or 0.9V at 3A peak (typ) from an input voltage of 1.1V to 3.6V. The MAX8794 sinks up to 3A peak (typ) as required in a termination supply. The MAX8794 provides shoot-through protection, ensuring that the source and sink MOSFETs do not conduct at the same time, yet produces a fast source-to-sink load transient. 3.3V BIAS SUPPLY ON IN OUT COUT1 100µF CIN2 10µF MAX8794 3.3V BIAS SUPPLY PGND VCC R3 100kΩ C1 1.0µF AGND POWER-GOOD PGOOD OUTS ON OFF SHDN R1 10kΩ VDDQ REFIN R2 10kΩ REFOUT CREFIN 1000pF VREFOUT = VTTR CREFOUT 0.33µF Figure 1. Standard Application Circuit VCC EN UVLO OFF VOUT = VTT = VDDQ / 2 VIN = 1.1V TO 3.6V SOFTSTART IN INPUT 1.1V TO 3.6V SHDN THERMAL SHDN REFIN VDDQ OUT Gm PGND VTTR 12kΩ REFOUT OUTS REFIN +150mV AGND EN 8Ω REFIN -150mV POWERGOOD PGOOD DELAY LOGIC MAX8794 Figure 2. Functional Diagram 8 _______________________________________________________________________________________ VTT Low-Voltage DDR Linear Regulator 3.3V Bias Supply (VCC) The VCC input powers the control circuitry and provides the gate drive to the pass transistor. This improves efficiency by allowing VIN to be powered from a lower supply voltage. Power V CC from a well-regulated 3.3V supply. Current drawn from the VCC supply remains relatively constant with variations in VIN and load current. Bypass VCC with a 1µF or greater ceramic capacitor as close to the device as possible. VCC Undervoltage Lockout (UVLO) The VCC input UVLO circuitry ensures that the regulator starts up with adequate voltage for the gate-drive circuitry to bias the internal pass transistor. The UVLO threshold is 2.55V (typ). VCC must remain above this level for proper operation. Power-Supply Input (IN) IN provides the source current for the linear regulator’s output, OUT. IN connects to the drain of the internal n-channel power MOSFET. IN can be as low as 1.1V, minimizing power dissipation. The input UVLO prohibits operation below 0.8V (typ). Bypass IN with a 10µF or greater capacitor as close to the device as possible. Reference Input (REFIN) The MAX8794 regulates OUTS to the voltage set at REFIN, making the MAX8794 ideal for memory applications where the termination supply must track the supply voltage. Typically, REFIN is set by an external resistive voltage-divider connected to the memory supply (VDDQ) as shown in Figure 1. The maximum output voltage of 1.5V is limited by the gate-drive voltage of the internal n-channel power transistor. Buffered Reference Output (REFOUT) REFOUT is a unity-gain transconductance amplifier that generates the DDR reference supply. It sources and sinks greater than 5mA. The reference buffer is typically connected to ceramic bypass capacitors (0.33µF to 1.0µF). REFOUT is active when VREFIN > 0.45V and VCC is above VUVLO. REFOUT is independent of SHDN. Shutdown Drive SHDN low to disable the error amplifier, gatedrive circuitry, and pass transistor (Figure 2). In shutdown, OUT is terminated to GND with an 8Ω MOSFET. REFOUT is independent of SHDN. Connect SHDN to VCC for normal operation. Current Limit The MAX8794 features source and sink current limits to protect the internal n-channel MOSFETs. The sourceand-sink MOSFETs have a typical 3A current limit (1.8A min). This current limit prevents damage to the internal power transistors, but the device can enter thermal shutdown if the power dissipation increases the die temperature above +165°C (see the Thermal-Overload Protection section). Soft-Start Current Limit Soft-start gradually increases the internal source current limit to reduce input surge currents at startup. Fullsource current limit is available after the 200µs soft-start timer has expired. The soft-start current limit is given by: I × t ILIMIT(SS) = LIMIT t SS where ILIMIT and tSS are from the Electrical Characteristics. Figure 3 shows the MAX8794 PGOOD and soft-start waveform. Thermal-Overload Protection Thermal-overload protection prevents the linear regulator from overheating. When the junction temperature exceeds +165°C, the linear regulator and reference buffer are disabled, allowing the device to cool. Normal operation resumes once the junction temperature cools by 15°C. Continuous short-circuit conditions result in a pulsed output until the overload is removed. A continuous thermal-overload condition results in a pulsed output. For continuous operation, do not exceed the absolute maximum junction-temperature rating of +150°C. _______________________________________________________________________________________ 9 MAX8794 The MAX8794 features an open-drain PGOOD output that transitions high 2ms after the output initially reaches regulation. PGOOD goes low within 10µs of when the output goes out of regulation by ±150mV. The MAX8794 features current- and thermal-limiting circuitry to prevent damage during fault conditions. MAX8794 Low-Voltage DDR Linear Regulator SHDN 200µs CURRENT LIMIT OUTPUT OVERLOAD CONDITION POWER-GOOD WINDOW OUT 2ms STARTUP DELAY PGOOD 10µs PROPAGATION DELAY 10µs PROPAGATION DELAY Figure 3. MAX8794 PGOOD and Soft-Start Waveforms Power-Good (PGOOD) The MAX8794 provides an open-drain PGOOD output that goes high 2ms (typ) after the output initially reaches regulation during startup. PGOOD transitions low 10µs after the output goes out of regulation by ±150mV, or when the device enters shutdown. Connect a pullup resistor from PGOOD to VCC for a logic-level output. Use a 100kΩ resistor to minimize current consumption. REFERENCE VOLTAGE (VREF) R1 MAX8794 CREFIN Applications Information REFIN Dynamic Output-Voltage Transitions By changing the voltage at REFIN, the MAX8794 can be used in applications that require dynamic outputvoltage changes between two set points (graphics processors). Figure 4 shows a dynamically adjustable resistive voltage-divider network at REFIN. Using an external signal MOSFET, a resistor can be switched in and out of the REFIN resistor-divider, changing the voltage at REFIN. The two output voltages are determined by the following equations: ⎛ R2 ⎞ VOUT(LOW) = VREF ⎜ ⎟ ⎝ R1 + R2 ⎠ ⎡ (R2 + R3) ⎤ VOUT(HIGH) = VREF ⎢ ⎥ ⎢⎣ R1 + (R2 + R3) ⎥⎦ 10 R2 VOUT(LOW) VOUT(HIGH) VOUT(LOW) = VREF R3 ( ) VOUT(HIGH) = VREF R2 R1 + R2 (R2 + R3) R1 + (R2 + R3) Figure 4. Dynamic Output-Voltage Change ______________________________________________________________________________________ Low-Voltage DDR Linear Regulator PDIS(MAX) = TJ(MAX) - TA θJC + θCA where TJ(MAX) is the maximum junction temperature (+150°C), TA is the ambient temperature, θJC is the thermal resistance from the die junction to the package case, and θCA is the thermal resistance from the case through the PC board, copper traces, and other materials to the surrounding air. For optimum power dissipation, use a large ground plane with good thermal contact to the backside pad, and use wide input and output traces. When 1in2 of copper is connected to the device, the maximum allowable power dissipation of a 10-pin TDFN package is 1951mW. The maximum power dissipation is derated by 24.4mW/°C above TA = +70°C. Extra copper on the PC board increases thermal mass and reduces thermal resistance of the board. Refer to the MAX8794 evaluation kit for a layout example. The MAX8794 delivers up to 3A and operates with input voltages up to 3.6V, but not simultaneously. High output currents can only be achieved when the input-output differential voltages are low (Figure 5). Dropout Operation A regulator’s minimum input-to-output voltage differential (dropout voltage) determines the lowest usable supply voltage. Because the MAX8794 uses an n-channel pass transistor, the dropout voltage is a function of the drain-to-source on-resistance (RDS(ON) = 0.25Ω max) multiplied by the load current (see the Typical Operating Characteristics): SAFE OPERATING REGION 3.5 MAXIMUM OUTPUT CURRENT (A) Operating Region and Power Dissipation The maximum power dissipation of the MAX8794 depends on the thermal resistance of the 10-pin TDFN package and the circuit board, the temperature difference between the die and ambient air, and the rate of airflow. The power dissipated in the device is: PSRC = ISRC x (VIN – VOUT) PSINK = ISINK x VOUT The resulting maximum power dissipation is: MAX8794 For a step-voltage change at REFIN, the rate of change of the output voltage is limited by the total output capacitance, the current limit, and the load during the transition. Adding a capacitor across REFIN and AGND filters noise and controls the rate of change of the REFIN voltage during dynamic transitions. With the additional capacitance, the REFIN voltage slews between the two set points with a time constant given by REQ x CREFIN, where REQ is the equivalent parallel resistance seen by the slew capacitor. DROPOUT VOLTAGE LIMITED MAXIMUM CURRENT LIMIT 3.0 2.5 2.0 TA = 0°C TO +70°C 1.5 VIN(MAX) - VOUT(MIN) 1.0 0.5 TA = +100°C 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 INPUT-OUTPUT DIFFERENTIAL VOLTAGE (V) Figure 5. Power Operating Region—Maximum Output Current vs. Input-Output Differential Voltage VDROPOUT = RDS(ON) x IOUT For low output-voltage applications, the sink current is limited by the output voltage and the RDS(ON) of the MOSFET. Input Capacitor Selection Bypass IN to PGND with a 10µF or greater ceramic capacitor. Bypass VCC to AGND with a 1µF ceramic capacitor for normal operation in most applications. Typically, the LDO is powered from the output of a step-down controller (memory supply) that has additional bulk capacitance (polymer or tantalum) and distributed ceramic capacitors. Output Capacitor Selection The MAX8794 output stability is independent of the output capacitance for C OUT from 10µF to 220µF. Capacitor ESR between 2mΩ and 50mΩ is needed to maintain stability. Within the recommended capacitance and ESR limits, the output capacitor should be chosen to provide good transient response: ∆IOUT(P-P) x ESR = ∆VOUT(P-P) where ∆IOUT(P-P) is the maximum peak-to-peak loadcurrent step (typically equal to the maximum source load plus the maximum sink load), and ∆VOUT(P-P) is the allowable peak-to-peak voltage tolerance. Using larger output capacitance can improve efficiency in applications where the source and sink currents change rapidly. The capacitor acts as a reservoir for the rapid source and sink currents, so no extra current is supplied by the MAX8794 or discharged to ground, improving efficiency. ______________________________________________________________________________________ 11 MAX8794 Low-Voltage DDR Linear Regulator Noise, PSRR, and Transient Response PC Board Layout Guidelines The MAX8794 operates with low-dropout voltage and low quiescent current in notebook computers while maintaining good noise, transient response, and ACrejection specifications. Improved supply-noise rejection and transient response can be achieved by increasing the values of the input and output capacitors. Use passive filtering techniques when operating from noisy sources. The MAX8794 load-transient response graphs (see the Typical Operating Characteristics) show two components of the output response: a DC shift from the output impedance due to the load-current change and the transient response. A typical transient response for a step change in the load current from -1.5A to +1.5A is 10mV. Increasing the output capacitor’s value and decreasing the ESR attenuate the overshoot. The MAX8794 requires proper layout to achieve the intended output power level and low noise. Proper layout involves the use of a ground plane, appropriate component placement, and correct routing of traces using appropriate trace widths. Refer to the MAX8794 evaluation kit for a layout example: 1) Minimize high-current ground loops. Connect the ground of the device, the input capacitor, and the output capacitor together at one point. 2) To optimize performance, a ground plane is essential. Use all available copper layers in applications where the device is located on a multilayer board. 3) Connect the input filter capacitor less than 10mm from IN. The connecting copper trace carries large currents and must be at least 2mm wide, preferably 5mm wide. 4) Connect the backside pad to a large ground plane. Use as much copper as necessary to decrease the thermal resistance of the device. In general, more copper provides better heatsinking capabilities. Chip Information TRANSISTOR COUNT: 3496 PROCESS: BiCMOS 12 ______________________________________________________________________________________ Low-Voltage DDR Linear Regulator 6, 8, &10L, DFN THIN.EPS PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm 21-0137 COMMON DIMENSIONS MIN. MAX. PKG. CODE N D2 E2 e JEDEC SPEC b A 0.70 0.80 T633-1 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF D 2.90 3.10 T633-2 6 1.50±0.10 2.30±0.10 0.95 BSC MO229 / WEEA 0.40±0.05 1.90 REF E 2.90 3.10 T833-1 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF A1 0.00 0.05 T833-2 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF 0.40 T833-3 8 1.50±0.10 2.30±0.10 0.65 BSC MO229 / WEEC 0.30±0.05 1.95 REF 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 2.00 REF 2.00 REF 0.20 1 2 PACKAGE VARIATIONS SYMBOL L H [(N/2)-1] x e k 0.25 MIN. T1033-1 10 1.50±0.10 A2 0.20 REF. T1033-2 10 1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05 T1433-1 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF T1433-2 14 1.70±0.10 2.30±0.10 0.40 BSC ---- 0.20±0.05 2.40 REF PACKAGE OUTLINE, 6,8,10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm -DRAWING NOT TO SCALE- 21-0137 H 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX8794 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)