19-1356; Rev 0; 4/98 Active-Matrix Liquid Crystal Display (AMLCD) Supply ____________________________Features ♦ Integrates All Active Circuitry for Three DC-DC Converters ________________________Applications ♦ Ultra-Small External Components (ceramic capacitors, 2µH to 5µH inductors) ♦ DC-DC Converters Phase-Locked to Backplane Frequency for Lowest Noise ♦ Low Operating Voltage (down to +2.8V) ♦ Adjustable Output Voltage from VIN to +5.5V ♦ Load Currents Up to 500mA ♦ Adjustable TFT Gate Driver Output: Positive, VIN to +28V Negative, 0 to -10V (-20V with added components) ♦ Includes 0.35Ω Backplane Driver ♦ 1µA Shutdown Current ♦ Power-Ready Output Signal _______________Ordering Information PART TEMP. RANGE MAX1664CUP PIN-PACKAGE 0°C to +70°C 20 TSSOP Typical Operating Circuit LCD Modules LCD Panels VSUPPLY 2.8V TO 5.5V REF ___________________Pin Configuration TOP VIEW -10V SHDN 1 INP FB2- LX1 LX2P 20 FPLL RDY 2 19 LX1 FB1 3 18 PGND1 5.5V FB1 MAX1664 PGND1 28V LX2N 17 PGND2 REF 4 GND 5 IN MAX1664 IN 6 FB2+ BPVDD PGND2 BPDRV PLLC GND FPLL BPVSS 16 LX2N 15 LX2P FB2- 7 14 INP FB2+ 8 13 BPCLK PLLC 9 12 BPVDD BPVSS 10 11 BPDRV RDY BPCLK SHDN BACKPLANE DRIVER ON OFF REF TSSOP ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MAX1664 ________________General Description The MAX1664 integrates power-supply and backplane drive circuitry for active-matrix thin-film-transistor (TFT) liquid crystal displays. Included are a single-output, pulsewidth-modulation boost converter (0.25Ω switch), a dual-output (positive and negative) gate-driver supply using one inductor, an LCD backplane driver, and a simple phase-locked loop to synchronize all three outputs. High switching frequency (1MHz nominal) and phaselocked operation allow the use of small, minimumheight external components while maintaining low output noise. A +2.8V to +5.5V input voltage range allows operation with any logic supply. Output voltages are adjustable to +5.5V (DC-DC 1) and to +28V and -10V (DC-DC 2). The negative output voltage can be adjusted to -20V with additional components. Also included are a logic-level shutdown and a “Ready” output (RDY) that signals when all three outputs are in regulation. The boost-converter operating frequency can be set at 16, 24, or 32 times the backplane clock. This flexibility allows a high DC-DC converter frequency to be used with LCD backplane clock rates ranging from 20kHz to 72kHz. The MAX1664 is supplied in a 1.1mm-high TSSOP package. MAX1664 Active-Matrix Liquid Crystal Display (AMLCD) Supply ABSOLUTE MAXIMUM RATINGS RDY, IN, BPVDD to GND...........................................-0.3V to +6V FB2-, PGND1, PGND2 to GND ..........................................±0.3V LX1 to PGND1 ..........................................................-0.3V to +6V BPVSS to GND .......................................................-3.3V to +0.3V BPVDD to BPVSS ......................................................-0.3V to +6V BPDRV to BPVSS ..................................-0.3V to (VBPVDD + 0.3V) LX2P to INP ............................................................-15V to +0.3V LX2N to PGND2......................................................-0.3V to +30V SHDN, INP, FB1, FB2+, REF, PLLC, BPCLK, FPLL to GND ................................-0.3V to (VIN +0.3V) RDY Sink Current ................................................................20mA LX2P, LX2N Peak Switch Currents .................................±750mA Continuous Power Dissipation (TA = +70°C) 20-Pin TSSOP (derate 7mW/°C above+70°C) ..............559mW Operating Temperature Range...............................0°C to +70°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = VINP = 3.3V, SHDN = IN, VBPVDD = 4V, VBPVSS = -1V, PGND1 = PGND2 = FPLL = GND, fBPCLK = 30kHz, TA = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Input Supply Range Undervoltage Lockout Threshold SYMBOL CONDITIONS MIN TYP MAX UNITS VIN 2.8 5.5 V VUVLO 2.5 2.8 V Quiescent Current IQ VFB1+ = VFB2+ = 1.3V, VFB2- = -0.1V; IIN + IINP 0.5 2 mA Shutdown Current ISD SHDN = GND, VIN = 5.5V; IIN + IINP 0.01 10 µA 5.5 V DC-DC 1 (PWM MAIN OUTPUT) Output Voltage Range VOUT1 VIN FPLL = GND 32 x fBPCLK FPLL = REF 24 x fBPCLK Operating Frequency fOP1 FB1 Regulation Voltage VFB1 0 < ILX1 < 1.2A IFB1 VFB1 = 1.3V FPLL = IN FB1 Input Bias Current LX1 On Resistance RON(LX1) LX1 Leakage Current ILKG(LX1) LX1 Peak Current Limit ILIM(LX1) Power-Ready Trip Level VTH_RDY 16 x fBPCLK 1.2125 1.2500 0.25 VLX1 = 6V Rising edge, 2% hysteresis Hz 1.275 V 100 nA 0.5 Ω 0.1 10 µA 1.2 1.5 1.8 A 1.091 1.125 1.159 V DC-DC 2 (PFM) Positive Output Voltage Range VOUT2+ VIN 28 V Negative Output Voltage Range VOUT2- -10 0 V Maximum Operating Frequency fOP2(MAX) 2 FPLL = GND 16 x fBPCLK FPLL = REF 12 x fBPCLK FPLL = IN 8 x fBPCLK _______________________________________________________________________________________ Hz Active-Matrix Liquid Crystal Display (AMLCD) Supply (VIN = VINP = 3.3V, SHDN = IN, VBPVDD = 4V, VBPVSS = -1V, PGND1 = PGND2 = FPLL = GND, fBPCLK = 30kHz, TA = 0°C to +70°C, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER MIN TYP MAX UNITS VFB2+ 1.225 1.25 1.275 V FB2- Regulation Voltage VFB2- -15 0 15 mV FB2+, FB2- Input Bias Current IFB2+, IFB2- 100 nA 0.9 1.7 Ω 0.05 10 µA FB2+ Regulation Voltage SYMBOL CONDITIONS VFB2+ = 1.3V, VFB2- = -0.1V -100 LX2N, LX2P On-Resistance RON(LX2N), RON(LX2P) LX2N, LX2P Leakage Current ILKG(LX2N), ILKG(LX2P) FB2- Power-Ready Trip Level VTH(RDY) Falling edge, 40mV hysteresis 85 120 165 mV FB2+ Power-Ready Trip Level VTH(RDY) Rising edge, 40mV hysteresis 1.091 1.125 1.159 V VLX2N = 28V, VLX2P = -10V BACKPLANE DRIVER BPVDD Supply Range VBPVDD 2.5 5.5 V BPVSS Supply Range VBPVSS -3 0 V VVDD to VSS 2.5 5.5 V µA BPVDD to BPVSS Voltage Range BPVDD Shutdown Current ISHDN(BP) SHDN = GND 0.1 10 BPDRV On-Resistance RON(BPDRV) Source and sink 0.35 0.7 Ω BPDRV Leakage Current ILKG(BPDRV) SHDN = GND 10 µA 200 µA BPVDD Supply Current IIN(BPVDD) BPCLK Input Low Voltage VIL(BPCLK) BPCLK Input High Voltage VIH(BPCLK) BPCLK Input Current IIN(BPCLK) -10 VBPCLK = 0 or 3.3V 80 0.3 x VIN 0.7 x VIN V V 0.01 1 µA 1.92 2.20 MHz PLL VCO Center Frequency (Note 1) fC BPCLK Input Frequency Range fBPCLK Reference Voltage VREF Undervoltage Lockout PLLC = REF, BPCLK = GND CPLLC = 22nF RPLLC = 100kΩ CSHUNT = 2.2nF 1.63 FPLL = GND 20 36 FPLL = REF 27 48 FPLL = IN 40 72 -2µA < IREF < 50µA VREF(UVLO) kHz 1.225 1.250 1.275 V 0.90 1.05 1.20 V LOGIC SIGNALS SHDN Input Low Voltage VIL(SHDN) SHDN Input High Voltage VIH(SHDN) SHDN Input Current IIN(SHDN) FPLL Input Current IIN(FPLL) RDY Output Low Voltage RDY Output High Leakage (0.10 x VIN) typical hysteresis 0.3 x VIN 0.7 x VIN V V 0.01 1 µA µA FPLL = GND or IN 0.01 1 ISINK = 2mA 0.05 0.4 V ILKG(RDYOH) VRDY = 5.5V 0.01 1 µA VOL(RDY) Note 1: DC-DC 1 operates at one-half of the VCO frequency (fC / 2). _______________________________________________________________________________________ 3 MAX1664 ELECTRICAL CHARACTERISTICS (continued) __________________________________________Typical Operating Characteristics (fBPCLK = 22.5kHz, FPLL = GND, L1 = 3.3µH, L2 = 4.7µH, TA = +25°C, unless otherwise noted.) DC-DC 1 EFFICIENCY vs. LOAD CURRENT (VOUT1 = +5V) 80 80 70 70 60 VOUT2+ UNLOADED 90 EFFICIENCY (%) EFFICIENCY (%) 100 VIN = 4.5V 50 40 30 MAX1664 TOC02 VIN = 3V 90 DC-DC 2 EFFICIENCY vs. LOAD CURRENT (VOUT2- = -5V) MAX1664 TOC01 100 VIN = 3.3V 60 50 VIN = 5V 40 30 20 20 10 10 0 0 1 10 100 1000 1 10 LOAD CURRENT (mA) DC-DC 2 EFFICIENCY vs. LOAD CURRENT (VOUT2+ = +15V) VOUT1 RIPPLE 80 VIN = 5V MAX1664 TOC03 90 100 MAX1664 TOC04 LOAD CURRENT (mA) 100 EFFICIENCY (%) 70 60 VIN = 3.3V 10mV/div 50 40 30 20 10 VOUT2- UNLOADED 0 1 10 500ns/div IOUT1 = 250mA, L = 3.3µH 100 LOAD CURRENT (mA) VOUT2- RIPPLE VOUT2+ RIPPLE VOUT2 100mV/ div 2µs/div VOUT2+ = 15V, VIN = 3.3V, ILOAD = 9mA, COUT2 = 0.22µF, AC COUPLED 4 MAX1664 TOC06 MAX1664 TOC05 MAX1664 Active-Matrix Liquid Crystal Display (AMLCD) Supply VOUT2- 50mV/ div 5µs/div VOUT2- = -5V, VIN = 3.3V, ILOAD = 5mA, COUT2- = 0.47µF, AC COUPLED _______________________________________________________________________________________ Active-Matrix Liquid Crystal Display (AMLCD) Supply VOUT2+ LINE-TRANSIENT RESPONSE MAX1664 TOC07 MAX1664 TOC08 VOUT1 LINE-TRANSIENT RESPONSE A 50mV/ div A 200mV/ div B 500mV/ div B 500mV/ div 2ms/div 2ms/div VOUT2+ = 15V, ILOAD = 5mA, COUT2+ = 0.22µF A: VOUT2+, 200mV/div, AC COUPLED B: VIN, 3V to 4V VOUT1 = 5V, ILOAD = 250mA, COUT1 = 20µF A: VOUT1, 50mV/div, AC COUPLED B: VIN, 3V to 4V VOUT2- LINE-TRANSIENT RESPONSE MAX1664 TOC10 MAX1664 TOC09 VOUT1 LOAD-TRANSIENT RESPONSE A 200mV/ div A 50mV/ div B 500mV/ div B 100mA/ div 2ms/div 2ms/div VOUT2- = -5V, ILOAD = 5mA, COUT2- = 0.47µF A: VOUT2-, 200mV/div, AC COUPLED B: VIN, 3V to 4V VOUT1 = 5V, VIN = 3.3V, COUT1 = 20µF A: VOUT1, 50mV/div, AC COUPLED B: IOUT1, 25mA TO 225mA, 100mA/div INTERNAL FET ON-RESISTANCE vs. TEMPERATURE BPDRV RISE AND FALL TIME vs. LOAD CAPACITANCE 1000 800 BPDRV P-CHANNEL 600 LX2P 400 250 RISE/FALL TIME (ns) LX2N MAX1664 TOC12 1200 300 MAX1664 TOC 11 INTERNAL FET ON-RESISTANCE (mΩ) 1400 200 RISE TIME 150 100 FALL TIME BPDRV N-CHANNEL 50 200 CLOAD FROM BPDRV TO GND LX1 0 0 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 90 0 0.001 0.01 0.1 1 LOAD CAPACITANCE (µF) _______________________________________________________________________________________ 5 MAX1664 Typical Operating Characteristics (continued) (fBPCLK = 22.5kHz, FPLL = GND, L1 = 3.3µH, L2 = 4.7µH, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (fBPCLK = 22.5kHz, FPLL = GND, L1 = 3.3µH, L2 = 4.7µH, TA = +25°C, unless otherwise noted.) BPCLK TO BPDRV RISING DELAY BPCLK TO BPDRV FALLING DELAY MAX1664 TOC14 MAX1664 TOC14(a)) 2V/div BPDRV 5V/div BPCLK BPCLK 5V/div 2V/div BPDRV 100ns/div 100ns/div CLOAD = 10,000pF CLOAD = 10,000pF NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE OUT-OF-SHUTDOWN SEQUENCE MAX1664 TOC16(a) MAX1664 TOC15 1.8 NO-LOAD SUPPLY CURRENT (mA) MAX1664 Active-Matrix Liquid Crystal Display (AMLCD) Supply 1.6 1.4 5V/div SHDN 2V/div 5V/div VREF 1.2 VOUT1 1.0 VOUT2- 0.8 5V/div 0.6 10V/div INCLUDES ALL EXTERNAL COMPONENT CURRENTS 0.4 0.2 VOUT2+ 5V/div RDY 0 0 1 2 3 4 5 6 500µs/div INPUT VOLTAGE (V) DC-DC 2 SWITCHING WAVEFORMS DISCONTINUOUS CONDUCTION DC-DC 1 SWITCHING WAVEFORMS MAX1664 TOC17(a) VLX1 5V/div 5V/div VLX2N 5V/div VLX2P ILI 500mA/div 500mA/ div IL2 500ns/div IOUT1 = 300mA, L1 = 3.3µH 6 1µs/div VIN = 3.3V; VOUT2+ = 15V/8mA, VOUT2- = -5V/10mA NOTE: LX2N, LX2P PULSES ARE SYNCHED TO DC-DC 1 _______________________________________________________________________________________ Active-Matrix Liquid Crystal Display (AMLCD) Supply PIN NAME FUNCTION 1 SHDN Shutdown Input. Drive low to enter shutdown mode. Drive high or connect to IN for normal operation. All IC sections are off when SHDN is low. 2 RDY Ready Indicator Output, DC-DC 1 and DC-DC 2. Open-drain N-channel output becomes high impedance when all three outputs are within 10% of regulation. 3 FB1 Regulator Feedback Input, DC-DC 1. Regulates to 1.25V nominal. 4 REF Internal Reference Output. Connect a 0.22µF capacitor from this pin to GND. REF can source up to 50µA. 5 GND Analog Ground. Connect to PGND1 and PGND2. See Supply Connections and Layout section. 6 IN 7 FB2- Regulator Feedback Input for Negative Output, DC-DC 2. Regulates to 0V nominal. 8 FB2+ Regulator Feedback Input for Positive Output, DC-DC 2. Regulates to 1.25V nominal. 9 PLLC PLL Compensation. Connect compensation network as in Figure 4. 10 BPVSS Backplane Driver Negative Supply. Typically connected to PGND1. May be connected to a separate supply. 11 BPDRV Backplane Driver Output 12 BPVDD Backplane Driver Positive Supply. Typically connected to VOUT1 of DC-DC 1. May be connected to a separate supply. 13 BPCLK Backplane Driver Clock Input. See Table 1 for input frequency ranges. 14 INP 15 LX2P Drain of Internal LX2P P-Channel MOSFET 16 LX2N Drain of Internal LX2N N-Channel MOSFET 17 PGND2 Power Ground 2. Connect to PGND1. Source of internal LX2N N-channel MOSFET. 18 PGND1 Power Ground 1. Connect to PGND2. Source of internal LX1 N-channel MOSFET. 19 LX1 Drain of Internal LX1 N-Channel MOSFET 20 FPLL Sets the BPCLK input frequency range for PLL synchronization. Connect to GND, REF, or IN. See Table 1. Supply Input to the IC. The input voltage range is +2.8V to +5.5V. DC-DC 2 Power Input. Source of Internal LX2P P-channel MOSFET. _______________________________________________________________________________________ 7 MAX1664 ______________________________________________________________Pin Description MAX1664 Active-Matrix Liquid Crystal Display (AMLCD) Supply REF INP VSUPPLY 2.8V TO 5.5V IN FB2- MAX1664 VOUT1 5.5V LX1 LX2P VOUT2-10V DC-DC 2 DC-DC 1 FB1 VOUT2+ 28V LX2N PGND1 FB2+ BPVDD PGND2 ÷4 ÷2 BPDRV BACKPLANE DRIVER PLLC BPVSS BPCLK PHASE DET FPLL VCO 1.25V REF ÷N RDY IN REF SHDN GND REF GND Figure 1. Functional Diagram _______________Detailed Description The MAX1664 combines power supply and backplane drive circuitry for active matrix thin-film-transistor (TFT) liquid crystal displays (LCD) into one IC. Included are a pulse-width-modulation (PWM) boost converter, a dualoutput (positive and negative) converter using one inductor, an LCD backplane driver, and a phaselocked loop (PLL) to synchronize all three outputs to the backplane clock. A high switching frequency (1MHz nominal) and phaselocked operation allow the use of small, minimumheight external components while maintaining low output noise. Output voltages are adjustable to +5.5V (DC-DC 1) and to +28V and -10V (DC-DC 2). The negative output voltage can be set to as low as -20V with additional components. The frequency ratio between the DC-DC 1 converter and the backplane clock can be set to 16, 24, or 32. This flexibility allows high DC-DC converter frequencies 8 to be used with LCD backplane clock rates ranging from 20kHz to 72kHz. Start-Up At start-up, both converters remain disabled until VREF reaches 90% of its nominal value. VOUT1 is activated first. Once V OUT1 is regulated, V OUT2- is enabled. VOUT2+ is held at 0 until VOUT2- is within 90% of its regulation target. All three outputs power up in a similar order when power is applied or when coming out of shutdown. See the Out-of-Shutdown Sequence photo in the Typical Operating Characteristics section. DC-DC 1 Boost Converter DC-DC 1 uses a current-mode boost PWM architecture to produce a positive regulated voltage, adjustable from 3V to 5.5V (but not less than VIN). This converter uses an internal N-channel MOSFET with a maximum on-resistance of 0.5Ω. Cycle-by-cycle peak current limiting protects the switch under fault conditions. Upon start-up, DC-DC 1 is the first converter to be enabled. _______________________________________________________________________________________ Active-Matrix Liquid Crystal Display (AMLCD) Supply MAX1664 Table 1. Switching Frequency Options FPLL fBPCLK (kHz) fDC-DC 1 (kHz) fDC-DC 2 MAX (kHz) fDC-DC 1: fBPCLK fDC-DC 2 MAX: fBPCLK N* IN 40 to 72 640 to 1152 320 to 576 16:1 8:1 32 REF 27 to 48 640 to 1152 320 to 576 24:1 12:1 48 GND 20 to 36 640 to 1152 320 to 576 32:1 16:1 64 *See Figure 2 Fixed-frequency, current-mode operation ensures that the switching noise exists only at the operating frequency and its harmonics. The switching frequency is phase locked to the backplane clock input. Table 1 illustrates the possible switching-frequency options. loads, the controller may skip one or more cycles of either polarity, thereby keeping the outputs in regulation. See Table 1 for the relationship between the maximum DC-DC 2 pulse frequency and the backplane clock frequency. DC-DC 2 Dual Outputs Outputs with Low Step-Up or Inversion Ratios For DC-DC 2 output voltage setpoints, which require minimum step-up or inversion ratios (for example, VOUT+ < 6V or VOUT- > -3V, when VINP = 5V), more than one half-cycle may be required to transfer the inductor energy to the appropriate output filter capacitor. In such cases, subsequent conversion cycles are delayed, as necessary, by one or more PFM clock cycles to preserve discontinuous mode operation. DC-DC 2 uses a synchronized, fixed on-time PFM architecture to provide the positive and negative output voltages that allow the driver ICs to turn the TFT gates on and off. When pulses occur, they are synchronized to DC-DC 1, thereby minimizing converter interactions and subharmonic interference. The DC-DC 2 inductor current is always discontinuous, enabling the dual outputs to be regulated independently. This allows one output to be at 100% load while the other is at no load. DC-DC 2 Operation In normal operation, DC-DC 2 alternates between charging the negative and positive outputs (Figure 1). During the first half-cycle of the PFM clock period, both the N-channel and P-channel MOSFETs turn on, applying the input supply across inductor L2. This causes the inductor current to ramp up at a rate proportional to V INP . During the second half-cycle, the P-channel MOSFET turns off and the inductor transfers its energy into the negative output filter capacitor. Assuming that the energy transfer is completed during this second half-cycle and the inductor current ramps down to zero, the process is repeated for the positive output during the next clock cycle. During the first half of the second clock cycle, both the N-channel and Pchannel MOSFETs turn on again. The current in the inductor again rises at the same rate. During the second half of the second clock cycle, the N-channel MOSFET is turned off and this time the inductor energy transfers to the positive output filter capacitor. During conditions of heavy loads, DC-DC 2 will continue to operate in this manner, alternately delivering pulses to the negative and positive outputs. For lighter Backplane Driver The MAX1664 provides a low-impedance backplane driver, as shown in Figure 1, that level-translates the BPCLK signal from a logic level to BPVDD/BPVSS levels. The backplane driver consists of an N-channel/P-channel complementary pair of high-current MOSFETs. These devices drive BPDRV to either BPVDD or BPVSS when BPCLK goes either high or low, respectively. The switches have a maximum on-resistance of 0.7Ω with a typical propagation delay of 50ns. Power for the backplane driver can be taken from the output of DC-DC 1, VOUT1, as shown in the Typical Operating Circuit. Phase-Locked Loop The MAX1664 contains an on-board PLL to synchronize the PWM and PFM converter clocks to the backplane clock (Figure 2). This will minimize noise and interference. The PLL is a frequency-multiplying type, generating a nominal 1MHz clock signal for DC-DC 1 and a nominal 500kHz clock for DC-DC 2. Three input frequency ranges, spanning 20kHz to 72kHz, permit synchronization over a broad range of backplane clock input frequencies while maintaining optimal conversion frequencies (Table 1). _______________________________________________________________________________________ 9 MAX1664 Active-Matrix Liquid Crystal Display (AMLCD) Supply REF PLLC PHASE DETECTOR VOUT1 VCO CSHUNT ÷2 RPLLC R5 DC-DC 1 FB2- VOUT2+ CPLLC R1 MAX1664 FB1 ÷4 ÷N* DC-DC 2 BPVDD CFB1 R6 R2 R7 R3 CC VOUT2FB2+ DC BIAS BPDRV BPCLK R8 *SEE TABLE 1 FOR SELECTED VALUES OF N. IN REF R4 GND BPVSS Figure 2. Internal PLL Operation within the MAX1664 Figure 3. Output Voltage Selection The heart of the PLL is the VCO, which is trimmed to a nominal frequency of 1.92MHz for a control voltage (at the PLLC pin) of 1.250V. This high-frequency internal clock is divided digitally with a division ratio selected by pin-strapping FPLL to GND, REF, or IN. This divided clock is compared to the backplane clock by an internal phase comparator (rising-edge triggered). The phase detector in turn adjusts the VCO control voltage until the two frequencies (and phases) match. This feedback loop is compensated at the PLLC pin. In some applications, the backplane clock may be halted for several cycles between screen scans or may not be immediately applied on power-up. The PLL contains a proprietary phase-detector architecture that minimizes frequency error during clock dropouts of more than two cycles and re-establishes lock immediately when the clock resumes. Ready Indicator (RDY) The RDY pin has an open-drain output and indicates when all three outputs are in regulation. The open-drain output becomes high impedance when all three converter outputs are within 10% of their regulation setpoints. Design Procedure and ______________Component Selection DC-DC 1 Output For VOUT1 = 5V, typical values are R2 = 100kΩ and R1 = 301kΩ. To set VOUT1 to another voltage, choose R2 = 100kΩ and CFB1 = 50pF, and calculate R1 as follows: V R1 = R2 OUT1 - 1 VFB1 DC-DC 2 Positive Output For VOUT2+ = 15V, typical values are R8 = 49.9kΩ and R7 = 549kΩ. To set VOUT2+ to another voltage, choose R8 = 49.9kΩ and calculate R7 as follows: V R7 = R8 OUT2 + - 1 VFB2 + DC-DC 2 Negative Output For the negative output voltage, the FB2- threshold voltage is 0. For VOUT2- = -5V, typical values are R5 = 49.9kΩ and R6 = 200kΩ. To set VOUT2+ to another voltage, choose R5 = 49.9kΩ and calculate R6 as follows: R6 = R5 VOUT2VREF Output Voltage Selection The three output voltages as well as the DC bias for the backplane clock are adjustable on the MAX1664, as shown in Figure 3. Set each output using two standard 1% resistors to form a voltage divider between the selected output and its respective feedback pin. Use the following equations to calculate the resistances. 10 DC Bias for the Backplane Driver For VDCBIAS = VBPVDD/2, typical values are R3 = R4 = 100kΩ. To set the DC bias to a different value, choose R4 and calculate R3 as follows: V - VBPVSS R3 = R4 BPVDD VDCBIAS - VBPVSS - 1 ______________________________________________________________________________________ Active-Matrix Liquid Crystal Display (AMLCD) Supply 2.2µF 10µF 2.2µF 3.3µH R5 49.9k IN INP VOUT1 5.5V LX1 FB2R6 200k VOUT2-5V LX2P 3 x 10µF R1 301k 50pF R2 100k FB1 D2 0.47µF MAX1664 0.47µF REF VSUPPLY 2.8V TO 5.5V 33Ω L2 4.7µH 0.22µF VOUT2+ 15V MAX1664 PGND1 LX2N R7 D3 549k FB2+ BPVDD R8 49.9k R3 100k 10µF PGND2 BPDRV 2 x 10µF PLLC 2.2nF 100k 22nF BACKPLANE DRIVER R4 100k BPVSS BPCLK RDY GND FPLL SHDN ON OFF REF 0.22µF Figure 4. Detailed Typical Operating Circuit Inductor Selection The optimum inductor value for L1 is 3.3µH, as shown in Figure 4. Inductors with less than 300mΩ DC series resistance are recommended to achieve the highest efficiency. Using a larger value for L1 (e.g., 4.7µH) increases the output current capability of DC-DC 1 (by reducing the peak ripple current) at the expense of size and the additional output filter capacitance needed for loop stability. For DC-DC 2, at large input voltages (i.e., 5V) and low switching frequencies (i.e., ≤400kHz), the value of L2 should be increased (e.g., 6.8µH or 10µH) to limit the peak current. In some cases it may be necessary to reduce the value of L2 to increase the output current capability of DC-DC 2 (Table 2). The relationship between input voltage, output voltage, switching frequency, inductor value, and maximum load current for DC-DC 2 is complex and nonlinear. This relationship is summarized in Table 2. The L2 equation is as follows: L2 > [ VINP - RON(LX2P) + RON(LX2N) + RL2 ( IPEAK x 2 fDC-DC 1 ) ] (I 2 PEAK ) where: Internal MOSFET on-resistance: RON(LX2P) = RON(LX2N) = 0.9Ω typical External inductor DC resistance: RL2 = 0.3Ω typical Inductor peak current: IPEAK = 700mA (750mA absolute maximum) Due to the MAX1664’s high switching frequency, inductors with a high-frequency core material such as ferrite are recommended. Powdered iron compounds are not recommended due to their higher core losses. Typical small-size, low-profile inductors include the ILS-3825 (Dale Electronics-Vishay) and the CLQ61B (Sumida). These inductors are primarily used for DC-DC converters with low height requirements. See Table 3 for more information on manufacturers who provide low-profile inductors. ______________________________________________________________________________________ 11 MAX1664 Active Matrix Liquid Crystal Display (AMLCD) Supply Table 2. Typical DC-DC 2 Operation VOUT2+ (V) VOUT2(V) VIN (V) fBPCLK (kHz) L2 (µH) IOUT2+(MAX) (mA) IOUT2-(MAX) (mA) fDC-DC 2(MAX) (kHz) INDUCTOR PEAK CURRENT* (mA) +15 +15 +15 +15 +15 +15 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 +20 -5 -5 -5 -5 -5 -5 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 -10 3.0 3.0 3.3 3.3 4.5 5.0 3.0 3.0 3.0 3.0 3.0 3.0 3.3 3.3 3.3 3.3 3.3 3.3 4.5 4.5 4.5 4.5 5.0 5.0 5.0 22.5 22.5 22.5 22.5 22.5 22.5 22.5 22.5 25.0 25.0 30.0 30.0 22.5 22.5 25.0 25.0 30.0 30.0 22.5 25.0 30.0 30.0 22.5 25.0 30.0 4.7 2.7 4.7 2.7 4.7 4.7 4.7 2.7 4.7 2.7 4.7 2.7 4.7 2.7 4.7 2.7 4.7 4.7 4.7 4.7 4.7 2.7 4.7 4.7 4.7 6 8 7 10 15 20 3 5 2 4 3 3 4 6 4 6 4 4 9 8 8 10 11 10 10 15 23 19 27 35 43 6 10 5 8 4 6 8 12 7 10 5 8 16 14 12 17 20 18 15 360 360 360 360 360 360 360 360 400 400 480 480 360 360 400 400 480 480 360 400 480 480 360 400 480 375 585 425 643 550 600 385 585 340 530 300 451 425 643 370 583 340 496 580 500 450 679 640 550 500 *Note: Absolute maximum peak current at LX2P and LX2N is 750mA. Diode Selection The MAX1664’s high switching frequency requires fast diodes. Schottky diodes such as the MBR0520L and MBR0540L (Motorola) are recommended because they have the necessary power ratings in a low-height SOD123 package. Also recommended is the MBRM5817 which is 1.1mm high. Use a Schottky diode with a forward current rating greater than: I V IF > OUT OUT 0.9VIN For the positive output of DC-DC 2, use a Schottky diode with a voltage rating that exceeds VOUT2+. For the negative output, use a Schottky diode with a rating 12 that exceeds VIN + V OUT2-. See Table 3 for more information on Schottky diode manufacturers. Filter Capacitor Selection An output filter capacitor’s ESR and size can greatly influence a switching converter’s output ripple, as shown in the following equation. t VRIPPLE(PK − PK) ≅ IPEAK x RESR + IOUT ON C OUT VOUT1 + VF - VIN fDC -DC 1 VOUT1 + VF 1 DC - DC 2 tON = 2 fDC -DC 1 DC - DC 1 tON = 1 ______________________________________________________________________________________ Active-Matrix Liquid Crystal Display (AMLCD) Supply 33Ω C1 3.3µF (x2) 0.47µF VSUPPLY 2.8V TO 3.6V 3.3µH IN INP PLL Compensation In most applications, the recommended compensation component values shown in Figure 4 will give optimal system performance. If no backplane clock is used, connect PLLC to REF. Table 3. Component Manufacturers MANUFACTURER PHONE D1 V1 LX1 C2 3.3µF (x2) D2 10V 150mA MAX1664 C4 3.3µF (x2) D3 FAX R1 91k C3 3.3µF (x6) FB1 INDUCTORS 50pF R2 13k Dale Inductors (605) 668-4131 (605) 665-1627 Sumida USA (847) 956-0666 (847) 956-0702 Central Semiconductor (516) 435-1110 (516) 435-1824 International Rectifier (310) 322-3331 (310) 322-3232 Motorola (602) 303-5454 (602) 994-6430 Figure 5. Charge Pump Configuration to Increase VOUT1 Above 5.5V. Marcon/United Chemicon (847) 696-2000 (847) 696-9278 TDK (847) 390-4373 (847) 390-4428 COUT are 0.47µF to 1µF and 4.7µF to 10µF, respectively. As a general rule, COUT should be ten times greater than CF. This circuit operates as follows: Taiyo Yuden (408) 573-4150 (408) 573-4159 Vishay/Vitramon (203) 268-6261 (203) 452-5670 PGND1 DIODES CERAMIC CAPACITORS _____________Applications Information Increasing VOUT Above 5.5V For VOUT1 output voltages above 5.5V, connect the supplemental charge pump circuit shown in Figure 5. The connection shown supplies a 10V 150mA output, but other voltages from 2 x VIN to 10V can be set by selecting the appropriate values for R1 and R2 (see DC-DC 1 Output section). C2–C4 are shown as parallel combinations of 3.3µF ceramic capacitors so that a 1.1mm height restriction can be met. If height is not restricted, then larger values can be used instead of parallel capacitor combinations. 3.3V to -20V Charge-Pump Configuration For applications requiring negative voltages down to -20V, an inverting charge-pump block can be added to the VOUT2- output (Figure 6). Typical values for CF and D1, D2, D3— MBRM5817 C1, C2, C3—ALL CERAMIC TYPES 1) During the first PFM cycle, the voltage at V1 is charged by inductor L2 to some fraction of its final steady-state voltage, in the normal manner described in the Detailed Description. 2) During the first half of subsequent PFM cycles, pin LX2P is pulled to VINP, and capacitor CF is charged to (VINP +V1 - VD), where VD is a diode forward voltage. 3) During subsequent second half-cycles when LX2P flies negatively below V1, capacitor C F transfers some of its energy to output capacitor COUT, which then is charged to a negative voltage of approximately (VINP + 2 x V1 - 2x VD). 4) This process continues until V OUT reaches the desired voltage, as determined by the ratio of the FB2- feedback resistors. 5) During steady-state (in-regulation) operation, the magnitude of the voltage at LX2P is equal to (VOUT / 2 - VINP / 2 + VD), which must be limited to less than 10V. ______________________________________________________________________________________ 13 MAX1664 Ceramic capacitors are recommended because they have low ESR and the lowest profile. Typical ceramic capacitors are the C3225X5R series from TDK and JMK325 series from Taiyo Yuden. See Table 3 for more information on the manufacturers who provide surfacemount ceramic capacitors. MAX1664 Active-Matrix Liquid Crystal Display (AMLCD) Supply Supply Connections and Layout The MAX1664 performs both precision analog and high-power switching functions. Carefully plan supply connections, bypassing, and layout. Bypass IN and INP with a 33Ω isolation resistor (R9, Figure 4) between them. In addition, sufficient low-ESR bypassing must be provided on the INP bus to ensure stability of DC-DC 1. A solid ground plane under the power components, with a separate ground plane under the analog nodes, is highly recommended. These ground planes should be connected at a single, quiet point. Analog reference and feedback signals should be referred to and routed over the analog ground plane. Figure 7 shows a typical layout using separate ground planes. REF R5 FB2R6 VOUT2-20V COUT 4.7µF D4 CF V1 0.47µF MAX1664 D5 LX2P D2 L2 0.22µF VOUT2+ 28V LX2N R7 D3 FB2+ R8 PGND2 Figure 6. VOUT2- Voltage-Doubler Charge Pump 1.0" Figure 7a. MAX1664 Component Placement Guide 14 1.0" Figure 7b. MAX1664 PC Board Layout—Component Side ______________________________________________________________________________________ Active-Matrix Liquid Crystal Display (AMLCD) Supply TRANSISTOR COUNT: 838 1.0" Figure 7c. MAX1664 PC Board Layout—Solder Side ______________________________________________________________________________________ 15 MAX1664 ___________________Chip Information ________________________________________________________Package Information TSSOP.EPS MAX1664 Active-Matrix Liquid Crystal Display (AMLCD) Supply Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.