DS26401DK Octal T1/E1/J1 Framer Design Kit Daughter Card www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26401DK is an easy-to-use evaluation board for the DS26401 octal T1/E1/J1 framer. It is intended to be used as a daughter card with the DK101 motherboard or the DK2000 motherboard. The DS26401DK comes complete with a DS26401 octal framer, two DS21448 quad LIUs, transformers, termination resistors, network connectors, and motherboard connectors. The DK101/DK2000 motherboard and the Dallas’ ChipView software give point-and-click access to configurations and status registers from a Windowsâ-based PC. On-board LEDs indicate loss-of-signal, loss-of-frame, and interrupt status. § Each DS26401DK is shipped with a free DK101 motherboard. For complex applications, the DK2000 high-performance demo kit motherboard can be purchased separately. Windows is a registered trademark of Microsoft Corp. DESIGN KIT CONTENTS DS26401DK Board DK101 Low-Cost Motherboard CD-ROM ChipView Software DS26401DK Data Sheet DK101 Data Sheet DS26401 Data Sheet DS21448 Data Sheet DS26401 Errata Sheet DS21448 Errata Sheet § § § § § § § Demonstrates Key Functions of the DS26401 Octal T1/E1/J1 Framer Includes Two DS21448 Quad LIUs, Transformers, BNC and RJ45 Connectors, and Termination Passives Compatible with DK101 and DK2000 Demo Kit Motherboards DK101/DK2000 and ChipView Software Provide Point-and-Click Access to the DS26401 Register Set All Equipment-Side Framer Pins are Easily Accessible for External Data Source/Sink Memory-Mapped FPGA Provides Flexible Clock/Data/Sync Connections Among Framer Ports and DK2000 Motherboard LEDs for Loss-of-Signal, Loss-of-Frame, and Interrupt Easy-to-Read Silk-Screen Labels Identify the Signals Associated with All Connectors, Jumpers, and LEDs ORDERING INFORMATION PART DS26401DK 1 of 34 DESCRIPTION DS26401 Demo Kit Daughter Card (with included DK101 motherboard) REV: 122203 DS26401DK Octal T1/E1/J1 Framer Design Kit COMPONENT LIST DESIGNATION C1, C3, C5, C7, C9, C11, C13, C15, C17–C24, C26, C28–C31, C35–C42 C2, C4, C6, C8, C10, C12, C14, C16 QTY DESCRIPTION SUPPLIER PART 29 00.1mF 20%, 16V X7R ceramic capacitors (0603) AVX 0603YC104MAT 8 1mF 10%, 16V ceramic capacitors (1206) Panasonic ECJ-3YB1C105K DS1, DS18 2 LED, green, SMD Panasonic LN1351C DS2–DS17 16 LED, red, SMD Panasonic LN1251C J1, J3–J10, J12-J18 16 5-pin connectors, 75W BNC vertical Bourns CP-BNCPC-004 J2, J11 2 Right-angle, RJ45 8-pin 4-port jack 3M Electronics 43223-8140 J19, J20 2 50-pin headers, socket, SMD dual row, vertical Samtec TFM-125-02-S-D-LC 8 20-pin headers, dual row, vertical Samtec HDR-TSW-110-14-T-D 8 10-pin headers, dual row, vertical Murrietta N/A 1 12-pin connector, dual row, vertical Murrietta N/A 17 0W 1%, 1/16W resistors (0603) AVX CJ10-000F 16 60.4W 1%, 1/16W resistors (0603) Panasonic ERJ-3EKF60R4V R33–R35 3 10kW 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ103V R36, R37, R68 3 330W 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ331V R38, R59–R66 9 30.1W 1%, 1/16W resistors (0603) Panasonic ERJ-3EKF30R1V R39–R54 16 300W 5%, 1/16W resistors (0603) Panasonic ERJ-3GEYJ301V R55–R58 4 10.0kW 1%, 1/16W resistors (0603) Panasonic ERJ-3EKF1002V T1–T8 8 XFMR, dual, 16-pin SMT Pulse Engineering TX1467 U1 1 Octal T1/E1/J1 framer Dallas Semiconductor DS26401 U2, U3 2 Dallas Semiconductor DS21448L U4 1 Xilinx XC18V01VQ44C_U U6 1 Maxim MAX1792EUA25 U7 1 Xilinx XC2S50-5FG256C J21, J23, J25, J27, J29, J31, J33, J35 J22, J24, J26, J28, J30, J32, J34, J36 JP1 R1, R2, R5, R6, R9, R10, R13, R14, R17, R18, R21, R22, R25, R26, R29, R30, R67 R3, R4, R7, R8, R11, R12, R15, R16, R19, R20, R23, R24, R27, R28, R31, R32 3.3V E1/T1/J1 quad LIU 128-pin LQFP, 0°C to +70°C 1M PROM for FPGA 44-pin TQFP 8-pin mMAX/SO 2.5V or Adj XILINX Spartan 2.5V FPGA, 256-pin BGA 2 of 34 DS26401DK Octal T1/E1/J1 Framer Design Kit LED RLOF, RLOS x 4 TEST POINTS (x4) TCLK RCLK TSYSCLK RSYSCLK TSYNC RSYNC TSSYNC RMSYNC TSIG RSIG TSER RSER TCHBLK RCHBLK TCLKO FPGA LED RLOF, RLOS x 4 CPU INTERFACE CONFIG PROM CPU INTERFACE JTAG I/F BOARD FLOORPLAN DS21448 LIU DS26401 FRAMER TEST POINTS (x4) TCLK RCLK TSYSCLK RSYSCLK TSYNC RSYNC TSSYNC RMSYNC TSIG RSIG TSER RSER TCHBLK RCHBLK TCLKO 3 of 34 DS21448 LIU XFMR TXRX PORT 8 BNC PORT 8 RJ45 XFMR TXRX PORT 7 BNC PORT 7 RJ45 XFMR TXRX PORT 6 BNC PORT 6 RJ45 XFMR TXRX PORT 5 BNC PORT 5 RJ45 XFMR TXRX PORT 4 BNC PORT 4 RJ45 XFMR TXRX PORT 3 BNC PORT 3 RJ45 XFMR TXRX PORT 2 BNC PORT 2 RJ45 XFMR TXRX PORT 1 BNC PORT 1 RJ45 DS26401DK Octal T1/E1/J1 Framer Design Kit QUICK SETUP (REGISTER VIEW) · Connect DS26401DK to DK101 motherboard. · Connect serial cable to a PC and DK101. · Power DK101 with 3.3V. · Load ChipView software. · Select COM port. · Select Register View. · For T1 applications, load the 401_global_t1_DS26401DC.def file. For E1 applications, load the 401_global_e1_DS26401DC.def file. · Make sure that all the register settings are correct for the proper function desired for the DS26401DK. Please refer to the DS26401 data sheet (www.maxim-ic.com/DS26401) and the DS21448 data sheet (www.maxim-ic.com/DS21448) for all questions pertaining to device functionality. ADDRESS MAP DK101 daughter card address space begins at 0x81000000. DK2000 daughter card address space begins at: 0x30000000 for slot 0 0x40000000 for slot 1 0x50000000 for slot 2 0x60000000 for slot 3 All offsets given below are relative to the beginning of the daughter card address space. Table 1. Daughter Card Address Map SPAN NUMBER 1 2 3 4 5 6 7 8 OFFSET DS26401 DS21448 FPGA 0x1000 0x1200 0x1400 0x1600 0x1800 0x1A00 0x1C00 0x1E00 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0x10 0x20 0x30 0x40 0x50 0x60 0x70 0x80 Registers in the FPGA can be easily modified using ChipView.exe host-based user-interface software along with the definition file named DS26401DC_FPGA.def. 4 of 34 DS26401DK Octal T1/E1/J1 Framer Design Kit FPGA REGISTER MAP Table 2. FPGA Register map OFFSET NAME TYPE 0X0000 0X0002 0X0003 0X0004 0X0005 0X0006 0X0007 BID XBIDH XBIDM XBIDL BREV AREV PREV Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Board ID High Nibble Extended Board ID Middle Nibble Extended Board ID Low Nibble Extended Board ID Board FAB Revision Board Assembly Revision PLD Revision 0X0010 0x0020 0x0030 0x0040 0x0050 0x0060 0x0070 0x0080 TSIG_SR –1 TSIG_SR –2 TSIG_SR –3 TSIG_SR –4 TSIG_SR –5 TSIG_SR –6 TSIG_SR –7 TSIG_SR –8 Control DS26401 TSIG Pin Setting Port 1 DS26401 TSIG Pin Setting Port 2 DS26401 TSIG Pin Setting Port 3 DS26401 TSIG Pin Setting Port 4 DS26401 TSIG Pin Setting Port 5 DS26401 TSIG Pin Setting Port 6 DS26401 TSIG Pin Setting Port 7 DS26401 TSIG Pin Setting Port 8 0X0011 0X0021 0X0031 0X0041 0x0051 0x0061 0x0071 0x0081 TSER_SR –1 TSER_SR –2 TSER_SR –3 TSER_SR –4 TSER_SR –5 TSER_SR –6 TSER_SR –7 TSER_SR –8 Control DS26401 TSER Pin Setting Port 1 DS26401 TSER Pin Setting Port 2 DS26401 TSER Pin Setting Port 3 DS26401 TSER Pin Setting Port 4 DS26401 TSER Pin Setting Port 5 DS26401 TSER Pin Setting Port 6 DS26401 TSER Pin Setting Port 7 DS26401 TSER Pin Setting Port 8 0X0012 0X0022 0X0032 0X0042 0X0052 0X0062 0X0072 0X0082 TSSYNC_SR –1 TSSYNC_SR –2 TSSYNC_SR –3 TSSYNC_SR –4 TSSYNC_SR –5 TSSYNC_SR –6 TSSYNC_SR –7 TSSYNC_SR –8 0X0013 0X0023 0X0033 0X0043 0X0053 0X0063 0X0073 0X0083 TSYSCLK –1 TSYSCLK –2 TSYSCLK –3 TSYSCLK –4 TSYSCLK –5 TSYSCLK –6 TSYSCLK –7 TSYSCLK –8 0X0014 0X0024 0X0034 0X0044 0X0054 0X0064 0X0074 0X0084 RSYSCLK –1 RSYSCLK –2 RSYSCLK –3 RSYSCLK –4 RSYSCLK –5 RSYSCLK –6 RSYSCLK –7 RSYSCLK –8 Control Control Control DESCRIPTION DS26401 TSSYNC Source Port 1 DS26401 TSSYNC Source Port 2 DS26401 TSSYNC Source Port 3 DS26401 TSSYNC Source Port 4 DS26401 TSSYNC Source Port 5 DS26401 TSSYNC Source Port 6 DS26401 TSSYNC Source Port 7 DS26401 TSSYNC Source Port 8 DS26401 TSYSCLK Source Port 1 DS26401 TSYSCLK Source Port 2 DS26401 TSYSCLK Source Port 3 DS26401 TSYSCLK Source Port 4 DS26401 TSYSCLK Source Port 5 DS26401 TSYSCLK Source Port 6 DS26401 TSYSCLK Source Port 7 DS26401 TSYSCLK Source Port 8 DS26401 RSYSCLK Source Port 1 DS26401 RSYSCLK Source Port 2 DS26401 RSYSCLK Source Port 3 DS26401 RSYSCLK Source Port 4 DS26401 RSYSCLK Source Port 5 DS26401 RSYSCLK Source Port 6 DS26401 RSYSCLK Source Port 7 DS26401 RSYSCLK Source Port 8 5 of 34 DS26401DK Octal T1/E1/J1 Framer Design Kit Table 2. Register Map (continued) OFFSET NAME 0X0015 0X0025 0X0035 0X0045 0X0055 0X0065 0X0075 0X0085 TCLK –1 TCLK –2 TCLK –3 TCLK –4 TCLK –5 TCLK –6 TCLK –7 TCLK –8 0X0016 0X0026 0X0036 0X0046 0X0056 0X0066 0X0076 0X0086 RSYNC –1 RSYNC –2 RSYNC –3 RSYNC –4 RSYNC –5 RSYNC –6 RSYNC –7 RSYNC –8 0X0017 0X0027 0X0037 0X0047 0X0057 0X0067 0X0077 0X0087 0X0090 TYPE DESCRIPTION Control DS26401TCLK Source Port 1 DS26401TCLK Source Port 2 DS26401TCLK Source Port 3 DS26401TCLK Source Port 4 DS26401TCLK Source Port 5 DS26401TCLK Source Port 6 DS26401TCLK Source Port 7 DS26401TCLK Source Port 8 Control DS26401RSYNC Source Port 1 DS26401RSYNC Source Port 2 DS26401RSYNC Source Port 3 DS26401RSYNC Source Port 4 DS26401RSYNC Source Port 5 DS26401RSYNC Source Port 6 DS26401RSYNC Source Port 7 DS26401RSYNC Source Port 8 TSYNC –1 TSYNC –2 TSYNC –3 TSYNC –4 TSYNC –5 TSYNC –6 TSYNC –7 TSYNC –8 Control DS26401TSYNC Source Port 1 DS26401TSYNC Source Port 2 DS26401TSYNC Source Port 3 DS26401TSYNC Source Port 4 DS26401TSYNC Source Port 5 DS26401TSYNC Source Port 6 DS26401TSYNC Source Port 7 DS26401TSYNC Source Port 8 CLK Control LIU MCLK and REF CLK Source ID Registers BID: BOARD ID (Offset = 0X0000) BID is read-only with a value of 0xD. XBIDH: HIGH NIBBLE EXTENDED BOARD ID (Offset = 0X0002) XBIDH is read-only with a value of 0x0. XBIDM: MIDDLE NIBBLE EXTENDED BOARD ID (Offset = 0X0003) XBIDM is read-only with a value of 0x1. XBIDL: LOW NIBBLE EXTENDED BOARD ID (Offset = 0X0004) XBIDL is read-only with a value of 0x6. BREV: BOARD FAB REVISION (Offset = 0X0005) BREV is read-only and displays the current fab revision. AREV: BOARD ASSEMBLY REVISION (Offset = 0X0006) AREV is read-only and displays the current assembly revision. PREV: PLD REVISION (Offset = 0X0007) PREV is read-only and displays the current PLD firmware revision. 6 of 34 DS26401DK Octal T1/E1/J1 Framer Design Kit Control Registers Register Name: TSIG_SR Register Description: DS26401 TSIG x Pin Setting Register Offset: 0x0010, 0x0020, 0x0030, 0x0040, 0x0050, 0x0060, 0x0070, 0x0080 Bit # Name 7 D7 6 D6 5 D5 4 D4 3 D3 Bit 0 to 7: DS26401 Port x TSIG Source (D7, D6, D5, D4, D3, D2, D1, D0) The source for TSER is Defined as shown in Table 3. Table 3. TSERx Source Definition D3, D2, D1, D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1010 1011 1100 1101 1110 1111 TSIG CONNECTION Tri-state TSIG Drive TSIG with RSIG1 Drive TSIG with RSIG2 Drive TSIG with RSIG3 Drive TSIG with RSIG4 Drive TSIG with RSIG5 Drive TSIG with RSIG6 Drive TSIG with RSIG7 Drive TSIG with RSIG8 Drive TSIG with T1 OSC Drive TSIG with E1 OSC Drive TSIG with 16.384MHz Drive TSIG with a logic 0 Drive TSIG with a logic 1 Tri-state TSIG Note: Initial values are such that all values are tri-stated. 7 of 34 2 D2 1 D1 0 D0 DS26401DK Octal T1/E1/J1 Framer Design Kit Register Name: TSER_SR Register Description: DS26401 TSERx Pin Setting Register Offset: 0x0011, 0x0021, 0x0031, 0x0041, 0x0051, 0x0061, 0x0071, 0x0081 Bit # Name 7 — 6 — 5 — 4 — Bit 0 to 3: DS26401 Port x TSER Source (D3, D2, D1, D0) The source for TSER is Defined as shown in Table 4. Table 4. TSERx Source Definition D3, D2, D1, D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1010 1011 1100 1101 1110 1111 TSER CONNECTION Tri-state TSER Drive TSER with RSER1 Drive TSER with RSER2 Drive TSER with RSER3 Drive TSER with RSER4 Drive TSER with RSER5 Drive TSER with RSER6 Drive TSER with RSER7 Drive TSER with RSER8 Drive TSER with T1 OSC Drive TSER with E1 OSC Drive TSER with 16.384MHz Drive TSER with a logic 0 Drive TSER with a logic 1 Tri-state TSER Note: Initial values are such that all ports are tri-stated. 8 of 34 3 D3 2 D2 1 D1 0 D0 DS26401DK Octal T1/E1/J1 Framer Design Kit Register Name: TSSYNC_SR Register Description: DS26401 TSSYNCx Pin Setting Register Offset: 0x0012, 0x0022, 0x0032, 0x0042, 0x0052, 0x0062, 0x0072, 0x0082 Bit # Name Default 7 — 0 6 — 0 5 — 0 4 — 0 Bit 0 to 2: DS26401 Port x TSSYNC Source (D3, D2, D1, D0) The source for TSSYNC is Defined as shown in Table 5. Table 5. TSSYNCx Source Definition D3, D2, D1, D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1010 1011 1100 1101 1110 1111 TSSYNC CONNECTION Tri-state TSSYNC Drive TSSYNC with RMSYNC1 Drive TSSYNC with RMSYNC2 Drive TSSYNC with RMSYNC3 Drive TSSYNC with RMSYNC4 Drive TSSYNC with RMSYNC5 Drive TSSYNC with RMSYNC6 Drive TSSYNC with RMSYNC7 Drive TSSYNC with RMSYNC8 Drive TSSYNC with T1 OSC Drive TSSYNC with E1 OSC Drive TSSYNC with 16.385MHz Drive TSSYNC with a logic 0 Drive TSSYNC with a logic 1 Tri-state TSSYNC Note: Initial values are such that all ports are tri-stated. 9 of 34 3 D3 0 2 D2 1 1 D1 0 0 D0 1 DS26401DK Octal T1/E1/J1 Framer Design Kit Register Name: TSYSCLK_SR Register Description: DS26401 TSYSCLKx Pin Setting Register Offset: 0x0013, 0x0023, 0x0033, 0x0043, 0x0053, 0x0063, 0x0073, 0x0083 Bit # Name 7 — 6 — 5 — 4 — Bit 0 to 2: DS26401 Port x TSYSCLKC Source (D3, D2, D1, D0) The source for TSYSCLK is Defined as shown in Table 6. Table 6. TSYCLKx Source Definition D3, D2, D1, D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 TSYSCLK CONNECTION Tri-state TSYSCLK Drive TSYSCLK with RCHBLK 1 Drive TSYSCLK with RCHBLK 2 Drive TSYSCLK with RCHBLK 3 Drive TSYSCLK with RCHBLK 4 Drive TSYSCLK with RCHBLK 5 Drive TSYSCLK with RCHBLK 6 Drive TSYSCLK with RCHBLK 7 Drive TSYSCLK with RCHBLK 8 BPCLK Drive TSYSCLK with T1 OSC Drive TSYSCLK with E1 OSC Drive TSYSCLK with 16.385MHz Drive TSYSCLK with a logic 0 Drive TSYSCLK with a logic 1 Tri-state TSYSCLK Note: Initial values are such that all ports are tri-stated. 10 of 34 3 D3 2 D2 1 D1 0 D0 DS26401DK Octal T1/E1/J1 Framer Design Kit Register Name: RSYSCLK_SR Register Description: DS26401 RSYSCLKx Pin Setting Register Offset: 0x0014, 0x0024, 0x0034, 0x0044, 0x0054, 0x0064, 0x0074, 0x0084 Bit # Name 7 — 6 — 5 — 4 — Bit 0 to 2: DS26401 Port x RSYSCLKC Source (D3, D2, D1, D0) The source for RSYSCLK is Defined as shown in Table 7. Table 7. RSYSCLKx Source Definition D3, D2, D1, D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 RSYSCLK CONNECTION Tri-state RSYSCLK Drive RSYSCLK with TCHBLK 1 Drive RSYSCLK with TCHBLK 2 Drive RSYSCLK with TCHBLK 3 Drive RSYSCLK with TCHBLK 4 Drive RSYSCLK with TCHBLK 5 Drive RSYSCLK with TCHBLK 6 Drive RSYSCLK with TCHBLK 7 Drive RSYSCLK with TCHBLK 8 BPCLK Drive RSYSCLK with T1 OSC Drive RSYSCLK with E1 OSC Drive RSYSCLK with 16.385MHz Drive RSYSCLK with a logic 0 Drive RSYSCLK with a logic 1 Tri-state RSYSCLK Note: Initial values are such that all ports are tri-stated. 11 of 34 3 D3 2 D2 1 D1 0 D0 DS26401DK Octal T1/E1/J1 Framer Design Kit Register Name: TCLK_SR Register Description: DS26401 TCLKx Pin Setting Register Offset: 0x0015, 0x0025, 0x0035, 0x0045, 0x0055, 0x0065, 0x0075, 0x0085 Bit # Name 7 — 6 — 5 — 4 — 3 D3 2 D2 1 D1 0 D0 Bit 0 to 2: DS26401 Port x TCLK Source (D3, D2, D1, D0) The source for TCLK is Defined as shown in Table 8. Table 8. TCLKx Source Definition D3, D2, D1, D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1010 1011 1100 1101 1110 1111 TCLK CONNECTION Tri-state TCLK Drive TCLK with TCLK 1 Drive TCLK with TCLK 2 Drive TCLK with TCLK 3 Drive TCLK with TCLK 4 Drive TCLK with TCLK 5 Drive TCLK with TCLK 6 Drive TCLK with TCLK 7 Drive TCLK with TCLK 8 Drive TCLK with T1 OSC Drive TCLK with E1 OSC Drive TCLK with 16.385MHz Drive TCLK with a logic 0 Drive TCLK with a logic 1 Tri-state TCLK Note: Initial values are such that all ports are tri-stated. Also note that RCLK from the LIU (DS21448) does not go directly to the FPGA. However, it is routed to the DS26401 and a test header. To get RCLK to fan out to all the ports on the DS26401, simply tri-state a port on the FPGA and manually jumper the RCLK X pin to the TCLK X pin. Then you can route that signal with register values 0001 to 1000 in the TCLK_SR. 12 of 34 DS26401DK Octal T1/E1/J1 Framer Design Kit Register Name: RSYNC_SR Register Description: DS26401 RSYNCx Pin Setting Register Offset: 0x0016, 0x0026, 0x0036, 0x0046, 0x0056, 0x0066, 0x0076, 0x0086 Bit # Name 7 — 6 — 5 — 4 — Bit 0 to 2: DS26401 Port x RSYNC Source (D3, D2, D1, D0) The source for RSYNC is Defined as shown in Table 9. Table 9. RSYNCx Source Definition D3, D2, D1, D0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1010 1011 1100 1101 1110 1111 RSYNC CONNECTION Tri-state RSYNC Drive RSYNC with TSYNC 1 Drive RSYNC with TSYNC 2 Drive RSYNC with TSYNC 3 Drive RSYNC with TSYNC 4 Drive RSYNC with TSYNC 5 Drive RSYNC with TSYNC 6 Drive RSYNC with TSYNC 7 Drive RSYNC with TSYNC 8 Drive RSYNC with T1 OSC Drive RSYNC with E1 OSC Drive RSYNC with 16.385MHz Drive RSYNC with a logic 0 Drive RSYNC with a logic 1 Tri-state RSYNC Note: Initial values are such that all ports are tri-stated. 13 of 34 3 D3 2 D2 1 D1 0 D0 DS26401DK Octal T1/E1/J1 Framer Design Kit Register Name: TSYNC_SR Register Description: DS26401 TSYNCx Pin Setting Register Offset: 0x0017, 0x0027, 0x0037, 0x0047, 0x0057, 0x0067, 0x0077, 0x0087 Bit # Name 7 — 6 — 5 — 4 D4 Bit 0 to 2: DS26401 Port x TSYNC Source (D4, D3, D2, D1, D0) The source for TSYNC is Defined as shown in Table 10. Table 10. TSYNCx Source Definition D4, D3, D2, D1, D0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01010 01011 01100 01101 01110 10001 10010 10011 10100 10101 10110 10111 11000 11111 TSYNC CONNECTION Tri-state TSYNC Drive TSYNC with RSYNC 1 Drive TSYNC with RSYNC 2 Drive TSYNC with RSYNC 3 Drive TSYNC with RSYNC 4 Drive TSYNC with RSYNC 5 Drive TSYNC with RSYNC 6 Drive TSYNC with RSYNC 7 Drive TSYNC with RSYNC 8 Drive TSYNC with T1 OSC Drive TSYNC with E1 OSC Drive TSYNC with 16.385MHz Drive TSYNC with a logic 0 Drive TSYNC with a logic 1 Drive TSYNC with RMSYNC 1 Drive TSYNC with RMSYNC 2 Drive TSYNC with RMSYNC 3 Drive TSYNC with RMSYNC 4 Drive TSYNC with RMSYNC 5 Drive TSYNC with RMSYNC 6 Drive TSYNC with RMSYNC 7 Drive TSYNC with RMSYNC 8 Tri-state TSYNC Note: Initial values are such that all ports are tri-stated. 14 of 34 3 D3 2 D2 1 D1 0 D0 DS26401DK Octal T1/E1/J1 Framer Design Kit Register Name: CLK_SR Register Description: DS21448 MCLK A, DS21448 MCLK B, and REF CLK Register Offset: 0x0090 Bit # Name 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Table 11. MCLK A Source Definition D1, D0 00 01 10 11 MCLK A (DS21448 PORTS 1 TO 4) Tri-state MCLK Drive MCLK with 1.544MHz Drive MCLK with 2.048MHz Tri-state MCLK Note: Initial values are such that MCLK is 2.048MHz. Table 12. MCLK B Source Definition D3, D2 00 01 10 11 MCLK B (DS21448 PORTS 5 TO 8) Tri-state MCLK Drive MCLK with 1.544MHz Drive MCLK with 2.048MHz Tri-state MCLK Note: Initial values are such that that MCLK is 2.048MHz. Table 13. MCLK A Source Definition D5, D4 00 01 10 11 REF CLK Tri-state REF CLK Drive REF with 1.544MHz Drive REF with 2.048MHz Tri-state REF CLK Note: Initial values are such that REF is 2.048MHz. DS26401 AND DS21448 INFORMATION For more information about the DS26401 and DS21448, please consult the respective data sheets, available on our website at www.maxim-ic.com/DS26401 and www.maxim-ic.com/DS21448. TECHNICAL SUPPORT For technical support, please email your questions to [email protected]. SCHEMATICS The DS26401DK schematics are featured in the following pages. Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. 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