DS21354DK T1 Single-Chip Transceiver Design Kit Daughter Card www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21354 design kit is an easy-to-use evaluation board for the DS21354 E1 single-chip transceiver (SCT). The DS21354DK is intended to be used as a daughter card with either the DK2000 or the DK101 motherboards. The DS21354DK comes complete with a DS21354 SCT, transformers, termination resistors, configuration switches, line-protection circuitry, network connectors, and motherboard connectors. The DK101/DK2000 motherboard and Dallas’ ChipView software give point-and-click access to configuration and status registers from a Windowsâ-based PC. On-board LEDs indicate receive loss-of-signal and interrupt status, as well as multiple clock and signal routing configurations. § Demonstrates Key Functions of the DS21354 E1 SCT Transceiver § Includes DS21354 SCT, Transformers, Bantum, BNC and RJ48 Network Connectors, and Termination Passives § § § BNC Connections for 75W E1 § Compatible with DK101 and DK2000 Demo Kit Motherboards Each DS21354DK is shipped with a free DK101 motherboard. For complex applications, the DK2000 high-performance demo kit motherboard can be purchased separately. § DK101/DK2000 and ChipView Software Provide Point-and-Click Access to the DS21354 Register Set § Software-Controlled (Register Mapped) Configuration Switches to Facilitate Clock and Signal Routing § All Equipment-Side Framer Pins are Easily Accessible for External Data Source/Sink § LEDs for Loss-Of-Signal and Interrupt Status as well as Indications for Multiple Clock and Signal Routing Configurations § Easy-to-Read Silk Screen Labels Identify the Signals Associated with all Connectors, Jumper, and LEDs § Network Interface Protection for Overvoltage and Overcurrent Events Area Available for Further Customization Windows is a registered trademark of Microsoft Corp. DESIGN KIT CONTENTS DS21354DK Design Kit Daughter Card DK101 Low-Cost Motherboard CD ROM ChipView Software DS21354DK Data Sheet DK101 Data Sheet DS21354 Data Sheet DS21354 Errata Sheet Bantam and RJ48 Connectors for 120W E1 Multitap Transformer to Facilitate True Impedance Matching for 75W and 120W/100W Paths ORDERING INFORMATION PART DS21354DK 1 of 20 DESCRIPTION DS21354 Design Kit Daughter Card (with include DK101 motherboard) REV: 011904 DS21354DK T1 Single-Chip Transceiver Design Kit Daughter Card TABLE OF CONTENTS COMPONENT LIST.....................................................................................................................3 BASIC OPERATION....................................................................................................................4 HARDWARE CONFIGURATION .................................................................................................................. 4 QUICK SETUP (DEMO MODE) .................................................................................................................. 4 QUICK SETUP (REGISTER VIEW ) ............................................................................................................. 4 REGISTER MAP..........................................................................................................................5 CPLD REGISTER MAP ........................................................................................................................... 5 DS21354 INFORMATION............................................................................................................7 DS21354DK INFORMATION.......................................................................................................7 TECHNICAL SUPPORT ..............................................................................................................7 SCHEMATICS .............................................................................................................................7 LIST OF TABLES Table 1. Daughter Card Address Map .........................................................................................5 Table 2. CPLD Register Map .......................................................................................................5 2 of 20 DS21354DK T1 Single-Chip Transceiver Design Kit Daughter Card COMPONENT LIST DESIGNATION C1–C5, C8–C12, C15–C19, C21, C22, C29–C34 C7, C36 QTY DESCRIPTION 23 0.1mF 10%, 16V ceramic capacitors (0603) SUPPLIER Digi-Key PART 311-1088-1-ND 2 1mF 10%, 16V ceramic capacitors (1206) Digi-Key PCC1882CT-ND C13, C14 2 0.1mF 10%, 16V ceramic capacitors (0805) Digi-Key 311-1142-1-ND C23 1 0.1mF 10%, 25V ceramic capacitor (1206) Digi-Key PCC1883CT-ND C24–C27 4 0.22mF, 50V ceramic capacitors Digi-Key UNK C35 DS1, DS4–DS18 DS2, DS3 F1–F6 J1, J2 J3, J4 J5, J6 1 16 2 6 2 2 2 10mF 20%, 16V tantalum capacitor (B case) LED, green, SMD LED, red, SMD 250V, 1.25A fuse, SMT Male 0.1, SMD, 50-pin, dual-row vertical Bantam connectors Connector BNC RA 5-pin Digi-Key Digi-Key Digi-Key Teccor Electronics Samtec SWK Kruvand J7–J9 3 Socket, SMD, 50-pin, dual-row vertical Samtec JT10 L1 R1, R14, R21 R2, R3, R58, R59 R4, R5, R60 R6, R9, R10, R13, R15–R19, R22, R23, R25–R29, R32, R37, R38, R44, R47–R49, R61 R7, R8, R11, R12, R30, R31, R35, R36, R39–R43, R45, R50–R53 R24 R33, R34 1 1 3 4 3 Connector, 10-pin, dual-row vertical Choke, dual 4-line 24mH, 8-pin SO 51.1W 1%, 1/8W resistors (1206) 0W 5%, 1/8W resistors (1206) 51.1W 1%, 1/10W resistors (0805) Digi-Key Pulse Engineering Digi-Key Digi-Key Digi-Key PCS3106CT-ND P501CT-ND P500CT-ND F1250T TSM-125-01-T-DV RTT34B02 UCBJR220 TFM-125-02-S-DLC S2012-05-ND PE-65857 P51.1FCT-ND P0.0ETR-ND P51.1CCT-ND 24 10kW 1%, 1/10W resistors (0805) Digi-Key P10.0KCCT-ND 18 330W 0.1%, 1/10W MF resistors (0805) Digi-Key P330ZCT-ND 1 2 1.0kW 1%, 1/10W resistor (0805) Not populate Digi-Key — R46 1 4.7kW 1%, 1/8W resistor (0805) Digi-Key R54, R55 R56, R57 RJ1 SW1 T1 U1–U4, U6 2 2 1 1 1 5 61.9W 1%, 1/8W resistors (1206) 49.9W 1%, 1/8W resistors (1206) RJ48 connector Switch DPDT slide 6-pin TH XFMR 16-pin SMT BBUS switch 10-bit CMOS, 150-mil, 24-pin SO Digi-Key Digi-Key Molex Avnet Pulse Engineering IDT U5 1 144-pin macrocell CPLD Avnet U7–U10 U11 Z1, Z6–Z8 Z2, Z3 Z4, Z5 Z9, Z10 4 1 4 2 2 2 Quad bus switch, 150-mil, 16-pin SO T1/E1/J1 XCVR 100-pin QFP, 0°C to +70°C 160V, 500A Sidactor 58V, 500A Sidactor 6V, 50A Sidactor 25V, 500A Sidactor IDT Dallas Semiconductor Teccor Electronics Teccor Electronics Teccor Electronics Teccor Electronics P1.00KCCT-ND Not populated 9C08052A4701FK HFT P61.9FCT-ND P49.9FCT-ND 43223 SSA22 TX1099 IDTQS3R861Q XC95144XL10TQ100C IDTQS3125Q DS2156L P1800SCMC P0640SCMC P0080SAMC P0300SCMC 3 of 20 DS21354DK T1 Single-Chip Transceiver Design Kit Daughter Card BASIC OPERATION This design kit relies upon several supporting files, which can be downloaded from our website at www.maximic.com/DS21354DK. See the DS21354DK QuickView data sheet for these files. Hardware Configuration Using the DK101 processor board: · Connect the daughter card to the DK101 processor board. · Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector and the TIM 5V supply headers are unused.) · All processor board DIP switch settings should be in the ON position with exception for the flash programming switch, which should be OFF. · From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs®ChipView®ChipView. Using the DK2000 processor board: · Connect the daughter card to the DK2000 processor board. · Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply can be connected to connector J2. · From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs®ChipView®ChipView. General: · Upon power-up the RLOS LED is lit, as well as the MCLK-2.048MHz and TCLK-2.048MHz LEDs. · Due to the dual winding transformer, only the 120W line build-out configuration setting is needed to cover 75W E1 and 120W E1. Quick Setup (Demo Mode) · · · The PC loads the program, offering a choice among Demo Mode, Register View, and Terminal Mode. Select Demo Mode. The program requests a configuration file, then select DS21354_E1_DSNCOM_DRVR.cfg. The Demo Mode screen appears. Upon external loopback, the LOS and OOF indicators extinguish. Quick Setup (Register View) · · · · The PC loads the program, offering a choice among Demo Mode, Register View, and Terminal Mode. Select Register View. The program requests a definition file, then select DS21354.def. The Register View screen appears, showing the register names, acronyms, and values. Note: During the definition file load process, all registers are initialized according to the init value filed in the definition file (because the SETUP field in the .def file is turned on). Predefined register settings for several functions are available as initialization files. ¾ INI files are loaded by selecting the menu File®Reg Ini File®Load Ini File. ¾ Load the INI file DS21354e1_fas_crc4_cas.ini. ¾ After loading the INI file the following may be observed: The RLOS LED extinguishes upon external loopback. The device is now configured for E1 FAS with CRC4 and CAS. Miscellaneous: · Clock frequencies and certain pin bias levels are provided by a register-mapped CPLD, which is on the DS21354 daughter card. · The definition file for this CPLD is named DS215x_35x_CPLD_V2.def. See the CPLD Register Map section for definitions. · All files referenced above are available for download in the section marked “File Locations.” 4 of 20 DS21354DK T1 Single-Chip Transceiver Design Kit Daughter Card REGISTER MAP The DK101 daughter card address space begins at 0x81000000. The DK2000 daughter card address space begins at: 0x30000000 for slot 0 0x40000000 for slot 1 0x50000000 for slot 2 0x60000000 for slot 3 All offsets given in Table 1 are relative to the beginning of the daughter card address space. Table 1. Daughter Card Address Map OFFSET 0X0000 to 0X0015 DEVICE DESCRIPTION CPLD Board identification and clock/signal routing 0X1000 to 0X10ff Single-Chip Transceiver Board is populated with one of the following: DS2155, DS2156, DS21352, or DS21354. Please see the data sheet(s) for details. Registers in the CPLD can be easily modified using ChipView.exe, a host-based user-interface software, along with the definition file named DS215x_35x_CPLD_V2.def. Definition files for the SCT are named DS2155.def, DS21352.def, or DS21354.def, depending on the board population option. CPLD Register Map Table 2. CPLD Register Map OFFSET NAME TYPE DESCRIPTION 0X0000 0X0002 0X0003 0X0004 0X0005 0X0006 0X0007 0X0011 0X0012 0X0013 0X0014 0X0015 BID XBIDH XBIDM XBIDL BREV AREV PREV SWITCH1 SWITCH2 SWITCH3 SWITCH4 LEVELS Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Write Read-Write Read-Write Read-Write Read-Write Board ID High-Nibble Extended Board ID Middle-Nibble Extended Board ID Low-Nibble Extended Board ID Board FAB Revision Board Assembly Revision PLD Revision Pin to 1.544MHz Pin to 2.048MHz Pin-to-Pin Connect Pin-to-Pin Connect Set Level on Pin 1 = 3.3V ID Registers OFFSET NAME TYPE VALUE 0X0000 0X0002 0X0003 0X0004 BID XBIDH XBIDM XBIDL Read-Only Read-Only Read-Only Read-Only 0X0005 BREV Read-Only 0X0006 AREV Read-Only 0X0007 PREV Read-Only 0xD 0x0 0x0 0x5 Displays current FAB revision Displays current assembly revision Displays current PLD firmware revision DESCRIPTION Board ID High-Nibble Extended Board ID Middle-Nibble Extended Board ID Low-Nibble Extended Board ID Board FAB Revision Board Assembly Revision PLD Revision 5 of 20 DS21354DK T1 Single-Chip Transceiver Design Kit Daughter Card Control Registers The control registers are used primarily to control several banks of FET switches that route clocks and backplane signals. Please note that certain register settings cause line contention, e.g., setting SWITCH1.4 and SWITCH2.4 both to 0 would drive MCLK with both 1.544MHz and 2.048MHz. SWITCH1: PIN TO 1.544MHz (OFFSET = 0x0011) INITIAL VALUE = 0xF (MSB) — — — NAME POSITION MCLK SWITCH1.3 TCLK SWITCH1.2 RSYSCLK SWITCH1.1 TSYSCLK SWITCH1.0 — MCLK TCLK RSYSCLK (LSB) TSYSCLK FUNCTION 0 = Connect MCLK to the 1.544MHz clock 1 = Open Switch 1.4 0 = Connect TCLK to the 1.544MHz clock 1 = Open Switch 1.3 0 = Connect RSYSCLK to the 1.544MHz clock 1 = Open Switch 1.2 0 = Connect TSYSCLK to the 1.544MHz clock 1 = Open Switch 1.1 SWITCH2: PIN TO 2.048MHz (Offset = 0X0012) INITIAL VALUE = 0x3 (MSB) — — — NAME POSITION MCLK SWITCH2.3 TCLK SWITCH2.2 RSYSCLK SWITCH2.1 TSYSCLK SWITCH2.0 — MCLK TCLK RSYSCLK (LSB) TSYSCLK FUNCTION 0 = Connect MCLK to the 2.048MHz clock 1 = Open Switch 2.4 0 = Connect TCLK to the 2.048MHz clock 1 = Open Switch 2.3 0 = Connect RSYSCLK to the 2.048MHz clock 1 = Open Switch 2.2 0 = Connect TSYSCLK to the 2.048MHz clock 1 = Open Switch 2.1 SWITCH3: PIN-TO-PIN CONNECT (Offset = 0X0013) INITIAL VALUE = 0xF (MSB) — — — NAME POSITION TSS_RS SWITCH3.3 TCL_RC SWITCH3.2 RSY_RC SWITCH3.1 TSY_RC SWITCH3.0 — TSS_RS TCL_RC FUNCTION 0 = Connect TSSYNC to RSYNC 1 = Open Switch 3.4 0 = Connect TCLK to RCLK 1 = Open Switch 3.3 0 = Connect RSYSCLK to RCLK 1 = Open Switch 3.2 0 = Connect TSYSCLK to RCLK 1 = Open Switch 3.1 6 of 20 RSY_RC (LSB) TSY_RC DS21354DK T1 Single-Chip Transceiver Design Kit Daughter Card SWITCH4: PIN-TO-PIN CONNECT (Offset = 0X0014) INITIAL VALUE = 0x3 (MSB) — (LSB) — — — NAME POSITION URCLK_2048 SWITCH4.3 UTCLK_2048 SWITCH4.2 RSER_TSER SWITCH4.1 RSYNC_TSYNC SWITCH4.0 URCLK_2048 UTCLK_2048 RSER_TSER RSYNC_TSYNC FUNCTION 0 = Connect UR_CLK (TSSYNC) to 2.048MHz 1 = Open Switch 4.4 0 = Connect UT_CLK (TCHCLK) to 2.048MHz 1 = Open Switch 4.3 0 = Connect RER to TSER 1 = Open Switch 4.2 0 = Connect RSYNC to TSYNC 1 = Open Switch 4.1 LEVELS: SET LEVEL ON PIN (Offset = 0X0015) INITIAL VALUE = 0x6 (MSB) — — — — — BP_EN PPCTDM_EN (LSB) TUSEL NAME POSITION FUNCTION — LEVELS1.3 — BP_EN LEVELS1.2 0 = Enable IDT switches that connect the UTOPIA bus to daughter card header PPCTDM_EN LEVELS1.1 0 = Enable IDT switches that connect the TDM bus to the daughter card header TUSEL LEVELS1.0 0 = Set DS2156.TUSEL to enable TDM backplane 1 = Set DS2156.TUSEL to enable UTOPIA backplane Note (DS2156 only): When the UTOPIA backplane is enabled (LEVELS.TUSEL = 1) there is a possibility for contention between the UTOPIA bus master and TSYSCLK, TSER, and RSER. To avoid this, the following switches should be opened when the UTOPIA backplane is enabled: SWITCH1.0, SWITCH2.0, SWITCH3.0, and SWITCH4.1 DS21354 INFORMATION For more information about the DS21354, please consult the DS21354 data sheet available on our website at www.maxim-ic.com/DS21354. Software downloads are also available for this design kit. DS21354DK INFORMATION For more information about the DS21354DK, including software downloads, please consult the DS21354DK data sheet available on our website at www.maxim-ic.com/DS21354DK. TECHNICAL SUPPORT For additional technical support, please e-mail your questions to [email protected]. SCHEMATICS The DS21354DK schematics are featured in the following 13 pages. Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products · Printed USA 7 of 20