DS1556 1MEG NV Y2KC Timekeeping RAM www.dalsemi.com FEATURES Integrated NV SRAM, real time clock, crystal, power-fail control circuit and lithium energy source Clock registers are accessed identically to the static RAM; these registers are resident in the 16 top RAM locations Century byte register; i.e., Y2K complaint Totally nonvolatile with over 10 years of operation in the absence of power Precision power-on reset Programmable watchdog timer and RTC alarm BCD coded year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 Battery voltage level indicator flag Power-fail write protection allows for ±10% VCC power supply tolerance Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time PIN ASSIGNMENT RST A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 32 31 30 29 28 27 26 25 24 23 22 21 VCC A15 IRQ/FT WE A13 A8 A9 A11 OE A10 CE A0 1 2 3 4 5 6 7 8 9 10 11 12 DQ0 13 20 DQ6 DQ1 DQ2 14 19 DQ5 15 18 DQ4 GND 16 17 DQ3 DQ7 32-Pin Encapsulated Package IRQ/FT A15 A16 RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 X1 GND VBAT X2 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 NC NC A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 34-Pin PowerCap® Module Board (Uses DS9034PCX PowerCap) 1 of 20 022101 DS1556 ORDERING INFORMATION DS1556 DS1556P 5V; 32-pin DIP Module 5V; 34-pin PowerCap Module board * DS1556W DS1556WP 3.3V; 32-pin DIP Module 3.3V; 34-pin PowerCap Module board* *DS9034PCX (PowerCap) Required: must be ordered separately PIN DESCRIPTION A0-A16 DQ0-DQ7 IRQ \FT RST CE OE WE VCC GND NC X1, X2 VBAT - Address Input - Data Input/Outputs - Interrupt, Frequency Test Output (Open Drain) - Power-On Reset Output (Open Drain) - Chip Enable - Output Enable - Write Enable - Power Supply Input - Ground - No Connection - Crystal Connection - Battery Connection DESCRIPTION The DS1556 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) with a RTC alarm, watchdog timer, power-on reset, battery monitor, and 128k x 8 non-volatile static RAM. User access to all registers within the DS1556 is accomplished with a bytewide interface as shown in Figure 1. The RTC Registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically. The RTC Registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers are continuously updated; this occurs regardless of external registers settings to guarantee that accurate RTC information is always maintained. The DS1556 has interrupt ( IRQ /FT) and reset ( RST ) outputs which can be used to control CPU activity. The IRQ /FT interrupt output can be used to generate an external interrupt when the RTC Register values match user programmed alarm values. The interrupt is always available while the device is powered from the system supply and can be programmed to occur when in the battery backed state to serve as a system wake-up. Either the IRQ /FT or RST outputs can also be used as a CPU watchdog timer, CPU activity is monitored and an interrupt or reset output will be activated if the correct activity is not detected within programmed limits. The DS1556 power-on reset can be used to detect a system power down or failure and hold the CPU in a safe reset state until normal power returns and stabilizes; the RST output is used for this function. 2 of 20 DS1556 The DS1556 also contains its own power-fail circuitry, which automatically deselects the device when the VCC supply enters an out of tolerance condition. This feature provides a high degree of data security during unpredictable system operation brought on by low VCC levels. PACKAGES The DS1556 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1556P after the completion of the surface mount process. Mounting the PowerCap after the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX. DS1556 BLOCK DIAGRAM Figure 1 3 of 20 DS1556 DS1556 OPERATING MODES Table 1 VCC VCC > VPF VSO < VCC <VPF VCC <VSO < VPF CE OE WE VIH VIL VIL VIL X X X X VIL VIH X X X VIL VIH VIH X X DQ0-DQ7 HIGH-Z DIN DOUT HIGH-Z HIGH-Z HIGH-Z MODE DESELECT WRITE READ READ DESELECT DATA RETENTION POWER STANDBY ACTIVE ACTIVE ACTIVE CMOS STANDBY BATTERY CURRENT DATA READ MODE The DS1556 is in the read mode whenever CE (chip enable) is low and WE (write enable) is high. The device architecture allows ripple-through access to any valid address location. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that CE and OE access times are satisfied. If CE or OE access times are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. DATA WRITE MODE The DS1556 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum of tWR prior to the initiation of a subsequent read or write cycle. Data in must be valid tDS prior to the end of the write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. DATA RETENTION MODE The 5-volt device is fully accessible and data can be written and read only when VCC is greater than VPF. However, when VCC is below the power-fail point VPF (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3 volt device is fully accessible and data can be written and read only when VCC is greater than VPF. When VCC falls below VPF, access to the device is inhibited. If VPF is less than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops below VPF. If VPF is greater than VSO, the device power is switched from VCC to the internal backup lithium battery when VCC drops below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All control, data, and address signals must be powered down when VCC is powered down. 4 of 20 DS1556 BATTERY LONGEVITY The DS1556 has a lithium power source that is designed to provide energy for the clock activity, and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1556 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in the absence of VCC. Each DS1556 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1556 will be much longer than 10 years since no internal battery energy is consumed when VCC is present. INTERNAL BATTERY MONITOR The DS1556 constantly monitors the battery voltage of the internal battery. The Battery Low Flag (BLF) bit of the Flags Register (B4 of 1FFF0h) is not writable and should always be a 0 when read. If a 1 is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable. POWER-ON RESET A temperature compensated comparator circuit monitors the level of VCC. When VCC falls to the power fail trip point, the RST signal (open drain) is pulled low. When VCC returns to nominal levels, the RST signal continues to be pulled low for a period of 40 ms to 200 ms. The power-on reset function is independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled. CLOCK OPERATIONS Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions. 5 of 20 DS1556 DS1556 REGISTER MAP Table 2 ADDRESS 1FFFFh 1FFFEh 1FFFDh 1FFFCh 1FFFBh 1FFFAh 1FFF9h 1FFF8h B7 X X X X X OSC W DATA B4 B3 B6 B5 10 Year X X 10 M X 10 Date FT X X X 10 HOUR 10 MINUTES 10 SECONDS R 10 CENTURY 1FFF7h WDS BMB4 1FFF6h 1FFF5h 1FFF4h 1FFF3h 1FFF2h 1FFF1h 1FFF0h AE AM4 AM3 AM2 AM1 Y WF Y Y Y BMB3 BMB2 ABE Y 10 DATE 10 HOURS 10 MINUTES 10 SECONDS Y Y Y AF 0 BLF X BMB 1 Y Y 0 X = Unused, read/writable under Write and Read bit control FT = Frequency Test bit OSC = Oscillator start/stop bit W = Write bit R = Read bit WDS = Watchdog Steering bit BMB0-BMB4 = Watchdog Multiplier bits RB0-RB1 = Watchdog Resolution bits B2 B1 YEAR MONTH DATE DAY HOUR MINUTES SECONDS CENTURY RB BMB0 1 Y Y DATE HOURS MINUTES SECONDS Y Y 0 0 B0 FUNCTION/RANGE YEAR MONTH DATE DAY HOUR MINUTES SECONDS CONTROL RB0 WATCHDOG Y INTERRUPTS ALARM DATE ALARM HOURS ALARM MINUTES ALARM SECONDS UNUSED FLAGS Y 0 00-99 01-12 01-31 01-07 00-23 00-59 00-59 00-39 01-31 00-23 00-59 00-59 AE = Alarm Flag Enable Y = Unused, read/writable without Write and Read bit control ABE = Alarm in battery Back-up mode enable AM1-AM4 = Alarm Mask bits WF = Watchdog Flag AF = Alarm Flag 0 = 0 and are read only BLF = Battery Low Flag CLOCK OSCILLATOR CONTROL The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB of the Seconds Register (B7 of 1FFF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the oscillator. The DS1556 is shipped from Dallas Semiconductor with the clock oscillator turned off, OSC bit set to a 1. READING THE CLOCK When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC Registers. This puts the external registers into a static state allowing data to be read without register values changing during the read process. Normal updates to the internal registers continue while in this state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (1FFF8h). As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is set to a 0 for a minimum of 500 µs. The read bit must be a zero for a minimum of 500 µs to ensure the external registers will be updated. 6 of 20 DS1556 SETTING THE CLOCK The MSB bit, B7, of the Control Register is the write bit. Setting the write bit to a 1, like the read bit, halts updates to the DS1556 (1FFF8h-1FFFFh) registers. After setting the write bit to a 1, RTC Registers can be loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to a 0 then transfers the values written to the internal RTC Registers and allows normal operation to resume. CLOCK ACCURACY (DIP MODULE) The DS1556 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. Clock accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information please see application note 58. CLOCK ACCURACY (POWERCAP MODULE) The DS1556 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the lowest level EMI section of the PCB layout. For additional information please see application note 58. FREQUENCY TEST MODE The DS1556 frequency test mode uses the open drain IRQ /FT output. With the oscillator running, the IRQ /FT output will toggle at 512 Hz when the FT bit is a 1, the Alarm Flag Enable bit (AE) is a 0, and the Watchdog Steering bit (WDS) is a 1 or the Watchdog Register is reset (Register 1FFF7h = 00h). The IRQ /FT output and the frequency test mode can be used as a measure of the actual frequency of the 32.768 kHz RTC oscillator. The IRQ /FT pin is an open drain output which requires a pull-up resistor for proper operation. The FT bit is cleared to a 0 on power-up. USING THE CLOCK ALARM The alarm settings and control for the DS1556 reside within Registers 1FFF2h-1FFF5h. Register 1FFF6h contains two alarm enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and ABE bits must be set as described below for the IRQ /FT output to be activated for a matched alarm condition. The alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS1556 is in the battery-backed state of operation to serve as a system wake-up. Alarm mask bits AM1-AM4 control the alarm mode. Table 3 shows the possible settings. Configurations not listed in the table default to the once per second mode to notify the user of an incorrect alarm setting. 7 of 20 DS1556 ALARM MASK BITS Table 3 AM4 1 1 1 1 0 AM3 1 1 1 0 0 AM2 1 1 0 0 0 AM1 1 0 0 0 0 ALARM RATE Once per second When seconds match When minutes and seconds match When hours, minutes, and seconds match When date, hours, minutes, and seconds match When the RTC Register values match Alarm Register settings, the Alarm Flag bit (AF) is set to a 1. If Alarm Flag Enable (AE) is also set to a 1, the alarm condition activates the IRQ /FT pin. The IRQ /FT signal is cleared by a read or write to the Flags Register (Address 1FFF0h) as shown in Figure 2 and 3. When CE is active, the IRQ /FT signal may be cleared by having the address stable for as short as 15 ns and either OE or WE active, but is not guaranteed to be cleared unless tRC is fulfilled. The alarm flag is also cleared by a read or write to the Flags Register but the flag will not change states until the end of the read/write cycle and the IRQ /FT signal has been cleared. CLEARING IRQ WAVEFORMS Figure 2 CE, 0V CLEARING IRQ WAVEFORMS Figure 3 CE=0 8 of 20 DS1556 The IRQ /FT pin can also be activated in the battery backed mode. The IRQ /FT will go low if an alarm occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition, however an alarm generated during power-up will set AF. Therefore the AF bit can be read after system power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm timing during the battery back-up mode and power-up states. BACK-UP MODE ALARM WAVEFORMS Figure 4 USING THE WATCHDOG TIMER The watchdog timer can be used to detect an out-of-control processor. The user programs the watchdog timer by setting the desired amount of time-out into the 8-bit Watchdog Register (Address 1FFF7h). The five Watchdog Register bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The watchdog time-out value is then determined by the multiplication of the 5-bit multiplier value with the 2-bit resolution value. (For example: writing 00001110 in the Watchdog Register = 3 X 1 second or 3 seconds.) If the processor does not reset the timer within the specified period, the Watchdog Flag (WF) is set and a processor interrupt is generated and stays active until either the Watchdog Flag (WF) is read or the Watchdog Register (1FFF7h) is read or written. The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS). When set to a 0, the watchdog will activate the IRQ /FT output when the watchdog times out. When WDS is set to a 1, the watchdog will output a negative pulse on the RST output for a duration of 40 ms to 200 ms. The Watchdog Register (1FFF7h) and the FT bit will reset to a 0 at the end of a watchdog time-out when the WDS bit is set to a 1. The watchdog timer resets when the processor performs a read or write of the Watchdog Register. The time-out period then starts over. The watchdog timer is disabled by writing a value of 00h to the Watchdog Register. The watchdog function is automatically disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ /FT output and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. POWER-ON DEFAULT STATES Upon application of power to the device, the following register bits are set to a 0: WDS=0, BMB0-BMB4=0, RB0-RB1=0, AE=0, ABE=0. 9 of 20 DS1556 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Storage Temperature Soldering Temperature -.3V to +6.0V -40°C to +85°C See J-STD-020A Specification (DIP Package) (See Note 8) See IPC/JEDEC Standard J-STD-020A for Surface Mount Devices * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATING RANGE Range Commercial Temperature 0°C to +70°C VCC 3.3V ± 10% or 5V ± 10% RECOMMENDED DC OPERATING CONDITIONS PARAMETER Logic 1 Voltage All Inputs VCC = 5V ±10% VCC = 3.3V ±10% Logic 0 Voltage All Inputs VCC = 5V ±10% VCC = 3.3V ±10% SYMBOL MIN VIH VIH VIL VIL (Over the Operating Range) TYP MAX UNITS NOTES 2.2 2.0 VCC +0.3V VCC +0.3V V V 1 1 -0.3 -0.3 0.8 0.6 1 1 DC ELECTRICAL CHARACTERISTICS (Over the Operating Range; VCC = 5.0V ±10%) PARAMETER Active Supply Current TTL Standby Current ( CE =VIH ) CMOS Standby Current ( CE ≥=VCC - 0.2V) Input Leakage Current (any input) Output Leakage Current (any output) Output Logic 1 Voltage (IOUT = -1.0 mA) Output Logic 0 Voltage (IOUT = 2.1 mA, DQ0-7 Outputs) (IOUT = 7.0 mA, IRQ /FT and RST outputs) Write Protection Voltage Battery Switch Over Voltage SYMBOL ICC ICC1 ICC2 MIN IIL IOL -1 -1 VOH 2.4 TYP 30 4 2 VOL1 VOL2 VPF VSO 4.25 VBAT 10 of 20 MAX 85 6 4 UNITS mA mA mA +1 +1 µA µA NOTES 2, 3 2, 3 2, 3 V 1 0.4 0.4 V V 1 1, 5 4.50 V V 1 1, 4 DS1556 DC ELECTRICAL CHARACTERISTICS (Over the Operating Range; VCC = 3.3V ±10%) PARAMETER Active Supply Current TTL Standby Current ( CE = VIH ) CMOS Standby Current ( CE ≥=VCC - 0.2V) Input Leakage Current (any input) Output Leakage Current (any output) Output Logic 1 Voltage (IOUT = -1.0 mA) Output Logic 0 Voltage (IOUT =2.1 mA, DQ0-7 Outputs) (IOUT =7.0 mA, IRQ /FT and RST Outputs) Write Protection Voltage Battery Switch Over Voltage SYMBOL ICC ICC1 ICC2 MIN IIL IOL -1 -1 VOH 2.4 TYP 20 2 1 VOL1 VOL2 VPF VSO 2.80 VBAT or VPF READ CYCLE TIMING DIAGRAM Figure 5 11 of 20 MAX 30 3 2 UNITS mA mA mA +1 +1 µA µA NOTES 2, 3 2, 3 2, 3 V 1 0.4 0.4 V V 1 1, 5 2.97 V V 1 1, 4 DS1556 READ CYCLE, AC CHARACTERISTICS PARAMETER Read Cycle Time Address Access Time to DQ Low-Z CE Access Time CE Data Off time OE to DQ Low-Z OE Access Time OE Data Off Time Output Hold from Address CE SYMBOL tRC tAA tCEL tCEA tCEZ tOEL tOEA tOEZ tOH VCC=5.0V ±% MIN MAX 70 70 5 70 25 5 35 25 5 WRITE CYCLE, AC CHARACTERISTICS PARAMETER Write Cycle Time Address Access Time Pulse Width CE Pulse Width Data Setup Time Data Hold time Data Hold time Address Hold Time Address Hold Time WE Data Off Time Write Recovery Time WE SYMBOL tWC tAS tWEW tCEW tDS tDH1 tDH2 tAH1 tAH2 tWEZ tWR VCC=5.0V ±% MIN MAX 70 0 50 60 30 0 0 5 5 25 5 12 of 20 (Over the Operating Range) VCC=3.3V ±% MIN MAX 120 120 5 120 40 5 100 35 5 UNITS NOTES ns ns ns ns ns ns ns ns ns (Over the Operating Range) VCC=3.3V ±% MIN MAX 120 0 100 110 80 0 0 0 5 40 10 UNITS NOTES ns ns ns ns ns ns 9 ns 10 ns 9 ns 10 ns ns DS1556 WRITE CYCLE TIMING, WRITE ENABLE CONTROLLED Figure 6 WRITE CYCLE TIMING, CHIP ENABLE CONTROLLED Figure 7 13 of 20 DS1556 POWER-UP/DOWN CHARACTERISTICS (Over the Operating Range; VCC = 5.0V ±10%) PARAMETER CE or WE at VIH , Before Power-Down VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Fall Time: VPF(MIN) to VSO VCC Rise Time: VPF(MIN) to VPF(MAX) VPF to RST High Expected Data Retention Time (Oscillator On) SYMBOL MIN TYP MAX tPD 0 µs tF 300 µs tFB 10 µs tR 0 µs tREC 40 tDR 10 200 UNITS ms years POWER-UP/DOWN WAVEFORM TIMING 5-VOLT DEVICE Figure 8 14 of 20 NOTES 6, 7 DS1556 POWER-UP/DOWN CHARACTERISTICS (Over the Operating Range; VCC = 3.3V ±10%) PARAMETER CE or WE at VIH , Before Power-Down VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Rise Time: VPF(MIN) to VPF(MAX) VPF to RST High Expected Data Retention Time (Oscillator On) SYMBOL MIN TYP MAX tPD 0 µs tF 300 µs tR 0 µs tREC 40 tDR 10 200 UNITS NOTES ms years 6, 7 POWER-UP/DOWN WAVEFORM TIMING 3.3-VOLT DEVICE Figure 9 CAPACITANCE PARAMETER Capacitance on all input pins Capacitance on IRQ /FT, RST , and DQ pins (TA = 25°C) SYMBOL CIN CIO MIN 15 of 20 TYP MAX 7 10 UNITS pF pF NOTES 1 1 DS1556 AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5 ns NOTES: 1. Voltage referenced to ground. 2. Typical values are at 25°C and nominal supplies. 3. Outputs are open. 4. Battery switch over occurs at the lower of either the battery voltage or VPF. 5. The IRQ /FT and RST outputs are open drain. 6. Data retention time is at 25°C. 7. Each DS1556 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined for DIP modules and PowerCap modules as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 8. Real Time Clock Modules (DIP) can be successfully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. In addition, for the PowerCap: a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented with the label side up (“live-bug”). b. Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder. 9. tAH1, tDH1 are measured from WE going high. 10. tAH1, tDH1 are measured from CE going high. 16 of 20 DS1556 DS1556 32-PIN PACKAGE PKG DIM A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 17 of 20 32-PIN MIN MAX 1.670 1.690 38.42 38.93 0.715 0.740 18.16 18.80 0.335 0.365 8.51 9.27 0.075 0.105 1.91 0.67 0.015 0.030 0.38 0.76 0.140 0.180 3.56 4.57 0.090 0.110 2.29 2.79 0.590 0.630 14.99 16.00 0.010 0.018 0.25 0.45 0.015 0.025 0.38 0.64 DS1556 DS1556P PKG DIM A B C D E F G MIN 0.920 0.980 0.052 0.048 0.015 0.025 INCHES NOM 0.925 0.985 0.055 0.050 0.020 0.027 MAX 0.930 0.990 0.080 0.058 0.052 0.025 0.030 NOTE: Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented with the label side up (“live-bug”). Hand Soldering and touch-up: Do not touch or apply the soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. 18 of 20 DS1556 DS1556P WITH DS9034PCX ATTACHED PKG DIM A B C D E F G 19 of 20 MIN 0.920 0.955 0.240 0.052 0.048 0.015 0.020 INCHES NOM 0.925 0.960 0.245 0.055 0.050 0.020 0.025 MAX 0.930 0.965 0.250 0.058 0.052 0.025 0.030 DS1556 RECOMMENDED POWERCAP MODULE LAND PATTERN PKG DIM A B C D E 20 of 20 INCHES MIN NOM MAX 1.050 0.826 0.050 0.030 0.112 -