DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs www.maxim-ic.com FEATURES PIN CONFIGURATIONS Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM. These Registers Reside in the Eight Top RAM Locations. Century Byte Register Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD-Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid through 2099 Low-Battery-Voltage Level Indicator Flag Power-Fail Write Protection Allows for ±10% VCC Power-Supply Tolerance Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time DIP Module Only Standard JEDEC Bytewide 8k x 8 Static RAM Pinout PowerCap Module Board Only Surface-Mountable Package for Direct Connection to PowerCap Containing Battery and Crystal Replaceable Battery (PowerCap) Power-On Reset Output Pin-for-Pin Compatible with Other Densities of DS174XP Timekeeping RAM Underwriters Laboratories (UL) Recognized to Prevent Charging of the Internal Lithium Battery TOP VIEW 28 1 2 DS1743 27 26 3 25 4 24 5 23 6 22 7 21 8 20 9 19 10 18 11 17 12 16 13 14 15 N.C. A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND VCC WE CE2 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 28-Pin Encapsulated Package (28 PIN 740) N.C. N.C. N.C. RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DS1743P X1 GND VBAT X2 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 N.C. N.C. N.C. N.C. A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 34-Pin PowerCap Module Board (Uses DS9034PCX PowerCap) Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 16 REV: 090407 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs PIN DESCRIPTION PIN PDIP PowerCap 1, 2, 3, 1 31–34 2 30 3 25 4 24 5 23 6 22 7 21 8 20 9 19 10 18 11 16 12 15 13 14 14 17 15 13 16 12 17 11 18 10 19 9 NAME FUNCTION N.C. No Connection A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND DQ3 DQ4 DQ5 DQ6 DQ7 PIN PDIP PowerCap Address Input Data Input/ Output NAME 20 8 CE 21 28 A10 22 7 OE 23 24 25 26 29 27 26 — A11 A9 A8 CE2 27 6 WE 28 5 VCC — 4 RST Ground Data Input/ Output 2 of 16 — X1, X2 — VBAT FUNCTION Chip Enable, Active Low Address Input Output Enable, Active Low Address Input Chip Enable 2 Write Enable, Active Low Power-Supply Input Power-On Reset Output, Active Low Crystal Connection Battery Connection DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS1743-85 DS1743-100 DS1743-100 IND DS1743P-85 DS1743P-100 DS1743P-100IND DS1743W-120 DS1743W-120 IND DS1743W-150 DS1743W-150 IND DS1743WP-120 DS1743WP-120 IND DS1743-85+ DS1743-100+ DS1743-100 IND+ DS1743P-85+ DS1743P-100+ DS1743P-100IND+ DS1743W-120+ DS1743W-120 IND+ DS1743W-150+ DS1743W-150 IND+ DS1743WP-120+ DS1743WP-120 IND+ DS9034PCX DS9034I-PCX DS9034PCX+ DS9034I-PCX+ 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 28 EDIP Module 28 EDIP Module 28 EDIP Module 34 PowerCap* 34 PowerCap* 34 PowerCap* 28 EDIP Module 28 EDIP Module 28 EDIP Module 28 EDIP Module 34 PowerCap* 34 PowerCap* 28 EDIP Module 28 EDIP Module 28 EDIP Module 34 PowerCap* 34 PowerCap* 34 PowerCap* 28 EDIP Module 28 EDIP Module 28 EDIP Module 28 EDIP Module 34 PowerCap* 34 PowerCap* PowerCap PowerCap IND PowerCap PowerCap IND VOLTAGE (V) 5 5 5 5 5 5 3.3 3.3 3.3 3.3 3.3 3.3 5 5 5 5 5 5 3.3 3.3 3.3 3.3 3.3 3.3 — — — — TOP MARK** DS1743-85 DS1743-100 DS1743-100-IND DS1743P-85 DS1743P-100 DS1743P-100 IND DS1743W-120 DS1743W-120 IND DS1743W-150 DS1743W-150 IND DS1743WP-120 DS1743WP-120 IND DS1743-85 DS1743-100 DS1743-100-IND DS1743P-85 DS1743P-100 DS1743P-100 IND DS1743W-120 DS1743W-120 IND DS1743W-150 DS1743W-150 IND DS1743WP-120 DS1743WP-120 IND DS9034PC DS9034PCI DS9034PC DS9034PCI +Denotes a lead-free package. *DS9034PCX required (must be ordered separately). **A ‘+’ indicates lead-free. The top mark will include a ‘+’ symbol on lead-free devices. DESCRIPTION The DS1743 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8 nonvolatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide interface as shown in Figure 1. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1743 also contains its own powerfail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. When VCC is above VPF, the device is fully accessible. When VCC is below VPF, the internal CE signal is forced high, preventing any access. When VCC rises above VPF, access remains inhibited for TREC, allowing time for the system to stabilize. These features prevent loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided. 3 of 16 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs PACKAGES The DS1743 is available in two packages: the 28-pin DIP and the 34-pin PowerCap module. The 28-pin DIP-style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the DS1743P after the completion of the surface-mount process. Mounting the PowerCap after the surfacemount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX. TIME AND DATE OPERATION The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The contents of the time and date registers are in the BCD format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday and so on). Illogical time and date entries result in undefined operation. CLOCK OPERATIONS-READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1743 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, bit 6 of the century register (see Table 2). As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the count that is day, date, and time that was current at the moment the halt command was issued. However, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All the DS1743 registers are updated simultaneously after the internal clock register updating process has been re-enabled. Updating is within a second after the read bit is written to 0. The READ bit must be a zero for a minimum of 500μs to ensure the external registers are updated. 4 of 16 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs Figure 1. Block Diagram Dallas Semiconductor DS1743 Table 1. Truth Table CE VCC VIH X VCC > VPF VIL VIL VIL VSO < VCC < VPF X VCC<VSO<VPF CE2 X VIL VIH VIH VIH X OE X X X VIL VIH X WE X X VIL VIH VIH X MODE Deselect Deselect Write Read Read Deselect DQ High-Z High-Z Data In Data Out High-Z High-Z X X X Deselect High-Z X POWER Standby Standby Active Active Active CMOS Standby Data-Retention Mode SETTING THE CLOCK As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock counters and allows normal operation to resume. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see Table 2. Setting it to a 1 stops the oscillator. FREQUENCY TEST BIT As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512Hz. When the seconds register is being read, the DQ0 line will toggle at the 512Hz frequency as long as conditions for access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and stable). 5 of 16 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs CLOCK ACCURACY (DIP MODULE) The DS1743 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The RTC is calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require additional calibration. For this reason, methods of field clock calibration are not available and not necessary. The electrical environment also affects clock accuracy, so caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional information, please refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. CLOCK ACCURACY (PowerCap MODULE) The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the module will typically keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C. The electrical environment also affects clock accuracy, so caution should be taken to place the RTC in the lowest-level EMI section of the PC board layout. For additional information, please refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. Table 2. Register Map ADDRESS B7 1FFF 1FFE X 1FFD 1FFC 1FFB 1FFA 1FF9 1FF8 X BF X X OSC W B6 B5 10 Year DATA B4 B3 10 X X Month X 10 Date FT X X X 10 Hour 10 Minutes 10 Seconds R 10 Century B2 B1 Year Month X Date Day Hour Minutes Seconds Century B0 FUNCTION RANGE Year 00–99 Month 01–12 Date Day Hour Minutes Seconds Control 01–31 01–07 00–23 00–59 00–59 00–39 R = READ BIT FT = FREQUENCY TEST OSC = STOP BIT W = WRITE BIT X = SEE NOTE BELOW BF = BATTERY FLAG Note: All indicated “X” bits must be set to “0” when written to ensure proper clock operation. RETRIEVING DATA FROM RAM OR CLOCK The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that the, CE and OE access times and states are satisfied. If CE, or OE access times and states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable access time (tCEA). The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address inputs are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH) but will then go indeterminate until the next address access. 6 of 16 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs WRITING DATA TO RAM OR CLOCK The DS1743 is in the write mode whenever WE, and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE, on CE. The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward. In a typical application, the OE signal will be high during a write cycle. However, OE can be active provided that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the data bus can become active with read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. DATA-RETENTION MODE The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF. However, when VCC is below the power-fail point, VPF, (point at which write protection occurs) the internal clock registers and SRAM are blocked from any access. At this time (PowerCap only) the powerfail reset-output signal (RST) is driven active and remains active until VCC returns to nominal levels. When VCC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC in to the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF. When VCC falls below the power-fail point, VPF, access to the device is inhibited. At this time the powerfail reset-output signal (RST) is driven active and remains active until VCC returns to nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than VSO, the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VSO. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. The RST (PowerCap only) signal is an open-drain output and requires a pullup resistor. Except for RST, all control, data, and address signals must be powered down when VCC is powered down. BATTERY LONGEVITY The DS1743 has a lithium power source that is designed to provide energy for clock activity and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1743 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running in the absence of VCC power. Each DS1743 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1743 will be longer than 10 years since no lithium battery energy is consumed when VCC is present. BATTERY MONITOR The DS1743 constantly monitors the battery voltage of the internal battery. The battery flag bit (bit 7) of the day register is used to indicate the voltage level range of the battery. This bit is not writeable and should always be a 1 when read. If a 0 is ever present, an exhausted lithium energy source is indicated and both the contents of the RTC and RAM are questionable. 7 of 16 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………………-0.3V to +6.0V Operating Temperature Range…………………………………………………………………….-40°C to +85°C Storage Temperature Range……………………………………………………………………….-40°C to +85°C Soldering Temperature (EDIP) (leads, 10 seconds)…………………….……………………………..…+260°C Soldering Temperature…………………………………………..….See J-STD-020 Specification (See Note 8) This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. OPERATING RANGE RANGE Commercial Industrial TEMP RANGE 0°C to +70°C -40°C to +85°C VCC 3.3V ±10% or 5V ±10% 3.3V ±10% or 5V ±10% RECOMMENDED DC OPERATING CONDITIONS (TA = Over the Operating Range.) PARAMETER Logic 1 Voltage All Inputs Logic 0 Voltage All Inputs SYMBOL VIH VIL CONDITIONS MIN VCC = 5V ±10% 2.2 VCC = 3.3V ±10% 2.0 VCC = 5V ±10% VCC = 3.3V ±10% TYP MAX VCC +0.3V VCC +0.3V UNITS NOTES V 1 V 1 -0.3 +0.8 V 1 -0.3 +0.6 V 1 TYP MAX UNITS NOTES ICC 15 50 mA 2, 3 ICC1 1 3 mA 2, 3 ICC2 1 3 mA 2, 3 DC ELECTRICAL CHARACTERISTICS (5V) ( VCC = 5.0V ±10%, TA = Over the Operating Range.) PARAMETER SYMBOL Active Supply Current TTL Standby Current (CE = VIH, CE2 = VIL) CMOS Standby Current (CE ≥ VCC - 0.2V; CE2 = GND + 0.2V) Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage (IOUT = 2.1mA) Write-Protection Voltage Battery Switchover Voltage MIN IIL -1 +1 μA IOL -1 +1 μA VOH 2.4 1 0.4 VOL1 VPF VSO 8 of 16 4.20 4.50 VBAT 1 V 1 1, 4 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs DC ELECTRICAL CHARACTERISTICS (3.3V) (VCC = 3.3V ±10%, TA = Over the Operating Range.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current ICC 10 30 mA 2, 3 TTL Standby Current (CE = VIH) CMOS Standby Current (CE ≥ VCC - 0.2V; CE2 = GND + 0.2V) Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage (IOUT =2.1mA) Write-Protection Voltage ICC1 0.7 2 mA 2, 3 ICC2 0.7 2 mA 2, 3 IIL -1 +1 μA IOL -1 +1 μA VOH 2.4 1 0.4 VOL1 VPF Battery Switchover Voltage 2.75 1 2.97 VBAT or VPF VSO V 1 V 1, 4 AC CHARACTERISTICS—READ CYCLE (5V) (VCC = 5.0V ±10%, TA = Over the Operating Range.) ACCESS PARAMETER SYMBOL 70ns MIN 85ns MAX MAX Address Access Time tAA CE to CE2 to DQ Low-Z tCEL CE Access Time tCEA 70 85 CE2 Access Time CE and CE2 Data-Off Time OE to DQ Low-Z tCE2A 80 tCEZ 25 OE Access Time tOEA 35 45 55 ns OE Data-Off Time Output Hold from Address tOEZ 25 30 35 ns 70 5 100 85 5 5 5 9 of 16 ns 100 5 ns ns 5 100 ns 5 95 105 ns 5 30 35 ns 5 5 NOTES MAX tRC tOH 85 MIN UNITS Read Cycle Time tOEL 70 MIN 100ns 5 5 ns ns DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs AC CHARACTERISTICS—READ CYCLE (3.3V) (VCC = 3.3V ±10%, TA = Over the Operating Range.) ACCESS PARAMETER 120ns SYMBOL MIN 150ns MAX 120 MIN UNITS MAX Read Cycle Time tRC 150 Address Access Time tAA CE and CE2 Low to DQ Low-Z tCEL CE and CE2 Access Time tCEA 120 CE and CE2 Data-Off time tCEZ 40 OE Low to DQ Low-Z tOEL OE Access Time tOEA 100 130 ns OE Data-Off Time tOEZ 35 35 ns Output Hold from Address tOH 120 5 5 READ CYCLE TIMING DIAGRAM 10 of 16 ns 150 5 5 ns ns 5 150 ns 5 50 ns 5 5 5 NOTES ns ns DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs AC CHARACTERISTICS—WRITE CYCLE (5V) (VCC = 5.0V ±10%, TA = Over the Operating Range.) ACCESS PARAMETER SYMBOL 70ns MIN 85ns MAX MIN UNITS 100ns MAX MIN NOTES MAX Write Cycle Time tWC 70 85 100 ns Address Setup Time tAS 0 0 0 ns WE Pulse Width tWEW 50 65 70 ns CE Pulse Width tCEW 60 70 75 ns 5 CE2 Pulse Width tCE2W 65 75 85 ns 5 Data Setup Time tDS 30 35 40 ns 5 Data Hold Time CE tDH 0 0 0 ns 5 Data Hold Time CE2 tDH 8 8 8 ns 5 Address Hold Time tAH 5 5 5 ns 5 WE Data-Off Time tWEZ Write Recovery Time tWR 25 30 10 35 10 5 ns 10 ns AC CHARACTERISTICS—WRITE CYCLE (3.3V) (VCC = 3.3V ±10%, TA = Over the Operating Range.) PARAMETER SYMBOL ACCESS 120ns 150ns MIN MAX MIN MAX UNITS NOTES Write Cycle Time tWC 120 150 ns Address Setup Time tAS 0 0 ns WE Pulse Width tWEW 100 130 ns CE and CE2 Pulse Width tCEW 110 140 ns 5 Data Setup Time tDS 80 90 ns 5 Data Hold Time CE tDH 0 0 ns 5 Data Hold Time CE2 tDH 10 10 ns 5 Address Hold Time tAH 0 0 ns 5 WE Data-Off Time tWEZ Write Recovery Time tWR 40 10 11 of 16 50 10 ns ns 5 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs WRITE CYCLE TIMING—WRITE-ENABLE CONTROLLED (See Note 5) WRITE CYCLE TIMING— CE /CE2-CONTROLLED (See Note 5) 12 of 16 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs POWER-UP/DOWN CHARACTERISTICS—5V (VCC = 5.0V ±10%, TA = Over the Operating Range.) PARAMETER SYMBOL MIN CE or WE at VIH, CE2 at VIL, Before Power-Down tPD 0 μs VCC Fall Time: VPF(MAX) to VPF(MIN) tF 300 μs VCC Fall Time: VPF(MIN) to VSO tFB 10 μs VCC Rise Time: VPF(MIN) to VPF(MAX) Power-Up Recover Time Expected Data-Retention Time (Oscillator On) tR 0 μs ms tREC tDR TYP MAX 35 10 POWER-UP/DOWN TIMING (5V DEVICE) 13 of 16 UNITS years NOTES 6, 7 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs POWER-UP/DOWN CHARACTERISTICS—3.3V (VCC = 3.3V ±10%, TA = Over the Operating Range.) PARAMETER CE or WE at VIH, Before Power-Down VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Rise Time: VPF(MIN) to VPF(MAX) VPF to RST High Expected Data-Retention Time (Oscillator On) SYMBOL MIN TYP MAX tPD 0 μs tF tR 300 0 μs μs ms tREC tDR 35 10 UNITS NOTES years 6, 7 MAX UNITS NOTES POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE) CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP Capacitance on All Input Pins CIN 7 pF Capacitance on All Output Pins CO 10 pF 14 of 16 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs AC TEST CONDITIONS Output Load: 50 pF + 1TTL Gate Input Pulse Levels: 0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltages are referenced to ground. 2) Typical values are at +25°C and nominal supplies. 3) Outputs are open. 4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF. 5) The CE2 control signal functions the same as the CE signal except that the logic levels for active and inactive levels are opposite. If CE2 is used to terminate a write, the CE2 data hold time (tDH) applies. 6) Data-retention time is at +25°C. 7) Each DS1743 has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined for DIP modules as a cumulative time in the absence of VCC starting from the time power is first applied by the user. 8) RTC Encapsulated DIP Modules (EDIP) can be successfully processed through conventional wavesoldering techniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used. See the PowerCap package drawing for details regarding the PowerCap package. 15 of 16 DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs PACKAGE INFORMATION For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. PACKAGE TYPE DOCUMENT NO. 28 EDIP (740) 56-G0002-001 34 PowerCap Module 56-G0003-001 16 of 16 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.