19-0394; Rev 0; 12/97 3-in-1 Silicon Delay Line ________________________Applications Clock Synchronization Digital Systems _________________Pin Configurations TOP VIEW IN1 1 8 VCC IN2 2 7 OUT1 3 6 OUT2 GND 4 5 OUT3 ____________________________Features ♦ Improved Second Source to DS1013 ♦ Available in Space-Saving 8-Pin µMAX Package ♦ 20mA Supply Current (vs. Dallas’ 40mA) ♦ Low Cost ♦ Three Separate Buffered Delays ♦ Delay Tolerance of ±2ns for MXD1013_ _ 010 through MXD1013_ _ 060 ♦ TTL/CMOS-Compatible Logic ♦ Leading- and Trailing-Edge Accuracy ♦ Custom Delays Available ______________Ordering Information PART TEMP. RANGE MXD1013C/D_ _ _ 0°C to +70°C PIN-PACKAGE Dice* MXD1013PA_ _ _ MXD1013PD_ _ _ MXD1013SA_ _ _ -40°C to +85°C -40°C to +85°C -40°C to +85°C 8 Plastic DIP 14 Plastic DIP 8 SO MXD1013SE_ _ _ MXD1013UA_ _ _ -40°C to +85°C -40°C to +85°C 16 Narrow SO 8 µMAX *Dice are tested at TA = +25°C. Note: To complete the ordering information, fill in the blank with the part number extension from the Part Numbers and Delay Times table to indicate the desired delay per output. MXD1013 IN3 DIP/SO/µMAX ___Part Numbers and Delay Times PART NUMBER EXTENSION (MXD1013_ _ _ ) OUTPUT DELAY (ns) PART NUMBER EXTENSION (MXD1013_ _ _ ) OUTPUT DELAY (ns) 010 10 050 50 012 12 060 60 IN 1 14 VCC 015 15 070 70 N.C. 2 13 N.C. 020 20 075 75 IN2 3 12 OUT1 025 25 080 80 11 N.C. 030 30 090 90 10 OUT2 035 35 100 100 N.C. 6 9 N.C. 040 40 150 150 GND 7 8 OUT3 045 45 200 200 N.C. 4 MXD1013 IN3 5 DIP Pin Configurations continued at end of data sheet. Functional Diagram appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 408-737-7600 ext. 3468. MXD1013 _______________General Description The MXD1013 contains three independent, monolithic, logic-buffered delay lines with delays ranging from 10ns to 200ns. Nominal accuracy is ±2ns for a 10ns to 60ns delay, ±3% for a 70ns to 100ns delay, and ±5% for a 150ns to 200ns delay. Relative to hybrid solutions, these devices offer enhanced performance and higher reliability, and reduce overall cost. Each output can drive up to ten standard 74LS loads. The MXD1013 is available in multiple versions, each offering a different combination of delay times. It comes in the space-saving 8-pin µMAX package, as well as a standard 8-pin SO and DIP. It is also offered in industry-standard 16-pin SO and 14-pin DIP packaging, allowing full compatibility with the DS1013 and other delay-line products. MXD1013 3-in-1 Silicon Delay Line ABSOLUTE MAXIMUM RATINGS VCC to GND ..............................................................-0.5V to +6V All Other Pins..............................................-0.5V to (VCC + 0.5V) Short-Circuit Output Current (1sec) ....................................50mA Continuous Power Dissipation (TA = +70°C) 8-Pin Plastic DIP (derate 9.1mW/°C above +70°C) .......727mW 14-Pin Plastic DIP (derate 10.0mW/°C above +70°C) ...800mW 8-Pin SO (derate 5.9mW/°C above +70°C)....................471mW 16-Pin Narrow SO (derate 8.7mW/°C above +70°C) .....696mW 8-Pin µMAX (derate 4.1mW/°C above +70°C) ...............330mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +5.0V ±5%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)(Note 1) MIN TYP MAX UNITS Supply Voltage PARAMETER SYMBOL VCC (Note 2) CONDITIONS 4.75 5.00 5.25 V Input Voltage High VIH (Note 2) 2.2 Input Voltage Low VIL (Note 2) Input Leakage Current IL 0V ≤ VIN ≤ VCC V -1 Active Current ICC VCC = 5.25V, period = minimum (Note 3) Output Current High IOH VCC = 4.75V, VOH = 4.0V Output Current Low IOL VCC = 4.75V, VOL = 0.5V Input Capacitance CIN TA = +25°C (Note 4) 20 0.8 V 1 µA 70 mA -1 mA 12 mA 5 10 pF TIMING CHARACTERISTICS (VCC = +5.0V ±5%, TA = +25°C, unless otherwise noted.) PARAMETER Input Pulse Width SYMBOL tWI Input-to-Output Delay (leading edge) tPLH Input-to-Output Delay (trailing edge) tPHL Power-Up Time tPU Period CONDITIONS (Note 5) MIN TYP MAX 100% of tPLH UNITS ns (Notes 6, 7, 8) See Part Number and Delay Times table ns (Notes 6, 7, 8) See Part Number and Delay Times table ns 100 (Note 5) 3(tWI) ms ns Specifications to -40°C are guaranteed by design, not production tested. All voltages referenced to GND. Measured with outputs open. Guaranteed by design. Pulse width and/or period specifications may be exceeded, but accuracy is application sensitive (i.e., layout, decoupling, etc.). VCC = +5V at +25°C. Typical delays are accurate on both rising and falling edges within ±2ns for delays from 10ns to 60ns, within ±3% for delays from 70ns to 100ns, and within ±5% for delays from 150ns to 200ns. Note 7: The Part Number and Delay Times table provides typical delays at +25°C with VCC = +5V. The delays may shift with temperature and supply variations. The combination of temperature (from +25°C to 0°C, or +25°C to +70°C) and supply variation (from 5V to 4.75V, or 5V to 5.25V) could produce an additional typical delay of ±1.5ns or ±3%, whichever is greater. Note 8: All output delays tend to vary unidirectionally with temperature or supply voltage variations (i.e., if OUT1 slows down, all other outputs also slow down). Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: 2 _______________________________________________________________________________________ 3-in-1 Silicon Delay Line MXD1013_ _100 PERCENT CHANGE IN DELAY vs. TEMPERATURE (OUT1) ACTIVE CURRENT vs. INPUT FREQUENCY 9.5 9.0 8.5 8.0 7.5 0.5 tPHL 0 tPLH tPLH tPHL -0.5 -1.0 MXD1013_ _075 -1.5 -2.0 6.0 0.0001 0.001 0.01 0.1 1 10 -40 100 -20 0 20 40 60 80 INPUT FREQUENCY (MHz) TEMPERATURE (°C) MXD1013_ _100 PERCENT CHANGE IN DELAY vs. TEMPERATURE (OUT2) MXD1013_ _00 PERCENT CHANGE IN DELAY vs. TEMPERATURE (OUT3) 2.0 MXD1013 TOC3 2.0 1.5 1.0 0.5 tPLH 0 tPHL tPHL -0.5 1.5 % CHANGE IN DELAY % CHANGE IN DELAY 1.0 MXD1013_ _030 7.0 6.5 MXD1013 TOC2 1.5 tPLH 1.0 tPLH tPHL 0 tPLH tPHL -0.5 -1.0 -1.5 -1.5 -2.0 tPHL 0.5 -1.0 100 MXD1013 TOC4 ACTIVE CURRENT (mA) ALL INPUTS CONNECTED TOGETHER 0V–3V INPUT NO LOAD % CHANGE IN DELAY 10.5 10.0 2.0 MXD1013 TOC01 11.0 tPLH -2.0 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) _______________________________________________________________________________________ 3 MXD1013 __________________________________________Typical Operating Characteristics (VCC = +5V, TA = +25°C, unless otherwise noted.) MXD1013 3-in-1 Silicon Delay Line ______________________________________________________________Pin Description PIN NAME FUNCTION 8-PIN DIP/SO/µMAX 14-PIN DIP 16-PIN SO 1 1 1 IN1 First Independent Input 2 3 4 IN2 Second Independent Input 3 5 6 IN3 Third Independent Input 4 7 8 GND Device Ground 5 8 9 OUT3 Third Delayed Output 6 10 11 OUT2 Second Delayed Output 7 12 13 OUT1 First Delayed Output 8 14 16 VCC Power-Supply Input — 2, 4, 6, 9, 11, 13 2, 3, 5, 7, 10, 12, 14, 15 N.C. Not Connected _______________Definitions of Terms ____________________Test Conditions Period: The time elapsed between the first pulse’s leading edge and the following pulse’s leading edge. Ambient Temperature: Supply Voltage (VCC): Pulse Width (t WI): The time elapsed on the pulse between the 1.5V level on the leading edge and the 1.5V level on the trailing edge, or vice versa. Input Rise Time (tRISE): The elapsed time between the 20% and 80% points on the input pulse’s leading edge. Input Fall Time (tFALL): The time elapsed between the 80% and 20% points on the input pulse’s trailing edge. Time Delay, Rising (tPLH): The time elapsed between the 1.5V level on the input pulse’s leading edge and the corresponding output pulse’s leading edge. Time Delay, Falling (tPHL): The time elapsed between the 1.5V level on the input pulse’s trailing edge and the corresponding output pulse’s trailing edge. Input Pulse: 5.0V ±0.1V High = 3.0V ±0.1V Source Impedance: Low = 0.0V ±0.1V 50Ω max Rise and Fall Times: Pulse Width: 3.0ns max 500ns max 4 +25°C Period: 1µs Each output is loaded with a 74F04 input gate. Delay is measured at the 1.5V level on the rising and falling edges. The time delay due to the 74F04 is subtracted from the measured delay. _______________________________________________________________________________________ 3-in-1 Silicon Delay Line MXD1013 TIME INTERVAL COUNTER PERIOD VIH IN VIL MXD1013 tFALL tRISE 74F04 PULSE GENERATOR 2.4V 1.5V 2.4V 1.5V 1.5V TD 50Ω 0.6V 0.6V 74F04 tWI PULSE GENERATOR TD 50Ω tPHL 74F04 tPLH PULSE GENERATOR TD 50Ω 1.5V 1.5V OUT EACH OUTPUT IS LOADED WITH THE EQUIVALENT OF ONE 74F04. THE DELAY OF THE 74F04 IS SUBTRACTED FROM THE MEASURED DELAY. Figure 2. Test Circuit Figure 1. Timing Diagram __________ Applications Information Supply and Temperature Effects on Delay Over the specified range, the MXD1013’s delays are typically 2% accurate. Variations in supply voltage may affect the MXD1013’s fixed output delays. Supply voltages beyond the specified range may result with larger variations. Although there might be a slight variance in delays over temperature, the MXD1013 is internally compensated to maintain its nominal values. Board Layout Considerations Bypass the MXD1013 with a 0.1µF capacitor to minimize the impact of high-speed switching on the power supply. The power supply must be able to deliver the required switching currents for proper operation. It is advisable to minimize trace lengths in order to reduce board capacitance as well as the traveling distance between devices. Sockets and wire-wrapped boards increase capacitance and should be avoided. Loading Effect on Delay Lines Capacitive loads increase delay times as they increase the rise and fall times of the delay lines. Other logic devices increase the capacitance at the output of the delays, which can affect device performance. ___________________Chip Information TRANSISTOR COUNT: 824 _______________________________________________________________________________________ 5 ____Pin Configurations (continued) ________________Functional Diagram TOP VIEW IN 1 16 VCC N.C. 2 15 N.C. N.C. 3 14 N.C. IN2 4 MXD1013 MXD1013 IN1 TD OUT1 IN2 TD OUT2 IN3 TD OUT3 13 OUT1 N.C. 5 12 N.C. IN3 6 11 OUT2 N.C. 7 10 N.C. GND 8 9 OUT3 SO ________________________________________________________Package Information 8LUMAXD.EPS MXD1013 3-in-1 Silicon Delay Line Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.