[ /Title (CD54 HC453 8, CD74 HC453 8, CD74 HCT45 38) /Subject (High Speed CMOS Logic Data sheet acquired from Harris Semiconductor SCHS123 CD54HC4538, CD74HC4538, CD74HCT4538 June 1998 High Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator Features Description • Retriggerable/Resettable Capability The Harris CD54HC4538, CD74HC4538 and CD74HCT4538 are dual retriggerable/resettable monostable precision multivibrators for fixed voltage timing applications. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q terminals. The propagation delay from trigger input-to-output transition and the propagation delay from reset input-to-output transition are independent of RX and CX. • Trigger and Reset Propagation Delays Independent of RX, CX • Triggering from the Leading or Trailing Edge • Q and Q Buffered Outputs Available • Separate Resets • Wide Range of Output-Pulse Widths • Schmitt Trigger Input on A and B Inputs Leading-edge triggering (A) and trailing edge triggering (B) inputs are provided for triggering from either edge of the input pulse. An unused “A” input should be tied to GND and an unused B should be tied to VCC. On power up the IC is reset. Unused resets and sections must be terminated. In normal operation the circuit retriggers on the application of each new trigger pulse. To operate in the non-triggerable mode Q is connected to B when leading edge triggering (A) is used or Q is connected to A when trailing edge triggering (B) is used. The period (τ) can be calculated from τ = (0.7) RX, CX; RMIN is 5kΩ. CMIN is 0pF. • Retrigger Time is Independent of CX • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs Ordering Information • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V TEMP. RANGE (oC) PACKAGE CD54HC4538F -55 to 125 16 Ld CERDIP F16.3 CD74HC4538E -55 to 125 16 Ld PDIP E16.3 CD74HCT4538E -55 to 125 16 Ld PDIP E16.3 CD74HC4538M -55 to 125 16 Ld SOIC M16.15 CD74HCT4538M -55 to 125 16 Ld SOIC M16.15 PART NUMBER • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Pinout NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. CD54HC4538, CD74HC4538, CD74HCT4538 (PDIP, SOIC, CERDIP) TOP VIEW 1CX 1 16 VCC 1RXCX 2 15 2CX 1R 3 14 2RXCX 1A 4 13 2R 1B 5 12 2A 1Q 6 11 2B 1Q 7 10 2Q GND 8 9 2Q 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright PKG. NO. © Harris Corporation 1998 1 File Number 1671.2 CD54HC4538, CD74HC4538, CD74HCT4538 Functional Diagram 1Cx 1Rx VCC 1 2 1Cx 1RxCx 6 4 1Q 1A MONO 1 5 7 1B 1Q 3 1R 2R 13 10 12 2Q 2A MONO 2 11 9 2B 2Q 2Cx 2RxCx 15 GND = 8 VCC = 16 14 VCC 2Cx 2Rx TRUTH TABLE R2 INPUTS OUTPUTS R A B Q Q L X X L H CL R1 p n D X H X L H X X L L H Q CL CL CL Q H L ↓ p n H ↑ H CL NOTE: H = High Level, L = Low Level, ↑ = Transition from Low to High, ↓ = Transition from High to Low, One High Level Pulse, One Low Level Pulse, X = Irrelevant. CL p n CL FIGURE 1. FF DETAIL 2 R1 CD54HC4538, CD74HC4538, CD74HCT4538 16 VCC VCC VCC VCC RX 2(14) CX COMP II + R1 6(10) Q - 1(15) R2 VCC VCC 8 7(9) Q HIGH Z 3(13) R VCC 4(12) D R1 A CL 5(11) R2 Q FF CL Q B FIGURE 2. LOGIC DIAGRAM (1 MONO) FUNCTIONAL TERMINAL CONNECTIONS VCC TO TERMINAL NUMBER GND TO TERMINAL NUMBER INPUT PULSE TO TERMINAL NUMBER MONO1 MONO2 MONO1 MONO1 MONO2 3, 5 11, 13 4 12 Leading-Edge Trigger/Non-Retriggerable 3 13 4 12 Trailing-Edge Trigger/Retriggerable 3 13 5 11 Trailing-Edge Trigger/Non-Retriggerable 3 13 5 11 FUNCTION Leading-Edge Trigger/Retriggerable MONO2 4 12 OTHER CONNECTIONS MONO1 MONO2 5-7 11-9 4-6 12-10 NOTES: 3. A retriggerable one-shot multivibrator has an output pulse width which is extended one full time period (T) after application of the last trigger pulse. 4. A non-triggerable one-shot multivibrator has a time period (T) referenced from the application of the first trigger pulse. T FIGURE 3. INPUT PULSE TRAIN FIGURE 4. RETRIGGERABLE MODE PULSE WIDTH (A MODE) 3 T FIGURE 5. NON-RETRIGGERABLE MODE PULSE WIDTH (A MODE) CD54HC4538, CD74HC4538, CD74HCT4538 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 7) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 160 N/A CERDIP Package . . . . . . . . . . . . . . . . 130 55 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC (Note 5) HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Times, tr, tf Reset Input: 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) Trigger Inputs A or B: 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited (Max) External Timing Resistor, RX (Note 6) . . . . . . . . . . . . . . . .5kΩ (Min) External Timing Capacitor, CX (Note 6) . . . . . . . . . . . . . . . . . 0 (Min) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 5. Unless otherwise specified, all voltages are referenced to ground. 6. The maximum allowable values of RX and CX are a function of leakage of capacitor CX, the leakage of the HC4538, and leakage due to board layout and surface resistance. Values of RX and CX should be chosen so that the maximum current into pin 2 or pin 14 is 30mA. Susceptibility to externally induced noise signals may occur for RX > 1MΩ. 7. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads VIL VOH - VIH or VIL - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 4 CD54HC4538, CD74HC4538, CD74HCT4538 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage CMOS Loads -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS SYMBOL VI (V) IO (mA) VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output Voltage TTL Loads Input Leakage Current A, B, R 25oC VCC (V) II VCC or GND Input Leakage Current RXCX (Note 9) - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V - 6 - - ±0.1 - ±1 - ±1 µA - 6 - - ±0.05 - ±0.5 - ±0.5 µA Quiescent Device Current ICC VCC or GND 0 6 - - 8 - 80 - 160 µA Active Device Current Q = High & Pins 2, 14 at VCC/4 ICC VCC or GND 0 6 - - 0.6 - 0.8 - 1 mA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V - 5.5 - ±0.1 - ±1 - ±1 µA - 5.5 - - ±0.05 - ±0.5 - ±0.5 µA HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC and GND Input Leakage Current RXCX (Note 9) Quiescent Device Current ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Active Device Current Q = High & Pins 2, 14 at VCC/4 ICC VCC or GND 0 5.5 - - 0.6 - 0.8 - 1 mA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ∆ICC (Note 8) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTES: 8. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. 9. When testing IIL the Q output must be high. If Q is low (device not triggered) the pull-up P device will be ON and the low resistance path from VDD to the test pin will cause a current far exceeding the specification. 5 CD54HC4538, CD74HC4538, CD74HCT4538 HCT Input Loading Table INPUT UNIT LOADS All 0.5 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g. 360µA max at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER SYMBOL -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns 2 5 - - 5 - - 5 - - ns 4.5 5 - - 5 - - 5 - - ns 6 5 - - 5 - - 5 - - ns 5 - 175 - - - - - - - ns 4.5 16 - - 20 - - 24 - - ns tWL 4.5 20 - - 25 - - 30 - - ns tREC 4.5 5 - - 5 - - 5 - - ns trr 5 - 175 - - - - - - - ns HC TYPES Input Pulse Widths tWH, tWL A, B R Reset Recovery Time Retrigger Time (Figure 11) tWL tREC trr HCT TYPES Input Pulse Widths tWH, tWL A, B R Reset Recovery Time Retrigger Time (Figure 11) 6 CD54HC4538, CD74HC4538, CD74HCT4538 Switching Specifications CL = 50pF, Input tr, tf = 6ns, RX = 10KΩ, CX = 0 -40oC TO 85oC 25oC PARAMETER SYMBOL TEST CONDITIONS tPLH CL = 50pF -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 250 - 315 - 375 ns 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 6 - - 43 - 54 - 64 ns CL = 50pF 2 - - 250 - 315 - 375 ns 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 6 - - 43 - 54 - 64 ns CL = 50pF 2 - - 250 - 315 - 375 ns 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 6 - - 43 - 54 - 64 ns CL = 50pF 2 - - 250 - 315 - 375 ns 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 6 - - 43 - 54 - 64 ns CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns 3 0.64 - 0.78 0.612 0.812 0.605 0.819 ms 5 0.63 - 0.77 0.602 0.798 0.595 0.805 ms - ±1 - - - - - % HC TYPES Propagation Delay A, B to Q A, B to Q R to Q R to Q Output Transition Time tPHL tPHL tPLH tTLH, tTHL Output Pulse Width RX = 10k, CX = 0.1µF τ Output Pulse Width Match, Same Package - - CPD CL = 15pF 5 - 136 - - - - - pF CI CL = 50pF - 10 - 10 - 10 - 10 pF CL = 50pF 4.5 - - 55 - 69 - 83 ns CL = 15pF 5 - 23 - - - - - ns CL = 50pF 4.5 - - 55 - 69 - 83 ns CL = 15pF 5 - 23 - - - - - ns CL = 50pF 4.5 - - 40 - 50 - 60 ns CL = 15pF 5 - 17 - - - - - ns Power Dissipation Capacitance Input Capacitance CL = 50pF HCT TYPES Propagation Delay tPLH A, B to Q A, B to Q R to Q tPHL tPHL 7 CD54HC4538, CD74HC4538, CD74HCT4538 Switching Specifications CL = 50pF, Input tr, tf = 6ns, RX = 10KΩ, CX = 0 (Continued) -40oC TO 85oC 25oC PARAMETER R to Q -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH CL = 50pF 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns Output Pulse Width RX = 10k, CX = 0.1µF τ CL = 50pF 5 0.63 - 0.77 0.602 0.798 0.595 0.805 ms Output Pulse Width Match, Same Package - - - - ±1 - - - - - % CPD CL = 15pF 5 - 134 - - - - - pF CI CL = 50pF - 10 - 10 - 10 - 10 pF Power Dissipation Capacitance Input Capacitance NOTES: 10. CPD is used to determine the dynamic power consumption, per one shot. 11. PD = (CPD + CX) VCC2 fi ∑(CL VCC2 fO) where fi = input frequency, fO = output frequency, CL = output load capacitance, CX = external capacitance VCC = supply voltage assuming fi « -Iτ Test Circuits and Waveforms tr = 6ns tf = 6ns VCC 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 6. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 8 CD54HC4538, CD74HC4538, CD74HCT4538 Typical Performance Curves HC4538 - TA11646C TA = 25oC 0.70 HCT4538 - TA13646C TA = 25oC 0.70 K FACTOR K FACTOR 10kΩ, 10nF 0.69 10kΩ, 100nF 100kΩ, 100nF 0.68 0.69 10kΩ, 10nF 10kΩ, 100nF 100kΩ, 100nF 0.68 100kΩ, 10nF 100kΩ, 10nF 0.67 0.67 2 3 4 4.5 5 5.5 6 2 VCC, DC SUPPLY VOLTAGE (V) trr, TYP MIN RETRIGGER TIME (ns) K FACTOR 1.1 1.0 0.9 0.8 2kΩ 0.7 10kΩ 100kΩ 102 103 104 5 5.5 104 1.2 10 4.5 6 FIGURE 9. K FACTOR vs DC SUPPLY VOLTAGE (VCC) - V HC/HCT4538 VCC = 5V, TA = 25oC 0.6 4 VCC, DC SUPPLY VOLTAGE (V) FIGURE 8. K FACTOR vs DC SUPPLY VOLTAGE (VCC) - V 1.3 3 105 TA = 25oC RX = 10kΩ 103 VCC = 4.5V 102 VCC = 5V 10 CX, TIMING CAPACITANCE (pF) 102 103 CX, TIMING CAPACITANCE (pF) FIGURE 10. K FACTOR vs CX FIGURE 11. MINIMUM RETRIGGER TIME vs TIMING CAPACITANCE 9 104 CD54HC4538, CD74HC4538, CD74HCT4538 Power-Down Mode During a rapid power-down condition, as would occur with a power-supply short circuit with a poorly filtered power supply, the energy stored in CX could discharge into Pin 2 or 14. To aviod possible device damage in this mode, when CX is ≥ 0.5µF, a protection diode with a 1 ampere or higher rating (1N5395 or equivalent) and a separate ground return for CX should be provided as shown in Figure 12. An alternate protection method is shown in Figure 13, where a 51Ω current-limiting resistor is inserted in series with CX. Note that a small pulse width decrease will occur however, and RX must be appropriately increased to obtain the originally desired pulse width. VCC VCC IN5395 OR EQUIVALENT RX RX 2(14) CX ≥0.5µF 16 2(14) 16 1(15) 8 51Ω + 1(15) CX ≥0.5µF 8 FIGURE 12. RAPID POWER-DOWN PROTECTION CIRCUIT FIGURE 13. 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