Design Workbook MVPX3DW/D Rev. 0.2, 5/2002 MVP X3 Multiprocessor Evaluation System Design Workbook Gary Milliorn CPD Applications 1 Introduction This document describes the design information on the MVP reference platform. MVP, short for Multiprocessing Verification Platform, is a dual-processor MPC7455-based platform which allows evaluation of the 60X or MPX bus interfaces. It provides all necessary computing platform devices needed to boot Linux, QNX, VxWorks, or other OSes. This version of the design document describes the “X3” version, which has slight architectural changes over the first versions. Features 1.1 Features The MVP includes the following features: • • • • Two MPC7455 Processors – 1 GHz or greater core frequency – 2MB, >= 200 MHz pipelined-burst (PB2) L3 Cache GT64260A System Controller – Dual Processor (60X bus mode) or Single-processor (MPX bus mode) interface – SDRAM controller – Dual PCI Interfaces – Dual 10/100base-T Ethernet interfaces – Dual serial ports SDRAM Modules – 2 PC133 SDRAM DIMM sockets – 2GB maximum memory (256MB standard) PCI Interface #1 – • PCI Interface #2 – • • • Two slots, 32 bit, 33 MHz, 5V Super IO – Dual USB 1.0/UHCI v1.1 interface – Dual UltraDMA ATA100 IDE disk interface – PS/2 keyboard and mouse interfaces – Floppy disk interface Flash/ROM Interface – 32-bit Boot ROM (1-16 MB, 8 MB standard) – 32-bit OS/User ROM (1-16 MB, 8 MB standard) Ethernet – • Two slots, 32 or 64 bit, 66 MHz, 3V Dual 10/100baseT Ethernet Three Serial Ports – Two 9-pin serial ports using the GT64260 MPSC logic – Standard 9-pin serial port, baud rates up to ~500kpbs – • • 2 One 10-pin AT header using the VIA PC16450 UART logic Power Supplies – Individual 20A 1.25 to 2.0V switching power supplies for each MPC7450 – Adjustable 10A 2.5V switching power supply for processor and memory I/O. – Fixed 1.8V 1.5A switching power supply for GT64260A core and PHY ATX Motherboard Form-factor MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Overview 1.2 Overview Figure 1 shows a block diagram of the MVP, for reference purposes. L3 PB2 SRAM POWER L3 PB2 SRAM M3 MPC7455 POWER POWER CLOCKS MPC7455 ODT optional DIMMs ROMs PCI Slot PCI Slot 32bit 33MHz 5V 64bit 66MHz 3V GT64260A PCI Slot 32bit 33MHz 5V PCI Slot 64bit 66MHz 3V Super IO IDE USB PS2 UARTs UART Ethernet Dual 10/100baseT I2C EEPROM System Monitor Figure 1. MVP Block Diagram 1.3 Differences between X3 and X2 This version of the MVP Design Document has been adjusted to accomodate revisions between X3 and X2. The board is architecturally similar, but numerous changes and enhancements were made, as described in Table 2. Table 1. MVP X2 to X3 Changes Category Serial Port ARB Config MOTOROLA Version Change X2 Baudclk not usable due to GT errata X3 25 MHz Baudclk on MPP pin is usable X2 External arbiter default X3 Internal arbiter default X2 Not all config options easily supported X3 More config switches, all GT options supported. MVP X3 Multiprocessor Evaluation System Design Workbook 3 Differences between X3 and X2 Table 1. MVP X2 to X3 Changes Category SuperIO Clock Ethernet GT64260 System Monitor Errata 4 Version Change X2 VIA 82C586A X3 VIA 82C686B X2 AT Keyboard on top of keyboard/mouse pair (non-standard) X3 AT Keyboard on bottom of keyboard/mouse pair (standard) X2 MPC972 with dividers; limited options X3 MPC9600+MPC9315, more options X2 Synchronized clock domains. X3 Decoupled clock domains (CPU vs. PCI). X2 Supports spread-spectrum oscillator X3 Not supported. X2 LXT971 PHY obsoleted X3 BroadComm BCM5222 PHY used X2 Programmable LEDs X3 Fixed-definition LEDs. X2 REGE (unused) on MPP port #25 X3 REGE on MPP port #29 X2 One LED, no switches. X3 GTSTAT drives two LEDS; unused ports to switches X2 MPP15 is an interrupt source. X3 MPP15 is not an interrupt source. X2 External LM87 X3 Integrated in VIA 82C686B X2 Unfixed X3 Fixed MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Processors 2 Architecture The following sections cover the MVP design in more detail. To describe the MVP system details, it is (perhaps) useful to track what devices are present on particular buses. The buses described in Table 2 are present on the MVP system. Table 2. MVP Bus Architecture Connections Bus Processor Cache CPU #1 CPU #2 GT64260A Mictor Debug Headers CPU #1 CPU #2 PB SRAM Size Max. Speed Description 32-bit address 4-bit address parity 64-bit data 8-bit data parity 133 MHz 60X or MPX bus 22-bit address 64-bit data 8-bit data parity 200 MHz Cache data bus Memory SDRAM DIMM #1 SDRAM DIMM #2 64 bits 8 parity/ECC bits 133 MHz SDRAM bus Device Boot Flash #1 Aux/OS Flash #2 Flash Emulator 32-bits 133 MHz IO bus Fast PCI PCI Slot #1 PCI Slot #2 64-bits 66 MHz Primary PCI bus Slow PCI PCI Slot #3 PCI Slot #4 SuperIO 32-bits 33 MHz Secondary PCI bus I2C DIMM #1 SPD EEPROM DIMM #2 SPD EEPROM Info EEPROM System Monitor 2 bits 1 MHz I2C bus MII PHY #1 PHY #2 15 bits 25 MHz Interface to Ethernet PHYs Serial Serial #1 Serial #2 5 bits 500 kbps Serial ports USB USB #1 USB #2 4 bits 1.5 Mbps USB 1.1 Host Port PS/2 PS/2 Keyboard PS/2 Mouse 4 bits ~100 kbps PS/2 Peripheral Port Notes 1 2 NOTES: 1 Limited to 200 MHz components for default configurations. 2 Note that the fast PCI bus is not auto-selected for 33 vs. 66 MHz. 2.1 Processors The MVP platform supports two MPC7455 “Apollo” processors or compatible devices. The system bus interface connects between the two MPC7455 processors and the GT64260A system controller, using either the MPX bus protocol or the 60X bus protocol. MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 5 System Controller 2.1.1 BVSEL/L2VSEL In addition to bus mode configuration, the MPC7455 processor must be configured for bus I/O voltage (BVSEL) and L3 I/O voltage (L3VSEL). MVP only supports 2.5V I/O on the system bus (for GT64260A compatibility) and 2.5V I/O on the L3 bus (for PB2 compatibility), so these options are not switch/resistor selectable on MVP. 2.1.2 BMODE The MPC7455 BMODE pins are controlled to select both the bus mode (MPX or 60X) and the processor ID. Processor ID is controlled with hardware, but bus mode is switch-selectable (see section 3 for details). Table 3. MPC745x Bus Mode/ID Selection Processor BMODE0 BMODE1 Bus Mode Processor ID MPC7455 #1 0 (ON) OVDD MPX Bus 0 MPC7455 #1 1 (OFF) OVDD 60X Bus 0 MPC7455 #2 0 (ON) not HRESET MPX Bus 1 MPC7455 #2 1 (OFF) not HRESET 60X Bus 1 Each processor may detect its ID by examining bit 26 (CPUID) of the MSSCR0 register. The BMODE information is also used to configure the GT64260 bus mode. 2.1.3 L3 Cache Each MPC7455 processor has a 2MB back-side L3 cache, implemented with two (2) 8Mbit PB2 SRAM devices, and operating in the range of 133-200 MHz. The maximum speed of the L3 on MVP will depend upon parts used and may vary subject to availability. The L3 SRAMs require a 3.3V core power supply and use 2.5V I/O signalling, compatible with the MPC7455. No other voltage options are provided for. 2.2 System Controller The system controller is the Marvell GT64260A “Discovery”, which provides the following features: • Multiprocessing 60X bus OR Single-processor MPX bus • SDRAM memory controller, 133 MHz • Dual 10/100-base-T Ethernet ports • Dual serial ports • I2C interface • Interrupt Controller • PCI Bus arbiters The GT64260A does not support two processors in MPX bus protocol, so the device must be configured to single-processor mode when MPX bus mode is configured (see section 3). 6 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA System Controller 2.2.1 GT64260A MPP Configuration GT64260A provides many more features than pins. To use particular functions, the MPP (Multi-Purpose Port) must be programmed to provide one of 16 selectable functions per port pin. MVP relies on each MPP port being set to the proper configuration option as described in Table 4; otherwise, the system may not operate properly. Table 4. MVP MPP Usage MPP Bit MPP Definition MPP Programming 0 GNT0[0]* MPPCTL0[3:0] 1 REQ0[0]* MPPCTL0[7:4] pPCI slot 1 REQ# 2 GNT0[1]* MPPCTL0[11:8] pPCI slot 2 GNT# 3 REQ0[1]* 4 GPP[4] 5 GPP[5] MPPCTL0[23:20] Cross-processor 0->1 output drive 6 GPP[6] MPPCTL0[27:24] pPCI INT 0 (Slot 1 INTA#, Slot 2 INTD#) 7 GPP[7] MPPCTL0[31:28] pPCI INT 1 (Slot 1 INTB#, Slot 2 INTA#) 8 GPP[8] Usage Notes pPCI slot 1 GNT# MPPCTL0[15:12] pPCI slot 2 REQ# MPPCTL0[19:16] Cross-processor 1->0 interrupt MPPCTL1[3:0] pPCI INT 2 (Slot 1 INTC#, Slot 2 INTB#) 9 GPP[9] MPPCTL1[7:4] pPCI INT 3 (Slot 1 INTD#, Slot 2 INTC#) 10 GPP[10] MPPCTL1[11:8] sPCI INT 0 (Slot 3 INTA#, Slot 4 INTD#) 11 GPP[11] MPPCTL1[15:12] sPCI INT 1 (Slot 3 INTB#, Slot 4 INTA#) 12 GPP[12] MPPCTL1[19:16] sPCI INT 2 (Slot 3 INTC#, Slot 4 INTB#) 13 GPP[13] MPPCTL1[23:20] sPCI INT 3 (Slot 3 INTD#, Slot 4 INTC#) 14 GPP[14] MPPCTL1[27:24] PHY INT* 15 GPP[15] MPPCTL1[31:28] BAUDCLK (25 MHz) 16 GNT1[0]* 17 REQ1[0]* MPPCTL2[7:4] sPCI slot 3 REQ# 18 GNT1[1]* MPPCTL2[11:8] sPCI slot 4 GNT# 19 REQ1[1]* MPPCTL2[15:12] sPCI slot 4 REQ# 20 GNT2[1]* MPPCTL2[19:16] sPCI SIO GNT# 21 REQ2[1]* MPPCTL2[23:20] sPCI SIO REQ# 22 GPP[22] MPPCTL2[27:24] SIOINT 1 23 GPP[23] MPPCTL2[31:28] BG1_EN 2 24 GPP[24] MPPCTL2[3:0] MPPCTL3[3:0] sPCI slot 3 GNT# GTSTAT0 3 25 GPP[25] MPPCTL3[7:4] GTSTAT1 3 26 GPP[26] MPPCTL3[11:8] GTOPT0 4 27 GPP[27] MPPCTL3[15:12] GTOPT1 4 28 GPP[28] MPPCTL3[19:16] GTOPT2 4 5 29 GPP[29] MPPCTL3[23:20] REGE 30 GPP[30] MPPCTL3[27:24] Cross-processor 0->1 interrupt 31 GPP[31] MPPCTL3[31:28] Cross-processor 1->0 output drive NOTES: 1 Active high interrupt. 2 GPIO signal set to output; active high enables secondary processor if external arbiter option is used. MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 7 MVP FPGAs 3 LED drive output; set to active low output. 4 Optional switch sensing; set to input. 5 Registered mode DIMM detect (common to both slots). 1 = registered; 0 = normal. 2.3 MVP FPGAs The MVP motherboard has two CPLDs which implement various functions, as described in Table 5. Table 5. MVP FPGA Functions FPGA ODT Function ODT generation External Arbiter 3 M Reset Controller Processor Bus Mode Selection COP Reset Merging Configuration Logic ROM Mode Selection The first FPGA, ODT, implements the ODT debugging assist logic. ODT functions can aid logic analyzers in recovering trace flow of overlapping/pipelined address and data buses such as the Motorola MPC7455 produces in MPX bus mode. Alternately, ODT can be used to implement an external arbiter, for evaluation purposes. Provisions to implement the external arbiter require the installation of special arbiter ‘bypass’ resistors, which are not installed by default. This is not a typical-end-user installable option. The second FPGA, M3, provides general support logic for MVP. In addition to the reset controller, which is discussed in Section 2.14, M3 also collects various logic and provides translation between 3.3V environments and the 2.5V MPC7455 and GT64260A system logic, and provides activity monitors with appropriate pulse-width stretching. 2.4 Clocking MVP must generate many clocks for various devices, as summarized in Table 6. Table 6. System Clocks Destination Signal Frequency Quantity VIO pCPUCLK sCPUCLK 66-133 MHz 2 2.5V GTCLK 66-133 MHz 1 2.5V ODT / external arbiter MODCLK 66-133 MHz 1 2.5V MMM3 MMMCLK 66-133 MHz 1 2.5V SDRAM modules (2 DIMMs @ 4 clocks ea.) SDCLK(0:7) 66-133 MHz 8 3.3V PHY interface clock CLK_25MHZ 25 MHz 1 3.3V BAUDCLK 25 MHz 1 3.3V MPC7455 processors GT64260A core Serial baud reference clock 8 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Clocking Table 6. System Clocks Destination Fast PCI clocks Signal Frequency Quantity VIO pPCICLK(0:3) 33-66 MHz 4 3.3V 25-33 MHz 4 3.3V pPCICLK0 = slot1 pPCICLK1 = slot2 pPCICLK2 = rsv pPCICLK3 = pPCI Slow PCI clocks sPCICLK(0:3) sPCICLK0 = slot3 sPCICLK1 = slot4 sPCICLK2 = SIO sPCICLK3 = sPCI USB Clock CLK_48MHZ 48 MHz 1 3.3V SIO Clock CLK_14MHZ 14.318 MHz 1 3.3V Since several of these clocks are completely independent of other clocks, they are generated by simple oscillator components where possible. This has the additional advantage of minimizing the amount of clock traces running over the MVP board, but it is not necessarily the most cost-effective solution. Integrated clock synthesizers can also provide such clocks where board space or cost is at a premium. The overall clock architecture is shown in Figure 2. MPC9315 pPCI 3.3V sPCI OSC 48 MHz OSC 14 MHz OSC sCPU 2.5V North tuning CPLDs MPC961C 33 MHz MPC9600 OSC 2.5V Buffer 25 MHz 3.3V Buffer pCPU DIMM #1 DIMM #2 PHY PIPC BAUDCLK Figure 2. MVP Clock Architecture MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 9 Memory The main clocks are generated by discrete oscillators, buffered down to 3.3V. This allows the use of 5V oscillators, which are wide-spread and inexpensive, and solves support issue for frequencies at or below 25MHz, which are difficult to obtain. The buffered clocks are sent to the PHY (25MHz) and the System IO (14.318MHz and 48 MHz (ISA and USB, respectively)). Buffered versions of the 25 MHz and 33 MHz clocks are sent to an MPC9600, which multiplies either value to produce the desired bus frequencies at the 2.5V switching levels required. The combinations of two oscillators to select from, two feedback selection options, and 1 of 8 multiplier modes results in the clock combinations shown in Table 7. Table 7. System Clock Selection FB_SEL FSELA FSELB FSELC REF_SEL1 System Bus Speed 1 0 0 0 0 200 MHz2 1 0 0 0 1 150 MHz2 0 0 0 0 0 133 MHz 1 1 1 1 0 100 MHz 0 0 0 0 1 100 MHz 1 1 1 1 1 75 MHz 0 1 1 1 0 66 MHz 0 1 1 1 1 50 MHz NOTES: 1 REF_SEL=0 selects a 33MHz clock source, which REF_SEL=1 selects a 25 MHZ clock source. 2 Experimental; not supported. Lastly, a buffered version of the 33 MHz clock is also sent to an MPC9315, which produces the 33MHz and 66 MHz signals needed for slow and fast PCI buses, respectively. These clocks are sent to the PCI slots and devices, as well as the GT64260A PCI interface buses. There is no defined relationship between PCI and the system bus clocks, they are fully asynchronous. 2.5 Memory The MVP system provides memory resources described in Table 8. Table 8. MVP Memory Resources Type Size Speed Address Range Memory Range SDRAM 0 .. 2GB 33 ... 133 MHz Direct 0000_0000 ... 3FFF_FFFF Flash 32 MB 33 ... 133 MHz Direct FF00_0000 ... FFFF_FFFF 2 FE00_0000 ... FEFF_FFFF NVRAM 256 B 33 MHz Indirect EEPROM 256 B 1 MHz Serial 1E00_0074 ... 1E00_0075 Notes 1 3 00 ... FF NOTES: 1 The maximum speed of SDRAM may be dependant on availability of particular revisions of silicon; refer to the system configuration sheet for details). 2 There are two separate 16MB flash devices at the addresses shown; the total size is 32MB. 10 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Memory 3 Access to NVRAM is via an address/data register in the real-time-clock component of the VIA SuperIO. 2.5.1 SDRAM MA[12:0] BA[1:0] SDRAS SDCAS SDWE DQM[7:0] MDP[71:0] DIMM to GT64260A MVP supports one or two standard PC-100/PC-133, 3.3 Volt, single-data-rate SDRAM DIMM sockets. Each socket connects to two separate bank enables on the GT64260A system controller, and each bank may be up to 1GB in size, so a total of up to 4GB may be supported. Figure 3 shows a block diagram of the SDRAM memory architecture. SCS0, SCS2 SCS1, SCS3 SDCLK MPC961C Figure 3. SDRAM Architecture The connections between GT64260A and the SDRAM sockets are fairly straightforward. Except for the databus, most SDRAM signals are output only and may be routed in a daisy-chain from GT64260A to each DIMM socket, keeping overall trace lengths short, paired and separated by at least 6-12 mils. Signals are source-series-terminated with impedance matching resistors; no other termination is used. The DIMM clocks are generated by an MPC961C, which generates in-phase copies of the SDCLK (SDRAM clock) that is matched to the GT64260A system clock (GTCLK). Registered mode SDRAM DIMMs are supported and can be enabled with an external configuration switch; the REGE signal is connected to the MPP port of the GT64260A; software should examine this bit and set the registered mode in the SDRAM setup software accordingly. Since the GT64260A does not support low-power modes, CKE is not supported and is simply tied high for each module. DIMMs are available in one- or two-physical bank configurations. MVP X2 connects chip selects [0:1] to the first DIMM, and chip select [2:3] to the second bank. If a single bank DIMM is installed in the first DIMM slot, software cannot use CS1 to address any memory; CS0 is followed by CS2. Software must manage the possibility of mixed single- and dual-bank DIMMs, and program chip select registers accordingly, as shown in Table 9. Table 9. MVP Memory Resources DIMM Type MOTOROLA #1 #2 SCS0 Used SCS1 Used SCS2 Used SCS3 Used Single Single Yes No Yes No Single Dual Yes No Yes Yes Notes 1 MVP X3 Multiprocessor Evaluation System Design Workbook 11 Flash Memory Table 9. MVP Memory Resources DIMM Type #1 #2 SCS0 Used SCS1 Used SCS2 Used SCS3 Used Dual Single Yes Yes Yes No Dual Dual Yes Yes Yes Yes Notes NOTES: 1 Single-bank DIMMs are generally preferred for higher-speed operation, especially at high speeds. 2.6 Flash Memory BOOTCS DCS3 Connector Flash Flash Flash Flash to GT64260A DD[31:0] Connector MVP supports two banks of 32-bit flash memory for startup code (“boot flash”) and other purposes, typically OS firmware storage. Each flash bank may be populated with 1, 2, 4, or 8MB TSSOP48W flash devices, supporting a maximum total of 32MB. Figure 4 shows a block diagram of the MVP flash memory architecture. M3 ROMMODE Figure 4. MVP Flash Architecture Socketable flash devices, no matter how attractive during the code development process, are no longer reasonable to use on systems due to limited size and power options. To support code development, a popular method to circumvent this is to desolder the flash devices and replace them with special cables to flash emulators; however this is difficult for many end users to accomplish. MVP instead adds two dedicated high-density connectors which are parallel to the flash memory bus. Dedicated cables may be used to connect the flash emulators to the MVP board, without removing the original devices. The M3 FPGA contains ROM selection mode which disables one of the on-board flash banks and redirects accesses to the flash emulator, for transparent switching between on-board and off-board flash. To allow the emulator to intercept the standard flash controls, the M3 FPGA alters the definition of the BOOTCS and DCS3 chip selects from GT64260A. Typically these signals are routed directly to the component, but on MVP M3 alters them according to Table 10. Table 10. Flash ROM Modes ROMMODE(0:1) 12 Mode Controls Description 00 Standard Boot BOOTCS: DCS3: RCS0 => Usual RCS1 => Aux Normal mode 01 Aux Boot BOOTCS: DCS3: RCS1 => Aux RCS0 => Usual Use to swap ROM images and directly boot from flash. MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA PCI Table 10. Flash ROM Modes ROMMODE(0:1) Mode Controls Description 10 Emulate Boot BOOTCS : Program Standard DCS3 : PromJet (J1+J2) RCS0 => Usual Use to install DINK or OS code from PJ to boot flash. 11 Emulate Boot Program Aux BOOTCS : DCS3 : PromJet (J1+J2) RCS1 => Aux Use to install other OSes from PJ to aux flash (those requiring DINK initialization). Using the ROMMODE option switches, startup code can be swapped among the flash memory banks, and each bank can be redirected to the ROM emulator sockets for quick download. Note that both banks cannot be emulated at the same time. 2.7 PCI 64/66 PCI 32/33 PCI 3.3V only! 64/66 PCI pPCI0 (Primary) 64-bit/66 MHz 32/33 PCI to GT64260A The GT64260A supports two independant PCI buses, each configurable for 32 or 64-bit operation, and at 33 or 66 MHz operation (among other frequencies). MVP separates the two buses into a high-speed 3.3V/64-bit/66 MHz PCI bus and a slower 5V/32-bit/33 MHz bus, as shown in Figure 5. The latter bus allows connection of the PCI-based VIA PIPC, which only operates at 33 MHz. 66 MHz sPCI (Secondary) 32-bit/33 MHz 33 MHz MPC9315 5V only! VIA PIPC Figure 5. MVP PCI Architecture All PCI signals are handled by the GT64260A with the exception of clocks. Interrupts and bus arbitration are available through the GT64260A MPP port (and optionally in the case of the secondary PCI bus, the VIA PCI interrupt controller), and will require proper and careful initialization to be setup properly. As the VIA PIPC works only at 33 MHz, the speed of the secondary PCI bus is fixed at 33 MHz only. The primary PCI may be set to 33, 50 or 66 MHz operation. MVP does not automatically switch between 66 and 33 MHz if a “33 MHz only” card is inserted in a 66 MHz slot. MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 13 Ethernet 2.7.1 PCI Configuration Each PCI device accessible as a target has an associated device number, implemented by connected the devices IDSEL pin to the corresponding PCI AD[31:0] bus. PCI device numbers start at 13 (for marginal compatibility reasons, with previous Motorola evaluation platforms) and increment. Table 11. PCI Configuration Addresses Device Number Notes Primary PCI Interface 19 2, 3 Slot 1 (J25) 13 2 Slot 2 (J26) 14 2 reserved 15 2 Secondary PCI Interface 16 1, 2 reserved 17 2 SuperIO 18 2 Slot 3 (J23) 19 2 Slot 4 (J24) 20 2 Component NOTES: 1 IDSEL for PCI interface provided for PCI test card probing only; performing PCI configuration cycles to self may or may not be valid. 2 The primary and secondary PCI domains have different IDSEL/configurations accesses, and so it is possible to have (for example) IDSEL=AD15 on both PCI buses. Separate devices numbers are therefore not a requirement, but having globally unique device numbers may aid software management. 3 The unusual number for the Primary PCI interface is an errata; however, no device should be performing configuration cycles, so it remains uncorrected. 2.8 Ethernet BCM5222 Dual RJ45 to GT64260A MVP supports two 10-/100-baseT ethernet ports. The ports are connected directly to a BroadCom BCM5222 dual PHY, using the standard MII interface. The physical signals are then connected through standard isolation transformers (Pulse H1102 or Midcom 7090-37) into a dual-RJ45 jack. Figure 6 shows the general arrangement. LEFT = Port #2 RIGHT = Port #1 Figure 6. MVP Ethernet Architecture 14 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA UART The Ethernet ports are connected to a dual RJ45 header block which includes two LEDs. Each pair of LEDs is driven by the corresponding LED outputs of the PHY interface (BCM5222). LEFT LED1 LINK UP LEFT LED2 ACTIVITY RIGHT LED1 LINK UP PORT #2 GT Ethernet #1 MII Device #5 RIGHT LED2 ACTIVITY PORT #1 GT Ethernet #0 MII Device #4 Figure 7. MVP Ethernet Ports with LEDs The LEDs are by default initialized to the functions shown in Table 12 (though software can select other options). Table 12. Ethernet Connector LED Functions LED 2.9 Default Function Left LED1 Link Status: ON=Active OFF=Inactive Left LED2 Activity Status: ON = RX or TX detected. Right LED1 Link Status: Right LED 2 Activity Status: ON = RX or TX detected. ON=Active OFF=Inactive UART The GT64260A supports two serial devices. MVP drives the UART signals to standard RS-232 levels by two Maxim MAX211CAI chips, which also provide ESD protection to the ports with no additional circuitry. The signals are then connected to a dual DB9 male connector (a PC standard). Table 13 shows the location and use of each port. Table 13. UART Information UART Location Function 0 Top DINK Console 1 Bottom DINK Host These serial ports are standard DTE (Data Terminal Equipment) ports, so to connect MVP to another computer (for terminal emulator purposes) requires a “null-modem” cable. Refer to the DINK User’s Manual for details on such a cable, if needed. In addition, the MVP X3 supports a third PC 16550 serial port through the VIA SuperIO facilities. This device is driven to RS232 levels, and then connected to a 2x5 header connector. This connector is compatible with standard AT motherboard serial header cables. MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 15 I2C 2.10 I2C MVP uses an I2C bus to communicate with various on-board peripherals. The I2C controller is provided in the GT64260A device. Table 14 describes the address at which each device may be found. Table 14. I2C Addresses Address 0x50 Device SDRAM DIMM #1 Description DIMM SPD Information 0x51 SDRAM DIMM #2 DIMM SPD Information 0x54 MAC ID Ethernet MAC IDs 0x57 EEPROM 256 bytes of general-purpose storage The MAC ID stores two Ethernet MAC IDs for the GT64260A ethernet ports. The first twelve bytes of the EEPROM should correspond with the two 6-byte OUI-based MAC ID labels on the motherboard. For details on format of DIMM SPD data, refer to the corresponding document in Table 34. 2.11 PIPC The PCI Integrated Peripheral Controller (PIPC), also referred to as SIO on MVP, contains numerous I/O and control facilities needed for modern computer systems or embedded OS support, including: • Dual UltraDMA-66 IDE disk interface • Dual USB interface • PS2 Keyboard and Mouse interface • NVRAM • Floppy Disk Controller • APC power controller • Secondary PCI interrupt controller The PIPC used on MVP is the Via Technologies VT82C686B. This PIPC is used on many PC motherboards, so OS support should be relatively straightforward and many drivers already exist for PIPC functions. The PIPC also includes an PCI interrupt controller which may be used to re-direct the interrupt hierarchies of MVP. Refer to the interrupt architecture section for more detail on the use of the VIA PIPC PCI interrupt in this manner. 2.11.1 IDE The PIPC has a PC-compatible dual-channel UltraDMA-100 IDE disk controller. Interrupts flow through the VIA PCI interrupt controller (which must be used whether the VIA PCI interrupt controller is used for other purposes or not) into the dedicated SIOINT interrupt pin to the GT64260A. 16 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Power 2.11.2 PS/2 The PIPC has a dual PS/2 driver which can be used to connect PS/2-style keyboard and mice. Table 15. PS/2 Port Location Location Function Top PS/2 Mouse Bottom PS/2 Keyboard The interface is identical to that used on PCs; once the VIA has been programmed as a valid PCI target for I/O accesses, the PS/2 interface may be controlled at standard PC addresses (i.e. XX00_0060/XX00_0064, where “XX” is software-determined). 2.11.3 USB The PIPC includes two USB 1.0/UHCI-1.1 compatible ports for connecting to keyboards, mice, scanners, printers, and other peripherals. MVP has an internal power supply capable of supplying up to 500mA to each USB device, and short-circuit protection at 1.25A. 2.11.4 NVRAM The SIO has 256 bytes of battery-backed (NV) RAM. The SIO maintains the state of the NVRAM using either the VSTBY power available from the ATX power supply when it is plugged in (but not necessarily “ON”), or from the lithium coin cell on the motherboard. 2.11.5 APC The SIO contains an APC power controller which allows “soft” power supply on-off via front-panel switches, by timers in the APC, or by software. The APC also manages transitions between standby power and the 3V coin-cell battery in maintaining the contents of the RTC and NVRAM. 2.12 Power Assuming that each component and each PCI slot draws the maximum amount of power, the total requirements of the MVP board are shown in Table 16. Table 16. MVP Power Requirements Symbol Voltage Tolerance Used By Amount Total Power, Maximum Notes pVCORE +1.8V ± 10% MPC7455: 20 A 20 A 40 W 2, 4 sVCORE +1.8V ± 10% MPC7455: 20 A 20 A 40 W 2, 4 VCC_1.8 +1.8V ± 10% GT64260A: 950 mA BCM5222: 153 mA 950 mA 1.8 W 4, 5 OVDD +2.5V ± 10% MPC7455: GT64260A: SRAM_IO: FPGA: 3.9 A 10 W 1, 4 MOTOROLA (2) @ 1.5A 500 mA (4) @ 72*1mA 200 mA MVP X3 Multiprocessor Evaluation System Design Workbook 17 Interrupts Table 16. MVP Power Requirements Symbol Voltage VCC Tolerance Used By Amount Power, Maximum Notes 45 A 225 W 1 39.5 A 132 W 1 100 mA 330 mW Total +5V ± 5% PCI: (4) @ 5A RS232: (2) @ (20mA+5*20mA) SIO: 80 mA USBPWR: 2.5 A ATPWR: 1A PWR_CORE:(2) @ 9.2A PWR_1.8 460 mA PWR_2.5 2.3 A VCC_3.3 +3.3V ± 10% SRAM: PCI: FPGA: GT64260A: SDRAM: MPC961: FLASH: PHY: (4) @ 640 mA (4) @ 7.6A 300 mA 1.4 A (3) @ 1.5A 40 mA 12 mA (2) @ 110 mA VCC_HOT_3.3 +3.3V ± 5% SIO-APC 100 mA VSTDBY +5V ± 5% SIO-APC 1 uA 1 mA 5 mW VBAT +3V ± 20% SIO-APC 1 uA 1 uA 3 uW VCC_12 +12V ± 5% PCI: (4) @ 500 mA 2000 mA 24 W VCC_12N -12V ± 10% PCI (4) @ 100 mA 400 mA 4.8 W Total 377 W NOTES: 1 Assumes 85% conversion efficiency. 2 Voltage may vary; 2.0VDC assumed for worst-case power calculations. 3 The previous standard that IO power is 10-15% of core power is no longer reasonable. Instead, equivalent 100 MHz bus for current G4 processors are assumed, rated w/CVVF. 4 Only input supplies are considered in the total; shaded totals are derived from other input supplies and are not included in the total power requirements. 5 The VCC1_8 power supply is overrated because MVP will switch from PBSRAM to DDR or PCDDR at the next revision, if any. Note that the table uses only worst-case numbers; few if any PCI cards use 500mA of 12V power. Nonetheless, to insure adequate power, MVP will require at bare minimum a 400W ATX power supply, with 450-500 W generally recommended. This is particularly true since the above table does not include power for external equipment such as disk drives. Standard ATX power supplies are available in this range. Table 17. lists some compatible power supplies. Table 17. MVP Power Supply Vendors Manufacturer Sparkle Power Part Number FSP400-60PFN(12V) Power 400W Contact www.sparklepower.com 2.13 Interrupts MVP uses the GT64260A as a the primary interrupt handler, and optionally can relegate some interrupts to the Via PIPC. The GT64260A has an extensive interrupt flexibilities, but it is somewhat limited in the 18 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Interrupts number of discrete interrupts supported. Furthermore, the interrupt controller is quite different from that of the MPC107/MPC8240 EPIC or PC PIC, so software may require some careful thought in this area. The MVP interrupt architecture is shown in Figure 8. secondary PCI primary PCI MPP31-24 MPP23-16 MPP15-8 MPP7-0 GT64260A PIPC CPUINT Interrupt Steering PCI0INT Interrupt Steering PCI1INT Interrupt Steering CPU #1 unused CPU #2 Ethernet PHYs Figure 8. MVP Interrupt Architecture There are many external interrupt sources possible on an MVP platform, in addition to the numerous ones available inside the GT64260A (including but not limited to ethernet, serial, DMA, PCI handling, and memory errors). Since the GT64260A has a limited number of directly triggerable interrupt input pins (basically interrupts are triggered on one of the four MPP byte lanes), interrupt handlers will have to essentially share interrupts. The PIPC PIC can be used to handle the secondary PCI bus interrupt for a reduction in interrupt sharing, though an additional level of interrupt processing hierarchy is introduced. The GT64260A has one primary CPUINT signal, which is used to signal CPU #1 (Primary). For the second CPU, the secondary PCI interrupt output PCI1INT is used. Despite the name, these interrupts have the same capabilities as the CPUINT signal, so once any of the interrupt sources have been routed as shown in Table 18, it may be further routed to a particular processor. Table 18. MVP Interrupt Resources Interrupt PCI Error MPP Byte Lane Connection (internal) N/A Driving Resource(s) Notes (internal) N/A Cross-processor 1->0 MOTOROLA MPP bit #4 0 MPP[31] MVP X3 Multiprocessor Evaluation System Design Workbook 19 Interrupts Table 18. MVP Interrupt Resources Interrupt MPP Byte Lane Connection Driving Resource(s) Notes Primary PCI Int0 MPP bit #6 0 pSLOT_INT(1)-INTA# pSLOT_INT(2)-INTD# 1, 2 Primary PCI Int1 MPP bit #7 0 pSLOT_INT(1)-INTB# pSLOT_INT(2)-INTA# 1, 2 Primary PCI Int2 MPP bit #8 1 pSLOT_INT(1)-INTC# pSLOT_INT(2)-INTB# 1, 2 Primary PCI Int3 MPP bit #9 1 pSLOT_INT(1)-INTD# pSLOT_INT(2)-INTC# 1, 2 Secondary PCI Int0 MPP bit #10 1 sSLOT_INT(1)-INTA# sSLOT_INT(2)-INTD# 1, 2 Secondary PCI Int1 MPP bit #11 1 sSLOT_INT(1)-INTB# sSLOT_INT(2)-INTA# 1, 2 Secondary PCI Int2 MPP bit #12 1 sSLOT_INT(1)-INTC# sSLOT_INT(2)-INTB# 1, 2 Secondary PCI Int3 MPP bit #13 1 sSLOT_INT(1)-INTD# sSLOT_INT(2)-INTC# 1, 2 ENet PHY Interrupt MPP bit #14 1 BCM5222 MDINT* SuperIO Interrupt MPP bit #22 2 SIOINT Cross-processor 0->1 MPP bit #30 3 MPP[5] 3 NOTES: 1 Requires MPP setup. 2 Interrupts are shared in a rotating fashion among PCI domains to handle multi-interrupt-capable boards. 3 An active-high/edge-triggered interrupt, unlike PCI interrupt drivers (active-low/level-sensitive). Note that all of the external interrupt resources are connected through the MPP port, so MPP setup is required for any interrupts. Since the GT64260A cannot trigger a distinct interrupt on the change of one MPP pin, as noted above interrupt handling software must be prepared to poll or otherwise handle the possibility that one or all of the devices on a single MPP byte lane are asserting interrupts. For example, an interrupt from MPP byte lane 1 could be caused by: • primary PCI slot 1 INTC#/INTD# pins (fairly rare) • primary PCI slot 2 INTB#/INTC# pins (fairly rare) • secondary PCI slot 1 INT(A:D)# pins (fairly likely) • secondary PCI slot 2 INT(A:D)# pins (fairly likely) • ethernet PHY interrupts (possible) 2.13.1 Cross-Processor Interrupts A common requirement for multiprocessing systems is to allow one CPU to interrupt another, referred to as a cross-processor interrupt. This facility may be used to allow one CPU to hand off interrupt processing to another, or to perform dynamic load balancing of processes. Since the GT64260A does not include a special path for cross-processor interrupts, MVP uses a combination of general-purpose software controlled outputs (GPIO ports), and general-purpose interrupt 20 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Interrupts inputs. These functions are all available through the MPP port of the GT64260A with appropriate programming. The cross-processor interrupt architecture is shown in Figure 9. 4 30 MPP31-24 MPP23-16 MPP15-8 5 MPP7-0 GT64260A CPUINT Interrupt Steering CPU #1 PCI0INT Interrupt Steering PCI1INT Interrupt Steering CPU #2 31 Figure 9. Cross-Processor Interrupts To use the cross-processor facility, the initialization software must set and use the MPP ports as described in see “MVP Cross-Processor Interrupts” on page 21.. Table 19. MVP Cross-Processor Interrupts Action Intiialization Actor CPU 1 -> CPU CPU #1 2 Output Setup Set MPP bit 5 to output. CPU #2 CPU 2 -> CPU CPU #2 1 CPU #1 Interrupt Setup Assert Action Interrupt Action Set MPP bit 5 = 0, Set MPP bit 5 = 1. Set MPP bit 30 to: active-low edge-triggered interrupt. Set MPP bit 31 to output. 0 OS-dependant Set MPP bit 31 = 0, Set MPP bit 31 = 1. Set MPP bit 4 to: active-low edge-triggered interrupt. Byte Lane 3 3 OS-dependant 0 Notice that in the table, CPU1 only uses byte lane 0 (aligned at 0xF100_XXX0) while CPU2 uses only byte lane 3 (aligned at 0xF100_XXX3). Since the GT64260A allows byte-access to the MPP control/status bits, processors can read from or write to the associated byte portion of the 32-bit MPP ports without requiring locks or semaphores for shared arbitration, as is otherwise often needed. MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 21 Reset 2.13.2 PCI Secondary PCI Interrupt Handling As noted in Section 2.2.1 earlier, the VIA PIPC can serve as a secondary PCI interrupt handler, merging the interrupt sources from the two secondary PCI slots with its own interrupt capabilities (IDE, USB, serial, PS/2) to the standard SIOINT pin. This allows modelling software which requires the presence of an 8259 PIC. 2.14 Reset The reset architecture of MVP is fairly straightforward, as long as these reset requirements are followed: • PCI resets must not be released before CPU or the GT64260A resets • Configuration logic drive must not be released until one clock after the GT64260A reset release In the M3 FPGA, a simple sequencer provides the required sequence, as described in Table 20. Table 20. MVP Reset Sequence Time tRH Event Outputs RESET input deasserted SYSRST deasserted tRH+1 PCI reset deasserted pPCIRST deasserted sPCIRST deasserted GENRST deasserted tRH+2 CPU resets deasserted pHRESET deasserted GT64260 reset deasserted sHRESET deasserted GT_RST deasserted tRH+3 Mode resets deasserted CFGDRV deasserted CPU MODE deasserted tRH+4 Flash resets deasserted rst deasserted The general reset architecture is shown in Figure 10. RSTDRV IDE ATX PWR PWRGD PCIRST VIA RST SWITCH M3 pCPU VIAINIT sCPU GT64260 COP #0 dly pPCI sPCI COP #1 FLASH PHY Figure 10. MVP Reset Architecture 22 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Reset In operation, the ATX power supply or either of the reset pushbutton switches may initiate a system reset and cause the PIPC reset controller to drive the general reset signals (RSTDRV and PCIRST) low. The FPGA, in turn, derives the secondary reset signals and drives them at the appropriate time. 2.14.1 Service Interrupt MVP includes two debounced SRESET switches which can be pressed to assert SRESET to either CPU. In DINK this interrupts code and forces a soft-reset exception, which can reveal the address of “stuck” code, etc. MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 23 Reset 3 Configuration MVP contains several slide-switches used to configure the board, processors(s) and chipsets for the options shown in Table 21. Underlined entries are the defaults, as shipped. Since the switches operate by connecting a pulled-up signal to ground, setting a switch to “ON” is indicated as ‘0’ in the table. All switches are oriented so that “ON”=”0”=“UP”, where “UP means toward the PCI and I/O connector back panel of the ATX chassis. If the chassis is standing up with the cover off, an alternate interpretation is “ON”=”0”=”LEFT” Table 21. MVP Configuration Switches Switch SW5 SW6 SW7 SW4 SW9 No Option Default Setting Description Notes 11010 See MPC745X HW spec 2 1:5 Primary CPU PLL(0:4) 6:7 Unused 00 None 8 Bus Mode 1 0 = MPX Bus Mode 1 = 60X Bus Mode 1:5 Secondary CPU PLL(0:4) 11010 See MPC745X HW spec 6 Registered SDRAM Mode 0 0 = Normal DIMMs 1 = Registered DIMMs 2 7:8 ROM Mode 00 See Table 10 1:5 Clock Code 11110 See Table 7. 6 MMM Option 0 0 = Normal 1 = TBD 1 7 Flash Write Enable 0 0 = Flash is read/write 1 = Flash write protected 4 8 SDRANGE 0 0 = Normal 1 = Low-speed clocks 1 1 SDCLK Direction 0 0 = In 1 = Out 1 2 GT64260A Register Base 1 0 = 0x1400_0000 1 = 0xF100_0000 3 GT64260A Serial Initialize 0 0 = Serial Init Disabled 1 =Serial Init Enabled 4 reserved 0 0 5 GT64260A Arbiter Enable 1 0 = Arbiter Disabled 1 =Arbiter Enabled 6:8 GT64260A PLL Tune 000 000 = GT64260A Default 1:4 reserved 1111 None 5 reserved 6:8 GT options 0 None 000 Sensed via GT64260A MPP(26:28) 5 NOTES: 1 For experimental purposes only; not guaranteed useful. 2 PLL_CFG(0:4) is the same as [PLL_EXT+PLL_CFG(0:3)] from the MPC7455 Hardware Specification. The bit order is the same as that shown in the PLL Encoding table and can be entered directly. 3 The remaining GT64260A options are set with resistors and are not easily changable. 4 Write protected flash cannot be detected or queried with flash programming algorithms. Only the data may be read, and nothing else. 24 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Diagnostic Functions 5 Do not change or RTC/ENV will not work. 3.1 Diagnostic Functions MVP includes several features to assist in hardware/software debugging, which are discussed in the remaining sections. 3.1.1 Mictors MVP (optionally) includes a set of 5 high-density Mictor headers, connected to the processors’ 60X/MPX bus between the MPC7455 processors and the GT64260A. This allows transactions on the bus to be monitored and captured on a standard logic analyzer. Since these headers are placed in a manner which may interfere with chassis insertion, they may or may not be present on the board; refer to the configuration checklist for details. Two of the most popular analyzers are made by Agilent(HP) and Tektronics. There is no standard numbering scheme on Mictor connectors, and Agilent and Tektronics use differing numbers. There is no standard shroud, and each has a different insertion scheme. Fortunately, both use the predefined connections on the system bus in a consistent manner, so as long as the proper cable adapters and software are used, either analyzer may be used. For a variety of reasons, MVP uses the standards shown in Table 22. Table 22. MVP Mictor Definitions Uses Company Reason Mictor Numbering Scheme Tektronics Historical Mictor Shroud Agilent Tektronics Low-profile Better mechanical retention Mictor Labelling Agilent Agilent definitions The Mictor headers are grouped into logical functions. While each signal can be individually captured and examined with a proper logic analyzer setup, typically the signals are grouped into 32-bit quantities and given a label; the logic analyzer disassemblers generally prefer this approach. Thus “TS” becomes part of the capture group “STAT”. Table 23 summarizes the connections. Table 23. MVP Mictor Groups Group Definition Includes Table STAT Transfer status signals AACK, DTI, ODT, TSIZ, TT, etc. Table 24 ADDR Standard Address TS, A[4:36] Table 25 DATA Data Bus D[0:31] (or DH[0:31]) Table 26 DATA_B Data Bus Lower DL[32:63] (or DL[0:31]) Table 27 STAT_B Status Miscellaneous BR1, BG1, DBG1 Table 28 Notes 1 NOTES: 1 The typical definition is “A0:31” for the MPC74xx family processors, where A0 is the MSB. On the MPC7455 and newer processors, the MSB is still A0, but since the system operates in 32-bit-address mode by default, MVP A(4:35) are the corresponding lowest 32 address bits. MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 25 Diagnostic Functions The the remaining tables describe the connections in detail. Table 24. Mictor STAT Definition Pin Signal 3 AACK Even Clock 4 pBR Even D15 (MSB) 5 pBG Even D14 6 pDBG Even D13 7 rsvd Even D12 8 rsvd Even D11 9 DTI[0] Even D10 10 DTI[1] Even D9 11 DTI[2] Even D8 12 DTI[3] Even D7 13 rsvd Even D6 14 ODT[0] Even D5 15 ODT[1] Even D4 16 ODT[2] Even D3 17 ODT[3] Even D2 18 ODT[4] Even D1 19 ARTRY Even D0 (LSB) 36 TA Odd Clock 35 TEA Odd D15 (MSB) 34 TSIZ[0] Odd D14 33 TSIZ[1] Odd D13 32 TSIZ[2] Odd D12 31 rsvd Odd D11 30 TT[0] Odd D10 29 TT[1] Odd D9 28 TT[2] Odd D8 27 TT[3] Odd D7 26 TT[4] Odd D6 25 TBST Odd D5 24 WT Odd D4 23 A[0] Odd D3 22 A[1] Odd D2 21 A[2] Odd D1 20 A[3] Odd D0 (LSB) Table 25. Mictor ADDR Definition Pin 26 Signal 3 TS Even Clock 4 A[4] Even D15 (MSB) MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Diagnostic Functions Table 25. Mictor ADDR Definition Pin Signal 5 A[5] Even D14 6 A[6] Even D13 7 A[7] Even D12 8 A[8] Even D11 9 A[9] Even D10 10 A[10] Even D9 11 A[11] Even D8 12 A[12] Even D7 13 A[13] Even D6 14 A[14] Even D5 15 A[15] Even D4 16 A[16] Even D3 17 A[17] Even D2 18 A[18] Even D1 19 A[19] Even D0 (LSB) 36 LACLK Odd Clock 35 A[20] Odd D15 (MSB) 34 A[21] Odd D14 33 A[22] Odd D13 32 A[23] Odd D12 31 A[24] Odd D11 30 A[25] Odd D10 29 A[26] Odd D9 28 A[27] Odd D8 27 A[28] Odd D7 26 A[29] Odd D6 25 A[30] Odd D5 24 A[31] Odd D4 23 A[32] Odd D3 22 A[33] Odd D2 21 A[34] Odd D1 20 A[35] Odd D0 (LSB) Table 26. Mictor DATA Definition MOTOROLA Pin Signal 3 rsvd Even Clock 4 D[0] Even D15 (MSB) 5 D[1] Even D14 6 D[2] Even D13 7 D[3] Even D12 8 D[4] Even D11 MVP X3 Multiprocessor Evaluation System Design Workbook 27 Diagnostic Functions Table 26. Mictor DATA Definition Pin Signal 9 D[5] Even D10 10 D[6] Even D9 11 D[7] Even D8 12 D[8] Even D7 13 D[9] Even D6 14 D[10] Even D5 15 D[11] Even D4 16 D[12] Even D3 17 D[13] Even D2 18 D[14] Even D1 19 D[15] Even D0 (LSB) 36 rsvd Odd Clock 35 D[16] Odd D15 (MSB) 34 D[17] Odd D14 33 D[18] Odd D13 32 D[19] Odd D12 31 D[20] Odd D11 30 D[21] Odd D10 29 D[22] Odd D9 28 D[23] Odd D8 27 D[24] Odd D7 26 D[25] Odd D6 25 D[26] Odd D5 24 D[27] Odd D4 23 D[28] Odd D3 22 D[29] Odd D2 21 D[30] Odd D1 20 D[31] Odd D0 (LSB) Table 27. Mictor DATA_B Definition 28 Pin Signal 3 rsvd Even Clock 4 D[32] Even D15 (MSB) 5 D[33] Even D14 6 D[34] Even D13 7 D[35] Even D12 8 D[36] Even D11 9 D[37] Even D10 10 D[38] Even D9 11 D[39] Even D8 12 D[40] Even D7 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Diagnostic Functions Table 27. Mictor DATA_B Definition Pin Signal 13 D[41] Even D6 14 D[42] Even D5 15 D[43] Even D4 16 D[44] Even D3 17 D[45] Even D2 18 D[46] Even D1 19 D[47] Even D0 (LSB) 36 rsvd Odd Clock 35 D[48] Odd D15 (MSB) 34 D[49] Odd D14 33 D[50] Odd D13 32 D[51] Odd D12 31 D[52] Odd D11 30 D[53] Odd D10 29 D[54] Odd D9 28 D[55] Odd D8 27 D[56] Odd D7 26 D[57] Odd D6 25 D[58] Odd D5 24 D[59] Odd D4 23 D[60] Odd D3 22 D[61] Odd D2 21 D[62] Odd D1 20 D[63] Odd D0 (LSB) Table 28. Mictor STAT_B Definition MOTOROLA Pin Signal 3 rsvd Even Clock 4 pINT Even D15 (MSB) 5 sINT Even D14 6 pCPU_HRST Even D13 7 X01 Even D12 8 X10 Even D11 9 rsvd Even D10 10 rsvd Even D9 11 rsvd Even D8 12 rsvd Even D7 13 rsvd Even D6 14 rsvd Even D5 15 rsvd Even D4 16 rsvd Even D3 MVP X3 Multiprocessor Evaluation System Design Workbook 29 Diagnostic Functions Table 28. Mictor STAT_B Definition Pin Signal 17 rsvd Even D2 18 rsvd Even D1 19 rsvd Even D0 (LSB) 36 rsvd Odd Clock 35 F1VIS Odd D15 (MSB) 34 F1VISA Odd D14 33 F1VISB Odd D13 32 F2VIS Odd D12 31 GBL 30 3.1.2 Odd D11 rsvd Odd D10 29 sBR Odd D9 28 sBG Odd D8 27 sDBG Odd D7 26 GTBR Odd D6 25 pBR_GTBG Odd D5 24 sBR_GTDBG Odd D4 23 rsvd Odd D3 22 rsvd Odd D2 21 rsvd Odd D1 20 rsvd Odd D0 (LSB) LEDs Table 29 describes the diagnostic LEDs on the MVP motherboard. Table 29. MVP Diagnostic LEDs LED PCB Label Definition Activation Method pBEAT CPU1 Activity on pBG, stretched to >10ms. CPU #1 performs bus cycles. sBEAT CPU2 Activity on pBG, stretched to >10ms. CPU #2 performs bus cycles. VIALED VIA0 User-defined. Set VIA GPO bit 0 to ‘0’. SUSB VIA1 User-defined. Set VIA GPO bit 2 to ‘0’. GTSTAT0 GT0 User-defined. Set MPP port pin 24 to ‘0’ to activate LED. GTSTAT1 GT1 User-defined. Set MPP port pin 25 to ‘0’ to activate LED. sPCILED sPCI Activity on secondary PCI bus. Initiated traffic on sPCI bus. CLKLED CLK Clock is running. Properly set CLK options. BOOTLED ROM Access to any flash device. Access 0xFXXX_XXXX. AUXLED AUX User-defined. MMM FPGA equations. DISKLED DISK Disk activity Access to IDE disk drives. 30 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Diagnostic Functions Table 29. MVP Diagnostic LEDs LED PCB Label Definition Activation Method VSTDBY VST5 ATX power supply is plugged in (and rear-panel None (if plugged in) switch is on) VCC_HOT_3.3 VST3 ATX power supply is plugged in (and rear-panel None (if plugged in) switch is on) OVDD V2_5 VCC_2.5 > 1.5V pVCORE pVCO pVCORE > 1.5V sVCORE sVCO sVCORE > 1.5V pVCORE_FLT pCORE sVCORE_FLT sCORE Power activated. pVCORE not limited. sVCORE not limited. ENET #1 Left Speed: On when 100baseT; else 10baseT ENET #1 Right Link Status: On when link is up. ENET #2 Left Speed: On when 100baseT; else 10baseT ENET #2 Right Link Status: On when link is up. 3.1.3 Upon HRESET, or via LXT971 LED control register. Power Consumption Measurement MVP supports the ability to measure the current consumed by measuring the voltage across low-ohm resistors and calculating the corresponding current. Table 30 shows some of the power measurements possible. Table 30. MVP Power Measurement Voltage Sense Resistor Used By Measurement Method Primary CPU ICORE = V_across_R217 / 0.0031 R218 Secondary CPU ICORE = V_across_R218 / 0.0031 R25 GT64260A Core IVCC1.8 = V_across_R25 / 0.010 R235 CPU Bus IO CPU Cache IO SRAM IO FPGA IO IOVDD = V_across_R133 / 0.010 pVCORE R217 sVCORE VCC_1.8 OVDD Notes 1 The other power supplies (5V, 3.3V) can be measured through the ATX power supply. MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 31 Diagnostic Functions 4 Placement and Layout The general placement of components on the MVP motherboard is shown in Figure 11. Figure 11. MVP Placement 32 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Address Map 5 Programmers Model This section describes support information which may be useful to hardware or software designers who are using MVP. 5.1 Address Map Table 31 shows the general address map of the MVP, while Table 32 shows the specific location of ISA/PCI I/O addresses. Table 31. Global Address Map START END Definition Notes 0000_0000 1BFF_FFFF SDRAM 1 1C00_0000 1CFF_FFFF PCI 0 ISA Memory space 2 1D00_0000 1DFF_FFFF PCI 0 ISA IO space 2 1E00_0000 1EFF_FFFF PCI 1 ISA Memory space 2 1F00_0000 1FFF_FFFF PCI 1 ISA IO space 2 2000_XXXX 3FFF_FFFF SDRAM 1 F100_0000 F100_XXXX GT64260A Configuration Registers 2 FE00_0000 FEFF_FFFF DCS3 ROM space (8MB) FF00_0000 FFFF_FFFF Boot ROM space (8MB) 3, 5, 6 5, 6 NOTES: 1. Requires SDRAM control registers to be properly programmed (TBD). 2. DINK 12.4 default; may be relocated. 3. Requires software setup (CS3 registers [CS3_ADDR_LO]). 4. Only software-enabled PCI/ISA I/O devices appear in this space. 5. Devices may be reassigned using the ROMMODE switches. See Section 3. 6. Devices default to an 8MB aperture, though 16MB is available. To get the full address range of each device, the BOOT/DCS3 address range registers must be reprogrammed. The detailed address map in Table 32 assumes that the PnP devices have not been changed from the default locations. Table 32. Detailed ISA I/O Address Map Start End Mode Register 1E00_0000 --- R/W DMA Channel 0 Base/Current Address 1E00_0001 --- R/W DMA Channel 0 Base/Current Word 1E00_0002 --- R/W DMA Channel 1 Base/Current Address 1E00_0003 --- R/W DMA Channel 1 Base/Current Word 1E00_0004 --- R/W DMA Channel 2 Base/Current Address 1E00_0005 --- R/W DMA Channel 2 Base/Current Word 1E00_0006 --- R/W DMA Channel 3 Base/Current Address 1E00_0007 --- R/W DMA Channel 3 Base/Current Word 1E00_0008 --- R DMA Controller 1 Status W DMA Controller 1 Command MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook Notes 33 Address Map Table 32. Detailed ISA I/O Address Map Start End Mode 1E00_0009 --- W DMA Controller 1 Request 1E00_000A --- W DMA Controller 1 Mask 1E00_000B --- W DMA Controller 1 Mode 1E00_000C --- W DMA Controller 1 Clear Byte Pointer 1E00_000D --- W DMA Controller 1 Master Clear 1E00_000E --- W DMA Controller 1 Clear Mask 1E00_000F --- W DMA Controller 1 Write All Mask 1E00_0010 1E00_001F 1E00_0020 --- R/W PIC 1 Command 1E00_0021 --- R/W PIC 1 Command 1E00_0022 1E00_003F 1E00_0040 --- R/W Counter 0 1E00_0041 --- R/W Counter 1 1E00_0042 --- R/W Counter 2 1E00_0043 --- W 1E00_0044 1E00_005F 1E00_0060 --- R/W Keyboard Controller Data 1E00_0061 --- R/W NMI Status/Control 1E00_0062 1E00_0063 1E00_0064 --- 1E00_0065 1E00_006F 1E00_0070 Notes unassigned unassigned Timer/Counter Control unassigned 1 unassigned R/W Keyboard Controller Command --- R/W RTC/APC Index --- W --- R/W NVRAM Address 1E00_0073 --- R/W NVRAM Data 1E00_0074 1E00_0077 unassigned 1E00_0078 1E00_007F unassigned 1E00_0080 --- unassigned 1E00_0081 --- R/W DMA Memory Page 2 1E00_0082 --- R/W DMA Memory Page 3 1E00_0083 --- R/W DMA Memory Page 1 1E00_0084 FF80_0086 - DMA Reserved Page 1E00_0087 --- R/W DMA Memory Page 0 1E00_0088 --- - DMA Reserved Page 1E00_0089 --- R/W DMA Memory Page 6 1E00_008A --- R/W DMA Memory Page 7 1E00_0072 34 Register 1 unassigned 1 RTC Index (shadow) 1E00_008B --- R/W DMA Memory Page 5 1E00_008C FF80_008E - DMA Reserved Page 1E00_008F 1E00_0091 1E00_0092 --- 1E00_0093 1E00_009F unassigned R/W Port 92: System Reset unassigned MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Address Map Table 32. Detailed ISA I/O Address Map Start End Mode 1E00_00A0 --- R/W PIC 2 Command 1E00_00A1 --- R/W PIC 2 Command 1E00_00A2 1E00_00BF 1E00_00C0 --- R/W DMA Channel 4 Base/Current Address 1E00_00C1 --- R/W DMA Channel 4 Base/Current Word 1E00_00C2 1E00_00C3 1E00_00C4 --- unassigned R/W --- R/W --- R/W --- R/W --- R/W --- R/W R DMA Controller 2 Status "W DMA Controller 2 Command W DMA Controller 2 Request unassigned 1E00_00D3 --- unassigned 1E00_00D3 --- W DMA Controller 2 Mask --- W DMA Controller 2 Mode W unassigned 1E00_00D5 1E00_00D6 unassigned 1E00_00D7 1E00_00D8 --- W DMA Controller 2 Clear Byte Pointer --- W DMA Controller 2 Master Clear unassigned 1E00_00D9 1E00_00DA unassigned 1E00_00DB 1E00_00DC DMA Channel 7 Base/Current Word unassigned 1E00_00D0 1E00_00D4 DMA Channel 7 Base/Current Address unassigned 1E00_00CF 1E00_00D2 DMA Channel 6 Base/Current Word unassigned 1E00_00CD 1E00_00CE DMA Channel 6 Base/Current Address unassigned 1E00_00CB 1E00_00CC DMA Channel 5 Base/Current Word unassigned 1E00_00C9 1E00_00CA DMA Channel 5 Base/Current Address unassigned 1E00_00C7 1E00_00C8 --- W DMA Controller 2 Clear Mask 1E00_00DE --- W DMA Controller 2 Write All Mask 1E00_00DF 1E00_00FF unassigned 1E00_0100 1E00_0CF7 unassigned unassigned 1E00_00DD 1E00_0CF8 1E00_CFB R/W PCI Configuration Index Register 1E00_0CFC 1E00_CFF R/W PCI Configuration Data Register 1E00_0D00 1E00_FFFF MOTOROLA Notes unassigned 1E00_00C5 1E00_00C6 Register unassigned MVP X3 Multiprocessor Evaluation System Design Workbook 35 Memory Resources 5.2 Memory Resources The SIO has the following non-volatile RAM resources: • 256 bytes of battery-backed RAM in the PIPC (32 of which are reserved for RTC functions). • 256 bytes of EEPROM in an I2C EEROM at address 0x54. • 256 bytes of EEPROM in an I2C EEROM at address 0x57. Unlike other Motorola reference design platforms such as Yellowknife or Sandpoint, MVP does not have a large amount of storage available for environment variables, so judicious use is recommended. It is also possible to use the flash devices with careful software management. 36 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Initializing MVP 5.3 Initializing MVP A typical multiprocessing start-up sequence is shown in Figure 12: HRESET 2. Initialize BATs 3. Initialize Cache 4. Initialize 64260 5. Initialize SDRAM 6. Setup stack pointer 7. Enable IO 8. Check bus speed 9. Setup memory 0 CPUID = ? 1 4. Set Msg 2 Wait Msg 1 Enable MP Arbiter 5. Get IP from Msg 6. Get MSR from Msg 7. rfi Wait Msg 2 or timeout msg2 Send code message to CPU #2 via msg1. Startup OS in multiCPU mode. Startup OS in multiCPU mode. Figure 12. Multiprocessing Startup Sequence MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 37 Motherboard Dimensions 6 Mechanical The following sections discuss mechanical issues of the MVP board, including board layout, thermal/heatsink issues, and placement. Nothing in this section should be considered a substitute for mechanical drawings. 6.1 Motherboard Dimensions MVP is a standard 12.0 x 9.6 inch (305 x 244 cm (the specification is written in inches)) motherboard, and follows standard ATX 2.01 clearance requirements. MVP implements the standard set of mounting holes for chassis attachment, with the addition of ATX 2.01 mounting hole “F”, located near the communications port adapter as shown in Figure 13. 12.0 in “F” 8.95 in 9.6 in 6.1 in 0.9 in 3.1 in 4.9 in 11.1 in Figure 13. MVP ATX Chassis Mounting Holes. This hole is required for ATX 2.01 standards and is needed for mechanical rigidity for MVP; most standard standard chassis punchouts implement the standard support area. 6.2 Mictor Clearance If the MVP is assembled with the Mictor headers for debugging, the connectors will protrude into the ATX motherboard carrier frame. To install MVP in an ATX chassis, either the Mictors must be removed or the 38 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Mictor Clearance motherboard carrier must have holes cut into the frame for clearance. Figure 14 shows the area which must be cut to install MVP with Mictors attached. A ATX BOARD OUTLINE F G H B E D C ATX BOARD CARRIER Figure 14. MVP ATX Chassis Carrier Frame Mictor Cutout. The dimensions are shown in Table 33. Table 33. Mictor Clearance Cutout Dimensions MOTOROLA Dimension Value Units A 3.5 in B 3.5 C 1.0 D 2.0 E 2.5 F 1.5 G 2.25 H 1.40 MVP X3 Multiprocessor Evaluation System Design Workbook 39 ATX Chassis Gasket Once the cutouts have been made, an MVP with Mictor headers (with or without Tektronix shrouds) can be installed in the carrier frame and also installed in the ATX chassis (no further clearance issues arise). This does not apply when the high-profile Agilent shrouds are used (MVP supports both styles). 6.3 ATX Chassis Gasket The particular set of IO ports provided by MVP do not match any particular ATX “gasket” (the removable panel which fits between the motherboard and the chassis to provide EMI compliance. Because of this, the MVP will require a custom gasket, as shown in Figure 15. Figure 15. MVP ATX Chassis Gasket 40 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA Heat Sinks 7 Thermal Management This section discusses some of the thermal issues related to MVP. Do NOT operate MVP without the heatsinks and/or without the attached fan. 7.1 Heat Sinks MVP uses heat sinks manufactured by Chip Coolers Inc. Refer to www.chipcoolers.com for further details. 7.2 Fan Sensing In addition to the heat sink, cooling fans are attached. MVP supports standard PC-style fan-sink speed sensors. The fans connect into a tachometry sensor in the VIA PIPC. To sense the fan speed, read the corresponding register in the PIPC system monitor function. MVP does not implement fan speed control (neither on/off nor modulation). MOTOROLA MVP X3 Multiprocessor Evaluation System Design Workbook 41 Fan Sensing 8 Reference Documentation Table 34 describes reference documentation which may be useful for understanding the operation of the MVP system. Table 34. Reference Documentation Document Number/Reference MPC7455 Hardware Specification e-www.motorola.com/brdata/PDFDB/docs/MPC7455EC.pdf MPC7455 User’s Manual e-www.motorola.com/brdata/PDFDB/docs/MPC7455UM.pdf ODT e-www.motorola.com/brdata/PDFDB/docs/AN2161.pdf (also in MPC7455 hardware specification) GD64260A (Discovery) Data Sheet www.Marvell.com DINK User’s Manual and code updates http://e-www.motorola.com/webapp/sps/site/prod_summary.jsp? code=DINK32 PCI 2.1 Specification www.pcisig.com VIA 82C686B Datasheet http://www.via.com.tw/en/datasheet/datasheets.jsp# SPD Serial Presence Detect Standard www.chips.ibm.com/products/memory/spddessd/spddessd.pdf Emulations Technologies “PromJET” www.emutec.com/pjetadpt.html BCM5222 Documentation Hardware Datasheet Programming Manual http://www.broadcom.com/products/5222.html Heatsinks www.chipcoolers.com 42 MVP X3 Multiprocessor Evaluation System Design Workbook MOTOROLA HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. 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