Product specification 12-Bit 20MSPS Sampling Analog-to-Digital Converter IP Core TSMC 0.35µ 2P3M FEATURES • • • • • • • nAD1220 APPLICATIONS 2.8-3.6V power supply SINAD typ. 59dB for (fin = 5MHz) Very low power ([email protected]) Sample rate: > 20MSPS Internal Sample/Hold Differential input Low input capacitance • • • • • Imaging Test equipment Computer scanners Communications Set top boxes GENERAL DESCRIPTION The nAD1220 is a compact, high-speed, very low power 12-bit monolithic analog-todigital converter, implemented in a 0.35µm CMOS process. It has 12-bit resolution with close to 10 effective bits, and more than 10 bit dynamic range for video signals. The converter includes sample and hold. The full-scale range can be set between ±0.6V and ±1.7V using external references. It operates from a single 2.8-3.6V supply - compatible with modern digital systems. Most converters in this performance range demand at least a +5V supply. Its low distortion and high dynamic range offers the performance needed for demanding imaging, multimedia, telecommunications and instrumentation applications. The conversion rate can be increased to 40MHz while keeping SINAD higher than 50dB. An evaluation kit is available, see ordering information below. QUICK REFERENCE DATA Symbol Parameter VDD PD DNL supply voltage power dissipation differential nonlinearity differential nonlinearity integral nonlinearity integral nonlinearity conversion rate resolution INL fS N Conditions Min. Typ. Max. Unit 2.8 3.3 76 3.6 V mW LSB(10bit) LSB(12bit) LSB(10bit) LSB(12it) MHz bit Ex. references fIN=0.9991MHz fIN=0.9991MHz fIN=0.9991MHz fIN=0.9991MHz ±0.4 ±1 ±1 ±3 20 12 Table 1. Quick reference data ORDERING INFORMATION Type number Name Description Version nAD1220-CORE nAD1220-KIT CORE KIT nAD1220 hard-core; layout available in 0.35µm CMOS nAD1220 evaluation kit with the nAD1220 on board c-1 k-1 Table 2. Ordering information Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 1 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC GENERAL DESCRIPTION (Continued) The nAD1220 has a pipelined architecture - resulting in low input capacitance. Digital error correction of the 11 most significant bits ensures good linearity for input frequencies approaching Nyquist. The excellent linearity at the color subcarrier frequency makes the converter ideally suited for video. It is also well suited for demanding ultrasonic imaging and flow measurements. The nAD1220 is very compact - occupying less than 3.2mm2 of die area in a standard dual poly 0.35µm CMOS process. The fully differential architecture makes it insensitive to substrate noise. Thus it is ideal as a mixed signal ASIC macro cell. The modular architecture of the converter and the flexible external biasing scheme means that scaling in number of bits and sampling rate is easily achieved. Power consumption is roughly proportional to the number of bits and to the maximum sampling rate. Thus, nAD1220 is an excellent choice as the core of a product family of very low power high speed converters with resolutions ranging from 8 - 12 bits and sampling rates ranging from 1-40MHz. BLOCK DIAGRAM BGAP REFBUFF EXTREF BGREF BIAS1 CM BIASCELL REFBUFF REFN REFP INP INN CLOCK BIAS0 STAGE1 CLOCKDR STAGE2 STAGE3 STAGE10 STAGE_LAST (2-bit flash) DIGITAL DELAYS, ERROR CORRECTION AND OUTPUT REGISTER OR BIT<11..0> Figure 1. Block diagram nAD1220 Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 2 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC ELECTRICAL SPECIFICATIONS (At TA = 25°C, VDD = 3.3V, Sampling Rate = 20MHz, Differential input, Input frequency = 4.4995MHz with a 50% duty cycle clock unless otherwise noted ) Symbol Parameter (condition) DNL INL VOS CMRR εG SINAD SNR SFDR DP DG PSRR VFSR VCMI CINA Test Level Min. Typ. Max. Units DC Accuracy Differential Nonlinearity fIN = 0.9991 MHz VI ±0.4 ±0.6 LSB (10 bit) LSB (12bit) Integral Nonlinearity fIN = 0.9991 MHz VI No Missing Codes Midscale offset VI V ±1.0 ±3.0 Guaranteed LSB (10 bit) LSB (12bit) (12 bit) % FSR Common Mode Rejection Ratio Gain Error Dynamic Performance Signal to Noise and Distortion Ratio fIN = 5 MHz fIN = 10 MHz Signal to Noise Ratio (without harmonics) fIN = 5 MHz fIN = 10 MHz Spurious Free Dynamic Range fIN = 5 MHz fIN = 10 MHz Differential Phase Differential Gain Power Supply Rejection Ratio Analog Input Input Voltage Range (Differential) Common mode input voltage Input Capacitance (from each input to ground) Reference Voltages Negative Input Voltage Positive Input Voltage Reference input voltage range ±1 V V 55 0.3 DB % FSR VI V 55 59 54 dB dB VI V 57 60 56 dB dB VI V V V V 60 65 59 0.2 0.5 63 dB dB degrees % dB IV IV V ±0.6 1.2 ±1 1.65 1.4 VREFNO IV VREFPO IV VREFP-VREFN IV 0.6 VCM VI 1.3 Common mode output voltage (Io=-1µA) Digital Inputs VIL Logic “0” voltage VI VIH Logic “1” voltage VI 80% VDD IIL Logic “0” current (VI=VSS) VI IIH Logic “1” current (VI=VDD) VI CIND Input Capacitance V Digital Outputs VOL Logic “0” voltage (I = + 2 mA) VI VOH Logic “1” voltage (I = - 2 mA) VI 85% VDD tH Output hold time IV tD Output delay time IV 4 (table continued on next page) 1.15 2.15 1.0 1.65 ±1.7 1.9 1.7 1.8 V V pF V V V V 20% VDD ±1 ±1 µA µA pF 0.4 V V ns ns 1.8 0.1 95% VDD 6 8 12 Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 3 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC fS σAP tAP VDD IDD IDD IDD VSS AVDDDVDD1 DVDD1DVDD2 PD Switching Performance Conversion Rate Pipeline Delay (see timing diagram) Aperture jitter Aperture delay Power Supply supply voltage supply current 1) supply current (sleep mode, EXTREF "0") supply current (sleep mode, EXTREF "1") supply voltage analog power - digital power pins VI IV V V 20 TBD MSPS Clocks ps ns IV VI VI VI 2.8 3.6 30 V mA mA mA V -0.2 +0.2 V digital power - output driver power V -0.2 +0.2 V Power dissipation VI 100 mW 7.5 10 5 3.3 24 6.6 1.8 GND 79 Table 3. Electrical specifications 1) Power down ("zero") power consumption available for IP core. Test Levels Test Level I: 100% production tested at +25°C Test Level II: 100% production tested at +25°C and sample tested at specified temperatures Test Level III: Sample tested only Test Level IV: Parameter is guaranteed by design and characterization testing Test Level V: Parameter is typical value only Test Level VI: 100% production tested at +25°C. Guaranteed by design and characterization testing for industrial temterature range ABSOLUTE MAXIMUM RATINGS Supply voltages AVDD ...............................- 0.5V to +6V DVDD1 ..................- 0.5V to VDD + 0.5V DVDD2 ..................- 0.5V to VDD + 0.5V Temperatures Operating Temperature….-55°C to +95°C Storage Temperature..- 65°C to +125°C Input voltages Analog In.......... - 0.5V to AVDD + 0.5V Digital In..............- 0.5V to VDD + 0.5V REFP ................. - 0.5V to AVDD + 0.5V REFN................. - 0.5V to AVDD + 0.5V CLOCK ...............- 0.5V to VDD + 0.5V Note: Stress above one or more of the limiting values may cause permanent damage to the device. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 4 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC PIN FUNCTIONS Pin Name Description INP INN REFP REFN Differential input signal pins. Common mode voltage: 1.65V Reference pins. Bypass with 100nF capacitors close to the pins. See Application Information below. Digital input: Reference select. EXTREF=1: Internal reference powered down, use external reference EXTREF=0: Internal reference is used Digital inputs for max. sampling rate programming. BIAS1=0, BIAS0=0: Sleep mode (power save) BIAS1=0, BIAS0=1: Max. 5MHz sampling BIAS1=1, BIAS0=0: Max. 20MHz sampling BIAS1=1, BIAS0=1: Max. 30MHz sampling Clock input Common mode voltage output. Digital outputs ( MSB to LSB) Band gap reference input / output voltage, nominally 2.413V Scan inputs. Connect to ground. Analog power pins. Should be connected to VDD Digital power pins. Should be connected to VDD Power pins for output drivers. Should be connected to VDD EXTREF BIAS0, BIAS1 CLOCK CM BIT11 - BIT0 BGAP QI, S AVDD DVDD1 DVDD2 Table 4. Pin functions. REFP REFN AVDD AVDD AVDD DVDD1 DVDD1 DVDD2 VSS CLOCK VSS PIN ASSIGNMENT 11 10 9 8 7 6 5 4 3 2 1 NC 12 44 DVDD2 EXTREF 13 43 BIT0 (LSB) BGAP 14 42 BIT1 VSS 15 41 BIT2 BIAS0 16 40 BIT3 BIAS1 17 39 BIT4 CM 18 38 BIT5 VSS 19 37 BIT6 INP 20 36 BIT7 35 BIT8 34 BIT9 23 24 25 26 27 28 29 30 31 32 33 VSS VSS VSS VSS QI S BIT11 BIT10 22 VSS VSS VSS 21 44 PIN QFP VSS INN nAD1220 Figure 2. Pin assignment Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 5 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC TIMING DIAGRAM CLOCK S A M P L E N-1 S A M P L E N S A M P L E N+1 tAP 2 ns S A M n+2 P L E th 6 ns td 8 ns ANALOG INPUT Data N-1 DATA Data N Data N+1 Figure 3. Timing diagram PACKAGE OUTLINE All dimensions are in inches and paranthetically in millimeters. Figure 5. Package outline Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 6 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC DEFINITIONS Data sheet status Objective product specification Preliminary product specification Product specification This datasheet contains target specifications for product development. This datasheet contains preliminary data; supplementary data may be published from Nordic VLSI ASA later. This datasheet contains final product specifications. Limiting values Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Table 5. Definitions LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic VLSI ASA customers using or selling these products for use in such applications do so at their own risk and agree fully indemnify Nordic VLSI ASA for any damages resulting from such improper use or sale. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 7 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC APPLICATION INFORMATION References The nAD1220 has a differential analog input. The input range is determined by the voltages VP and VN applied to reference pins REFP and REFN respectively, and is equal to ±(VP-VN). Externally generated reference voltages connected to REFP and REFN should be symmetric around 1.5V. The input range can be defined between ±0.6V and ±1.5V. Internal reference buffers exists – providing reference voltages at pins REFP and REFN equal to +2.00V (VREFP) and +1.00V (VREFN). These can be connected to REFP and REFN by connecting pin EXTREF to VSS. The references should be bypassed as close to the converter pins as possible using 100nF capacitors in parallel with smaller capacitors (e.g. 220pF) (to ground). Series resistance from IP reference pins to pad window should be in the range 1 - 5 ohms. Analog input The input of the nAD1220 can be configured in various ways - dependent upon whether a single ended or differential, AC- or DC-coupled input is wanted. AC-coupled input is most conveniently implemented using a transformer with a center tapped secondary winding. The center tap is connected to the CM-node, as shown in Figure 1. In order to obtain low distortion, it is important that the selected transformer does not exhibit core saturation at full-scale. Excellent results are obtained with the Mini Circuits T1-6T or T1-1T. Proper termination of the input is important for input signal purity. A small capacitor (typ. 68pF) across the inputs attenuates kickbacknoise from the sample and hold. A small capacitor (1nF) between CM and ground has also been proven to be advantageous. 68pF Vin ADC Mini Circuits T1-6T INP 51Ω CM INN Figure 6. AC coupled input using transformer If a DC-coupled single ended input is wanted, a solution based on operational amplifiers - as shown in Figure 7, is usually preferred. The AD826 is suggested for low distortion and video bandwidth. Lower cost operational amplifiers may be used if the demands are less strict. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 8 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC 51Ω 470Ω AD826 Input offset Video in 470Ω ADC 51Ω 100Ω AD826 INP 15pF 100Ω INN 51Ω 51Ω 470Ω AD826 470Ω 470Ω Figure 7. DC-coupled single ended to differential conversion (power supplies and bypassing not shown) Clock The nAD1220 accepts a CMOS logic level clock at the CLK-node. The duty cycle of the clock should be close to 50%. Consecutive pipeline stages in the ADC are clocked in antiphase. With a 50% duty cycle, every stage has the same time for settling. If the duty cycle deviates from 50%, every second stage has a shorter time for settling - thus it operates less accurately, potentially causing degradation of SNR. In order to preserve accuracy at high input frequency, it is important that the clock has low jitter and steep edges. Rise/fall times should be kept shorter than 2ns whenever possible. Overshoot should be avoided. Low jitter is especially important when converting high frequency input signals. Jitter causes the noise floor to rise proportionally to input signal frequency. Jitter may be caused by crosstalk on the PCB. It is therefore recommended that the clock trace on the PCB is made as short as possible. Digital outputs The digital output data appears in offset binary code at CMOS logic levels. Full-scale negative input results in output code 000...0. Full-scale positive input results in output code 111...1. Output data are available 7.5 clock cycles after the data are sampled. The analog input is sampled one aperture delay (tAP) after the high to low clock transition. Output data should be sampled on the low to high clock transition, as shown in the timing diagram. Output data are invalid for the first 20 clock cycles after wake-up from power down mode. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 9 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC PCB layout and decoupling A well designed PCB is necessary to get good spectral purity from any high performance ADC. A multilayer PCB with a solid ground plane is recommended for optimum performance. If the system has a split analog and digital ground plane, it is recommended that all ground pins on the ADC are connected to the analog ground plane. It is our experience that this gives the best performance. The power supply pins should be bypassed using 100nF surface mounted capacitors as close to the package pins as possible. Analog and digital supply pins should be separately filtered. One should make sure that the analog and digital supply voltages are equal. Dynamic testing Careful testing using high quality instrumentation is necessary to achieve accurate test results on high speed A/D-converters. It is important that the clock source and signal source has low jitter. A spectrally pure, low noise RF signal generator - such as the HP8662A or HP 8644B is recommended for the test signal. Low pass filtering or band pass filtering of the input signal is usually necessary to obtain the required spectral purity (SFDR > 75dB). The clock signal can be obtained from either a crystal oscillator or a low-jitter pulse generator. Alternatively, a low-jitter RF-generator can be used as a clock source. At Nordic VLSI, the Marconi Instruments 2041A is used. The sinewave clock must then be applied to an ultra high speed comparator (e.g. AD9696) and a TTL to CMOS level shifter (e.g. 74LV04) before application to the converter. The most consistent results are obtained if the clock signal is phase locked to the input signal. Phase locking allows testing without windowing of output data. A logic analyzer with deep memory - such as the HP16500-series, is recommended for test data acquisition. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 10 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC YOUR NOTES Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 11 of 12 February 27th 2001 Product Specification nAD1220 12-Bit 20MSPS Sampling ADC DESIGN CENTER Main office: Nordic VLSI ASA Vestre Rosten 81 N-7075 TILLER NORWAY Telephone: +47 72898900 Telefax: +47 72898989 Branch office: Nordic VLSI ASA Drammensveien 165 P.O.Box 436 Skøyen, N-0212 OSLO NORWAY Telephone: +47 22511050 Telefax: +47 22511099 E-mail: For further information regarding datasheets, please send mail to [email protected] World Wide Web/Internet: Visit our site at http://www.nvlsi.no Product specification. Revision Date: February 27th, 2001 All rights reserved ®. Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. Company and product names referred to in this datasheet belong to their respective copyright/trademark holders. Main office: Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway - Phone +4772898900 - Fax +4772898989 Branch office: Nordic VLSI ASA - P.O.Box 436 Skøyen, N-0212 Oslo, Norway - Phone +4722511050 - Fax +4722511099 Revision: 3.3 Page 12 of 12 February 27th 2001