FAIRCHILD SPT7936SCT

SPT7936
12-BIT, 28 MSPS SAMPLING A/D CONVERTER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
3.0-3.6 V Power Supply
Typical SINAD: 60 dB for (fIN = 10 MHz)
Low power: (260 mW @3.3 V)
Sample Rate: 28 MSPS
Internal Sample/Hold
Differential Input
Sleep Mode (Power Down)
Imaging
Test Equipment
Computer Scanners
Communications
Set-Top Boxes
performance needed for demanding imaging, multimedia,
telecommunications and instrumentation applications.
GENERAL DESCRIPTION
The SPT7936 is a compact, high-speed, low power 12-bit
monolithic analog-to-digital converter, implemented in a
0.5 µm CMOS process. The converter includes sample and
hold. The full scale range can be set between ±0.6 V and ±1.2
V using external references. It operates from a single 3.0-3.6
V supply-compatible with modern digital systems. Most converters in this performance range demand at least a +5 V
supply. Its low distortion and high dynamic range offers the
The SPT7936 has a pipelined architecture - resulting in low
input capacitance. Digital error correction of the 11 most
significant bits ensures good linearity for input frequencies
approaching Nyquist.
The device is available in a 44L TQFP package over the
commercial temperature range of 0 to +70 °C.
BLOCK DIAGRAM
BGAP
Ref Buff
Ext Ref
Bias 0 Bias 1
BGREF
CM
BIAS CELL
Ref Buff
VREF+
VREFVIN+
THA
Stage 1
Stage 2
Stage 3
Stage 10
VIN-
Clock
Clock
Driver
Digital Delays, Error Correction and Output Register
OR
Bit <11...0)
Stage_Last
(2-Bit Flash)
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
VDD1 ................................................................... - 0.3 V to +6 V
VDD2 ................................................................... - 0.3 V to +6 V
Temperatures
Operating Temperature ................................. 0 to +70 °C
Storage Temperature.. ............................. - 65 to +125 °C
Input Voltages
Analog In ....................................... - 0.3 V to VDD + 0.3 V
Digital In ........................................ - 0.3 V to VDD + 0.3 V
REFP .................................................... - 0.3 V to VDD + 0.3 V
REFN .................................................... - 0.3 V to VDD + 0.3 V
CLOCK.......................................... - 0.3 V to VDD + 0.3 V
Note:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA = TMIN-TMAX, VDD1 =VDD2 = 3.3 V, Sampling Rate = 28 MSPS, Differential input signal, 50% duty cycle clock with 2.5 ns rise and fall times, unless otherwise
specified.
PARAMETERS
TEST
CONDITIONS
DC Accuracy
Differential Nonlinearity (DNL)
Integral Nonlinearity
Common Mode Rejection Ratio (CMRR)
No Missing Codes
Analog Input
Input Voltage Range (differential) VFSR
Common Mode Input Voltage VCMI
Input Capacitance CIN
(From Each Input to Ground)
Midscale Offset VOS
Gain Error
Input Bandwidth
TEST
LEVEL
MIN
VI
VI
V
IV
IV
V
VIN+=VIN–=VCM
Large Signal
Reference Voltages
Internal Reference Voltage on Pin 10 (VREFNI)
Internal Reference Voltage on Pin 11 (VREFPI)
Internal Reference Voltage Drift
Negative Input Voltage (VREF-)
Positive Input Voltage (VREF+)
Reference Input Voltage Range (VREF+ — VREF-)
Common Mode Output Voltage (VCM)
Bandgap Output Voltage (VBGAP)
0.6
1.2
MAX
UNITS
±0.5
±1.3
54
Guaranteed
±1.0
±3.0
LSB
LSB
dB
±1
1.5
2
±1.2
1.6
V
V
pF
±2
-0.2
150
V
V
V
VI
VI
IV
VI
VI
IV
VI
VI
SPT7936
TYP
0.95
1.95
1.0
2.0
0.9
1.9
0.6
1.45
2.365
1.0
2.0
1.0
1.50
2.415
%
%
MHz
1.05
2.05
100
1.3
2.3
1.2
1.55
2.465
V
V
ppm/°C
V
V
V
V
V
Dynamic Performance
Effective Number of Bits
Signal to Noise and Distortion Ratio (SINAD)
Signal to Noise Ratio (SNR)
Without Harmonics
Total Harmonic Distortion (THD)
fIN = 5.0 MHz
fIN = 10.0 MHz
fIN = 5.0 MHz
fIN = 10.0 MHz
fIN = 5.0 MHz
fIN = 10.0 MHz
fIN = 5.0 MHz
fIN = 10.0 MHz
V
VI
V
VI
V
VI
V
VI
9.2
57
59
10.0
9.7
62
60
64
63
–66
–64
–61
Bits
Bits
dB
dB
dB
dB
dB
dB
SPT7936
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ELECTRICAL SPECIFICATIONS
TA = TMIN-TMAX, VDD1 =VDD2 = 3.3 V, Sampling Rate = 28 MSPS, Differential input signal, 50% duty cycle clock with 2.5 ns rise and fall times, unless otherwise
specified.
TEST
CONDITIONS
TEST
LEVEL
fIN = 5.0 MHz
fIN = 10.0 MHz
Differential Phase (DP)
Differential Gain (DG)
V
VI
V
V
Digital Inputs
Logic 0 Voltage (VIL)
Logic 1 Voltage (VIH)
Logic 0 Current (IIL)
Logic 1 Current (IIH)
Input Capacitance (CIND)
VI
VI
VI
VI
V
PARAMETERS
Dynamic Performance
Spurious Free Dynamic Range (SFDR)
Digital Outputs
Logic 0 Voltage (VOL)
Logic 1 Voltage (VOH)
Output Hold Time (tH)
Output Delay Time (tD)
(VI=VSS)
(VI=VDD)
(I = +2 mA)
(I = -2 mA)
VI
VI
V
V
Switching Performance
Maximum Conversion Rate (fS)
Minimum Conversion Rate
Pipeline Delay (See Timing Diagram)
Aperture Jitter σAP
Aperture Delay tAP
Power Supply
Supply Voltage VDD
Supply Current IDD
ext ref
int ref
Power Dissipation PD
ext ref
int ref
Sleep Mode Current
ext ref
int ref
Sleep Mode Power Dissipation
ext ref
int ref
Power Supply Rejection Ratio (PSRR)
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions: All parameters having min/
max specifications are guaranteed. The Test
Level column indicates the specific device testing actually performed during production and
Quality Assurance inspection. Any blank section in the data column indicates that the specification is not tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
MIN
62
SPT7936
TYP
MAX
67
64
0.08
0.27
UNITS
dB
dB
degrees
%
20% VDD
80% VDD
±1
±1
µA
µA
pF
0.4
V
V
ns
ns
1.8
85% VDD
VI
IV
IV
V
V
28
1
IV
3.0
0.2
90% VDD
5
8
MSPS
MSPS
Clocks
ps
ns
8.0
10
2
3.3
3.6
V
VI
VI
75
79
87
91
mA
mA
VI
VI
248
260
288
300
mW
mW
VI
VI
8
11
9
12
mA
mA
VI
VI
V
25
36
52
29
40
mW
mW
dB
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = +25 °C. Parameter is
guaranteed over specified temperature range.
SPT7936
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TYPICAL PERFORMANCE CHARACTERISTICS
THD, SNR, SINAD vs Sample Rate
THD, SNR, SINAD vs Input Frequency
80
80
70
70
fIN = 10 MHz
THD
THD, SNR, SINAD (dB)
THD, SNR, SINAD (dB)
THD
60
SNR
SINAD
50
40
60
SNR
50
SNR
SINAD
THD
SINAD
40
30
30
20
20
100
101
10 0
102
Input Frequency (MHz)
101
102
Sample Rate (MSPS)
Note: Bias1 and Bias2 currents optimized for each sample rate.
THD, SNR, SINAD vs Temperature
THD, SNR, SINAD vs Clock Duty Cycle
70
80
fIN = 10 MHz
70
THD
SNR
66
THD, SNR, SINAD (dB)
THD, SNR, SINAD (dB)
68
THD
64
SNR
62
SINAD
60
60
SNR
SINAD
THD
SINAD
50
40
30
58
20
56
0
25
Temperature (°C)
45
70
46
47
48
49
50
51
52
53
54
55
Clock Duty Cycle
Power Dissipation vs Sample Rate
(Internal Reference)
350
Power Dissipation (mW)
300
250
200
150
100
50
Sleep Mode
0
10 0
101
102
Sample Rate (MSPS)
Note: Bias1 and Bias2 optimized for each sample rate.
SPT7936
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Figure 1 - Timing Diagram
Clock
S
A
M
P
L
E
S
A
M N+1
P
L
E
N
S
tAP A N+2
M
P
L
E
tD
tH
Analog Input
Data
N-1
Data
Data
N
Data
N+1
pling rate, this device is ideal for very low power applications
in the range of 1 to 28 MSPS.
GENERAL DESCRIPTION
The SPT7936 is a low power, 12-bit, 28 MSPS ADC. It has a
pipelined architecture and incorporates digital error correction of the 11 most significant bits. This error correction
ensures good linearity performance for input frequencies up
to Nyquist. The inputs are fully differential, making the device
insensitive to system-level noise. This device can also be
used in a single-ended mode. (See analog input section.)
With the power dissipation roughly proportional to the sam-
TYPICAL INTERFACE CIRCUIT
The SPT7936 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7936 in
normal circuit operation. The following sections provide a description of the functions and outline critical performance criteria to
consider for achieving the optimal device performance.
Figure 2 - Typical Interface Circuit
+1.0 V
+2.0 V
Clock Input +3.3 V
(3.3 V Logic)
+3.3 V
4.7 µF
+
+
4.7 µF
+
4.7 µF
.01µF
.01
µF
.01 µF
CLK
GND
GND
VDD
2
VDD
2
VDD2
VDD
1
VDD
1
VDD
1
N/C
VREF-
1 kΩ
1 kΩ
VREF+
.01µF
+3.3 V
VDD
1 kΩ
2
ExtRef
D0
BGAP
D1
GND
D2
(LSB)
ExtRef
Bias0
D3
SPT7936
Bias1
Bias1
D10
D11
OR
GND
GND
D9
GND
D8
GND
GND
D7
VIN-
GND
.01µF
D6
VIN+
GND
Mini-Circuit
T1-6T
68 pF
D5
GND
GND
50 Ω
D4
CM
GND
VIN
Interfacing Logic
.01 µF
Bias0
(MSB)
NOTES:
1) Place the ferrite bead (*) as close to the device as possible.
2) Place 0.01 microfarad capacitors as close to the device as possible.
3) All capacitors are surface-mount unless otherwise specified.
FB
4) All input pins (references, analog input, clock input) must be
(*)
protected. (See absolute maximum rating.)
5) Set Bias1 and Bias0 for maximum sample rate.
Bias1Bias0
0
0
Sleep mode
0
1
Max. 5 MHz sampling
1
0
Max. 20 MHz sampling
1
1
Max. 28 MHz sampling
6) Use internal or external reference. Do not connect external voltage reference when using internal references.
7) All VDD and VDD must be connected together. Do not leave any pin unconnected.
1
2
8) All GND must be connected together. Do not leave any pin unconnected.
+3.3 V
SPT7936
5
8/1/00
ANALOG INPUT
REFERENCES
The SPT7936 has a differential input that should have a
common mode voltage of +1.5 V. The input voltage range is
determined by the reference voltages which may be generated internally or applied externally.
The SPT7936 can use either an internal or external voltage
reference. When the digital input EXTREF is high, the external reference is used. When EXTREF is low, the internal
reference is used.
The input of the SPT7936 can be configured in various ways
depending on if a single-ended or differential, AC- or DCcoupled input is desired.
INTERNAL REFERENCE
The internal references are set at +1.0 V and +2.0 V. When
the internal reference is used, the full-scale range of the
analog input is set at ±1.0 V differential. Do not connect
external references when the internal reference is used.
The AC coupled input is most conveniently implemented
using a transformer with a center tapped secondary winding.
The center tap is connected to the VCM pin as shown in
figure 2. To obtain low distortion, it is important that the
selected transformer does not exhibit core saturation at the
full-scale voltage. Excellent results are obtained with the Mini
Circuits T1-6T or T1-1T. Proper termination of the input is
important for input signal purity. A small capacitor across the
inputs attenuates kickback noise from the internal sample
and hold.
EXTERNAL REFERENCE
When external references are used, the voltages applied to
the VREF+ and VREF- pins determine the input voltage range
which is equal to ±(VREF+ - VREF-). Externally generated
reference voltages must be connected to these pins and
should be symmetric about the common mode voltage. (See
figure 2, Typical Interface Circuit.)
Figure 3 illustrates a solution (based on operational amplifiers) that can be used if a a DC coupled single-ended input is
desired. The selection criteria of the buffer op-amps is as
follows:
- Open loop gain >75 dB
- Gain bandwidth product >50 MHz
- Total harmonic distortion ≤-75 dB
- Signal to Noise ratio >75 dB
COMMON MODE OUTPUT VOLTAGE
REFERENCE CIRCUIT
The SPT7936 has an on-board common mode voltage reference circuit (VCM). It is set at +1.5 V and can drive loads of up
to 20 µA. This circuit is commonly used to drive the center tap
of the RF transformer in fully differential applications. For
single-ended applications, this output can be used to provide
the level shifting required for the single-to-differential converter conversion circuit.
Figure 3 - DC-Coupled Single-Ended-to-Differential
Conversion (Power Supplies are Not
Shown)
R3
_
VCM
R3
The best AC performance is achieved when the bias currents
are optimized for the selected sample rate. Two digital input
pins are provided to control the optimum internal bias currents. Table I shows the settings for Bias 0 and Bias 1 at
selected frequencies.
R
ADC
+
R
51 Ω
_
Input
Voltage
(±0.5 V)
BIAS CIRCUITS
(R3)/2
R2
+
VIN+
15 pF
R2
VIN–
51 Ω
R
R
Table I - Frequencies for Biases 0 and 1
51 Ω
+
_
Typical Power
R
Bias 1 Bias 0
0
0
0
1
1
0
1
1
POWER SUPPLIES AND GROUNDING
The SPT7936 is operated from a single power supply in the
range of 3.0 to 3.6 volts. Nominal operation is suggested to
be 3.3 volts. All power supply pins should be bypassed as
close to the package as possible. The analog and digital
grounds should be connected together with a ferrite bead as
shown in the typical interface circuit and as close to the ADC
as possible.
Dissipation
Description
Ext. Ref.
Int. Ref.
Sleep mode (power save)* 25 mW
36 mW
≤5 MHz sampling
61 mW
73 mW
≤20 MHz sampling
172 mW
184 mW
≤28 MHz sampling
248 mW
260 mW
*Clock = 28 MHz
SPT7936
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8/1/00
8 clock cycles after the data is sampled. The input signal is
sampled on the high to low transition of the input clock. Output
data should be latched on the low to high clock transition as
shown in figure 1, the Timing Diagram. The output data is
invalid for the first 20 clock cycles after the device is powered up.
CLOCK
The SPT7936 accepts a +3.3 V CMOS logic level at the CLK
input. The duty cycle of the clock should be kept as close to
50% as possible. Because consecutive stages in the ADC are
clocked in opposite phase to each other, a non-50% duty
cycle reduces the settling time available for every other stage,
thus potentially causing a degradation of dynamic performance.
OUT OF RANGE OUTPUT (OR)
The digital output OR goes to a logic high to indicate that the
analog input is out of range.
For optimal performance at high input frequencies, the clock
should have low jitter and fast edges. The rise/fall times
should be kept shorter than 3 ns. Overshoot and undershoot
should be avoided. Clock jitter causes the noise floor to rise
proportional to the input frequency. Because jitter can be
caused by crosstalk on the PC board, it is recommended that
the clock trace be kept as short as possible and standard
transmission line practices be followed.
EVALUATION BOARD
The EB7936 Evaluation Board is available to aid designers in
demonstrating the full performance capability of the SPT7936.
The board includes an on-board clock driver, adjustable
voltage references, adjustable bias current circuits, single-todifferential input buffers with adjustable levels, a single-todifferential transformer (1:1), digital output buffers and 3.3/5 V
adjustable logic outputs. An application note (AN7936) is also
available which describes the operation of the evaluation
board and provides an example of the recommended power
and ground layout and signal routing. Contact the factory for
price and availability.
DIGITAL OUTPUTS
The digital output data appears in an offset binary code at
3.3 V CMOS logic levels. A negative full scale input results in
an all zeros output code (000…0). A positive full scale input
results in an all 1’s code (111…1). The output data is available
PACKAGE OUTLINE
44L TQFP
A
B
INCHES
C
D
Index
Pin 1
E
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.472 Typ
12.00 Typ
B
0.394 Typ
10.00 Typ
C
0.394 Typ
10.00 Typ
D
0.472 Typ
12.00 Typ
E
0.031 Typ
F
0.012
0.018
0.300
0.45
G
0.053
0.057
1.35
1.45
0.80 Typ
H
0.002
0.006
0.05
0.15
I
0.018
0.030
0.450
0.750
J
0.039 Typ
1.00 Typ
K
0-7°
0-7°
F
G
K
I
H
J
SPT7936
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PIN ASSIGNMENTS
EXTREF
D7
D8
D9
37
36
35
34
40
D6
41
39
42
38
D2
D3
43
D5
D1
44
D4
VDD2
D0 (LSB)
GND
1
33
D10
CLK
2
32
D11
Digital input: Reference select.
EXTREF=1: Use external reference. Internal reference powered
down. EXTREF=0: Internal reference is used.
8
26
GND
Digital inputs for maximum sampling rate programming.
BIAS1=0, BIAS0=0: Sleep mode (power save)
BIAS1=0, BIAS0=1: Max. 5 MHz sampling
BIAS1=1, BIAS0=0: Max. 20 MHz sampling
(Default by internal pull up/pull down)
BIAS1=1, BIAS0=1: Max. 28 MHz sampling
VDD1
9
25
GND
CLOCK
Clock input
VREF–
10
24
GND
CM
VREF+
11
23
GND
Common mode voltage output.
(1.5 V typ)
GND
3
31
OR
VDD2
4
30
GND
VDD2
5
29
GND
VDD2
6
28
GND
VDD1
7
27
GND
VDD1
BIAS0, BIAS1
22
21
20
19
18
17
16
15
14
13
12
GND
VIN+
VIN–
GND
CM
Bias1
Bias0
GND
EXTREF
BGAP
N/C
PIN FUNCTIONS
Name
Function
VIN+, VIN-
Differential input signal pins.
VREF+, VREF-
Reference input pins. Bypass with
100 nF capacitors close to the pins.
See Application Information.
D11-DØ
Digital outputs ( MSB to LSB)
OR
Out-of-Range digital output. OR=1
indicates input out of range
VDD1
VDD2
Analog power supply
Digital power supply
GND
Analog Ground
N/C
No Connect Pins. Recommended
to connect to analog ground.
BGAP
Internal Bandgap Reference
Output: Bypass to ground for
normal operation.
ORDERING INFORMATION
PART NUMBER
SPT7936SCT
TEMPERATURE RANGE
PACKAGE TYPE
0 to +70 °C
44L TQFP
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO
IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF
ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF
OTHERS.
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FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body, or (b) support or sustain life,
and whose failure to perform, when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected
to result in a significant injury to the user.
2. A critical component is any component of a life support device or system
whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
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© Copyright 2002 Fairchild Semiconductor Corporation
SPT7936
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