PCI 9030 Design Notes Rev. 1.0 December 2001 9222 A. Product Status Product PCI9030 PCI9030 Revision PCI9030-AA60PI PCI9030-AA60BI Description Released 176-pin PQFP Product Released 180-pin mBGA Product Samples Mar 2000 Mar 2000 Production April 2000 April 2000 B. Documentation Status Document Data Book Revision 1.2 Description PCI 9030 Data Book Date December 2001 C. Design Notes 1. Power Management Interface Specification version support Design Issue: The PCI 9030 Data Book indicates compliance with the PCI Power Management Interface Specification revision 1.1, however the PMC register description is compliant with revision 1.0. The PCI 9030 can support either revision. The only differences between these revisions, with respect to PCI 9030 support, are the Version bits [2:0] value (programmable by EEPROM), and the descriptions for bits [8:6, 4] for which the values are read-only and return a value of 0 regardless of revision. The Version bits value (001b or 010b), which has no effect on PCI 9030 operation, is used by software to determine PMC register format. Recommendation: PMC register descriptions for revisions 1.0 and 1.1 are listed below. If revision 1.1 rather than revision 1.0 is to be supported, program the serial EEPROM with the Version value (010b) to overwrite the PMC register default value, by changing the 32-bit value at EEPROM offset 18h from 48014801h to 48024801h. Document number: 9030-SIL-DN-P0-1.0 -1- Register 10-27. (PMC; PCI:42h) Power Management Capabilities (PCI Power Mgmt. r1.0) Bit 2:0 3 4 5 8:6 9 10 15:11 Description Version. The value 001 indicates compliance with PCI Power Mgmt. r1.0. PCI Clock Required for PME# Signal. When set to 1, indicates a function relies on PCI clock presence for PME# operation. The PCI 9030 does not require the PCI clock for PME#, so this bit should set to 0. Auxiliary Power Source. Because the PCI 9030 does not support PME# while in a D3cold state, this bit is always set to 0. Not Supported. Device-Specific Initialization (DSI). When set to 1, the PCI 9030 requires special initialization following a transition to a D0 uninitialized state before a generic class device driver is able to use it. Reserved. D1_Support. When set to 1, the PCI 9030 supports the D1 power state. Not Supported. D2_Support. When set to 1, the PCI 9030 supports the D2 power state. Not Supported. PME Support. Indicates power states in which the PCI 9030 may assert PME#. Values: XXXX1 = PME# can be asserted from D0 XXXXX = The PCI 9030 does not support the D1 power state XXXXX = The PCI 9030 does not support the D2 power state X1XXX = PME# can be asserted from D3hot XXXXX = PME# cannot be asserted from D3cold Read Write Value after Reset Yes Serial EEPROM 001 Yes Serial EEPROM 0 Yes No 0 Yes Serial EEPROM 0 Yes No 000 Yes No 0 Yes No 0 Yes [14:11]: Serial EEPROM 01001 [15]: No Register 10-27. (PMC; PCI:42h) Power Management Capabilities (PCI Power Mgmt. r1.1) Bit 2:0 3 4 5 8:6 9 10 15:11 Description Version. The default value 001 indicates compliance with PCI Power Mgmt. r1.0. To instead indicate PMC register format compliance with Revision 1.1, this value should be set to 010. PCI Clock Required for PME# Signal. When set to 1, indicates a function relies on PCI clock presence for PME# operation. The PCI 9030 does not require the PCI clock for PME#, so this bit should set to 0. Reserved. Device-Specific Initialization (DSI). When set to 1, the PCI 9030 requires special initialization following a transition to a D0 uninitialized state before a generic class device driver is able to use it. Aux_Current. Supported by way of the PMDATA register per PCI Power Mgmt. r1.1. D1_Support. When set to 1, the PCI 9030 supports the D1 power state. Not Supported. D2_Support. When set to 1, the PCI 9030 supports the D2 power state. Not Supported. PME Support. Indicates power states in which the PCI 9030 may assert PME#. Values: XXXX1 = PME# can be asserted from D0 XXXXX = The PCI 9030 does not support the D1 power state XXXXX = The PCI 9030 does not support the D2 power state X1XXX = PME# can be asserted from D3hot XXXXX = PME# cannot be asserted from D3cold Read Write Value after Reset Yes Serial EEPROM 001 Yes Serial EEPROM 0 Yes No 0 Yes Serial EEPROM 0 Yes No 000 Yes No 0 Yes No 0 Yes [14:11]: Serial EEPROM 01001 [15]: No Copyright ã 2001 by PLX Technology, Inc. All rights reserved. PLX is a trademark of PLX Technology, Inc. which may be registered in some jurisdictions. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology reserves the right, without notice, to make changes in product design or specification. Document number: 9030-SIL-DN-P0-1.0 -2-