HD74AC112/HD74ACT112 Dual JK Negative Edge-Triggered Flip-Flop ADE-205-364 (Z) 1st. Edition Sep. 2000 Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse. Features • Outputs Source/Sink 24 mA • HD74ACT112 has TTL-Compatible Inputs Pin Arrangement CP1 1 16 VCC K1 2 15 CD1 J1 3 14 CD2 SD1 4 13 CP2 Q1 5 12 K2 Q1 6 11 J2 Q2 7 10 SD2 GND 8 9 Q2 (Top view) HD74AC112/HD74ACT112 Logic Symbol 4 10 SD1 3 J1 1 CP1 2 K1 Q1 5 11 13 CD1 15 Q1 6 12 SD2 J2 K2 VCC = Pin16 GND = Pin8 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active Low) Direct Set Inputs (Active Low) Outputs Asynchronous Inputs: Low input to SD sets Q to High level Low input to CD sets Q to Low level Clear and Set are independent of clock Simultaneous Low on CD and SD makes both Q and Q High 2 9 Q2 7 CP2 Pin Names J1, J2, K1, K2 CP1, CP2 C D1, CD2 S D1, SD2 Q1, Q2, Q1, Q 2 Q2 CD2 14 HD74AC112/HD74ACT112 Truth Table Inputs Outputs @tn @tn + 1 J K Q L L Qn L H L H L H H H Qn tn tn + 1 H L : : : : Bit time before clock pulse. Bit time after clock pulse. High Voltage Level Low Voltage Level Logic Diagram SD Q CD J #CP CP Q K # CP CP CP CP # # CP # CP CP CP CP DC Characteristics (unless otherwise specified) Item Symbol Max Unit Condition Maximum quiescent supply current I CC 40 µA VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case Maximum quiescent supply current I CC 4.0 µA VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C Maximum additional ICC/input (HD74ACT112) I CCT 1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V Ta = Worst case 3 HD74AC112/HD74ACT112 AC Characteristics: HD74AC112 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum clock f max 3.3 125 — — 100 — MHz 5.0 150 — — 125 — 3.3 1.0 11.0 14.0 1.0 15.0 5.0 1.0 8.5 11.0 1.0 12.0 3.3 1.0 11.0 14.0 1.0 15.0 5.0 1.0 8.5 11.0 1.0 12.0 3.3 1.0 9.5 12.5 1.0 13.5 5.0 1.0 7.0 9.5 1.0 10.5 3.3 1.0 11.5 14.5 1.0 15.5 5.0 1.0 9.0 11.0 1.0 12.5 frequency Propagation delay t PLH CP to Q or Q Propagation delay t PHL CP to Q or Q Propagation delay t PLH CD, SD to Q or Q Propagation delay t PHL CD, SD to Q or Q Note: ns 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements: HD74AC112 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Setup time t su 3.3 3.0 5.5 6.0 ns 5.0 2.0 4.5 4.5 3.3 –1.5 0.0 0.0 5.0 –0.5 0.0 0.0 3.3 2.0 5.5 7.0 5.0 2.0 4.5 5.0 3.3 1.5 3.5 3.5 5.0 1.0 3.0 3.0 J or K to CP Hold time th CP to J or K Pulse width tw CP or CD or SD Recovery time CD or SD to CP Note: 4 t rec 1. Voltage Range 3.3 is 3.3 V ± 0.3 V Voltage Range 5.0 is 5.0 V ± 0.5 V HD74AC112/HD74ACT112 AC Characteristics: HD74ACT112 Ta = +25°C CL = 50 pF Ta = –40°C to +85°C CL = 50 pF Item Symbol VCC (V)*1 Min Typ Max Min Max Unit Maximum clock frequency f max 5.0 100 — — 80 — MHz Propagation delay CP to Q or Q t PLH 5.0 1.0 10.5 13.0 1.0 14.0 ns Propagation delay CP to Q or Q t PHL 5.0 1.0 10.5 13.0 1.0 14.0 Propagation delay CD, SD to Q or Q t PLH 5.0 1.0 8.0 10.0 1.0 11.0 Propagation delay CD, SD to Q or Q t PHL 5.0 1.0 10.5 12.5 1.0 13.5 Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V AC Operating Requirements: HD74ACT112 Ta = –40°C to +85°C CL = 50 pF Ta = +25°C CL = 50 pF Item Symbol VCC (V)*1 Typ Guaranteed Minimum Unit Setup time J or K to CP t su 5.0 2.5 7.0 8.0 ns Hold time CP to J or K th 5.0 0.0 1.5 1.5 Pulse width CP or CD or SD tw 5.0 4.5 7.0 8.0 Recovery time CD , SD to CP t rec 5.0 –2.5 3.0 3.0 Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V Capacitance Item Symbol Typ Unit Condition Input capacitance CIN 4.5 pF VCC = 5.5 V Power dissipation capacitance CPD 35.0 pF VCC = 5.0 V 5 HD74AC112/HD74ACT112 Package Dimensions Unit: mm 19.20 20.00 Max 6.30 9 1 7.40 Max 16 8 1.3 0.48 ± 0.10 7.62 2.54 Min 5.06 Max 2.54 ± 0.25 0.51 Min 1.11 Max + 0.13 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Mass (reference value) DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 9 1 8 1.27 *0.42 ± 0.08 0.40 ± 0.06 0.10 ± 0.10 0.80 Max *0.22 ± 0.05 0.20 ± 0.04 2.20 Max 5.5 16 0.20 7.80 +– 0.30 1.15 0° – 8° 0.70 ± 0.20 0.15 0.12 M *Dimension including the plating thickness Base material dimension 6 Hitachi Code JEDEC EIAJ Mass (reference value) FP-16DA — Conforms 0.24 g HD74AC112/HD74ACT112 Unit: mm 9.9 10.3 Max 9 1 8 *0.42 ± 0.08 0.40 ± 0.06 *0.22 ± 0.03 0.20 ± 0.03 0.635 Max + 0.11 1.27 0.14 – 0.04 1.75 Max 3.95 16 + 0.10 6.10 – 0.30 1.08 0° – 8° 0.67 0.60 +– 0.20 0.15 0.25 M Hitachi Code JEDEC EIAJ Mass (reference value) *Dimension including the plating thickness Base material dimension FP-16DN Conforms Conforms 0.15 g Unit: mm 4.40 5.00 5.30 Max 16 9 1 8 0.65 1.10 Max 0.65 Max 0.10 *Dimension including the plating thickness Base material dimension 6.40 ± 0.20 0.07 +0.03 –0.04 0.20 ± 0.06 1.0 0.13 M *0.17 ± 0.05 0.15 ± 0.04 0.08 *0.22 +– 0.07 0° – 8° 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Mass (reference value) TTP-16DA — — 0.05 g 7 HD74AC112/HD74ACT112 Cautions 1. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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