IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS FEATURES: – – – – – – – – – IDT74ALVC162836 DESCRIPTION: 0.5 MICRON CMOS Technology Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range VCC = 2.5V ± 0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Available in SSOP, TSSOP, and TVSOP packages This 20-bit universal bus driver is built using advanced dual metal CMOS technology. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVC162836 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive ±12mA at the designated threshold levels. Drive Features for ALVC162836: – Light Balanced Output Drivers: ±12mA – Minimal switching noise APPLICATIONS: • SDRAM Modules • PC Motherboards • Workstations FUNCTIONAL BLOCK DIAGRAM OE CLK LE A1 1 56 29 55 1D C1 2 Y1 CLK TO 19 OTHER CHANNELS JULY 2001 INDUSTRIAL TEMPERATURE RANGE 1 c 1999 Integrated Device Technology, Inc. DSC-4900/3 IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS (1) ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Symbol VTERM(2) Description Terminal Voltage with Respect to GND Max. – 0.5 to + 4.6 Unit V – 0.5 to VCC + 0.5 V °C OE 1 56 CLK VTERM(3) Terminal Voltage with Respect to GND Y1 2 55 A1 TSTG Storage Temperature – 65 to + 150 Y2 3 54 A2 – 50 to + 50 mA 4 53 GND IOUT IIK DC Output Current GND ± 50 mA Y3 5 52 A3 Y4 6 51 A4 VCC 7 – 50 ±100 mA mA 50 V CC Y5 8 49 A5 Y6 9 48 A6 Y7 10 47 A7 GND 11 46 GND Y8 12 45 A8 Y9 13 14 Y 11 15 44 SO56-1 SO56-2 43 SO56-3 42 A9 Y 10 Y 12 16 41 A 12 Y 13 17 40 A 13 GND 18 39 GND Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND IOK ICC ISS NEW16link NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. A 10 A 11 CAPACITANCE (TA = +25oC, f = 1.0MHz) Symbol CIN Parameter(1) Input Capacitance Conditions Min. Typ. VIN = 0V 3.3 5 6 pF 7 9 pF 7 9 pF Y 14 19 38 A 14 COUT Output Capacitance VOUT = 0V — Y 15 20 37 A 15 CI/O I/O Port Capacitance VIN = 0V — Y 16 21 36 A 16 VCC 22 35 V CC Y 17 23 34 A 17 Y 18 24 33 A 18 GND 25 32 GND Y 19 26 31 A 19 Y 20 27 30 A 20 29 LE NC 28 FUNCTION TABLE (1) Inputs PIN DESCRIPTION Pin Names Description OE 3-State Output Enable Inputs (Active LOW) CLK Register Input Clock LE Latch Enable (Active LOW) Ax Data Inputs Yx 3-State Outputs NC No Internal Connection 1998 Integrated Device Technology, Inc. Max. Unit NOTE: 1. As applicable to the device type. SSOP/ TSSOP/ TVSOP TOP VIEW c INDUSTRIAL TEMPERATURE RANGE Outputs OE LE CLK Ax Yx H X X X Z L L X L L L L X H H L H ↑ L L L H ↑ H L H H X H Y0 L H L X Y0 NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High-Impedance ↑= LOW-to-HIGH Transition Y0 = Output level before the indicated steady-state input conditions were established. 2 DSC-123456 IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = – 40°C to +85°C Symbol VIH Parameter Input HIGH Voltage Level VIL Input LOW Voltage Level Test Conditions VCC = 2.3V to 2.7V Min. 1.7 Typ.(1) — Max. — VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Unit V V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ± 10 µA IOZL (3-State Output pins) VO = GND — — ± 10 µA VIK Clamp Diode Voltage VCC = 2.3V, IIN = – 18mA — – 0.7 – 1.2 V VH Input Hysteresis VCC = 3.3V — 100 — mV ICCL ICCH ICCZ ∆ICC Quiescent Power Supply Current VCC = 3.6V VIN = GND or VCC — 0.1 40 µA Quiescent Power Supply Current Variation One input at VCC − 0.6V, other inputs at VCC or GND — — 750 µA NEW16link NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. OUTPUT DRIVE CHARACTERISTICS Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V to 3.6V Test Conditions(1) IOH = – 0.1mA VCC = 2.3V VCC = 2.7V VOL Output LOW Voltage Min. VCC – 0.2 Max. — IOH = – 4mA 1.9 — IOH = – 6mA 1.7 — IOH = – 4mA 2.2 — IOH = – 8mA 2 — VCC = 3.0V IOH = – 6mA 2.4 — IOH = – 12mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 4mA — 0.4 IOL = 6mA — 0.55 IOL = 4mA — 0.4 IOL = 8mA — 0.6 IOL = 6mA — 0.55 IOL = 12mA — 0.8 VCC = 2.7V VCC = 3.0V Unit V V NEW16link NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. 3 IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE OPERATING CHARACTERISTICS, TA= 25°C Symbol CPD Parameter Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Typical 31 Typical 36 Unit 7 11 pF Test Conditions CL = 0pF, f = 10Mhz pF SWITCHING CHARACTERISTICS (1) VCC = 2.5V ± 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tW Parameter Propagation Delay Ax to Yx Propagation Delay LE to Yx Propagation Delay CLK to Yx Output Enable Time OE to Yx Output Disable Time OE to Yx Pulse Duration, LE LOW VCC = 2.7V VCC = 3.3V ± 0.3V Min. 150 Max. — Min. 150 Max. — Min. 150 Max. — Unit MHz 1 4.4 — 4.6 1.2 4 ns 1.1 5.8 — 6.1 1.4 5.1 ns 1 5.2 — 5.5 1.9 4.5 ns 1.1 6.4 — 6.5 1.2 5.5 ns 1 4.7 — 5.2 1.7 5.1 ns 3.3 — 3.3 — 3.3 — ns tW Pulse Duration, CLK HIGH or LOW 3.3 — 3.3 — 3.3 — ns tSU Setup Time, data before CLK↑ 1.4 — 1.7 — 1.5 — ns tSU Setup Time, data before LE ↑, CLK HIGH 1.2 — 1.6 — 1.3 — ns tSU Setup Time, data before LE ↑, CLK LOW 1.4 — 1.5 — 1.2 — ns tH Hold Time, data after CLK↑ 0.7 — 0.7 — 0.7 — ns tH Hold Time, data after LE ↑, CLK HIGH or LOW 1.1 — 1.1 — 1.1 — ns Output Skew(2) — — — — — 500 ps tSK(o) NOTES: 1. See test circuits and waveforms. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. SWITCHING CHARACTERISTICS FROM 0°C TO 65°C, CL = 5pF VCC = 3.3V ± 0.15V Symbol tPLH tPHL Parameter Min. 1.9 Propagation Delay CLK to Yx 4 Max. 4.5 Unit ns IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V 6 6 2 x Vcc Unit V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF V IH VT 0V SAM E PH AS E IN PU T TR AN SITION t PLH tPHL t PLH tPHL VOH VT V OL O U TPU T V IH VT 0V O PPOS ITE PH ASE IN PU T TR AN SITION NEW16link ALVC Link TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES V LOAD V CC 500 Ω (1, 2) V IN C O N TR O L IN PU T GND tPZL V OUT Pulse G enerator D .U .T. O U TPU T SW ITCH N O R M ALLY CLO SE D LO W t PZH O U TPU T SW ITCH N O R M ALLY OP EN H IGH 500 Ω RT CL DEFINITIONS: ALVC Link CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. V LOAD/2 V LOAD/2 VT V OL + V LZ V OL t PHZ V OH V OH - V HZ VT 0V 0V SET-UP, HOLD, AND RELEASE TIMES D ATA IN PU T Switch VLOAD t SU V IH VT 0V V IH VT 0V V IH VT 0V V IH VT 0V tH TIM IN G IN PU T GND ASYN C H RO N OU S C O N TR O L Open SYN C H RO N OU S C O N TR O L NEW16link TSK 0V NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. SWITCH POSITION Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests t PLZ V IH VT ALVC Link NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns. OUTPUT SKEW - D ISABLE EN ABLE O pen t R EM t SU tH (x) ALVC Link V IH IN PU T t PLH1 VT 0V t PHL1 PULSE WIDTH LO W -H IG H -LO W PU LSE V OH O U TPU T 1 t SK (x) VT V OL t SK (x) tW V OH H IGH -LO W -H IG H PU LSE VT V OL O U TPU T 2 t PLH2 VT VT ALVC Link t PHL2 t SK (x) = t PLH2 - t PLH1 or t PHL2 - tP HL1 ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.. 5 IDT74ALVC162836 3.3V CMOS 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION ID T XX X XX X XX X XX Bus-H old Fam ily D evice Type Package ALVC Tem p. R ange CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA PF Shrink S m all O utline Package (S O 56-1) Thin Shrink Sm all O utline Package (SO 56-2) Thin Very Sm all O utline Package (SO 56-3) 836 20-Bit U niversal Bus D river w ith 3 -State O utputs 162 D ouble-D ensity w ith R e sistors, ±12m A Blank N o Bus-H old 74 –40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 6 for Tech Support: [email protected] (408) 654-6459