IDT IDT74ALVCF162835APF

IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
IDT74ALVCF162835A
DESCRIPTION:
FEATURES:
This 18-bit universal bus driver is built using advanced dual metal CMOS
technology. Data flow from A to Y is controlled by the output-enable (OE)
input. The device operates in the transparent mode when the latch-enable
(LE) input is high. The A data is latched if the clock (CLK) input is held at
a high or low logic level. If LE is low, the A data is stored in the latch flip-flop
on the low-to-high transition of CLK. When OE is high, the outputs are in the
high-impedance state.
The ALVCF162835A has series resistors in the device output structure
which will reduce switching noise in 128MB and 256MB SDRAM modules.
Designed with a drive capability of ±18mA, the ALVCF162835A is a midway drive between the ALVC162835 (±12mA) and ALVC16835 (±24mA).
The ALVCF162835A is a faster version of the ALVCF162835 or
ALVC162835. It is suitable for PC133 applications and particularly SDRAM
Modules clocked at 133 MHz.
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
µ W typ. static)
• CMOS power levels (0.4µ
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP and TVSOP packages
DRIVE FEATURES:
• Balanced Output Drivers: ±18mA
• Low switching noise
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONAL BLOCK DIAGRAM
OE
CLK
LE
A1
27
30
28
54
1D
3
C1
Y1
CLK
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC-4920/3
IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
VTERM(2)
Max
Unit
Terminal Voltage with Respect to GND
–0.5 to +4.6
V
NC
1
56
GND
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
NC
2
55
NC
TSTG
Storage Temperature
–65 to +150
°C
Y1
3
54
A1
–50 to +50
mA
±50
mA
IOUT
DC Output Current
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
GND
4
53
GND
Y2
5
52
A2
IOK
Continuous Clamp Current, VO < 0
–50
mA
Y3
6
51
A3
mA
7
50
V CC
Continuous Current through each
VCC or GND
±100
V CC
ICC
ISS
Y4
8
49
A4
Y5
9
48
A5
Y6
10
47
A6
GND
11
46
GND
Y7
12
45
A7
Y8
13
44
A8
Y9
14
43
A9
Y 10
15
42
A 10
Y 11
16
41
A 11
Y 12
17
40
A 12
Symbol
Conditions
Min.
Typ.
Max.
Unit
GND
18
39
GND
CIN
Input Capacitance
VIN = 0V
4
5
6
pF
Y 13
19
38
A 13
COUT
Output Capacitance
VOUT = 0V
—
7
9
pF
COUT
I/O Port Capacitance
VIN = 0V
—
7
9
pF
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Y 14
20
37
A 14
Y 15
21
36
A 15
V CC
22
35
V CC
Y 16
23
34
A 16
Y 17
24
33
A 17
GND
25
32
GND
Y 18
26
31
A 18
OE
OE
27
30
CLK
H
LE
28
29
GND
L
L
NOTE:
1. As applicable to the device type.
FUNCTION TABLE(1)
Inputs
TSSOP/ TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
Description
OE
3-State Output Enable Inputs (Active LOW)
CLK
Register Input Clock
LE
Latch Enable (Transparent HIGH)
Ax
Data Inputs
Yx
3-State Outputs
Parameter(1)
LE
Outputs
CLK
Ax
Yx
X
X
X
Z
H
X
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
L
L
H
X
Y0
L
L
L
X
Y0
(2)
(3)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
2. Output level before indicated steady-state input conditions were established, provided that CLK is HIGH before LE went LOW.
3. Output level before the indicated steady-state input conditions were established.
2
IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
IIH
Input HIGH Current
VCC = 3.6V
VI = VCC
—
—
±5
µA
IIL
Input LOW Current
VCC = 3.6V
VI = GND
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = VCC
—
—
±10
µA
IOZL
(3-State Output pins)
VO = GND
—
—
±10
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
∆ICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
0.1
—
40
mV
µA
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
Test Conditions(1)
Parameter
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC = 2.3V
VCC = 2.7V
VOL
Output LOW Voltage
Min.
Max.
Unit
VCC – 0.2
—
V
IOH = – 6mA
1.9
—
IOH = – 8mA
1.7
—
IOH = – 6mA
2.2
—
IOH = – 12mA
2
—
VCC = 3V
IOH = – 8mA
2.4
—
IOH = – 18mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA
—
0.4
IOL = 8mA
—
0.55
IOL = 6mA
—
0.4
IOL = 12mA
—
0.6
IOL = 8mA
—
0.55
IOL = 18mA
—
0.8
VCC = 2.7V
VCC = 3V
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance Outputs enabled
CPD
Power Dissipation Capacitance Outputs disabled
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Test Conditions
Typical
Typical
Unit
CL = 0pF, f = 10Mhz
30
35
pF
12.5
14
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
Symbol
Parameter
fCLOCK
tPLH
Propagation Delay
tPHL
Ax to Yx
tPLH
Propagation Delay
tPHL
LE to Yx
tPLH
Propagation Delay
tPHL
CLK to Yx
tPZH
Output Enable Time
VCC = 2.7V
Min.
Max.
Min.
150
—
1
4
1.3
VCC = 3.3V ± 0.3V
Max.
Min.
Max.
Unit
150
—
—
4.6
150
—
MHz
1
3.5
ns
5.5
—
5.4
1.3
4.6
ns
1.4
5.9
—
5.6
1.4
3.5
ns
1.4
5.9
—
6
1.1
5
ns
1
4.7
—
4.6
1.3
4.2
ns
tPZL
OE to Yx
tPHZ
Output Disable Time
tPLZ
OE to Yx
tW
Pulse Duration, LE HIGH
3.3
—
3.3
—
3.3
—
ns
tW
Pulse Duration, CLK HIGH or LOW
3.3
—
3.3
—
3.3
—
ns
tSU
Set-up Time, data before CLK↑
1.8
—
1.5
—
1
—
ns
tSU
Set-up Time, data before LE↓, CLK HIGH
1.9
—
1.6
—
1.5
—
ns
tSU
Set-up Time, data before LE↓, CLK LOW
1.3
—
1.1
—
1
—
ns
tH
Hold Time, data after CLK↑
0.6
—
0.6
—
0.6
—
ns
tH
Hold Time, data after LE↓, CLK HIGH or LOW
1.4
—
1.7
—
1.4
—
ns
Output Skew(2)
—
—
—
—
—
500
ps
tSK(O)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS FROM 0°C TO 65°C, CL = 50pF
VCC = 3.3V ± 0.15V
Symbol
tPLH
tPHL
Parameter
Propagation Delay
CLK to xYx
4
Min.
Max.
Unit
1.8
3.5
ns
IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
Symbol
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
VCC(2)= 2.5V±0.2V
Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
tPLH
tPHL
tPLH
tPHL
OUTPUT
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
ALVC Link
Propagation Delay
VLOAD
VCC
Open
500Ω
(1, 2)
VIN
CONTROL
INPUT
VOUT
Pulse
Generator
DISABLE
ENABLE
GND
D.U.T.
tPZL
OUTPUT
SWITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
500Ω
RT
CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test
Switch
Open Drain
Disable Low
Enable Low
TIMING
INPUT
VLOAD
ASYNCHRONOUS
CONTROL
Open
tPHZ
VOH
VOH - VHZ
0V
VT
0V
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
All Other Tests
VLOAD/2
VOL + VLZ
VOL
ALVC Link
DATA
INPUT
GND
VLOAD/2
VT
Enable and Disable Times
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
Disable High
Enable High
tPLZ
VIH
VT
0V
SYNCHRONOUS
CONTROL
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
tH
tREM
tSU
tH
ALVC Link
INPUT
OUTPUT 1
VIH
VT
0V
tPHL1
tPLH1
tSK (x)
tSK (x)
OUTPUT 2
tPLH2
Set-up, Hold, and Release Times
VOH
VT
VOL
LOW-HIGH-LOW
PULSE
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
tW
VT
ALVC Link
Pulse Width
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
VT
ALVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCF162835A
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
ALVC X
XX
Bus-Hold
Temp. Range
XXX
Family
XXX
XX
Device Type Package
PA
PAG
PF
PFG
Thin Shrink Small Outline Package
TSSOP - Green
Thin Very Small Outline Package
TVSOP - Green
835A
18-Bit Universal Bus Driver with 3-State Outputs
F162
Double-Density with Resistors, ±18mA
Blank No Bus-hold
74
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6
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