7c147: 12/4/89 Revision: Thursday, November 11, 1993 CY7C147 4K x 1 Static RAM D Features D Automatic powerĆdown when deseĆ lected D D CMOS for optimum speed/power D D D Capable of withstanding greater than 2001V electrostatic discharge Functional Description The CY7C147 is a highĆperformance CMOS static RAMs organized as 4096 words by 1 bit. Easy memory expansion is provided by an active LOW chip enable (CE) and threeĆstate drivers. The CY7C147 has an automatic powerĆdown feature, reducing the power consumption by 80% when deselected . Writingtothedeviceisaccomplishedwhen the chip select (CE) and write enable High speed Ċ 25 ns Low active power Ċ 440 mW (commercial) Ċ 605 mW (military) Low standby power Ċ 55 mW TTLĆcompatible inputs and outputs Logic Block Diagram (WE) inputs are both LOW. Data on the input pin (DI) is written into the memory location specified on the address pins (A0 through A11). Readingthedeviceisaccomplished bytakĆ ingthechipenable(CE)LOWwhile(WE) remains HIGH. Under these conditions, the contents of the location specified on the address pins will appear on the data output (DO) pin. The output pin remains in a highĆimpeĆ dance state when chip enable is HIGH, or write enable (WE) is LOW. Pin Configuration DIP Top View DI INPUT BUFFER A2 A3 A6 SENSE AMP A1 1 18 VCC A1 2 17 A6 A2 3 16 A7 A3 4 15 A8 A4 5 14 A9 6 13 A10 7 12 A11 WE 8 11 DI GND 9 10 CE A5 ROW DECODER A0 A0 64 x 64 ARRAY DO DO A7 C147Ć2 CE COLUMN DECODER POWER DOWN WE A4 A5 A8 A A 9 10 A11 C147Ć1 Selection Guide Maximum Access Time (ns) ( ) Commercial Military Maximum Operating p g Current (mA) ( ) Commercial Military Maximum Standbyy Current (mA) ( ) Commercial Military Cypress Semiconductor Corporation D 3901 North First Street 7C147-25 25 90 15 D 7C147-35 35 35 80 110 10 10 7C147-45 45 45 80 110 10 10 San Jose D CA 95134 D 408-943-2600 December 1985 - Revised November 1992 7c147: 12/4/89 Revision: Thursday, November 11, 1993 CY7C147 Maximum Ratings $CB>CB C@@4<B 8<B= $CB>CBA !$+ ; 'B0B82 8A270@64 *=:B064 * >4@ " !K'(K "4B7=3 !0B27K)> C@@4<B ; 1=D4 E7827 B74 CA45C: :854 ;0G 14 8;>08@43 =@ CA4@ 6C834:8<4A <=B B4AB43 'B=@064 (4;>4@0BC@4 _ B= _ ;184<B (4;>4@0BC@4 E8B7 %=E4@ >>:843 _ B= _ Operating Range 'C>>:G *=:B064 B= @=C<3 %=B4<B80: %8< B= %8< * B= * *=:B064 >>:843 B= $CB>CBA 8< 867 - 'B0B4 * B= * <>CB *=:B064 * B= * Electrical Characteristics Ambient Range =;;4@280: "8:8B0@G./ Temperature VCC _ B= _ * I _ B= _ * I $D4@ B74 $>4@0B8<6 &0<64./ 7C147-25 Parameter Description Test Conditions Min. * "8< $ ; * "8< $! ; *$ $CB>CB 867 *=:B064 *$! $CB>CB !=E *=:B064 * *! <>CB 867 *=:B064 <>CB !=E *=:B064 , <>CB !=03 C@@4<B # * * $- $CB>CB !409064 C@@4<B # *$ * $CB>CB 8A01:43 $' $CB>CB '7=@B 8@2C8B C@@4<B./ * "0F *$)( # * $>4@0B8<6 > 6 ' 'C>>:G : C@@4<B B * "0F $)( ; =;: ' CB=;0B82 ./ % %=E4@K=E< C@@4<B B "0F * * =;: 7C147-35, 45 Max. Min. Unit Max. * * * * m m ; ; "8: "8: ; ./ Capacitance Parameter # $)( Description <>CB 0>028B0<24 $CB>CB 0>028B0<24 Test Conditions ( _ 5 "H * * Notes: ( 8A B74 8<AB0<B =< 20A4 B4;>4@0BC@4 '44 B74 :0AB >064 =5 B78A A>4285820B8=< 5=@ @=C> AC16@=C> B4AB8<6 8<5=@;0B8=< C@0B8=< =5 B74 A7=@B 28@2C8B A7=C:3 <=B 4F2443 A42=<3A Max. Unit > > >C::KC> @4A8AB=@ B= * =< B74 8<>CB 8A @4?C8@43 B= 944> B74 34K D824 34A4:42B43 3C@8<6 * >=E4@KC> =B74@E8A4 ' E8:: 4F2443 D0:C4A 68D4< (4AB43 8<8B80::G 0<3 05B4@ 0<G 34A86< =@ >@=24AA 270<64A B70B ;0G 05K 542B B74A4 >0@0;4B4@A 7c147: 12/4/89 Revision: Thursday, November 11, 1993 CY7C147 AC Test Loads and Waveforms R1 329W 5V OUTPUT R2 255W 30 pF INCLUDING JIG AND SCOPE THÉVENIN EQUIVALENT 125W OUTPUT ALL INPUT PULSES 90% 90% 10% 10% < 5 ns 3.0V 5 pF INCLUDING JIG AND SCOPE (a) Equivalent to: R1 329W 5V OUTPUT R2 255W GND < 5 ns C147Ć4 C147Ć3 (b) 1.90V Switching Characteristics Over the Operating Range[6] 7C147-25 Parameter Description Min. Max. 7C147-35 Min. Max. 7C147-45 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tLZCE CE LOW to Low Z 25 [7] 35 25 3 CE HIGH to High Z tPU CE LOW to PowerĆUp tPD CE HIGH to PowerĆDown 35 5 25 5 0 45 35 20 5 0 ns ns 30 0 20 ns ns 45 30 20 ns 5 5 [7, 8] tHZCE 45 ns ns 20 ns WRITE CYCLE[9] tWC Write Cycle Time 25 35 45 ns tSCE CE LOW to Write End 25 35 45 ns tAW Address SetĆUp to Write End 25 35 45 ns tHA Address Hold from Write End 0 0 0 ns tSA Address SetĆUp to Write Start 0 0 0 ns tPWE WE Pulse Width 15 20 25 ns tSD Data SetĆUp to Write End 15 20 25 ns tHD Data Hold from Write End 0 10 10 ns 0 0 0 ns tLZWE tHZWE WE HIGH to Low Z WE LOW to High Z [7] [7, 8] 15 Notes: 6. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30ĆpF load capacitance. 7. At any given temperature and voltage condition, tHZ is less than tLZ for all devices. 8. tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 9. 3 20 25 ns The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data inĆ put setĆup and hold timing should be referenced to the rising edge of the signal that terminates the write. 7c147: 12/4/89 Revision: Thursday, November 11, 1993 CY7C147 Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS DATA OUT tOHA PREVIOUS DATA VALID tAA DATA VALID C147Ć5 Read Cycle No. 2[10, 12] tRC CE tACE DATA OUT tLZCE HIGH IMPEDANCE VCC SUPPLY CURRENT tHZCE DATA VALID HIGH IMPEDANCE tPD tPU ICC ISB 50% 50% C147Ć6 Write Cycle No. 1 (WE Controlled)[9] tWC ADDRESS tSCE CE tSA tAW WE tSD DATAIN VALID DATA IN tHZWE DATA OUT tHA tPWE DATA UNDEFINED tHD tLZWE HIGH IMPEDANCE C147Ć7 Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected, CE = VIL. 12. 4 Address valid prior to or coincident with CE transition LOW. 7c147: 12/4/89 Revision: Thursday, November 11, 1993 CY7C147 Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[9, 13] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tHD tSD DATAIN VALID DATA IN tHZWE HIGH IMPEDANCE DATA UNDEFINED DATA OUT C147Ć8 Notes: 13. If CE goes HIGH simultaneously with WE HIGH, the output reĆ mains in a highĆimpedance state. NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 SB 1.2 NORMALIZED I CC, I ICC 1.0 0.8 VIN = 5.0V TA = 25_C 0.6 0.4 ICC 1.0 0.8 0.6 0.4 VCC = 5.0V VIN = 5.0V 0.2 0.2 ISB ISB 0.0 4.0 4.5 5.0 5.5 0.0 -55 6.0 1.6 1.3 1.4 NORMALIZED tAA NORMALIZED tAA 1.4 1.2 TA = 25_C 1.0 5.0 5.5 SUPPLY VOLTAGE (V) 100 80 VCC = 5.0V 60 TA = 25_C 40 20 0 0.0 1.2 1.0 VCC = 5.0V 6.0 0.6 -55 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 0.8 0.9 4.5 120 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 0.8 4.0 125 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE AMBIENT TEMPERATURE (_C) SUPPLY VOLTAGE (V) 1.1 25 OUTPUT SINK CURRENT (mA) NORMALIZED I CC, I SB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics 160 140 120 100 80 VCC = 5.0V 60 TA = 25_C 40 20 0 25 125 AMBIENT TEMPERATURE (_C) 5 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) 4.0 7c147: 12/4/89 Revision: Thursday, November 11, 1993 CY7C147 Typical DC and AC Characteristics (continued) TYPICAL POWERĆON CURRENT vs. SUPPLY VOLTAGE (7C148) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING W CS PULLĆUP AA 1K 2.0 (ns) TA = 25_C RESISTOR TO VCC 1.5 ISB 1.0 1.4 25.0 1.3 20.0 15.0 10.0 0.5 VCC = 4.5V TA = 25_C 5.0 0.0 0.0 1.0 2.0 3.0 4.0 NORMALIZED ICC vs. CYCLE TIME 30.0 NORMALIZED I CC 2.5 DELTA t NORMALIZED I PO 3.0 5.0 SUPPLY VOLTAGE (V) 0.0 VCC = 5.0V TA = 25_C VIN = 0.5V 1.2 1.1 1.0 0.9 0.8 0 200 400 600 800 1000 10 0 CAPACITANCE (pF) Ordering Information Speed (ns) 25 35 45 Ordering Code CY7C147-25PC CY7C147-35PC CY7C147-35DMB CY7C147-45PC CY7C147-45DMB Package Name P3 P3 D4 P3 D4 Package Type 18ĆLead(300ĆMil)MoldedDIP 18ĆLead(300ĆMil)MoldedDIP 18ĆLead (300ĆMil) CerDIP 18ĆLead(300ĆMil)MoldedDIP 18ĆLead (300ĆMil) CerDIP Operating Range Commercial Commercial Military Commercial Military MILITARY SPECIFICATIONS Group A Subgroup Testing Switching Characteristics DC Characteristics Parameters VOH VOL VIH VIL Max. IIX IOZ ICC ISB Parameters Subgroups Subgroups READ CYCLE 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 tRC tAA tOHA tACE 7,8,9,10,11 7,8,9,10,11 7,8,9,10,11 7,8,9,10,11 WRITE CYCLE tWC 7,8,9,10,11 tSCE 7,8,9,10,11 tAW 7,8,9,10,11 tHA 7,8,9,10,11 tSA 7,8,9,10,11 tPWE 7,8,9,10,11 tSD 7,8,9,10,11 tHD 7,8,9,10,11 Document #: 38Ć00030ĆD 6 20 30 40 CYCLE FREQUENCY (MHz) 50 7c147: 12/4/89 Revision: Thursday, November 11, 1993 CY7C147 Package Diagrams 18ĆLead (300ĆMil) CerDIP D4 MIL-STD-1835 D-8 Config. A 18ĆLead (300ĆMil) Molded DIP P3 E Cypress Semiconductor Corporation, 1992. The information contained herein is subject to change without notice. Cypress Semiconductor Corporatio n assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor Corporation product. Nor does it convey or imply any license under pa tent or other rights. Cypress SemiconĆ 7 ductor does not authorize its products for use as critical components in lifeĆsupport systems where a malfunction or failure of the product may reason ably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in lifeĆsupport systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.