CY7C128A 2K x 8 Static RAM Features Functional Description • Automatic power-down when deselected The CY7C128A is a high-performance CMOS static RAM organized as 2048 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), and active LOW Output Enable (OE) and tri-state drivers. The CY7C128A has an automatic power-down feature, reducing the power consumption by 83% when deselected. • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 660 mW (commercial) Writing to the device is accomplished when the Chip Enable (CE) and Write Enable (WE) inputs are both LOW. • Low standby power — 110 mW (20 ns) Data on the eight I/O pins (I/O0 through I/O7) is written into the memory location specified on the address pins (A0 through A10). • TTL-compatible inputs and outputs • Capable of withstanding greater than 2001V electrostatic discharge • Available in Pb-free and non Pb-free 24-pin Molded SOJ, non Pb-free 24-pin (300-Mil) Molded DIP Reading the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the eight I/O pins. The I/O pins remain in high-impedance state when Chip Enable (CE) or Output Enable (OE) is HIGH or Write Enable (WE) is LOW. The CY7C128A utilizes a die coat to insure alpha immunity. Pin Configurations Logic Block Diagram DIP/SOJ Top View I/O0 INPUT BUFFER A6 A5 A4 I/O2 SENSE AMPS A8 A7 I/O1 ROW DECODER A10 A9 128 x 16 x 8 ARRAY I/O3 VCC A8 A9 WE OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 C128A–2 I/O6 POWER DOWN COLUMN DECODER 1 24 23 2 22 3 4 21 5 20 6 19 7C128A 18 7 17 8 9 16 10 15 11 14 12 13 I/O4 I/O5 CE WE A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND I/O7 OE A3 A2 A1 A0 Cypress Semiconductor Corporation Document #: 38-05028 Rev. *A C128A–1 • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 CY7C128A Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) -15 15 120 40 -20 20 120 20 -35 35 120 20 -45 45 120 20 Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage to Ground Potential (Pin 28 to Pin 14) ........................................... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... –0.5V to +7.0V Range Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% DC Input Voltage............................................ –3.0V to +7.0V Electrical Characteristics Over the Operating Range[2] -15 Parameter Description Test Conditions Min. -20 Max. 2.4 Min. -35, -45 Max. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC 2.2 VCC VIL Input LOW Voltage[3] –0.5 0.8 –0.5 IIX Input Leakage Current GND < VI < VCC –10 +10 IOZ Output Leakage Current GND < VI < VCC Output Disabled –10 +10 ICC VCC Operating Supply Current VCC = Max. IOUT = 0 mA 120 ISB1 Automatic CE Power-Down Current Max. VCC, CE > VIH, Min. Duty Cycle = 100% ISB2 Automatic CE Power-Down Current Max. VCC, CE1 >VCC –0.3V, VIN > VCC–0.3V or VIN < 0.3V 0.4 Min. Max. 2.4 0.4 Unit V 0.4 V 2.2 VCC V 0.8 –0.5 0.8 V –10 +10 –10 +10 µA –10 +10 –10 +10 µA 120 120 mA 40 40 20 mA 40 20 20 mA Notes: 1. TA is the “instant on” case temperature. 2. See the last page of this specification for Group A subgroup testing information. 3. VIL (min.) = –3.0V for pulse durations less than 30 ns. Document #: 38-05028 Rev. *A Page 2 of 9 CY7C128A Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF AC Test Loads and Waveforms R1 481Ω 5V R1 481Ω 5V OUTPUT ALL INPUT PULSES 3.0V 10% GND R2 255 Ω 30 pF INCLUDING JIG AND SCOPE R2 255 Ω 5 pF INCLUDING JIG AND SCOPE (a) 90% 10% 90% OUTPUT ≤ 5 ns ≤ 5 ns C128A–5 (b) Equivalent to: C128A–4 THÉVENIN EQUIVALENT 167Ω OUTPUT 1.73V Switching Characteristics Over the Operating Range[2, 5] -15 Parameter Description Min. -20 Max. Min. -35 Max. Min. -45 Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[6] tLZCE CE LOW to Low 15 Z[7] 5 tHZCE CE HIGH to High CE LOW to Power-Up tPD CE HIGH to Power-Down 35 20 5 15 5 5 5 8 0 20 3 12 8 15 15 20 ns ns ns 15 0 20 ns ns 5 0 ns ns 45 15 5 0 15 5 3 8 ns 45 35 10 3 8 45 35 20 10 3 Z[6, 7] tPU 20 15 ns ns 25 ns [8] WRITE CYCLE tWC Write Cycle Time 15 20 25 40 ns tSCE CE LOW to Write End 12 15 25 30 ns tAW Address Set-Up to Write End 12 15 25 30 ns tHA Address Hold from Write End 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 ns tPWE WE Pulse Width 12 15 20 20 ns tSD Data Set-Up to Write End 10 10 15 15 ns tHD Data Hold from Write End 0 0 0 0 ns Z[6] tHZWE WE LOW to High tLZWE WE HIGH to Low Z 7 5 7 5 10 5 15 5 ns ns Notes: 4. Tested initially and after any design or process changes that may affect these parameters 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05028 Rev. *A Page 3 of 9 CY7C128A Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID C128A–6 Read Cycle No. 2[9, 11] t RC CE tACE OE DATA OUT tHZOE tHZCE tDOE tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB C128A–7 Write Cycle No. 1 (WE Controlled)[8] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATAIN VALID DATA IN tHZWE DATA I/O tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED C128A–8 Notes: 9. WE is HIGH for read cycle. 10. Device is continuously selected. OE, CE = VIL. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05028 Rev. *A Page 4 of 9 CY7C128A Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled)[8, 12, 13] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tSD tHD DATA IN VALID DATA IN tHZWE DATA I/O HIGH IMPEDANCE DATA UNDEFINED C128A–9 Notes: 12. Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write. 13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. Document #: 38-05028 Rev. *A Page 5 of 9 CY7C128A NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 NORMALIZED ICC, ISB 1.2 ICC 0.8 0.6 0.4 0.0 4.0 4.5 5.0 0.8 0.6 0.4 VCC = 5.0V VIN = 5.0V 0.2 ISB 0.2 ICC 5.5 ISB 0.0 –55 6.0 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.6 1.4 1.3 NORMALIZED tAA NORMALIZED tAA 125 1.2 1.1 TA = 25°C 1.0 1.4 1.2 1.0 VCC = 5.0V 0.8 0.9 0.8 4.0 4.5 5.0 5.5 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 0.6 –55 6.0 40 20 0 0.0 25 TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 100 60 40 20 1.3 DELTA t AA (ns) 25.0 10.0 VCC = 4.5V TA = 25°C 5.0 0.5 2.0 3.0 4.0 SUPPLY VOLTAGE(V) Document #: 38-05028 Rev. *A 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) 2.0 3.0 4.0 NORMALIZED I CC vs. CYCLE TIME 2.5 1.0 1.0 OUTPUT VOLTAGE(V) 1.4 1.0 VCC =5.0V TA = 25°C 80 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 15.0 4.0 120 30.0 1.5 3.0 140 0 0.0 125 20.0 2.0 OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 3.0 2.0 1.0 OUTPUT VOLTAGE(V) AMBIENT TEMPERATURE(°C) SUPPLY VOLTAGE(V) 0.0 0.0 VCC =5.0V TA = 2 5°C) 60 AMBIENT TEMPERATURE(°C) SUPPLY VOLTAGE(V) NORMALIZED IPO 25 OUTPUT SINK CURRENT (mA) 1.0 1.0 NORMALIZED ICC NORMALIZED ICC, ISB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics VCC = 5.0V TA = 25°C VIN = 0.5V 1.2 1.1 1.0 0.9 0.8 0 10 20 30 40 CYCLE FREQUENCY (MHz) Page 6 of 9 CY7C128A Ordering Information Speed (ns) 15 20 35 45 Ordering Code CY7C128A-15PC CY7C128A-15VC CY7C128A-15VXC CY7C128A-20VXC CY7C128A-35VC CY7C128A-45PC Package Diagram 51-85013 51-85030 51-85030 51-85030 51-85013 24-pin 24-pin 24-pin 24-pin 24-pin 24-pin Operating Range Commercial Package Type (300-Mil) Molded DIP Molded SOJ Molded SOJ Molded SOJ (Pb-free) Molded SOJ (300-Mil) Molded DIP Commercial Commercial Commercial Please contact local sales representative regarding availability of these parts Package Diagrams 24-pin (300-Mil) Molded DIP (51-85013) 51-85013-*B Document #: 38-05028 Rev. *A Page 7 of 9 CY7C128A Package Diagrams (continued) 24-pin (300-mil) SOJ (51-85030) PIN 1 ID 12 1 MIN. DIMENSIONS IN INCHES[MM] MAX. REFERENCE JEDEC MO-088 0.291[7.39] 0.300[7.62] 0.330[8.38] 0.350[8.89] PACKAGE WEIGHT 0.75gms PART # 13 24 0.597[15.16] 0.613[15.57] V24.3 STANDARD PKG. VZ24.3 LEAD FREE PKG. SEATING PLANE 0.120[3.05] 0.140[3.55] 0.007[0.17] 0.013[0.33] 0.004[0.10] 0.050[1.27] TYP. 0.025[0.63] MIN. 0.262[6.65] 0.272[6.91] 0.013[0.33] 0.019[0.48] 51-85030-*B Document #: 38-05028 Rev. *A Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress CY7C128A Document History Page Document Title: CY7C128A 2K x 8 Static RAM Document Number: 38-05028 Issue Date Orig. of Change Description of Change 106814 09/10/01 SZV Change from Spec number: 38-00094 to 38-05028 493543 See ECN NXR Removed 25 ns speed bin Removed Military Operating Range Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated ordering Information Table REV. ECN NO. ** *A Document #: 38-05028 Rev. *A Page 9 of 9