CY7C1324F 2-Mb (128K x 18) Flow-Through Sync SRAM Features • 128K x 18 common I/O • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) • Provide high-performance 2-1-1-1 access rate Intel • User-selectable burst counter supporting Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Supports 3.3V I/O level • Offered in JEDEC-standard 100-pin TQFP package • “ZZ” Sleep Mode option Functional Description[1] The CY7C1324F is a 131,072 x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1324F allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1324F operates from a +3.3V core power supply while all outputs may operate with a +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram A0,A1,A ADDRESS REGISTER A[1:0] MODE BURST Q1 COUNTER AND LOGIC CLR Q0 ADV CLK ADSC ADSP BWB BWA DQB,DQPB WRITE DRIVER DQB,DQPB WRITE REGISTER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQA,DQPA WRITE DRIVER DQA,DQPA WRITE REGISTER DQs DQPA DQPB BWE GW CE1 CE2 CE3 INPUT REGISTERS ENABLE REGISTER OE ZZ SLEEP CONTROL Note: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05431 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 29, 2004 CY7C1324F Selection Guide 133 MHz 117 MHz Unit Maximum Access Time 6.5 7.5 ns Maximum Operating Current 225 220 mA Maximum Standby Current 40 40 mA Pin Configurations Document #: 38-05431 Rev. ** A A 45 46 47 48 49 50 A A A A NC 44 42 NC NC A A 43 41 38 NC NC 40 37 A0 VSS 36 A1 VDD 35 A 39 34 A 81 82 83 84 BWE OE ADSC ADSP ADV 85 86 GW 89 87 CLK 91 88 VDD VSS 93 90 BWA CE3 94 92 NC BWB 95 CE2 NC 96 98 97 A CE1 99 A 31 VSS VDDQ NC NC NC 33 VSS DQB DQB VDDQ VSS DQB DQB DQPB NC 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 CY7C1324F A BYTE B DQB DQB VSS VDDQ DQB DQB NC VDD NC 32 VDDQ VSS NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A NC NC NC 100 100-Pin TQFP A NC NC VDDQ VSS NC DQPB DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ BYTE A DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC Page 2 of 15 CY7C1324F Pin Descriptions Name TQFP I/O Description A0, A1, A 37,36,32, InputAddress Inputs used to select one of the 128K address locations. Sampled at 33,34,35, Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 44,45,46, are sampled active. A[1:0] feed the 2-bit counter. 47,48,49,80, 81,82, 99,100 BWA,BWB 93,94, InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes Synchronous to the SRAM. Sampled on the rising edge of CLK. GW 88 InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge Synchronous of CLK, a global Write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE). BWE 87 InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This Synchronous signal must be asserted LOW to conduct a Byte Write. CLK 89 CE1 98 InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE2 97 InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE3 to select/deselect the device. CE3 92 OE 86 InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE and CE to select/deselect the device. 1 2 InputOutput Enable, asynchronous input, active LOW. Controls the direction of the Asynchronou I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O s pins are three-stated, and act as input data pins. OE is masked during the first clock of a Read cycle when emerging from a deselected state. ADV 83 InputAdvance Input signal, sampled on the rising edge of CLK. When asserted, it Synchronous automatically increments the address in a burst cycle. ADSP 84 InputAddress Strobe from Processor, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH ADSC 85 InputAddress Strobe from Controller, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ 64 InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a Asynchronou non-time-critical “sleep” condition with data integrity preserved. For normal s operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs 58,59,62,63, I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register 68,69,72, Synchronous that is triggered by the rising edge of CLK. As outputs, they deliver the data 73,8,9,12, contained in the memory location specified by the addresses presented during the 13,18,19,22, previous clock rise of the Read cycle. The direction of the pins is controlled by OE. 23 When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a three-state condition. 24,74 DQPA, DQPB Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. VDD 15,41, 65, 91 Power Supply Power supply inputs to the core of the device. VSS 5,10,17,21, 26,40,55,60, 67,71,76, 90 Ground Ground for the device. Document #: 38-05431 Rev. ** Page 3 of 15 CY7C1324F Pin Descriptions (continued) Name TQFP VDDQ 4,11,20, 27,54,61, 70,77 MODE 31 NC 1,2,3,6,714, 16,25,28,29, 30,38,39, 42,43,50,51, 52,53,56, 57,66,75,78, 79,95,96 I/O I/O Power Supply InputStatic Description Power supply for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not Internally connected to the die. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CDV) is 6.5 ns (133-MHz device). The CY7C1324F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses Document #: 38-05431 Rev. ** presented are loaded into the address register and the burst inputs (GW, BWE, and BW[A:B]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a Write) on the next clock rise, the appropriate data will be latched and written into the device. Byte Writes are allowed. During Byte Writes, BWA controls DQA and BWB controls DQB. All I/Os are three-stated during a Byte Write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[A:B]) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] will be written into the specified address location. Byte Writes are allowed. During Byte Writes, BWA controls DQA and BWB controls DQB. All I/Os are three-stated when a Write is detected, even a Byte Write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are three-stated once a Write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1324F provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to an interleaved burst sequence. Page 4 of 15 CY7C1324F Sleep Mode Linear Burst Address Table (MODE = GND) The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Snooze mode standby current ZZ > VDD – 0.2V Min. tZZS Device operation to ZZ ZZ > VDD – 0.2V tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ Active to snooze current This parameter is sampled tRZZI ZZ Inactive to exit snooze current This parameter is sampled Max. Unit 40 mA 2tCYC ns 2tCYC ns 2tCYC ns 0 ns Truth Table[2, 3, 4, 5] Cycle Description Deselected Cycle, Power-down ADDRESS Used CE1 CE3 CE2 None H X X ZZ ADSP ADSC ADV L X L X WE OE CLK X X L-H Three-State DQ Deselected Cycle, Power-down None L X L L L X X X X L-H Three-State Deselected Cycle, Power-down None L H X L L X X X X L-H Three-State Deselected Cycle, Power-down None L X L L H L X X X L-H Three-State Deselected Cycle, Power-down None X X X L H L X X X L-H Three-State Snooze Mode, Power-down None X X X H X X X X X X Three-State Read Cycle, Begin Burst External L L H L L X X X L L-H Q Read Cycle, Begin Burst External L L H L L X X X H L-H Three-State Write Cycle, Begin Burst External L L H L H L X L X L-H D Notes: 2. X = “Don't Care.” H = Logic HIGH, L =Logic LOW. 3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals (BWA, BWB), BWE, GW = H.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 4. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the Write cycle 5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a read cycle all data bits are Three-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW) Document #: 38-05431 Rev. ** Page 5 of 15 CY7C1324F Truth Table[2, 3, 4, 5] ADDRESS Used CE1 CE3 CE2 External L L H Cycle Description Read Cycle, Begin Burst ZZ ADSP ADSC ADV WE OE CLK DQ L H L X H L L-H Q External L L H L H L X H H L-H Three-State Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H Three-State Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H Three-State Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Begin Burst Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H Three-State Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H Three-State Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D Truth Table for Read/Write[2, 3] Function Read GW H BWE H BWB X BWA X Read H L H H Write Byte (A, DQPA) H L H L Write Byte (B, DQPB) H L L H Write All Bytes H L L L Write All Bytes L X X X Document #: 38-05431 Rev. ** Page 6 of 15 CY7C1324F Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V DC Voltage Applied to Outputs in Three-State ..................................... –0.5V to VDDQ + 0.5V Ambient Temperature] Range Commercial Industrial 0°C to +70°C –40°C to +85°C VDD VDDQ 3.3V −5%/+10% 3.3V –5% to VDD DC Input Voltage....................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range [6, 7] CY7C1324F Parameter Description Test Conditions VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA VOL Output LOW Voltage VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VIH Input HIGH Voltage VDDQ = 3.3V VDDQ = 3.3V Voltage[6] Min. Max. Unit 3.135 3.6 V 3.135 3.6 2.4 V V 0.4 V 2.0 VDD + 0.3V V VIL Input LOW –0.3 0.8 V IX Input Load Current (except ZZ and MODE) GND ≤ VI ≤ VDDQ −5 5 µA Input Current of MODE Input = VSS –30 5 µA Input = VDD Input Current of ZZ 30 Input = VDD Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled IOS Output Short Circuit Current VDD = Max., VOUT = GND IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC Automatic CE Power-Down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = fMAX, inputs switching ISB2 Automatic CE Power-Down Current—CMOS Inputs ISB3 ISB1 ISB4 µA –5 Input = VSS IOZ µA µA 5 µA –300 mA 7.5-ns cycle, 133 MHz 225 mA 8.0-ns cycle, 117 MHz 220 mA 7.5-ns cycle, 133 MHz 90 mA 8.0-ns cycle, 117 MHz 85 mA Max. VDD, Device Deselected, All speeds VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static 40 mA Automatic CE Power-Down Current—CMOS Inputs 7.5-ns cycle, 133 MHz Max. VDD, Device Deselected, VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, 8.0-ns cycle, 117 MHz f = fMAX, inputs switching 75 mA 70 mA Automatic CE Power-Down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static 45 mA –5 All speeds Notes: 6. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2). 7. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05431 Rev. ** Page 7 of 15 CY7C1324F Thermal Resistance[8] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions TQFP Package Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 41.83 °C/W 9.99 °C/W Capacitance[8] Parameter Description Test Conditions Max. Unit 5 pF CIN Input Capacitance CCLK Clock Input Capacitance 5 pF CI/O Input/Output Capacitance 5 pF TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 351Ω INCLUDING JIG AND SCOPE 90% 10% 90% 10% ≤ 1 ns ≤ 1 ns VL = 1.5V (a) ALL INPUT PULSES VDD (c) (b) Switching Characteristics Over the Operating Range[9, 10] 133 MHz Parameter tPOWER Description VDD(Typical) to the First Access[11] Min. 117 MHz Max. Min. Max. Unit 1 1 ms 8.5 ns Clock tCYC Clock Cycle Time 7.5 tCH Clock HIGH 2.5 3.0 ns tCL Clock LOW 2.5 3.0 ns Output Times tCDV Data Output Valid after CLK Rise tDOH Data Output Hold after CLK Rise tCLZ Clock to Low-Z[12, 13, 14] tCHZ Clock to High-Z[12, 13, 14] 3.5 3.5 ns tOEV OE LOW to Output Valid 3.5 3.5 ns 3.5 ns Low-Z[12, 13, 14] tOELZ OE LOW to Output tOEHZ OE HIGH to Output High-Z[12, 13, 14] 6.5 7.5 ns 2.0 2.0 ns 0 0 ns 0 0 3.5 ns Notes: 8. Tested initially and after any design or process change that may affect these parameters. 9. Timing reference level is 1.5V when VDDQ = 3.3V. 10. Test conditions shown in (a) of AC Test Loads unless otherwise noted. 11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a Read or Write operation can be initiated. 12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. Document #: 38-05431 Rev. ** Page 8 of 15 CY7C1324F Switching Characteristics Over the Operating Range[9, 10] 133 MHz Parameter Description Min. Max. 117 MHz Min. Max. Unit Set-up Times tAS Address Set-up before CLK Rise 1.5 2.0 ns tADS ADSP, ADSC Set-up before CLK Rise 1.5 2.0 ns tADVS ADV Set-up before CLK Rise 1.5 2.0 ns tWES GW, BWE, BW[A:B] Set-up before CLK Rise Data Input Set-up before CLK Rise 1.5 2.0 ns tDS 1.5 2.0 ns tCES Chip Enable Set-up 1.5 2.0 ns tAH Address Hold after CLK Rise 0.5 0.5 ns tADH 0.5 0.5 ns tWEH ADSP, ADSC Hold after CLK Rise GW,BWE, BW[A:B] Hold after CLK Rise 0.5 0.5 ns tADVH ADV Hold after CLK Rise 0.5 0.5 ns tDH Data Input Hold after CLK Rise 0.5 0.5 ns tCEH Chip Enable Hold after CLK Rise 0.5 0.5 ns Hold Times Document #: 38-05431 Rev. ** Page 9 of 15 CY7C1324F Timing Diagrams Read Cycle Timing[15] tCYC CLK t tADS CH t CL tADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 t WES t WEH GW, BWE,BW [A:B] tCES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst. OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t OELZ tCDV t CHZ tDOH Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Single READ BURST READ DON’T CARE Burst wraps around to its initial state UNDEFINED Note: 15. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05431 Rev. ** Page 10 of 15 CY7C1324F Timing Diagrams (continued) Write Cycle Timing[15, 16] t CYC CLK t tADS t CH CL tADH ADSP tADS ADSC extends burst. tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst. tWES tWEH BWE, BW[A:B] t t WES WEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst. OE t Data in (D) High-Z t OEHZ t DS DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE Extended BURST WRITE UNDEFINED Note: 16. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW... Document #: 38-05431 Rev. ** Page 11 of 15 CY7C1324F Timing Diagrams (continued) Read/Write Timing[15, 17, 18] tCYC CLK t CH tADS tADH tAS tAH t CL ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) t t WES WEH BWE, BW[A:B] tCES tCEH CE ADV OE tDS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH tOELZ D(A3) tCDV Q(A2) Back-to-Back READs Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ DON’T CARE Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes: 17. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed. 18. GW is HIGH. Document #: 38-05431 Rev. ** Page 12 of 15 CY7C1324F Timing Diagrams (continued) ZZ Mode Timing[19, 20] CLK t ZZ I t t ZZ ZZREC ZZI SUPPLY I t RZZI DDZZ ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) Ordering Code Package Name Package Type 133 CY7C1324F-133AC A101 100-Lead Thin Quad Flat Pack 117 CY7C1324F-117AC A101 100-Lead Thin Quad Flat Pack CY7C1324F-117AI A101 100-Lead Thin Quad Flat Pack Operating Range Commercial Industrial Notes: 19. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 20. DQs are in High-Z when exiting ZZ sleep mode. Document #: 38-05431 Rev. ** Page 13 of 15 CY7C1324F Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 1.40±0.05 14.00±0.10 100 81 80 1 20.00±0.10 22.00±0.20 0.30±0.08 0.65 TYP. 30 SEE DETAIL 50 0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX. 0.25 GAUGE PLANE 0.10 0° MIN. 0°-7° A 51 31 R 0.08 MIN. 0.20 MAX. 12°±1° (8X) SEATING PLANE R 0.08 MIN. 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL A 51-85050-*A Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05431 Rev. ** Page 14 of 15 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1324F Document History Page Document Title: CY7C1324F 2-Mb (128K x 18) Flow-Through Sync SRAM Document Number: 38-05431 REV. ECN NO. Issue Date Orig. of Change ** 200780 See ECN NJY Document #: 38-05431 Rev. ** Description of Change New Data Sheet Page 15 of 15