CYPRESS CY7C1372DV25

CY7C1370DV25
CY7C1372DV25
18-Mbit (512K x 36/1M x 18)
Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
• Pin-compatible and functionally equivalent to ZBT™
The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x
36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1370DV25 and
CY7C1372DV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1370DV25
and CY7C1372DV25 are pin-compatible and functionally
equivalent to ZBT devices.
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V core power supply (VDD)
• 2.5V I/O power supply (VDDQ)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in JEDEC-standard lead-free 100-Pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165-Ball
FBGA packages
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1370DV25 and BWa–BWb for
CY7C1372DV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
• IEEE 1149.1 JTAG-Compatible Boundary Scan
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram-CY7C1370DV25 (512K x 36)
A0, A1, A
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
S
E
N
S
E
ADV/LD
BWa
BWb
BWc
BWd
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
A
M
P
S
WE
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
INPUT
REGISTER 1
OE
CE1
CE2
CE3
ZZ
Cypress Semiconductor Corporation
Document #: 38-05558 Rev. *D
E
O
U
T
P
U
T
D
A
T
A
S
T
E
E
R
I
N
G
INPUT
REGISTER 0
B
U
F
F
E
R
S
DQs
DQPa
DQPb
DQPc
DQPd
E
E
READ LOGIC
SLEEP
CONTROL
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 29, 2006
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CY7C1370DV25
CY7C1372DV25
Logic Block Diagram-CY7C1372DV25 (1M x 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
MODE
CLK
CEN
ADV/LD
C
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
BWb
WE
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
D
A
T
A
R
E
G
I
S
T
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
OE
CE1
CE2
CE3
ZZ
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPa
DQPb
E
INPUT
REGISTER 0 E
READ LOGIC
Sleep
Control
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Document #: 38-05558 Rev. *D
250 MHz
200 MHz
167 MHz
Unit
2.6
350
70
3.0
300
70
3.4
275
70
ns
mA
mA
Page 2 of 27
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CY7C1370DV25
CY7C1372DV25
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1372DV25
(1M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
NC(36)
NC(72)
VSS
VDD
A
A
A
A
A
A
A
NC(36)
NC(72)
VSS
VDD
NC(288)
NC(144)
MODE
A
A
A
A
A1
A0
Document #: 38-05558 Rev. *D
NC
DQPb
NC
DQb
NC
DQb
VDDQ VDDQ
VSS
VSS
NC
DQb
DQb
NC
DQb
DQb
DQb
DQb
VSS
VSS
VDDQ VDDQ
DQb
DQb
DQb
DQb
NC
VSS
VDD
NC
NC
VDD
VSS
ZZ
DQb
DQa
DQa
DQb
VDDQ VDDQ
VSS
VSS
DQa
DQb
DQa
DQb
DQa DQPb
NC
DQa
VSS
VSS
V
DDQ
VDDQ
NC
DQa
DQa
NC
DQPa
NC
NC(288)
NC(144)
CY7C1370DV25
(512K × 36)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
DQPc
DQc
DQc
VDDQ
A
A
A
A
CE1
CE2
NC
NC
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWd
BWc
BWb
BWa
CE3
VDD
VSS
CLK
WE
CEN
OE
ADV/LD
A
A
100-Pin TQFP Pinout
Page 3 of 27
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CY7C1370DV25
CY7C1372DV25
Pin Configurations (continued)
119-Ball BGA Pinout
CY7C1370DV25 (512K × 36)
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
A
VDDQ
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
NC/1G
DQc
CE2
A
DQPc
A
A
VSS
ADV/LD
VDD
NC
A
A
VSS
CE3
A
DQPb
NC
NC
DQb
R
T
U
DQc
DQc
VSS
CE1
VSS
DQb
DQb
VDDQ
DQc
VSS
VSS
DQb
VDDQ
DQc
DQc
BWb
DQb
DQb
DQc
VDDQ
DQc
VDD
BWc
VSS
NC
OE
A
WE
VDD
VSS
NC
DQb
VDD
DQb
VDDQ
DQd
DQd
DQd
DQd
VSS
BWd
CLK
NC
DQa
DQa
VDDQ
DQd
VSS
DQd
DQd
DQd
BWa
DQa
DQa
VSS
DQa
VDDQ
VSS
CEN
A1
VSS
DQa
DQa
DQPd
VSS
A0
VSS
DQPa
DQa
NC/144M
A
MODE
VDD
NC/288M
NC
NC/72M
A
A
NC
A
A
NC/36M
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
VSS
CY7C1372DV25 (1M x 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Document #: 38-05558 Rev. *D
1
2
3
4
5
6
7
VDDQ
A
A
A
A
A
VDDQ
NC/576M
CE2
A
A
A
ADV/LD
VDD
A
NC/1G
A
CE3
A
NC
DQb
NC
VSS
NC
VSS
DQPa
NC
NC
NC
DQb
VSS
CE1
VSS
NC
DQa
VDDQ
NC
VSS
VSS
DQa
VDDQ
NC
DQb
VDDQ
DQb
NC
VDD
BWb
VSS
NC
OE
A
WE
VDD
NC
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
VSS
NC
DQa
BWa
VSS
DQa
NC
NC
VDDQ
NC
DQb
VSS
CLK
DQb
NC
NC
NC
VDDQ
DQb
VSS
DQb
NC
VSS
CEN
A1
VSS
DQa
NC
NC
DQPb
VSS
A0
VSS
NC
DQa
NC/144M
A
MODE
VDD
NC
A
NC/288M
NC/72M
A
A
NC/36M
A
A
ZZ
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Page 4 of 27
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CY7C1370DV25
CY7C1372DV25
Pin Configurations (continued)
165-Ball FBGA Pinout
1
2
3
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/576M
A
CE1
NC/1G
A
CE2
DQPc
DQc
NC
DQc
VDDQ
DQc
R
MODE
CY7C1370DV25 (512K × 36)
4
5
6
7
8
9
10
11
BWb
CE3
A
A
NC
BWa
VSS
OE
A
A
NC
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
BWd
VSS
VDD
CEN
WE
ADV/LD
CLK
VDDQ
NC
DQb
DQPb
DQb
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
BWc
DQc
DQc
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
DQc
NC
DQd
DQc
NC
DQd
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQb
NC
DQa
DQb
ZZ
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQPd
DQd
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
DQa
DQPa
A
A
TDI
A1
TDO
A
A
A
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
9
10
11
NC/144M NC/72M
NC/36M
CY7C1372DV25 (1M × 18)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
NC/576M
NC/1G
6
7
8
A
CE1
BWb
A
CE2
NC
NC
CE3
CEN
ADV/LD
A
A
A
BWa
CLK
WE
VSS
VSS
OE
VSS
VDD
A
A
NC
NC
NC
NC
DQb
VDDQ
VSS
VDDQ
VSS
VDD
VSS
VSS
VSS
VDDQ
VDDQ
NC
NC
DQPa
DQa
NC
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
DQb
VDDQ
VDD
NC
NC
DQb
DQb
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQa
DQa
ZZ
NC
DQb
NC
VDDQ
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
DQPb
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQa
NC
NC
NC
NC/144M NC/72M
A
A
TDI
A1
TDO
A
A
A
NC/288M
NC/36M
A
A
TMS
A0
TCK
A
A
A
A
MODE
Document #: 38-05558 Rev. *D
5
Page 5 of 27
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CY7C1370DV25
CY7C1372DV25
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
InputAddress Inputs used to select one of the address locations. Sampled at the rising edge of
Synchronous the CLK.
BWa
BWb
BWc
BWd
InputByte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Synchronous Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd.
WE
InputWrite Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
Synchronous signal must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/Load Input used to advance the on-chip address counter or load a new address.
Synchronous When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
CLK
InputClock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
CE1
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device.
CE2
InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
Synchronous with CE1 and CE3 to select/deselect the device.
CE3
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device.
OE
InputOutput Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
CEN
InputClock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
Synchronous SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
DQS
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are
automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE.
DQPX
I/OBidirectional Data Parity I/O lines. Functionally, these signals are identical to DQs. During write
Synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc,
and DQPd is controlled by BWd.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
Synchronous
TDI
JTAG serial Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
input
Synchronous
TMS
Test Mode This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Select
Synchronous
TCK
JTAG-Clock Clock input to the JTAG circuitry.
Document #: 38-05558 Rev. *D
Page 6 of 27
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CY7C1370DV25
CY7C1372DV25
Pin Definitions (continued)
Pin Name
VDD
VDDQ
VSS
NC
NC/(36M, 72M,
144M, 288M,
576M, 1G)
ZZ
I/O Type
Pin Description
Power Supply Power supply inputs to the core of the device.
I/O Power
Supply
Ground
–
–
Power supply for the I/O circuitry.
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
These pins are not connected. They will be used for expansion to the 36M, 72M, 144M, 288M,
576M, and 1G densities.
InputZZ “Sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left
floating. ZZ pin has an internal pull-down.
Introduction
Functional Overview
The
CY7C1370DV25
and
CY7C1372DV25
are
synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.6 ns (250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(250-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
Document #: 38-05558 Rev. *D
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
Burst Read Accesses
The CY7C1370DV25 and CY7C1372DV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented is loaded into the
Address Register. The write signals are latched into the
Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b
for CY7C1372DV25). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the
Address Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 & DQa,b/DQPa,b for
CY7C1372DV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1370DV25 and BWa,b for CY7C1372DV25)
Page 7 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
signals. The CY7C1370DV25/CY7C1372DV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the Write Enable input (WE) with the selected
Byte Write Select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly
simplify Read/Modify/Write sequences, which can be reduced
to simple byte write operations.
Because the CY7C1370DV25 and CY7C1372DV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b
for CY7C1372DV25) inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1370DV25 and DQa,b/DQPa,b
for CY7C1372DV25) are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
Burst Write Accesses
The CY7C1370DV25/CY7C1372DV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four WRITE operations without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load the initial address, as described in the Single
Write Access section above. When ADV/LD is driven HIGH on
the subsequent clock rise, the chip enables (CE1, CE2, and
CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW (BWa,b,c,d for CY7C1370DV25 and
BWa,b for CY7C1372DV25) inputs must be driven in each
cycle of the burst write in order to write the correct bytes of
data.
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD − 0.2V
80
mA
tZZS
Device operation to ZZ
ZZ > VDD − 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to sleep current
This parameter is sampled
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
Document #: 38-05558 Rev. *D
2tCYC
ns
2tCYC
0
ns
ns
Page 8 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Truth Table[1, 2, 3, 4, 5, 6, 7]
Address
Used
Operation
CE
ZZ
ADV/LD
WE
BWx
Deselect Cycle
None
H
L
L
X
X
X
L
L-H
Tri-state
Continue Deselect Cycle
None
X
L
H
X
X
X
L
L-H
Tri-state
Read Cycle (Begin Burst)
External
L
L
L
H
X
L
L
L-H
Data Out (Q)
Read Cycle (Continue Burst)
Next
X
L
H
X
X
L
L
L-H
Data Out (Q)
NOP/Dummy Read (Begin Burst)
External
L
L
L
H
X
H
L
L-H
Tri-state
Dummy Read (Continue Burst)
Next
X
L
H
X
X
H
L
L-H
Tri-state
Write Cycle (Begin Burst)
External
L
L
L
L
L
X
L
L-H
Data In (D)
Write Cycle (Continue Burst)
Next
X
L
H
X
L
X
L
L-H
Data In (D)
NOP/Write Abort (Begin Burst)
None
L
L
L
L
H
X
L
L-H
Tri-state
Write Abort (Continue Burst)
Next
X
L
H
X
H
X
L
L-H
Tri-state
Ignore Clock Edge (Stall)
Current
X
L
X
X
X
X
H
L-H
–
Sleep Mode
None
X
H
X
X
X
X
X
X
Partial Write Cycle
OE
CEN
CLK
DQ
Tri-state
Description[1, 2, 3, 8]
WE
BWd
BWc
BWb
BWa
Read
Function (CY7C1370DV25)
H
X
X
X
X
Write – No bytes written
L
H
H
H
H
Write Byte a – (DQa and DQPa)
L
H
H
H
L
Write Byte b – (DQb and DQPb)
L
H
H
L
H
Write Bytes b, a
L
H
H
L
L
Write Byte c – (DQc and DQPc)
L
H
L
H
H
Write Bytes c, a
L
H
L
H
L
Write Bytes c, b
L
H
L
L
H
Write Bytes c, b, a
L
H
L
L
L
Write Byte d – (DQd and DQPd)
L
L
H
H
H
Write Bytes d, a
L
L
H
H
L
Write Bytes d, b
L
L
H
L
H
Write Bytes d, b, a
L
L
H
L
L
Write Bytes d, c
L
L
L
H
H
Write Bytes d, c, a
L
L
L
H
L
Write Bytes d, c, b
L
L
L
L
H
Write All Bytes
L
L
L
L
L
Notes:
1. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid
signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.
2. Write is defined by WE and BWX. See Write Cycle Description table for details.
3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
4. The DQ and DQP pins are controlled by the current cycle and the OE signal.
5. CEN = H inserts wait states.
6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQPX = Three-state when
OE is inactive or when the device is deselected, and DQs = data when OE is active.
8. Table only lists a partial listing of the byte write combinations. Any Combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05558 Rev. *D
Page 9 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Function (CY7C1372DV25)
Read
WE
BWb
BWa
H
x
x
Write – No Bytes Written
L
H
H
Write Byte a – (DQa and DQPa)
L
H
L
Write Byte b – (DQb and DQPb)
L
L
H
Write Both Bytes
L
L
L
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Mode Select (TMS)
The CY7C1370DV25/CY7C1372DV25 incorporates a serial
boundary scan test access port (TAP).This part is fully
compliant with 1149.1. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1370DV25/CY7C1372DV25 contains a TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should be
left unconnected. Upon power-up, the device will come up in
a reset state which will not interfere with the operation of the
device.
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
RUN-TEST/
IDLE
0
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
(See Tap Controller Block Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
0
1
CAPTURE-DR
0
CAPTURE-IR
0
Bypass Register
0
2 1 0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
0
Selection
Circuitry
TDO
x . . . . . 2 1 0
0
Boundary Scan Register
1
0
Instruction Register
Identification Register
PAUSE-IR
1
EXIT2-DR
Selection
Circuitry
31 30 29 . . . 2 1 0
1
0
PAUSE-DR
EXIT2-IR
1
1
UPDATE-DR
1
TDI
1
EXIT1-DR
0
0
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05558 Rev. *D
TCK
TMS
TAP CONTROLLER
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Page 10 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
Document #: 38-05558 Rev. *D
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required—that is, while data
captured is shifted out, the preloaded data can be shifted in.
Page 11 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST Output Bus Tri-State
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package) or bit #89 (for 165-fBGA package).
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
preset HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
Test Clock
(TCK)
3
tTH
tTMSS
tTMSH
tTDIS
tTDIH
t
TL
4
5
6
tCYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTDOV
tTDOX
Test Data-Out
(TDO)
DON’T CARE
Document #: 38-05558 Rev. *D
UNDEFINED
Page 12 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
TAP AC Switching Characteristics Over the Operating Range[9, 10]
Parameter
Description
Min.
Max.
Unit
20
MHz
Clock
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH time
20
ns
tTL
TCK Clock LOW time
20
ns
50
ns
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
ns
0
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
5
ns
tTDIS
TDI Set-up to TCK Clock Rise
5
ns
tCS
Capture Set-up to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
Hold Times
Notes:
9. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
Document #: 38-05558 Rev. *D
Page 13 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
2.5V TAP AC Test Conditions
2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels ................................................ VSS to 2.5V
Input rise and fall time..................................................... 1 ns
50Ω
Input timing reference levels .........................................1.25V
Output reference levels.................................................1.25V
TDO
Test load termination supply voltage.............................1.25V
Z O= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 2.5V ±0.125V unless otherwise noted)[11]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = –1.0 mA, VDDQ = 2.5V
2.0
V
VOH2
Output HIGH Voltage
IOH = –100 µA, VDDQ = 2.5V
2.1
V
VOL1
Output LOW Voltage
IOL = 8.0 mA, VDDQ = 2.5V
IOL = 100 µA
VDDQ = 2.5V
0.4
V
VOL2
Output LOW Voltage
0.2
V
VIH
Input HIGH Voltage
VDDQ = 2.5V
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
VDDQ = 2.5V
–0.3
0.7
V
IX
Input Load Current
–5
5
µA
GND < VIN < VDDQ
Scan Register Sizes
Bit Size (x18)
Bit Size (x36)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan Order (119-ball BGA package)
85
85
Boundary Scan Order (165-ball fBGA package)
89
89
Register Name
Identification Register Definitions
Instruction Field
CY7C1372DV25
CY7C1370DV25
Description
Revision Number (31:29)
000
000
Cypress Device ID (28:12)
01011001000100101
01011001000010101
Cypress JEDEC ID (11:1)
00000110100
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
Indicate the presence of an ID
register.
Reserved for version number.
Reserved for future use.
Note:
11.All voltages referenced to VSS (GND).
Document #: 38-05558 Rev. *D
Page 14 of 27
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CY7C1370DV25
CY7C1372DV25
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
119-Ball BGA Boundary Scan Order [12, 13]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
H4
23
F6
45
G4
67
L1
2
T4
24
E7
46
A4
68
M2
3
T5
25
D7
47
G3
69
N1
4
T6
26
H7
48
C3
70
P1
5
R5
27
G6
49
B2
71
K1
6
L5
28
E6
50
B3
72
L2
7
R6
29
D6
51
A3
73
N2
8
U6
30
C7
52
C2
74
P2
9
R7
31
B7
53
A2
75
R3
10
T7
32
C6
54
B1
76
T1
11
P6
33
A6
55
C1
77
R1
12
N7
34
C5
56
D2
78
T2
13
M6
35
B5
57
E1
79
L3
14
L7
36
G5
58
F2
80
R2
15
K6
37
B6
59
G1
81
T3
16
P7
38
D4
60
H2
82
L4
17
N6
39
B4
61
D1
83
N4
18
L6
40
F4
62
E2
84
P4
19
K7
41
M4
63
G2
85
Internal
20
J5
42
A5
64
H1
21
H6
43
K4
65
J3
22
G7
44
E4
66
2K
Notes:
12. Balls which are NC (No Connect) are pre-set LOW.
13. Bit# 85 is pre-set HIGH.
Document #: 38-05558 Rev. *D
Page 15 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
165-Ball FBGA Boundary Scan Order [12, 14]
Bit #
Ball ID
Bit #
Ball ID
Bit #
Ball ID
1
N6
31
D10
61
G1
2
N7
32
C11
62
D2
3
N10
33
A11
63
E2
4
P11
34
B11
64
F2
5
P8
35
A10
65
G2
6
R8
36
B10
66
H1
7
R9
37
A9
67
H3
8
P9
38
B9
68
J1
9
P10
39
C10
69
K1
10
R10
40
A8
70
L1
11
R11
41
B8
71
M1
12
H11
42
A7
72
J2
13
N11
43
B7
73
K2
14
M11
44
B6
74
L2
15
L11
45
A6
75
M2
16
K11
46
B5
76
N1
17
J11
47
A5
77
N2
18
M10
48
A4
78
P1
19
L10
49
B4
79
R1
20
K10
50
B3
80
R2
21
J10
51
A3
81
P3
22
H9
52
A2
82
R3
23
H10
53
B2
83
P2
24
G11
54
C2
84
R4
25
F11
55
B1
85
P4
26
E11
56
A1
86
N5
27
D11
57
C1
87
P6
28
G10
58
D1
88
R6
29
F10
59
E1
89
Internal
30
E10
60
F1
Note:
14. Bit# 89 is pre-set HIGH.
Document #: 38-05558 Rev. *D
Page 16 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Maximum Ratings
DC Input Voltage ................................... –0.5V to VDD + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
DC to Outputs in Tri-State ................... –0.5V to VDDQ + 0.5V
Range
Commercial
Industrial
Ambient
Temperature
VDD/VDDQ
0°C to +70°C
2.5V ±5%
–40°C to +85°C
Electrical Characteristics Over the Operating Range[15, 16]
Parameter
Description
Test Conditions
Min.
Max.
Unit
2.375
2.625
V
2.375
VDD
V
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
for 2.5V I/O
VOH
Output HIGH Voltage
for 2.5V I/O, IOH = −1.0 mA
VOL
Output LOW Voltage
for 2.5V I/O, IOL= 1.0 mA
0.4
V
VIH
Input HIGH Voltage[17]
for 2.5V I/O
1.7
VDD + 0.3V
V
VIL
Input LOW
Voltage[17]
for 2.5V I/O
–0.3
0.7
V
IX
Input Leakage Current
except ZZ and MODE
–5
5
µA
2.0
GND ≤ VI ≤ VDDQ
Input Current of MODE Input = VSS
5
Input = VSS
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
IDD
VDD Operating Supply
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
µA
µA
–5
30
µA
5
µA
4.0-ns cycle, 250 MHz
350
mA
5.0-ns cycle, 200 MHz
300
mA
Input = VDD
IOZ
µA
–30
Input = VDD
Input Current of ZZ
V
–5
6.0-ns cycle, 167 MHz
275
mA
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX = 5.0-ns cycle, 200 MHz
1/tCYC
6.0-ns cycle, 167 MHz
160
mA
150
mA
140
mA
ISB2
Automatic CE
Max. VDD, Device Deselected, All speed grades
Power-down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
Current—CMOS Inputs f = 0
70
mA
ISB3
Automatic CE
Max. VDD, Device Deselected, 4.0-ns cycle, 250 MHz
Power-down
VIN ≤ 0.3V or VIN > VDDQ − 0.3V, 5.0-ns cycle, 200 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
6.0-ns cycle, 167 MHz
135
mA
130
mA
125
mA
Automatic CE
Power-down
Current—TTL Inputs
80
mA
ISB4
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
All speed grades
Notes:
15. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
16. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
17. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05558 Rev. *D
Page 17 of 27
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CY7C1370DV25
CY7C1372DV25
Capacitance[17]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TA = 25°C, f = 1 MHz,
VDD = 2.5V.
VDDQ = 2.5V
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Unit
5
8
9
pF
5
8
9
pF
5
8
9
pF
100 TQFP
Package
119 BGA
Package
165 FBGA
Package
Unit
28.66
23.8
20.7
°C/W
4.08
6.2
4.0
°C/W
Thermal Resistance[17]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA/JESD51.
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
Z0 = 50Ω
10%
R = 1538Ω
VT = 1.25V
Document #: 38-05558 Rev. *D
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50Ω
(b)
≤ 1 ns
≤ 1 ns
(c)
Page 18 of 27
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CY7C1370DV25
CY7C1372DV25
Switching Characteristics Over the Operating Range
[22, 23]
–250
Parameter
tPower
[18]
Description
VCC (typical) to the first access read or write
Min.
Max.
1
–200
Min.
–167
Max.
1
Min.
Max.
1
Unit
ms
Clock
tCYC
Clock Cycle Time
FMAX
Maximum Operating Frequency
4.0
5
tCH
Clock HIGH
1.7
2.0
2.2
ns
tCL
Clock LOW
1.7
2.0
2.2
ns
250
6
200
ns
167
MHz
Output Times
tCO
Data Output Valid After CLK Rise
2.6
3.0
3.4
ns
tEOV
OE LOW to Output Valid
2.6
3.0
3.4
ns
tDOH
Data Output Hold After CLK Rise
tCHZ
Clock to
High-Z[19, 20, 21]
tCLZ
Clock to Low-Z[19, 20, 21]
tEOHZ
tEOLZ
OE HIGH to Output
High-Z[19, 20, 21]
OE LOW to Output
Low-Z[19, 20, 21]
1.0
1.3
2.6
1.0
1.3
3.0
1.3
2.6
ns
3.4
1.3
3.0
ns
ns
3.4
ns
0
0
0
ns
Set-up Times
tAS
Address Set-up Before CLK Rise
1.2
1.4
1.5
ns
tDS
Data Input Set-up Before CLK Rise
1.2
1.4
1.5
ns
tCENS
CEN Set-up Before CLK Rise
1.2
1.4
1.5
ns
tWES
WE, BWx Set-up Before CLK Rise
1.2
1.4
1.5
ns
tALS
ADV/LD Set-up Before CLK Rise
1.2
1.4
1.5
ns
tCES
Chip Select Set-up
1.2
1.4
1.5
ns
tAH
Address Hold After CLK Rise
0.3
0.4
0.5
ns
tDH
Data Input Hold After CLK Rise
0.3
0.4
0.5
ns
tCENH
CEN Hold After CLK Rise
0.3
0.4
0.5
ns
tWEH
WE, BWx Hold After CLK Rise
0.3
0.4
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.3
0.4
0.5
ns
tCEH
Chip Select Hold After CLK Rise
0.3
0.4
0.5
ns
Hold Times
Notes:
18. This part has a voltage regulator internally; tPower is the time power needs to be supplied above VDD minimum initially, before a Read or Write operation can
be initiated.
19. tCHZ, tCLZ, tEOLZ, and tEOHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
21. This parameter is sampled and not 100% tested.
22. Timing reference 1.25V when VDDQ = 2.5V.
23. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05558 Rev. *D
Page 19 of 27
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CY7C1370DV25
CY7C1372DV25
Switching Waveforms
Read/Write/Timing[24, 25, 26]
1
2
3
t CYC
4
5
6
A3
A4
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWx
A1
ADDRESS
A2
tCO
tAS
tDS
tAH
Data
tDH
D(A1)
tCLZ
D(A2)
D(A2+1)
tDOH
Q(A3)
tOEV
Q(A4)
tCHZ
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
tOEHZ
tDOH
tOELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
UNDEFINED
Notes:
24. For this waveform ZZ is tied LOW.
25. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
26. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05558 Rev. *D
Page 20 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Switching Waveforms (continued)
NOP,STALL and DESELECT Cycles[24, 25, 27]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BWx
ADDRESS
A5
tCHZ
D(A1)
Data
Q(A2)
D(A4)
Q(A3)
Q(A5)
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
DON’T CARE
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
ZZ Mode Timing[28, 29]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes:
27. The Ignore Clock Edge or Stall cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
28. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
29. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05558 Rev. *D
Page 21 of 27
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CY7C1370DV25
CY7C1372DV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
167
Ordering Code
CY7C1370DV25-167AXC
Package
Diagram
Part and Package Type
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Operating
Range
Commercial
CY7C1372DV25-167AXC
CY7C1370DV25-167BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372DV25-167BGC
CY7C1370DV25-167BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-167BGXC
CY7C1370DV25-167BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372DV25-167BZC
CY7C1370DV25-167BZXC
CY7C1372DV25-167BZXC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
CY7C1370DV25-167AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
CY7C1372DV25-167AXI
CY7C1370DV25-167BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372DV25-167BGI
CY7C1370DV25-167BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-167BGXI
CY7C1370DV25-167BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372DV25-167BZI
CY7C1370DV25-167BZXI
200
CY7C1372DV25-167BZXI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
CY7C1370DV25-200AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1372DV25-200AXC
CY7C1370DV25-200BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372DV25-200BGC
CY7C1370DV25-200BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-200BGXC
CY7C1370DV25-200BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372DV25-200BZC
CY7C1370DV25-200BZXC
CY7C1372DV25-200BZXC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
CY7C1370DV25-200AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
CY7C1372DV25-200AXI
CY7C1370DV25-200BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372DV25-200BGI
CY7C1370DV25-200BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-200BGXI
CY7C1370DV25-200BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372DV25-200BZI
CY7C1370DV25-200BZXI
CY7C1372DV25-200BZXI
Document #: 38-05558 Rev. *D
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
Page 22 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Ordering Information (continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
250
CY7C1370DV25-250AXC
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Commercial
CY7C1372DV25-250AXC
CY7C1370DV25-250BGC
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372DV25-250BGC
CY7C1370DV25-250BGXC 51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-250BGXC
CY7C1370DV25-250BZC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372DV25-250BZC
CY7C1370DV25-250BZXC
CY7C1372DV25-250BZXC
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
CY7C1370DV25-250AXI
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Industrial
CY7C1372DV25-250AXI
CY7C1370DV25-250BGI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1372DV25-250BGI
CY7C1370DV25-250BGXI
51-85115 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free
CY7C1372DV25-250BGXI
CY7C1370DV25-250BZI
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
CY7C1372DV25-250BZI
CY7C1370DV25-250BZXI
CY7C1372DV25-250BZXI
Document #: 38-05558 Rev. *D
51-85180 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)
Lead-Free
Page 23 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) (51-85050)
16.00±0.20
1.40±0.05
14.00±0.10
100
81
80
1
20.00±0.10
22.00±0.20
0.30±0.08
0.65
TYP.
30
12°±1°
(8X)
SEE DETAIL
A
51
31
50
0.20 MAX.
R 0.08 MIN.
0.20 MAX.
0.10
1.60 MAX.
0° MIN.
SEATING PLANE
STAND-OFF
0.05 MIN.
0.15 MAX.
0.25
NOTE:
1. JEDEC STD REF MS-026
GAUGE PLANE
0°-7°
R 0.08 MIN.
0.20 MAX.
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.60±0.15
0.20 MIN.
51-85050-*B
1.00 REF.
DETAIL
Document #: 38-05558 Rev. *D
A
Page 24 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Package Diagrams (continued)
119-Ball BGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
Document #: 38-05558 Rev. *D
Page 25 of 27
[+] Feedback
CY7C1370DV25
CY7C1372DV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.4 mm) (51-85180)
BOTTOM VIEW
BOTTOM VIEW
PIN 1 CORNER
PIN 1 CORNER
TOP VIEW
TOP VIEW
Ø0.05 M C
Ø0.05 M C
Ø0.25 M C A B
Ø0.25 M C A B
-0.06
Ø0.50 (165X) -0.06
Ø0.50
(165X)
+0.14
PIN 1 CORNER
PIN 1 CORNER
1
A
2
4
3
5
4
6
5
7
6
8
7
9
10
8
11
9
10
11
11
10
9
11
8
10
9
7
6
8
+0.14
2
4
3
D
H
J
K
K
M
N
L
7.00
7.00
L
M
M
N
N
P
P
P
R
R
R
A
A
A
5.00
1.00
5.00
10.00
B
B
13.00±0.10
13.00±0.10
0.35±0.06
0.35±0.06
SEATINGSEATING
PLANE PLANE
C
0.15 C
1.40 MAX.
0.15 C
0.53±0.05
1.40 MAX.
0.15(4X)
C
1
A
C
14.00
14.00
15.00±0.10
J
K
2
G
H
J
1
F
15.00±0.10
H
0.36
3
E
G
L
0.53±0.05
0.25 C
5
F
G
0.36
4
E
F
0.25 C
6
1.00
1.00
D
E
B
5
7
B
C
D
15.00±0.10
3
B
C
15.00±0.10
1
A
B
A
2
B
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1.00
10.00
13.00±0.10
13.00±0.10
0.15(4X)
NOTESNOTES
:
:
SOLDER
PAD TYPE
NON-SOLDER
MASK MASK
DEFINED
(NSMD)
SOLDER
PAD: TYPE
: NON-SOLDER
DEFINED
(NSMD)
PACKAGE
WEIGHT
: 0.475g
PACKAGE
WEIGHT
: 0.475g
JEDEC JEDEC
REFERENCE
:
MO-216
/
DESIGN
4.6C
REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE
CODE CODE
: BB0AC
PACKAGE
: BB0AC
51-85180-*A
51-85180-*A
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology, Inc. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05558 Rev. *D
Page 26 of 27
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C1370DV25
CY7C1372DV25
Document History Page
Document Title: CY7C1370DV25/CY7C1372DV25 18-Mbit (512K x 36/1M x 18)
Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05558
REV.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
254509
See ECN
RKF
New data sheet
*A
288531
See ECN
SYT
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for
non-compliance with 1149.1
Removed 225 Mhz Speed Bin
Added lead-free information for 100-Pin TQFP, 119 BGA and 165 FBGA
package
Added comment of ‘Lead-free BG packages availability’ below the Ordering
Information
*B
326078
See ECN
PCI
Address expansion pins/balls in the pinouts for all packages are modified as
per JEDEC standard
Added description on EXTEST Output Bus Tri-State
Changed description on the Tap Instruction Set Overview and Extest
Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and
4.08 °C/W respectively
Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2
°C/W respectively
Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and
4.0 °C/W respectively
Modified VOL, VOH test conditions
Removed comment of ‘Lead-free BG packages availability’ below the
Ordering Information
Updated Ordering Information Table
*C
418125
See ECN
NXR
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Changed the description of IX from Input Load Current to Input Leakage
Current on page# 18
Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA
to –30 µA and 5 µA
Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA
to –5 µA and 30 µA
Changed VIH < VDD to VIH < VDDon page # 18
Updated Ordering Information Table
*D
475677
See ECN
VKN
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP
AC Switching Characteristics table.
Updated the Ordering Information table.
Document #: 38-05558 Rev. *D
Page 27 of 27
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