ISO422 ISO 422 ISO 422 www.ti.com DIFFERENTIAL BUS TRANSCEIVER FEATURES DESCRIPTION ● FULL-/HALF-DUPLEX OPERATION ● 1500Vrms ISOLATION (cont) ● 2500Vrms ISOLATION (1 min) ISO422 provides 1500Vrms isolation for industrial bus transmission systems. ISO422 may be configured in full or half duplex modes providing the user with best flexibility for the application. Transmission rates of 2.5Mbps can be obtained covering most requirements. A loop-back test facility is included. LBE allows data on the D input to be routed to the R output for test purposes. ● 2.5Mbps PERFORMANCE ● LOOP-TEST FACILITY APPLICATIONS ● BUS TRANSMISSION SYSTEMS ● GROUND LOOP ISOLATION ISO422 is available in 24-pin PDIP and 24-pin Gull Wing packages and is specified over the temperature range –40°C to +85°C. DE Y D Z LBE A R B RE Copyright © 2000, Texas Instruments Incorporated SBOS113A Printed in U.S.A. November, 2000 SPECIFICATIONS At TA = +25°C, and VS = +5V, unless otherwise noted. ISO422P, P-U PARAMETER ISOLATION Rated Continuous Isolation Partial Discharge Voltage Barrier Impedance Leakage Current VISO CONDITIONS MIN 50Hz, 60Hz 1s, 5 x 5pC/per cycle(1) 1500 2500 5kV/µs Edge and DE Inputs(2) and DE Inputs(2) and DE Inputs(2) and DE Inputs(2) VY or VZ IOY or I OZ = 0 RL = 100Ω RL = 54Ω RL = 100Ω or 54Ω(3) RL = 100Ω or 54Ω RL = 100Ω or 54Ω(3) VO = VCC2, Output Disabled VO = 0V, Output Disabled VO = VCC2, Continuous VO = 0V, Continuous VIH VIL IL CIN VO VOD D D D D ∆|VOD| VOC ∆|VOC| IO Short-Circuit Output Current DRIVER SWITCHING CHARACTERISTICS Differential Output Delay Time Skew |tDDH - tDDL| Differential Output Transition Time Output Enable Time to HIGH Output Enable Time to LOW Output Disable Time from HIGH Output Disable Time from LOW RECEIVER DC CHARACTERISTICS High Level Output Voltage Low Level Output Voltage Output Short-Circuit Current Output HI-Z Leakage Enable Input HIGH Threshold Enable Input LOW Threshold Input Leakage Current Input Capacitance Differential Input HIGH Threshold Differential Input LOW Threshold Input Hysteresis Line Input Current Line Voltage Input Resistance (Figure 6) t DD tDT tDZH tDZL tDHZ tDLZ VOH VOL I OS I OZ VIH VIL IL CIN VTH VTL IBI VBI RIN 1 2 0.8 5 5 0 1.5 2 1.5 IOH = 6mA I OL = 6mA 1s max VOUT = 0V to VCC1 RE Input(2) RE Input(2) RE Input(2) RE Input(2) VO = 2.8V VO = 0.4V See Note 4 Power On (GNDB < VBI < VSB) Power Off (IBI ±10mA max) 3.6 2.8 ±40 ±40 ±10 ±10 100 –110 RL = 54Ω RL = 54Ω RL = 54Ω R L = 100Ω R L = 100Ω R L = 100Ω R L = 100Ω RECEIVER SWITCHING CHARACTERISTICS (Figure 7) Propagation Delay L to H tRLH VID = –1.5V to 1.5V, CL = 10pF Propagation Delay H to L tRHL VID = 1.5V to –1.5V, CL = 10pF Skew |tRLH - tRHL| Output Rise Time tR CL = 10pF Output Fall Time tF CL = 10pF Output Enable Time to HIGH tRZH CL = 10pF Output Enable Time to LOW tRZL CL = 10pF Output Disable Time from HIGH tRHZ CL = 10pF Output Disable Time from LOW tRLZ CL = 10pF 2 16 8.6 0.1 DRIVER DC CHARACTERISTICS High Level Input Voltage Low Level Input Voltage Input Leakage Current Input Capacitance Output Voltage Differential Output Voltage Change in Mag Diff Out Voltage Common-Mode Output Voltage Change in Mag CM Out Voltage Output Current MAX > 1014 || 10 1 240V, 60Hz 2500V, 50Hz Creepage Distance Internal Isolation Distance Transient Recovery Time TYP 120 25 120 120 120 120 5 5 5 5 ±200 3 ±200 ±1000 ±1000 150 50 100 150 150 150 150 VCC – 1 0.4 30 ±10 ±1000 2 0.8 –200 5 5 100 –100 60 ±10 ±12 200 ±1000 1 120 120 40 10 10 15 15 15 15 150 150 25 25 25 25 UNITS V V Ω || pF µA µA mm mm µs V V nA pF V V V V mV V mV nA nA mA mA ns ns ns ns ns ns ns V V mA nA V V nA pF mV mV mV nA V MΩ ns ns ns ns ns ns ns ns ns ISO422 SBOS113A SPECIFICATIONS (CONT) At TA = +25°C, and VS = +5V, unless otherwise noted. ISO422P, P-U PARAMETER CONDITIONS POWER Supply Voltage—Data Side Supply Current—Data Side Supply Current—Data Side Supply Voltage—Bus Side Supply Voltage—Bus Side VSA ISA ISA VSB ISB MIN TYP 4.5 Output Unloaded, dc Output Unloaded, max Rate 10 20 4.5 Output Unloaded, dc Output Unloaded, max Rate UNITS 5.5 13 V mA mA V mA mA 5.5 20 12 20 BUS LIMITS Input Current Maximum Differential Input Maximum Data Rate MAX ±10 ±5 mA V Mbps +85 +125 °C °C °C/W 2.5 TEMPERATURE RANGE Operating Storage Thermal Resistance –40 –40 θJA 75 NOTES: (1) All devices receive a 1s test. Failure criterion is > 5 pulses of > 5pC per cycle. (2) Logic inputs are HCT-type and thresholds are a function of power supply voltage with approximately 100mV hysteresis. (3) Change in magnitude when the input is changed from HIGH to LOW. (4) The difference between the differential low to high and high to low transition points. ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Top View DIP DE 1 24 RE D 2 23 R NC 3 22 LBE VSA 4 21 GNDA 9 16 VSB GNDB 10 15 VSB Y 11 14 A Z 12 13 B ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. BurrBrown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ISO422 GNDB Supply Voltage: VSA ............................................................. –0.5V to +6V VSB ............................................................. –0.5V to +6V Continuous Isolation Voltage ..................................................... 1500Vrms Storage Temperature ...................................................... –40°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) ISO422P ISO422P-U 24-Pin Plastic DIP 24-Pin Gull Wing Surface Mount 249-4 243-5 SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA –40°C to +85°C –40°C to +85°C ISO422P ISO422P-U ISO422P ISO422P-U Rails Rails NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ISO422 SBOS113A 3 TYPICAL PERFORMANCE CURVES At TA = +25°C, and VS = +5V, unless otherwise noted. BUS 0 TO 1 TRANSITION PROPAGATION DELAY Y-Z D Z Y-Z Y 20ns/div 2µs/div BUS 1 TO 0 TRANSITION TERMINATED 200m CABLE Y-Z Y-Z Y Z Z Y 20ns/div 50ns/div 2kΩ RESISTORS INSERTED IN TERMINATED CABLE Y-Z Z Y 200ns/div 4 ISO422 SBOS113A OPERATION ISO422 is an isolated, full-duplex bus transceiver which is compatible with three-wire data bus systems using EIA standards RS-422-A and RS-485. It is based on Burr-Brown’s capacitive barrier technology. The data bus input is designed to present a very high impedance to the data bus, thus allowing a virtually unlimited number of receivers on any data bus section. To allow this feature, the data bus input is limited to a common-mode range within the magnitude of the supplies. This limitation requires that all nodes on the bus are referenced to a common ground. However, systems attached to the bus through ISO422, are isolated up to 1500Vrms and may, therefore, have local floating ground potentials up to this isolation voltage. The circuit encodes all data passed across the barrier to ensure that the input values and control signals are correctly passed across the barrier under all power up conditions. The ISO422 also allows data recovery to the current input state, after any transient upset. TRANSMIT Data is passed from the D input to the data bus outputs after a barrier transmission delay (tDD) when the DE input is HIGH. When DE is LOW, the data bus drivers are switched off, and assume the high impedance state. When enabling the data bus output, i.e., switching DE from LOW to HIGH, the enable signal is passed directly across the barrier and enables the output, after a barrier transmission delay and output enable time (tDLZ/tDHZ). Similarly, when disabling the data bus output, i.e., switching DE from HIGH to LOW, the disable signal is passed directly across the barrier and disables the output after a barrier transmission delay and output disable time (tDLZ/tDHZ). DE D tDZL tDD tDD tDLZ tDZH tDHZ active. The receive enable/disable time is simply the time to enable/disable the R output (tRLZ) and does not require any additional barrier transmission time. RE tRZH tRLZ tRZL tRZH R tRLH tRHL A B FIGURE 2. ISO422 Data Receive. DATA CORRUPTION If, due to transient upset, the data passed across the barrier is corrupted, the data will be restored within 100ns from the end of the corrupting signal. SYNCHRONIZATION The data transmitted across the barrier is coded using an internal clock. This clock also captures the incoming asynchronous data and synchronizes it to the clock edges. This will give rise to an rms propagation delay jitter of approximately 50ns. LOOPBACK A loopback function is provided by the LBE input. If this input is HIGH, then enabling both the transmitter and the receiver will cause the device to route the D input to the R output, in addition to the data bus outputs. Data on the incoming bus is ignored. This feature allows a simple connection test to be performed during any application. When LBE is LOW, transmit and receive will operate in the normal full-duplex mode. Y DATA BUS CONNECTION Z FIGURE 1. ISO422 Data Transmit. RECIEVE The receive data is determined by the data bus differential signal after a barrier transmission delay (tRZL). When the difference between the A input and the B input (A-B) is greater than +200mV, the R output will be HIGH. If A-B is more negative than –200mV, the R output is undefined. Since the reciver has a high impedance input, no disable signal is required for the data bus input, which is always ISO422 SBOS113A ISO422 can be used in half duplex, or full duplex data communication bus systems. It is capable of continuously driving a 54Ω load, equivalent to a double-terminated transmission line, at the fully specified data rate. When connecting to the data bus, the voltage on the A and B input lines must remain between VSB and GNDB. This can be achieved by using a common bus ground connection, such as GNDB, as shown in Figures 5 and 6. For any system connected to the bus, the isolation provided by ISO422 allows the independent local ground potential to be as high as 1500Vrms with respect to the date bus ground reference. This feature replaces the limited +12V to –7V range of the RS-485 standard with the full-isolation voltage capability of the ISO422. 5 DE 1 24 RE DE 1 24 RE D 2 23 R D 2 23 R NC 3 22 LBE NC 3 22 LBE VCC 4 21 GNDA VCC 4 21 GNDA GNDB 9 16 VCC GNDB 9 16 VCC GNDB 10 15 VCC GNDB 10 15 VCC Y 11 14 A Y 11 14 A Z 12 13 B Z 12 13 B Loopback Enabled Transmit and Receive Active Loopback Disabled Transmit and Receive Active FIGURE 3. Loopback. CONNECTION TO CAN BUS Since the bus can be enabled and disabled at the same rate as the data (2.5MHz), it is possible to use ISO422 as an isolated bus driver in CAN systems. Again, the ISO422 bus line must be constrained within the supply voltages. Figure 4 shows the connections which allow ISO422 to be used in CANbus systems. The DE input of the ISO422 is used as the CAN TX0 input and is used to transmit the data by enabling and disabling the Y and Z outputs. The D and RE inputs of the ISO422 are tied to GNDA. This ensures that the Y output can only pull down, and the Z output can only pull up. With D tied to GNDA, the DE input of ISO422 (TX0 of CAN) activates the Y output as an open drain pull-down driver, and activates the Z output as an open drain pull-up driver. Therefore, the Y line acts as CANL and the Z line acts as CANH. When DE (TX0) is HIGH, ISO422 makes the bus state dominant i.e., Y pulls LOW and Z pulls HIGH. With DE (TX0) LOW, Y and Z are high impedance and the bus state is recessive. Data is received in the normal manner which is half duplex. Line A is connected to CANH, and line B is connected to CANL. The R output becomes RX0. RE is tied to GNDA to keep R (RX0) enabled. If required, RE may be used to disable the RX0 output. 6 DE Y CANH D Z TX0 A R RX0 RE B CANL ISO422 FIGURE 4. CANBus Connection. TX0 CANH CANL BUS H H L Dominant RX0 L L Hi-Z Hi-Z Recessive H TABLE I. CAN. ISO422 SBOS113A Shielded Twisted Pair EIA485 GNDB GNDB FIGURE 5. Half-Duplex Connection. Shielded Twisted Pair EIA485 GNDB GNDB FIGURE 6. Full-Duplex Connection. ISO422 SBOS113A 7 R 120Ω 1.2kΩ 1.2kΩ Half-duplex and Full-duplex resistor values are the same. Half-duplex line should be terminated at both ends. Half Duplex Full Duplex FIGURE 7. Suggested Bus Termination Methods. +5V +5V MAX202 MAX202 +5V Isolated 1.2kΩ(1) D9 D25 3 2 TD 2 3 RD 5 7 SG 4 20 DTR 6 6 DSR 1 8 CD 7 4 RTS 8 5 CTS 8 9 7 10 +5V Isolated 1.2kΩ(1) R 120Ω R 120Ω ISO422 1.2kΩ(1) 1.2kΩ(1) 10 7 9 8 RD ISO422 TD SG DTR GNDA GND Isolation GND Isolation GNDB DSR CD RTS CTS NOTE: (1) If using screened cable or ground wire, connected as shown, shaded resistors may be omitted. If using only twisted pairs, shaded resistors are recommended. FIGURE 8. Isolated RS232 to RS422. Null Modem Configuration. 8 ISO422 SBOS113A IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated