CYPRESS CY7C1355B

CY7C1355B
CY7C1357B
9-Mb (256K x 36/512K x 18) Flow-Through
SRAM with NoBL™ Architecture
Features
• JTAG boundary scan for BGA and fBGA packages
• No Bus Latency™ (NoBL™) architecture eliminates
dead cycles between write and read cycles.
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 7.0 ns (for 117-MHz device)
— 7.5 ns (for 100-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and
165-Ball fBGA packages
• Three chip enables for simple depth expansion.
• Automatic Power-down feature available using ZZ
mode or CE deselect.
• Burst Capability—linear or interleaved burst order
• Low standby power
Functional Description[1]
The CY7C1355B/CY7C1357B is a 3.3V, 256K x 36/ 512K x 18
Synchronous Flow-through Burst SRAM designed specifically
to support unlimited true back-to-back Read/Write operations
without
the
insertion
of
wait
states.
The
CY7C1355B/CY7C1357B is equipped with the advanced No
Bus Latency (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data through the SRAM, especially in systems that require
frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Selection Guide
133 MHz
117 MHz
100 MHz
Unit
Maximum Access Time
6.5
7.0
7.5
ns
Maximum Operating Current
250
220
180
mA
Maximum CMOS Standby Current
30
30
30
mA
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05117 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised January 27, 2004
CY7C1355B
CY7C1357B
1
Logic Block Diagram – CY7C1355B (256K x 36)
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
CE
C
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
BWA
BWA1,
B
A0,
A
BWC
A0
BWMODE
D
CLK
CEN
WRITE
DRIVERS
WRITE REGISTRY
ADDRESS AND DATA COHERENCY
CONTROL LOGIC
A1
REGISTER
CE
WEC
D1
D0
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
INPUT
E
REGISTER
SLEEP
CONTROL
ADV/LD
BWA
WRITE
DRIVERS
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWB
MEMORY
ARRAY
Logic Block Diagram – CY7C1357B (512K x 18)
A0, A1, AWE
ADDRESS
REGISTER
A1
D1
A0
D0
MODE
CLK
CEN
CE
C
OE
CE1
CE2
CE3
ZZ
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
BWB
Document #: 38-05117 Rev. *B
E
WRITELOGIC
ADDRESS
READ
REGISTER
SLEEP
CONTROL
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
DQs
DQPA
DQPB
INPUT E
REGISTER
ADV/LD
BWA
E
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
A
M
P
S
DQs
DQPA
DQPB
DQPC
DQPD
O
U
T
P
U
T
D
A
T
A
S
E
N
S
E
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
READ LOGIC
ZZ
2
MEMORY
ARRAY
A
M
P
S
WRITE ADDRESS
REGISTER
OE
CE1
CE2
CE3
D
A
T
A
S
E
N
S
E
ADV/LD
O
U
T
P
U
T
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
E
INPUT
E
REGISTER
READ LOGIC
SLEEP
CONTROL
Page 2 of 33
CY7C1355B
CY7C1357B
Pin Configurations
Document #: 38-05117 Rev. *B
A
81
A
82
A
83
84
NC / 18M
ADV/LD
85
OE
86
CEN
VSS
90
87
VDD
91
WE
CE3
92
CLK
BWA
93
89
BWC
BWB
BWD
96
94
CE2
97
95
CE1
A
98
88
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
A
NC / 36M
49
43
NC / 72M
A
42
48
41
VDD
47
40
VSS
A
39
NC / 144M
A
38
NC / 288M
46
37
A0
A
36
A1
45
35
A
A
34
A
A
33
A
44
32
A
CY7C1355B
31
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
Vss/DNU
VDD
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
99
100
A
100-lead TQFP
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 3 of 33
CY7C1355B
CY7C1357B
Pin Configurations (continued)
Document #: 38-05117 Rev. *B
A
81
A
82
A
83
84
NC / 18M
ADV/LD
85
OE
86
90
CEN
VSS
91
87
VDD
92
WE
CE3
93
CLK
BWA
94
89
NC
BWB
95
NC
CE2
97
96
CE1
A
98
88
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
A
NC / 36M
49
43
NC / 72M
A
42
48
41
VDD
47
40
VSS
A
39
NC / 144M
A
38
NC / 288M
46
37
A0
A
36
A1
45
35
A
A
34
A
A
33
A
44
32
A
CY7C1357B
31
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
Vss/DNU
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
NC
NC
NC
99
100
A
100-lead TQFP
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
BYTE A
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 4 of 33
CY7C1355B
CY7C1357B
Pin Configurations (continued)
119-ball BGA (3 Chip Enables with JTAG)
1
CY7C1355B (256K x 36)
3
4
5
A
NC / 18M
A
A
VDDQ
2
A
B
C
NC
NC
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
D
E
DQC
DQC
DQPC
DQC
VSS
VSS
NC
CE1
VSS
VSS
DQPB
DQB
DQB
DQB
F
VDDQ
DQC
VSS
VSS
DQB
VDDQ
G
H
J
K
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
DQD
BWC
VSS
NC
VSS
BWB
VSS
NC
VSS
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
BWA
VSS
DQA
DQA
DQA
VDDQ
VSS
DQA
DQA
OE
A
WE
VDD
CLK
NC
6
A
7
VDDQ
L
DQD
DQD
M
VDDQ
DQD
BWD
VSS
N
DQD
DQD
VSS
CEN
A1
P
DQD
DQPD
VSS
A0
VSS
DQPA
DQA
R
NC
A
MODE
VDD
NC
A
NC
T
U
NC
VDDQ
NC / 72M
TMS
A
TDI
A
TCK
A
TDO
NC / 36M
NC
ZZ
VDDQ
3
4
5
6
7
A
NC / 18M
A
A
VDDQ
ADV/LD
VDD
A
CE3
A
NC
A
CY7C1357B (512K x 18)
1
2
A
VDDQ
A
B
NC
CE2
A
C
NC
A
A
D
DQB
NC
VSS
NC
VSS
DQPA
NC
E
NC
DQB
VSS
CE1
VSS
NC
DQA
OE
A
VSS
DQA
VDDQ
NC
DQA
VDD
DQA
NC
VDDQ
NC
F
VDDQ
NC
VSS
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
BWB
VSS
NC
WE
VDD
VSS
VSS
NC
K
NC
DQB
VSS
CLK
VSS
NC
DQA
L
M
DQB
VDDQ
NC
DQB
VSS
VSS
NC
BWA
VSS
DQA
NC
NC
VDDQ
N
DQB
NC
VSS
CEN
A1
VSS
DQA
NC
P
NC
DQPB
VSS
A0
VSS
NC
DQA
R
T
U
NC
NC / 72M
VDDQ
A
A
TMS
MODE
A
TDI
VDD
NC / 36M
TCK
NC
A
TDO
A
A
NC
NC
ZZ
VDDQ
Document #: 38-05117 Rev. *B
Page 5 of 33
CY7C1355B
CY7C1357B
Pin Configurations (continued)
165-ball fBGA (3 Chip enable with JTAG)
CY7C1355B (256K x 36)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
A
CE1
BWC
BWB
CE3
CEN
ADV/LD
A
A
NC
R
NC
A
CE2
BWD
BWA
CLK
WE
OE
NC / 18M
A
NC / 144M
DQPC
DQC
NC
DQC
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VSS
VDD
VDDQ
NC
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
NC
DQD
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
DQB
DQB
DQC
VDD
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
NC / 72M
A
A
TDI
NC
A1
VSS
NC
TDO
A
A
A
NC
MODE
NC / 36M
A
A
TMS
A0
TCK
A
A
A
A
CY7C1357B (512K x 18)
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC / 288M
1
A
CE1
BWB
NC
CE3
CEN
ADV/LD
A
A
A
NC
A
CE2
NC
BWA
CLK
WE
OE
NC / 18M
A
NC / 144M
NC
NC
NC
DQB
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC
NC
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
DQB
DQB
VDD
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
NC
NC / 72M
A
A
R
MODE
NC / 36M
A
A
Document #: 38-05117 Rev. *B
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
TDI
NC
A1
TDO
A
A
A
NC
TMS
A0
TCK
A
A
A
A
Page 6 of 33
CY7C1355B
CY7C1357B
CY7C1355B–Pin Definitions
Name
TQFP
BGA
fBGA
I/O
A0, A1, A
37,36,32,33,
34,35,44,45,
46,47,48,49,
50,81,82,83,
99,100
P4,N4,A2,
C2,R2,A3,
B3,C3,T3,
G4,T4,A5,
B5,C5,T5,
A6,C6,R6
R6,P6,A2,
A9,A10,B2,
B10,P3,P4,
P8,P9,P10,
R3,R4,R8,
R9,R10,R11
InputSynchronous
Address Inputs used to select one of the 256K
address locations. Sampled at the rising edge of the
CLK. A[1:0] are fed to the two-bit burst counter.
BWA, BWB
93,94,95,96 L5,G5,G3,
L3
B5,A5,A4,
B4
InputSynchronous
Byte Write Inputs, active LOW. Qualified with WE to
conduct Writes to the SRAM. Sampled on the rising edge
of CLK.
BWC, BWD
Description
WE
88
H4
B7
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
ADV/LD
85
B4
A8
InputSynchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK
89
K4
B6
InputClock
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.
98
E4
A3
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE2, and CE3 to
select/deselect the device.
CE2
97
B2
B3
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE3 to
select/deselect the device.
CE3
92
B6
A6
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE2 to
select/deselect the device.
OE
86
F4
B8
InputOutput Enable, asynchronous input, active LOW.
Asynchronous Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW,
the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as
input data pins. OE is masked during the data portion of
a write sequence, during the first clock when emerging
from a deselected state, when the device has been deselected.
87
M4
A7
InputSynchronous
64
T7
H11
InputZZ “Sleep” Input. This active HIGH input places the deAsynchronous vice in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be
connected to VSS or left floating.
CE1
CEN
ZZ
Document #: 38-05117 Rev. *B
Clock Enable Input, active LOW. When asserted LOW
the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
Page 7 of 33
CY7C1355B
CY7C1357B
CY7C1355B–Pin Definitions (continued)
Name
DQs
DQP[A:D]
MODE
TQFP
52,53,56,57,
58,59,62,63,
68,69,72,73,
74,75,78,79,
2,3,6,7,8,9,
12,13,18,19,
22,23,24,25,
28,29
BGA
fBGA
K6,L6,M6, M11,L11,
K11,J11,
N6,K7,L7,
N7,P7,E6, J10,K10,
F6,G6,H6, L10,M10,
D7,E7,G7, D10,E10,
H7,D1,E1, F10,G10,
G1,H1,E2, D11,E11,
F2,G2,H2, F11,G11,
K1,L1,N1, D1,E1,F1,
P1,K2,L2, G1,D2,E2,
F2,G2,J1,
M2,N2
K1,L1,M1,
J2,K2,L2
M2,
51,80,1,30 P6,D6,D2, N11,C11,C1,
P2
N1
31
R3
R1
VDD
15,41,65,91 J2,C4,J4,
R4,J6
D4,D8,E4,
E8,F4,F8,
G4,G8,H2,
H4,H8,J4,
J8,K4,K8,
L4,L8,M4,
M8
VDDQ
4,11,20,27, A1,F1,J1,
54,61,70,77 M1,U1,
A7,F7,J7,
M7,U7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
VSS
5,10,17,21, D3,E3,F3, C4,C5,C6,
26,40,55,60, H3,K3,
C7,C8,D5,
D6,D7,E5,
67,71,76,90 M3,N3,
P3,D5,E5, E6,E7,F5,
F5,H5,K5, F6,F7,G5,
M5,N5,P5 G6,G7,H5,
H6,H7,J5,
J6,J7,K5,K6,
K7,L5,L6,L7,
M5,M6,M7,
N4,N8
TDO
-
U5
P7
TDI
-
U3
P5
Document #: 38-05117 Rev. *B
I/O
Description
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge
of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented
during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs
and DQP[A:D] are placed in a three-state condition.The
outputs are automatically three-stated during the data
portion of a Write sequence, during the first clock when
emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
I/OSynchronous
Bidirectional Data Parity I/O Lines. Functionally, these
signals are identical to DQs. During Write sequences,
DQP[A:D] is controlled by BW[A:D] correspondingly.
Input Strap Pin Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When
tied to VDD or left floating selects interleaved burst
sequence.
Power Supply Power supply inputs to the core of the device.
I/O Power
Supply
Ground
JTAG serial
output
Synchronous
JTAG serial
input
Synchronous
Power supply for the I/O circuitry.
Ground for the device.
Serial data-out to the JTAG circuit. Delivers data on the
negative edge of TCK. If the JTAG feature is not being
utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be left floating or connected to VDD through a pull
up resistor. This pin is not available on TQFP packages.
Page 8 of 33
CY7C1355B
CY7C1357B
CY7C1355B–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
I/O
Description
TMS
-
U2
R5
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be disconnected or connected to VDD. This pin is
not available on TQFP packages.
TCK
-
U4
R7
JTAG-Clock
Clock input to the JTAG circuitry. If the JTAG feature is
not being utilized, this pin must be connected to VSS. This
pin is not available on TQFP packages.
-
No Connects. Not internally connected to the die.
18M,36M, 72M, 144M and 288M are address expansion
pins and are not internally connected to the die.
NC
VSS/DNU
16,38,39,42, B1,C1,R1, A1,A11,B1,
43,66,84
T1,T2,J3, B9,B11,C2,
A4,D4,L4, C10,H1,H3,
J5,R5,T6, H9,H10,N2,
U6,B7,C7, N5,N6,N7,
R7
N10,P1,P2,
P11,R2
14
-
-
Ground/DNU
This pin can be connected to Ground or should be left
floating.
CY7C1357B–Pin Definitions
Name
TQFP
BGA
fBGA
I/O
Description
A0, A1, A
37,36,32,33,
34,35,44,45,
46,47,48,49,
50,80,81,82,
83,99,100
P4,N4,A2,
C2,R2,T2,
A3,B3,C3,
T3,A5,B5,
C5,T5,A6,
C6,R6,T6
R6,P6,A2,
A9,A10,A11,
B2,B10,P3,
P4,P8,P9,
P10,R3,R4,
R8,R9,R10,
R11
InputSynchronous
Address Inputs used to select one of the 512K address
locations. Sampled at the rising edge of the CLK. A[1:0]
are fed to the two-bit burst counter.
BWA,BWB
93,94
G3,L5
B5,A4
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with WE
to conduct Writes to the SRAM. Sampled on the rising
edge of CLK.
WE
88
H4
B7
InputSynchronous
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a Write sequence.
ADV/LD
85
B4
A8
InputSynchronous
Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
CLK
89
K4
B6
InputClock
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW.
98
E4
A3
InputSynchronous
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE2, and CE3 to
select/deselect the device.
CE2
97
B2
B3
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE3 to
select/deselect the device.
CE3
92
B6
A6
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE1 and CE2 to
select/deselect the device.
CE1
Document #: 38-05117 Rev. *B
Page 9 of 33
CY7C1355B
CY7C1357B
CY7C1357B–Pin Definitions (continued)
Name
TQFP
BGA
fBGA
OE
86
F4
B8
InputOutput Enable, asynchronous input, active LOW.
Asynchronous Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW,
the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a
deselected state, when the device has been deselected.
CEN
87
M4
A7
InputSynchronous
ZZ
64
T7
H11
InputZZ “Sleep” Input, active HIGH. When asserted HIGH
Asynchronous places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
DQs
DQP[A:B]
MODE
58,59,62,63,
68,69,72,73,
8,9,12,13,
18,19,22,23
P7,K7,G7, J10,K10,
E7,F6,H6, L10,M10,
L6,N6,D1, D11,E11,
H1,L1,N1, F11,G11,J1,
E2,G2,K2, K1,L1,M1,
M2
D2,E2,F2,
G2
74,24
D6,P2
C11,N1
31
R3
R1
VDD
15,41,65,91 C4,J2,J4,
J6,R4
D4,D8,E4,
E8,F4,F8,
G4,G8,H2,
H4,H8,J4,
J8,K4,K8,
L4,L8,M4,
M8
VDDQ
4,11,20,27, A1,A7,F1,
54,61,70,77 F7,J1,J7,
M1,M7,U1
,U7
C3,C9,D3,
D9,E3,E9,
F3,F9,G3,
G9,J3,J9,
K3,K9,L3,
L9,M3,M9,
N3,N9
Document #: 38-05117 Rev. *B
I/O
Description
Clock Enable Input, active LOW. When asserted LOW
the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an
on-chip data register that is triggered by the rising edge of
CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented
during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs
and DQP[A:B] are placed in a three-state condition.The
outputs are automatically three-stated during the data portion of a Write sequence, during the first clock when
emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
I/OSynchronous
Bidirectional Data Parity I/O Lines. Functionally, these
signals are identical to DQs. During Write sequences,
DQP[A:B] is controlled by BW[A:B] correspondingly.
Input Strap Pin Mode Input. Selects the burst order of the device.
When tied to Gnd selects linear burst sequence. When
tied to VDD or left floating selects interleaved burst
sequence.
Power Supply Power supply inputs to the core of the device.
I/O Power
Supply
Power supply for the I/O circuitry.
Page 10 of 33
CY7C1355B
CY7C1357B
CY7C1357B–Pin Definitions (continued)
Name
VSS
TQFP
BGA
fBGA
5,10,17,21, D3,D5,E3, C4,C5,C6,
26,40,55,60, E5,F3,F5, C7,C8,D5,
D6,D7,E5,
67,71,76,90 G5,H3,
H5,K3,K5, E6,E7,F5,
F6,F7,G5,
L3,M3,
G6,G7,H5,
M5,N3,
N5,P3,P5 H6,H7,J5,
J6,J7,K5,K6,
K7,L5,L6,L7,
M5,M6,M7,
N4,N8
I/O
Ground
Ground for the device.
TDO
-
U5
P7
TDI
-
U3
P5
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be left floating or connected to VDD through a pull
up resistor. This pin is not available on TQFP packages.
TMS
-
U2
R5
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising
edge of TCK. If the JTAG feature is not being utilized, this
pin can be disconnected or connected to VDD. This pin is
not available on TQFP packages.
TCK
-
U4
R7
JTAG-Clock
Clock input to the JTAG circuitry. If the JTAG feature is
not being utilized, this pin must be connected to VSS. This
pin is not available on TQFP packages.
NC
1,2,3,6,7,16,
25,28,29,30,
38,39,42,43,
51,52,53,56,
57,66,75,78,
79,84,95,96
A4,B1,B7,
C1,C7,D2,
D4,D7,E1,
E6,H2,F2,
G1,G6,
H7,J3,J5,
K1,K6,L4,
L2,L7,M6,
N2,N7,L7,
P1,P6,R1,
R5,R7,T1,
T4,U6
A1,A5,B1,
B4,B9,B11,
C1,C2,C10,
D1,D10,E1,
E10,F1,F10,
G1,G10,H1,
H3,H9,H10,
J2,J11,K2,
K11,L2,L11,
M2,M11,N2,
N5,N6,N7,
N10,N11,P1,
P2,P11,R2
-
No Connects. Not internally connected to the die.
18M,36M, 72M, 144M and 288M are address expansion
pins and are not internally connected to the die.
14
-
-
Ground/DNU
VSS/DNU
Document #: 38-05117 Rev. *B
JTAG serial
output
Synchronous
Description
Serial data-out to the JTAG circuit. Delivers data on the
negative edge of TCK. If the JTAG feature is not being
utilized, this pin should be left unconnected. This pin is not
available on TQFP packages.
This pin can be connected to Ground or should be left
floating.
Page 11 of 33
CY7C1355B
CY7C1357B
Functional Overview
The CY7C1355B/CY7C1357B is a synchronous flow-through
burst SRAM designed specifically to eliminate wait states
during Write-Read transitions. All synchronous inputs pass
through input registers controlled by the rising edge of the
clock. The clock signal is qualified with the Clock Enable input
signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous
operations are qualified with CEN. Maximum access delay
from the clock rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BWX can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed Write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Read Accesses
The CY7C1355B/CY7C1357B has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
Document #: 38-05117 Rev. *B
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enable inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to the address bus
is loaded into the address register. The write signals are
latched into the Control Logic block. The data lines are
automatically three-stated regardless of the state of the OE
input signal. This allows the external logic to present the data
on DQs and DQPX.
On the next clock rise the data presented to DQs and DQPX
(or a subset for byte write operations, see Truth Table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BWX signals. The CY7C1355B/CY7C1357B provides byte
write capability that is described in the Truth Table. Asserting
the Write Enable input (WE) with the selected Byte Write
Select input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations. Byte Write
capability has been included in order to greatly simplify
Read/Modify/Write sequences, which can be reduced to
simple Byte Write operations.
Because the CY7C1355B/CY7C1357B is a common I/O
device, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQs and DQPX inputs.
Doing so will three-state the output drivers. As a safety
precaution, DQs and DQPX are automatically three-stated
during the data portion of a write cycle, regardless of the state
of OE.
Burst Write Accesses
The CY7C1355B/CY7C1357B has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four Write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subsequent clock rise, the Chip Enables (CE1, CE2, and CE3) and
WE inputs are ignored and the burst counter is incremented.
The correct BWX inputs must be driven in each cycle of the
burst write, in order to write the correct bytes of data.
Page 12 of 33
CY7C1355B
CY7C1357B
Interleaved Burst Address Table
(MODE = Floating or VDD)
.
Linear Burst Address Table
(MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
01
00
10
11
11
10
01
11
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
11
10
00
01
10
11
00
01
01
10
11
00
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
.
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD – 0.2V
35
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
tZZI
ZZ active to snooze current
This parameter is sampled
tRZZI
ZZ Inactive to exit snooze current
This parameter is sampled
Document #: 38-05117 Rev. *B
2tCYC
ns
2tCYC
0
ns
ns
Page 13 of 33
CY7C1355B
CY7C1357B
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Address
Used
CE1 CE2 CE3 ZZ
None
H
X
X
L
ADV/LD
L
WE
X
BWX
X
OE
X
DQ
CEN CLK
L
L->H Three-State
Deselect Cycle
None
X
X
H
L
L
X
X
X
L
L->H Three-State
Deselect Cycle
None
X
L
X
L
L
X
X
X
L
L->H Three-State
Continue Deselect Cycle
None
X
X
X
L
H
X
X
X
L
L->H Three-State
External
L
H
L
L
L
H
X
L
L
L->H Data Out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data Out (Q)
External
L
H
L
L
L
H
X
H
L
L->H Three-State
Next
X
X
X
L
H
X
X
H
L
L->H Three-State
External
L
H
L
L
L
L
L
X
L
L->H Data In (D)
WRITE Cycle
(Continue Burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data In (D)
NOP/WRITE ABORT
(Begin Burst)
None
L
H
L
L
L
L
H
X
L
L->H Three-State
WRITE ABORT
(Continue Burst)
Next
X
X
X
L
H
X
H
X
L
L->H Three-State
IGNORE CLOCK
EDGE (Stall)
Current
X
X
X
L
X
X
X
X
H
L->H
-
SNOOZE MODE
None
X
X
X
H
X
X
X
X
X
X
Three-State
READ Cycle
(Begin Burst)
READ Cycle
(Continue Burst)
NOP/DUMMY READ
(Begin Burst)
DUMMY READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired Byte Write
Selects are asserted, see Truth Table for details.
3. Write is defined by BWX, and WE. See Truth Table for Read/Write.
4. When a Write cycle is detected, all I/Os are three-stated, even during Byte Writes.
5. The DQs and DQPX pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQs and DQPX = Three-state when
OE is inactive or when the device is deselected, and DQs and DQPX = data when OE is active.
9. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05117 Rev. *B
Page 14 of 33
CY7C1355B
CY7C1357B
Partial Truth Table for Read/Write[2, 3, 9]
Function (CY7C1355B)
WE
H
BWA
X
BWB
X
BWC
X
BWD
X
Write No bytes written
L
H
H
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
L
L
H
H
H
L
H
L
H
H
Write Byte C – (DQC and DQPC)
L
H
H
L
H
Write Byte D – (DQD and DQPD)
L
H
H
H
L
Write All Bytes
L
L
L
L
L
Read
Truth Table for Read/Write[2, 3]
Function (CY7C1357B)
Read
WE
H
BWA
X
BWB
X
Write - No bytes written
L
H
H
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
L
H
H
L
H
H
Write All Bytes
L
L
L
Document #: 38-05117 Rev. *B
Page 15 of 33
CY7C1355B
CY7C1357B
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test MODE SELECT (TMS)
The CY7C1355B/CY7C1357B incorporates a serial boundary
scan test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These functions
from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of
the SRAM. Note that the TAP controller functions in a manner
that does not conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
The CY7C1355B/CY7C1357B contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure .
TDI is internally pulled up and can be unconnected if the TAP
is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
1
0
Bypass Register
TEST-LOGIC
RESET
2 1 0
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
1
CAPTURE-DR
0
TDO
x . . . . . 2 1 0
SHIFT-IR
0
Boundary Scan Register
1
EXIT1-DR
1
EXIT1-IR
0
1
TCK
0
PAUSE-DR
0
PAUSE-IR
1
0
TMS
TAP CONTROLLER
1
EXIT2-DR
0
EXIT2-IR
1
Performing a TAP Reset
1
UPDATE-DR
0
UPDATE-IR
1
0
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Document #: 38-05117 Rev. *B
Selection
Circuitry
Identification Register
CAPTURE-IR
1
Instruction Register
31 30 29 . . . 2 1 0
0
SHIFT-DR
1
TDI
Selection
Circuitry
0
0
0
1
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Page 16 of 33
CY7C1355B
CY7C1357B
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
Boundary Scan Register
IDCODE
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The SRAM has a 71-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
TAP Instruction Set
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Document #: 38-05117 Rev. *B
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold time (tCSplus tCH).
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
Page 17 of 33
CY7C1355B
CY7C1357B
BYPASS
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
Test Clock
(TCK)
3
t TH
t TMSS
t TMSH
t TDIS
t TDIH
t
TL
4
5
6
t CYC
Test Mode Select
(TMS)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the operating Range[10, 11]
Parameter
Description
Clock
TCK Clock Cycle Time
tTCYC
tTF
TCK Clock Frequency
TCK Clock HIGH time
tTH
TCK Clock LOW time
tTL
Output Times
TCK Clock LOW to TDO Valid
tTDOV
TCK Clock LOW to TDO Invalid
tTDOX
Set-up Times
TMS Set-Up to TCK Clock Rise
tTMSS
TDI Set-Up to TCK Clock Rise
tTDIS
tCS
Capture Set-Up to TCK Rise
Hold Times
TMS hold after TCK Clock Rise
tTMSH
tTDIH
TDI Hold after Clock Rise
Capture Hold after Clock Rise
tCH
Min.
Max.
50
20
25
25
5
0
Unit
ns
MHz
ns
ns
ns
ns
5
5
5
ns
ns
5
5
5
ns
ns
ns
Notes:
10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document #: 38-05117 Rev. *B
Page 18 of 33
CY7C1355B
CY7C1357B
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ........ ........................................VSS to 3.3V
Input pulse levels........ ........................................VSS to 2.5V
Input rise and fall times ..................... ..............................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels ...........................................1.5V
Input timing reference levels................... ......................1.25V
Output reference levels...................................................1.5V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage...............................1.5V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; VDD = 3.3V ±0.165V unless otherwise noted)[12]
Parameter
Description
Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = –4.0 mA
VDDQ = 3.3V
2.4
V
IOH = –1.0 mA
VDDQ = 2.5V
2.0
V
VOH2
Output HIGH Voltage
IOH = –100 µA
VDDQ = 3.3V
2.9
V
VDDQ = 2.5V
2.1
VOL1
Output LOW Voltage
IOL = 8.0 mA
VDDQ = 3.3V
0.4
V
IOL = 8.0 mA
VDDQ = 2.5V
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
VDDQ = 3.3V
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Load Current
VDDQ = 2.5V
0.2
V
2.0
VDD + 0.3
V
VDDQ = 2.5V
1.7
VDD + 0.3
V
VDDQ = 3.3V
–0.5
0.7
V
VDDQ = 2.5V
–0.3
0.7
V
–5
5
µA
VDDQ = 3.3V
GND < VIN < VDDQ
V
Note:
12. All voltages referenced to VSS (GND).
Document #: 38-05117 Rev. *B
Page 19 of 33
CY7C1355B
CY7C1357B
Identification Register Definitions
CY7C1355B
(256KX36)
CY7C1357B
(512KX18)
001
001
Device Depth (28:24)
01010
01010
Device Width (23:18)
000000
000000
Defines memory type and architecture
Cypress Device ID (17:12)
100110
010110
Defines width and density
00000110100
00000110100
1
1
Instruction Field
Revision Number (31:29)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Description
Describes the version number
Reserved for Internal Use
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Scan Register Sizes
Bit Size (x36)
Bit Size (x18)
Instruction
3
3
Bypass
1
1
Register Name
ID
32
32
Boundary Scan Order
71
71
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Document #: 38-05117 Rev. *B
Page 20 of 33
CY7C1355B
CY7C1357B
119-Ball BGA Boundary Scan Order
CY7C1355B (256K x 36)
CY7C1357B (512K x 18)
BIT
#
BALL
ID
Signal
Name
BIT
#
BALL
ID
Signal
Name
BIT#
BALL ID
Signal
Name
BIT#
BALL ID
Signal
Name
1
K4
CLK
37
R6
A
1
K4
CLK
37
R6
A
2
H4
WE
38
T5
A
2
H4
WE
38
T5
A
3
M4
CEN
39
T3
A
3
M4
CEN
39
T3
A
4
F4
OE
40
R2
A
4
F4
OE
40
R2
A
5
B4
ADV/LD
41
R3
MODE
5
B4
41
R3
MODE
6
G4
A
42
P2
DQPD
6
G4
A
42
Internal
Internal
7
C3
A
43
P1
DQD
7
C3
A
43
Internal
Internal
8
B3
A
44
L2
DQD
8
B3
A
44
Internal
Internal
9
D6
DQPB
45
K1
DQD
9
T2
A
45
Internal
Internal
10
H7
DQB
46
N2
DQD
10
Internal
Internal
46
P2
DQPB
11
G6
DQB
47
N1
DQD
11
Internal
Internal
47
N1
DQB
12
E6
DQB
48
M2
DQD
12
Internal
Internal
48
M2
DQB
13
D7
DQB
49
L1
DQD
13
D6
DQPA
49
L1
DQB
14
E7
DQB
50
K2
DQD
14
E7
DQA
50
K2
DQB
ADV/LD
15
F6
DQB
51
Internal
Internal
15
F6
DQA
51
Internal
Internal
16
G7
DQB
52
H1
DQC
16
G7
DQA
52
H1
DQB
17
H6
DQB
53
G2
DQC
17
H6
DQA
53
G2
DQB
18
T7
ZZ
54
E2
DQC
18
T7
ZZ
54
E2
DQB
19
K7
DQA
55
D1
DQC
19
K7
DQA
55
D1
DQB
20
L6
DQA
56
H2
DQC
20
L6
DQA
56
Internal
Internal
21
N6
DQA
57
G1
DQC
21
N6
DQA
57
Internal
Internal
22
P7
DQA
58
F2
DQC
22
P7
DQA
58
Internal
Internal
23
N7
DQA
59
E1
DQC
23
Internal
Internal
59
Internal
Internal
24
M6
DQA
60
D2
DQPC
24
Internal
Internal
60
Internal
Internal
25
L7
DQA
61
C2
A
25
Internal
Internal
61
C2
A
26
K6
DQA
62
A2
A
26
Internal
Internal
62
A2
A
27
P6
DQPA
63
E4
CE1
27
Internal
Internal
63
E4
CE1
28
T4
A
64
B2
CE2
28
T6
A
64
B2
CE2
29
A3
A
65
L3
BWD
29
A3
A
65
Internal
Internal
30
C5
A
66
G3
BWC
30
C5
A
66
G3
BWB
31
B5
A
67
G5
BWB
31
B5
A
67
Internal
Internal
32
A5
A
68
L5
BWA
32
A5
A
68
L5
BWA
33
C6
A
69
B6
CE3
33
C6
A
69
B6
CE3
34
A6
A
34
A6
A
35
P4
A0
35
P4
A0
36
N4
A1
36
N4
A1
Document #: 38-05117 Rev. *B
Page 21 of 33
CY7C1355B
CY7C1357B
165-Ball fBGA Boundary Scan Order
CY7C1355B (256K x 36)
CY7C1357B (512K x 18)
BIT#
BALL
ID
Signal
Name
BIT#
BALL
ID
Signal
Name
BIT#
BALL
ID
Signal
Name
BIT#
BALL ID
Signal
Name
1
B6
CLK
37
R4
A
1
B6
CLK
37
R4
A
2
B7
WE
38
P4
A
2
B7
WE
38
P4
A
3
A7
CEN
39
R3
A
3
A7
CEN
39
R3
A
4
B8
OE
40
P3
A
4
B8
OE
40
P3
A
5
A8
ADV/LD
41
R1
MODE
5
A8
41
R1
MODE
6
A9
A
42
N1
DQPD
6
A9
A
42
Internal
Internal
7
B10
A
43
L2
DQD
7
B10
A
43
Internal
Internal
8
A10
A
44
K2
DQD
8
A10
A
44
Internal
Internal
9
C11
DQPB
45
J2
DQD
9
A11
A
45
Internal
Internal
10
E10
DQB
46
M2
DQD
10
Internal
Internal
46
N1
DQPB
11
F10
DQB
47
M1
DQD
11
Internal
Internal
47
M1
DQB
12
G10
DQB
48
L1
DQD
12
Internal
Internal
48
L1
DQB
13
D10
DQB
49
K1
DQD
13
C11
DQPA
49
K1
DQB
14
D11
DQB
50
J1
DQD
14
D11
DQA
50
J1
DQB
15
E11
DQB
51
Internal
Internal
15
E11
DQA
51
Internal
Internal
16
F11
DQB
52
G2
DQC
16
F11
DQA
52
G2
DQB
17
G11
DQB
53
F2
DQC
17
G11
DQA
53
F2
DQB
18
H11
ZZ
54
E2
DQC
18
H11
ZZ
54
E2
DQB
19
J10
DQA
55
D2
DQC
19
J10
DQA
55
D2
DQB
20
K10
DQA
56
G1
DQC
20
K10
DQA
56
Internal
Internal
21
L10
DQA
57
F1
DQC
21
L10
DQA
57
Internal
Internal
22
M10
DQA
58
E1
DQC
22
M10
DQA
58
Internal
Internal
23
J11
DQA
59
D1
DQC
23
Internal
Internal
59
Internal
Internal
24
K11
DQA
60
C1
DQPC
24
Internal
Internal
60
Internal
Internal
25
L11
DQA
61
B2
A
25
Internal
Internal
61
B2
A
26
M11
DQA
62
A2
A
26
Internal
Internal
62
A2
A
27
N11
DQPA
63
A3
CE1
27
Internal
Internal
63
A3
CE1
28
R11
A
64
B3
CE2
28
R11
A
64
B3
CE2
29
R10
A
65
B4
BWD
29
R10
A
65
Internal
Internal
30
P10
A
66
A4
BWC
30
P10
A
66
Internal
Internal
31
R9
A
67
A5
BWB
31
R9
A
67
A4
BWB
32
P9
A
68
B5
BWA
32
P9
A
68
B5
BWA
33
R8
A
69
A6
CE3
33
R8
A
69
A6
CE3
34
P8
A
34
P8
A
35
R6
A0
35
R6
A0
36
P6
A1
36
P6
A1
Document #: 38-05117 Rev. *B
ADV/LD
Page 22 of 33
CY7C1355B
CY7C1357B
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State ..................................... –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Operating Range
Ambient
Range
Temperature
VDD
VDDQ
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
to VDD
Industrial
-40°C to +85°C
Electrical Characteristics Over the Operating Range[13, 14]
Parameter
Description
VDD
VDDQ
Power Supply Voltage
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VIH
Input HIGH Voltage[13]
VIL
Input LOW Voltage[13]
IX
Input Load
Test Conditions
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
Input Current of MODE Input = VSS
Min.
Max.
Unit
3.135
3.135
2.375
2.4
2.0
3.6
VDD
2.625
V
V
2.0
1.7
–0.3
–0.3
–5
5
Input = VSS
µA
µA
–5
30
µA
5
µA
-300
µA
7.5-ns cycle, 133 MHz
250
mA
8.8-ns cycle, 117 MHz
220
mA
10-ns cycle, 100 MHz
180
All speeds
40
mA
All speeds
30
mA
VDD = Max, Device Deselected, or All speeds
Automatic CE
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX, inputs switching
Automatic CE
VDD = Max, Device Deselected,
All Speeds
Power-down
VIN ≥ VDD - 0.3V or VIN ≤ 0.3V, f =
Current—TTL Inputs
0, inputs static
40
mA
40
mA
Input = VDD
IOZ
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
IOS
Output Short Circuit
Current
VDD = Max., VOUT = GND
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
ISB1
Automatic CE
Power-down
Current—TTL Inputs
VDD = Max, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX, inputs switching
ISB2
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≤ 0.3V or VIN > VDD – 0.3V,
Current—CMOS Inputs f = 0, inputs static
ISB3
ISB4
µA
–30
Input = VDD
Input Current of ZZ
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
0.7
5
V
V
V
V
V
V
V
V
µA
–5
Notes:
13. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
14. TPower-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document #: 38-05117 Rev. *B
Page 23 of 33
CY7C1355B
CY7C1357B
Thermal Resistance[15]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
TQFP
Package
BGA
Package
fBGA
Package
Unit
25
25
27
°C/W
9
6
6
°C/W
Test conditions follow standard
test methods and procedures
for measuring thermal
impedance, per EIA / JESD51.
Capacitance[15]
Parameter
Description
Test Conditions
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
TQFP
Package
BGA
Package
fBGA
Package
Unit
5
5
5
pF
5
5
5
pF
5
7
7
pF
TA = 25°C, f = 1 MHz,
VDD = 3.3V.
VDDQ = 2.5V
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R = 351Ω
INCLUDING
JIG AND
SCOPE
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
VL = 1.5V
(a)
ALL INPUT PULSES
VDD
(c)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
RL = 50Ω
Z0 = 50Ω
GND
5 pF
R =1538Ω
VL = 1.25V
(a)
ALL INPUT PULSES
VDD
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
≤ 1 ns
≤ 1 ns
(c)
Notes:
15. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05117 Rev. *B
Page 24 of 33
CY7C1355B
CY7C1357B
Switching Characteristics Over the Operating Range[16, 17]
133 MHz
Parameter
tPOWER
Description
VDD(Typical) to the First Access[18]
Min.
Max.
117 MHz
Min.
Max.
100 MHz
Min.
Max.
Unit
1
1
1
ms
Clock
tCYC
Clock Cycle Time
7.5
8.5
10
ns
tCH
Clock HIGH
3.0
3.2
4.0
ns
tCL
Clock LOW
3.0
3.2
4.0
ns
Output Times
tCDV
Data Output Valid after CLK Rise
tDOH
Data Output Hold after CLK Rise
tCLZ
Clock to Low-Z[19, 20, 21]
tCHZ
High-Z[19, 20, 21]
3.5
3.5
3.5
ns
OE LOW to Output Valid
3.5
3.5
3.5
ns
tOEV
tOELZ
tOEHZ
Clock to
Low-Z[19, 20, 21]
OE LOW to Output
[19, 20, 21]
OE HIGH to Output High-Z
6.5
7.0
7.5
ns
2.0
2.0
2.0
ns
0
0
0
ns
0
0
3.5
0
3.5
ns
3.5
ns
Set-up Times
tAS
Address Set-up before CLK Rise
1.5
1.5
1.5
ns
tALS
ADV/LD Set-up before CLK Rise
1.5
1.5
1.5
ns
1.5
1.5
ns
tCENS
WE, BWX Set-up before CLK Rise
CEN Set-up before CLK Rise
1.5
1.5
1.5
1.5
ns
tDS
Data Input Set-up before CLK Rise
1.5
1.5
1.5
ns
tCES
Chip Enable Set-Up before CLK Rise
1.5
1.5
1.5
ns
tWES
Hold Times
tAH
Address Hold after CLK Rise
0.5
0.5
0.5
ns
tALH
ADV/LD Hold after CLK Rise
0.5
0.5
0.5
ns
tWEH
WE, BWX Hold after CLK Rise
0.5
0.5
0.5
ns
0.5
0.5
ns
tDH
CEN Hold after CLK Rise
Data Input Hold after CLK Rise
0.5
0.5
0.5
0.5
ns
tCEH
Chip Enable Hold after CLK Rise
0.5
0.5
0.5
ns
tCENH
Notes:
16. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
18. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially, before a Read or Write operation
can be initiated.
19. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
20. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
21. This parameter is sampled and not 100% tested.
Document #: 38-05117 Rev. *B
Page 25 of 33
CY7C1355B
CY7C1357B
Switching Waveforms
Read/Write Waveforms[22, 23, 24]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BWX
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes:
22. For this waveform ZZ is tied LOW.
23. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
24. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05117 Rev. *B
Page 26 of 33
CY7C1355B
CY7C1357B
Switching Waveforms (continued)
NOP, STALL AND DESELECT Cycles[22, 23, 25]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS tCENH
tCH
tCL
CEN
tCES
tCEH
CE
ADV/LD
WE
BWX
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
tDH
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Note:
25. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
Document #: 38-05117 Rev. *B
Page 27 of 33
CY7C1355B
CY7C1357B
Switching Waveforms (continued)
ZZ Mode Timing [26, 27]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes:
26. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
27. DQs are in high-Z when exiting ZZ sleep mode.
Ordering Information
3
Speed
(MHz)
133
Ordering Code
Package
Name
Operating
Range
CY7C1355B-133AC
CY7C1357B-133AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
CY7C1355B-133AI
CY7C1357B-133AI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
CY7C1355B-133BGC
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Commercial
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
BB165A
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Commercial
BB165A
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Industrial
CY7C1357B-133BGC
CY7C1355B-133BGI
CY7C1357B-133BGI
CY7C1355B-133BZC
CY7C1357B-133BZC
CY7C1355B-133BZI
CY7C1357B-133BZI
117
Part and Package Type
CY7C1355B-117AC
CY7C1357B-117AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
CY7C1355B-117AI
CY7C1357B-117AI
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
CY7C1355B-117BGC
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Commercial
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
CY7C1357B-117BGC
CY7C1355B-117BGI
CY7C1357B-117BGI
Shaded areas contain advance information.
Please contact your local sales representative for availability of these parts.
Document #: 38-05117 Rev. *B
Page 28 of 33
CY7C1355B
CY7C1357B
Ordering Information (continued)
Speed
(MHz)
Ordering Code
CY7C1355B-117BZC
Package
Name
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Commercial
BB165A
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Industrial
CY7C1357B-117BZI
100
CY7C1355B-100AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Industrial
CY7C1357B-100AC
CY7C1355B-100AI
CY7C1357B-100AI
CY7C1355B-100BGC
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Commercial
BG119
119-ball (14 x 22 x 2.4 mm) BGA 3 Chip Enables and
JTAG
Industrial
BB165A
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Commercial
BB165A
165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
3 Chip Enables and JTAG
Industrial
CY7C1357B-100BGC
CY7C1355B-100BG
ICY7C1357B-100BGI
CY7C1355B-100BZC
CY7C1357B-100BGC
CY7C1355B-100BZI
CY7C1357B-100BGI
Operating
Range
BB165A
CY7C1357B-117BZC
CY7C1355B-117BZI
Part and Package Type
Shaded areas contain advance information.
Please contact your local sales representative for availability of these parts.
Document #: 38-05117 Rev. *B
Page 29 of 33
CY7C1355B
CY7C1357B
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05117 Rev. *B
Page 30 of 33
CY7C1355B
CY7C1357B
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05117 Rev. *B
Page 31 of 33
CY7C1355B
CY7C1357B
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05117 Rev. *B
Page 32 of 33
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1355B
CY7C1357B
Document History Page
Document Title: CY7C1355B/CY7C1357B 9-Mb (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05117
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
117908
08/28/02
RCS
New Data Sheet
*A
123161
12/18/02
RCS
Removed Preliminary Statue (all pages).
Updated JTAG Revision number and Device depth.
Added JTAG boundary scan orders.
Added tPower specification and Note 15. These devices require 1 ms of VDD
above VDD minimum (3.135V) before operating.
*B
205060
See ECN
NJY
Final Data Sheet
Document #: 38-05117 Rev. *B
Page 33 of 33