CY8C9520A, CY8C9540A
CY8C9560A
20-, 40-, and 60-Bit IO Expander with
EEPROM
Features
Overview
2
■
I C™ interface logic electrically compatible with SMBus
■
Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A)
IO data pins independently configurable as inputs, outputs,
bi-directional input/outputs, or PWM outputs
■
4/8/16 PWM sources with 8-bit resolution
■
Extendable Soft Addressing™ algorithm allowing flexible
I2C-address configuration
■
Internal 3-/11-/27-Kbyte EEPROM
■
User default storage, IO port settings in internal EEPROM
■
Optional EEPROM Write Disable (WD) input
■
Interrupt output indicates input pin level changes and Pulse
Width Modulator (PWM) state changes
■
Internal Power On Reset (POR)
■
Internal configurable Watchdog timer
EEPROM
User
Settings
Area
User
Available
Area
GPort 0
8 Bit IO
GPort 1
5 Bit IO
3 Bit IO
or A4-A6
GPort 2
4 Bit IO
or A1-A3, WD6
GPort 3
8 Bit IO
GPort 7
8 Bit IO
24 MHz
1.5 MHz
93.75 kHz
Divider (1-255)
PWM 0
Control
Unit
PWM 15
SCL
INT
SDA
V dd
Power-on-Reset
A0
V ss
Cypress Semiconductor Corporation
Document Number: 38-12036 Rev. *B
The IO expander's data pins can be independently assigned as
inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs.
The individual data pins can be configured as open drain or
collector, strong drive (10 mA source, 25 mA sink), resistively
pulled up or down, or high impedance. The factory default configuration is pulled up internally.
There is one dedicated pin that is configured as an interrupt
output (INT) and can be connected to the interrupt logic of the
system master. This signal can inform the system master that
there is incoming data on its ports or that the PWM output state
was changed.
Clocks
32 kHz
The CY8C95xxA operates as two I2C slave devices. The first
device is a multi port IO expander (single I2C address to access
all ports through registers). The second device is a serial
EEPROM. Dedicated configuration registers can be used to
disable the EEPROM. The EEPROM uses 2-byte addressing to
support the 28 Kbyte EEPROM address space. The selected
device is defined by the most significant bits of the I2C address
or by specific register addressing.
The system master writes to the IO configuration registers
through the I2C bus. Configuration and output register settings
are storable as user defaults in a dedicated section of the
EEPROM. If user defaults were stored in EEPROM, they are
restored to the ports at power up. While this device can share the
bus with SMBus devices, it can only communicate with I2C
masters.
Top Level Block Diagram
WD
The CY8C95xxA is a multi-port IO expander with on board user
available EEPROM and several PWM outputs. All devices in this
family operate identically but differ in IO pins, number of PWMs,
and internal EEPROM size.
•
The EEPROM is byte readable and supports byte-by-byte
writing. A pin can be configured as an EEPROM Write Disable
(WD) input that blocks write operations when set high. The
configuration registers can also disable EEPROM operations.
The CY8C95xxA has one fixed address pin (A0) and up to six
additional pins (A1-A6), which allow up to 128 devices to share
a common two wire I2C data bus. The Extendable Soft
Addressing algorithm provides the option to choose the number
of pins needed to assign the desired address. Pins not used for
address bits are available as GPIO pins.
There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A)
independently configurable 8-bit PWMs. These PWMs are listed
as PWM0-PWM15. Each PWM can be clocked by one of six
available clock sources.
For details on how to configure I2C, see Application Note
"Communication - I2C Port Expander with Flash Storage AN2304" at http://www.cypress.com/design/2304.
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 03, 2007
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CY8C9520A, CY8C9540A
CY8C9560A
Architecture
Figure 1. Logical Structure of the IO Port
The “Top Level Block Diagram” on page 1 illustrates the device
block diagram. The main blocks include the control unit, PWMs,
EEPROM, and IO ports. The control unit executes commands
received from the I2C bus and transfers data between other bus
devices and the master device.
The on chip EEPROM can be separated conventionally into two
regions. The first region is designed to store data and is available
for byte wide read/writes through the I2C bus. It is possible to
prevent write operations by setting the WD pin to high. All
EEPROM operations can be blocked by configuration register
settings. The second region allows the user to store the port and
PWM default settings using special commands. These defaults
are automatically reloaded and processed after device power on.
GPortx
7 Drive Mode
Registers
DriveMode
Pull-Up
Data
PWMs
DriveMode
High Z
Select PWM
The number of IO lines and PWM sources are listed in table 1.
Table 1. GPIO Availability
Port
CY8C9520A
CY8C9540A
CY8C9560A
GPort 0
8 bit
8 bit
8 bit
GPort 1
5-8 bita
5-8bita
5-8 bita
GPort 2
0-4 bita
0-4ita
0-4 bita
GPort 3
-
8 bit
8 bit
GPort 4
-
8 bit
8 bit
GPort 5
-
4 bit
8 bit
GPort 6
-
-
8 bit
GPort 7
-
-
8 bit
PWMs
4
8
16
a. This port contains configuration-dependant GPIO lines or A1-A6 and WD
lines.
There are four pins on GPort 2 and three on GPort 1 that can be
used as general purpose IO or EEPROM Write Disable (WD) and
I2C-address input (A1-A6), depending on configuration settings.
The figure titled “Logical Structure of the IO Port” shows the
single port logical structure. The Port Drive Mode register gives
the option to select one of seven available modes for each pin
separately: pulled up/down, open drain high/low, strong drive
fast/slow, or high-impedance. By default these configuration
registers store values setting IO pins to pulled up. The Invert
register allows for inversion of the logic of the Input registers
separately for each pin. The Select PWM register assigns pins
as PWM outputs. All of these configuration registers are
read/writable using corresponding commands in the multi-port
device.
Output
Register
Interrupt
Status
Input Register
8 Bit IO
Interrupt
Mask
Pin Direction
Inversion
The Port Input and Output registers are separated. When the
Output register is written, the data is sent to the external pins.
When the Input register is read, the external pin logic levels are
captured and transferred. As a result, the read data can be
different from written Output register data. This allows for implementation of a quasi-bidirectional input-output mode, when the
corresponding binary digit is configured as pulled up/down
output.
Each port has an Interrupt Mask register and an Interrupt Status
register. Each high bit in the Interrupt Status register signals that
there has been a change in the corresponding input line since
the last read of that Interrupt Status register. The Interrupt Status
register is cleared after each read. The Interrupt Mask register
enables/disables activation of the INT line when input levels are
changed. Each high in the Interrupt Mask register masks
(disables) an interrupt generated from the corresponding input
line.
Applications
Each GPIO pin can be used to monitor and control various board
level devices, including LEDs and system intrusion detection
devices.
The on board EEPROM can be used to store information such
as error codes or board manufacturing data for read-back by
application software for diagnostic purposes.
Document Number: 38-12036 Rev. *B
Page 2 of 24
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CY8C9520A, CY8C9540A
CY8C9560A
Device Access Addressing
Following a start condition, the I2C master device sends a byte
to address an I2C slave. This address accesses the device in the
CY8C95xx. By default there are two possible address formats in
binary representation: 010000A0X and 101000A0X. The first is
used to access the multi port device and the second to access
the EEPROM. If additional address lines (A1-A6) are used then
the Device Addressing. Table 2 defines the device addresses.
This addressing method uses a technique called Extendable Soft
Addressing™, described “Extendable Soft Addressing™” on
page 8.
Table 2. Device Addressing
Multi-Port Device
01
EEPROM Device
0
0
0
0
A0
R/W
1
0
1
0
0
0
A0 R/W
0
0
A1
A0
R/W
1
0
1
0
0
A1
A0 R/W
0
1
0
0
1
0
0
A2
A1
A0
R/W
1
0
1
0
A2
A1
A0 R/W
0
1
0
A3 A2
A1
A0
R/W
1
0
1
A3
A2
A1
A0 R/W
0
1
A4 A3 A2
A1
A0
R/W
1
0
A4
A3
A2
A1
A0 R/W
0
A5
A4 A3 A2
A1
A0
R/W
1
A5
A4
A3
A2
A1
A0 R/W
A6
A5
A4 A3 A2
A1
A0
R/W
A6 A5
A4
A3
A2
A1
A0 R/W
an EEPROM write sequence. If the end of available EEPROM
space is reached, then further writes are responded to with a
NAK.
Refer to Figure 6, “Memory Reading and Writing,” on page 9,
which illustrates memory reading and writing procedures for the
EEPROM device.
Multi Port IO Device
This device allows the user to set configurations and IO operations through internal registers.
Each data transfer is preceded by the command byte. This byte
is used as a pointer to a register that receives or transmits data.
Available registers are listed in Table 7, “The Device Register
Address Map,” on page 10.
Document Conventions
Acronyms
Table 3 lists the acronyms that are used in this document.
Table 3. Acronyms
Acronym
Description
AC
alternating current
DC
direct current
EEPROM
electrically erasable programmable read-only
memory (E2)
GPIO
general purpose IO
IO
input/output
Serial EEPROM Device
MSb
most-significant bit
EEPROM reading and writing operations require 2 bytes, AHI
and ALO, which indicate the memory address to use.
POR
power on reset
PWM
pulse width modulator
When all address lines A1-A6 are used, the device being
accessed is defined by the first byte following the address in the
write transaction. If the most significant bit (MSb) of this byte is
‘0’, this byte is treated as a command (register address) byte of
the multi-port device. If the MSb is ‘1’, this byte is the first of a
2-byte EEPROM address. In this case, the device masks the
MSb to determine the EEPROM address.
To read one or more bytes, the master device addresses the unit
with a write cycle (= 0) to send AHI followed by ALO, readdresses
the unit with a read cycle (= 1), and reads one or more data bytes.
Each data byte read increments the internal address counter by
one up to the end of the EEPROM address space. A read or write
beyond the end of the EEPROM address space must result in a
NAK response by the Port Expander.
To write data to the EEPROM, the master device performs one
write cycle, with the first two bytes being AHI followed by ALO.
This is followed by one or more data bytes. In the case of block
writing it is advisable to set the starting address on the beginning
of the 64-byte boundary, for example 01C0h or 0080h, but this is
not mandatory. When a 64-byte boundary is crossed in the
EEPROM, the I2C clock is stretched while the device performs
Document Number: 38-12036 Rev. *B
Units of Measure
A units of measure table is located in the Electrical Specifications
section. Table 17, “Units of Measure,” on page 15 lists all the
abbreviations used in Section 4.
Numeric Naming
Hexidecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
Page 3 of 24
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CY8C9520A, CY8C9540A
CY8C9560A
Pinouts
The CY8C95xxA device is available in a variety of packages, which are listed and illustrated in the following tables.
28-Pin Part Pinout
Table 4. 28-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GPort0_Bit0_PWM3
GPort0_Bit1_PWM1
GPort0_Bit2_PWM3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM3
GPort0_Bit5_PWM1
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
VSS
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
GPort2_Bit3_PWM3/A1
A0
VSS
GPort2_Bit2_PWM0/WD
INT
GPort2_Bit1_PWM0/A2
GPort2_Bit0_PWM2/A3
Port 0, Bit 0, PWM 3.
Port 0, Bit 1, PWM 1.
Port 0, Bit 2, PWM 3.
Port 0, Bit 3, PWM 1.
Port 0, Bit 4, PWM 3.
Port 0, Bit 5, PWM 1.
Port 0, Bit 6, PWM 3.
Port 0, Bit 7, PWM 1.
Ground connection.
I2C Clock.
I2C Data.
Port 2, Bit 3, PWM 3, Address 1.
Address 0.
Ground connection.
Port 2, Bit 2, PWM 0, E2 Write Disable.
19
XRES
20
21
22
23
24
25
26
27
28
GPort1_Bit7_PWM0/A4
GPort1_Bit6_PWM2/A5
GPort1_Bit5_PWM0/A6
GPort1_Bit4_PWM2
GPort1_Bit3_PWM0
GPort1_Bit2_PWM2
GPort1_Bit1_PWM0
GPort1_Bit0_PWM2
Vdd
Active high external reset with internal pull
down.
Port 1, Bit 7, PWM 0, Address 4.
Port 1, Bit 6, PWM 2, Address 5.
Port 1, Bit 5, PWM 0, Address 6.
Port 1, Bit 4, PWM 2.
Port 1, Bit 3, PWM 0.
Port 1, Bit 2, PWM 2.
Port 1, Bit 1, PWM 0.
Port 1, Bit 0, PWM 2.
Supply voltage.
Pin Name
Description
Figure 2. CY8C9520A 28-Pin Device
GPort0_Bit0_PWM3
GPort0_Bit1_PWM1
GPort0_Bit2_PWM3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM3
GPort0_Bit5_PWM1
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
Vss
I2C Serial Clock (SCL)
I2C Serial Clock (SDA)
GPort2_Bit3_PWM3/A1
A0
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
GPort1_Bit0_PWM2
GPort1_Bit1_PWM0
GPort1_Bit2_PWM2
GPort1_Bit3_PWM0
GPort1_Bit4_PWM2
GPort1_Bit5_PWM0/A6
GPort1_Bit6_PWM2/A5
GPort1_Bit7_PWM0/A4
XRES
GPort2_Bit0_PWM2/A3
GPort2_Bit1_PWM0/A2
INT
GPort2_Bit2_PWM0/WD
Port 2, Bit 1, PWM 0, Address 2.
Port 2, Bit 0, PWM 2, Address 3.
Document Number: 38-12036 Rev. *B
Page 4 of 24
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CY8C9520A, CY8C9540A
CY8C9560A
48-Pin Part Pinout
Table 5. 48-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
GPort0_Bit0_PWM7
GPort0_Bit1_PWM5
GPort0_Bit2_PWM3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM7
GPort0_Bit5_PWM5
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
GPort3_Bit0_PWM7
GPort3_Bit1_PWM5
GPort3_Bit2_PWM3
GPort3_Bit3_PWM1
VSS
GPort3_Bit4_PWM7
GPort3_Bit5_PWM5
GPort3_Bit6_PWM3
GPort3_Bit7_PWM1
GPort5_Bit2_PWM3
GPort5_Bit3_PWM1
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
GPort2_Bit3_PWM3/A1
A0
VSS
GPort2_Bit2_PWM0/WD
INT
GPort2_Bit1_PWM4/A2
GPort2_Bit0_PWM6/A3
GPort5_Bit1_PWM0
GPort5_Bit0_PWM2
GPort4_Bit7_PWM0
GPort4_Bit6_PWM2
GPort4_Bit5_PWM4
GPort4_Bit4_PWM6
XRES
36
37
38
39
40
41
42
43
44
45
46
47
48
GPort4_Bit3_PWM0
GPort4_Bit2_PWM2
GPort4_Bit1_PWM4
GPort4_Bit0_PWM6
GPort1_Bit7_PWM0/A4
GPort1_Bit6_PWM2/A5
GPort1_Bit5_PWM4/A6
GPort1_Bit4_PWM6
GPort1_Bit3_PWM0
GPort1_Bit2_PWM2
GPort1_Bit1_PWM4
GPort1_Bit0_PWM6
Vdd
Pin Name
Description
Port 0, Bit 0, PWM 7.
Port 0, Bit 1, PWM 5.
Port 0, Bit 2, PWM 3.
Port 0, Bit 3, PWM 1.
Port 0, Bit 4, PWM 7.
Port 0, Bit 5, PWM 5.
Port 0, Bit 6, PWM 3.
Port 0, Bit 7, PWM 1.
Port 3, Bit 0, PWM 7.
Port 3, Bit 1, PWM 5.
Port 3, Bit 2, PWM 3.
Port 3, Bit 3, PWM 1.
Ground connection.
Port 3, Bit 4, PWM 7.
Port 3, Bit 5, PWM 5.
Port 3, Bit 6, PWM 3.
Port 3, Bit 7, PWM 1.
Port 5, Bit 2, PWM 3.
Port 5, Bit 3, PWM 1.
I2C Clock.
I2C Data.
Port 2, Bit 3, PWM 3, Address 1.
Address 0.
Ground connection.
Port 2, Bit 2, PWM 0, E2 Write Disable.
Figure 3. CY8C9540A 48-Pin Device
GPort0_Bit0_PWM7
GPort0_Bit1_PWM5
GPort0_Bit2_PWM3
GPort0_Bit3_PWM1
GPort0_Bit4_PWM7
GPort0_Bit5_PWM5
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
GPort3_Bit0_PWM7
GPort3_Bit1_PWM5
GPort3_Bit2_PWM3
GPort3_Bit3_PWM1
Vss
GPort3_Bit4_PWM7
GPort3_Bit5_PWM5
GPort3_Bit6_PWM3
GPort3_Bit7_PWM1
GPort5_Bit2_PWM3
GPort5_Bit3_PWM1
I2C Serial Clock (SCL)
I2C Serial Data (SDA)
GPort2_Bit3_PWM3/A1
A0
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
GPort1_Bit0_PWM6
GPort1_Bit1_PWM4
GPort1_Bit2_PWM2
GPort1_Bit3_PWM0
GPort1_Bit4_PWM6
GPort1_Bit5_PWM4/A6
GPort1_Bit6_PWM2/A5
GPort1_Bit7_PWM0/A4
GPort4_Bit0_PWM6
GPort4_Bit1_PWM4
GPort4_Bit2_PWM2
GPort4_Bit3_PWM0
XRES
GPort4_Bit4_PWM6
GPort4_Bit5_PWM4
GPort4_Bit6_PWM2
GPort4_Bit7_PWM0
GPort5_Bit0_PWM2
GPort5_Bit1_PWM0
GPort2_Bit0_PWM6/A3
GPort2_Bit1_PWM4/A2
INT
GPort2_Bit2_PWM0/WD
Port 2, Bit 1, PWM 4, Address 2.
Port 2, Bit 0, PWM 6, Address 3.
Port 5, Bit 1, PWM 0.
Port 5, Bit 0, PWM 2.
Port 4, Bit 7, PWM 0.
Port 4, Bit 6, PWM 2.
Port 4, Bit 5, PWM 4.
Port 4, Bit 4, PWM 6.
Active high external reset with internal pull
down.
Port 4, Bit 3, PWM 0.
Port 4, Bit 2, PWM 2.
Port 4, Bit 1, PWM 4.
Port 4, Bit 0, PWM 6.
Port 1, Bit 7, PWM 0, Address 4.
Port 1, Bit 6, PWM 2, Address 5.
Port 1, Bit 5, PWM 4, Address 6.
Port 1, Bit 4, PWM 6.
Port 1, Bit 3, PWM 0.
Port 1, Bit 2, PWM 2.
Port 1, Bit 1, PWM 4.
Port 1, Bit 0, PWM 6.
Supply voltage.
Document Number: 38-12036 Rev. *B
Page 5 of 24
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CY8C9520A, CY8C9540A
CY8C9560A
100-Pin Part Pinout
Table 6. 100-Pin Part Pinout (TQFP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Name
DNU
DNU
GPort0_Bit3_PWM1
GPort0_Bit4_PWM7
GPort0_Bit5_PWM5
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
GPort3_Bit0_PWM7
GPort3_Bit1_PWM5
GPort3_Bit2_PWM3
GPort3_Bit3_PWM1
DNU
DNU
DNU
VSS
GPort3_Bit4_PWM15
GPort3_Bit5_PWM13
GPort3_Bit6_PWM11
GPort3_Bit7_PWM9
GPort5_Bit7_PWM15
GPort5_Bit6_PWM13
GPort5_Bit2_PWM11
GPort5_Bit3_PWM9
I2C Serial Clock (SCL)
DNU
DNU
DNU
I2C Serial Data (SDA)
GPort2_Bit3_PWM11/A1
A0
DNU
Vdd
DNU
VSS
DNU
GPort7_Bit7_PWM15
GPort7_Bit6_PWM14
GPort7_Bit5_PWM13
GPort7_Bit4_PWM12
GPort7_Bit3_PWM11
GPort7_Bit2_PWM10
GPort7_Bit1_PWM9
GPort7_Bit0_PWM8
GPort2_Bit2_PWM8/WD
INT
GPort2_Bit1_PWM12/A2
GPort2_Bit0_PWM14/A3
DNU
DNU
DNU
Description
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
Port 0, Bit 3, PWM 1.
Port 0, Bit 4, PWM 7.
Port 0, Bit 5, PWM 5.
Port 0, Bit 6, PWM 3.
Port 0, Bit 7, PWM 1.
Port 3, Bit 0, PWM 7.
Port 3, Bit 1, PWM 5.
Port 3, Bit 2, PWM 3.
Port 3, Bit 3, PWM 1.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
Ground connection.
Port 3, Bit 4, PWM 15.
Port 3, Bit 5, PWM 13.
Port 3, Bit 6, PWM 11.
Port 3, Bit 7, PWM 9.
Port 5, Bit 7, PWM 15.
Port 5, Bit 6, PWM 13.
Port 5, Bit 2, PWM 11.
Port 5, Bit 3, PWM 9.
I2C Clock.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
I2C Data.
Port 2, Bit 3, PWM 11, Address 1.
Address 0.
DNU = Do Not Use; leave floating.
Supply voltage.
DNU = Do Not Use; leave floating.
Ground connection.
DNU = Do Not Use; leave floating.
Port 7, Bit 7, PWM 15.
Port 7, Bit 6, PWM 14.
Port 7, Bit 5, PWM 13.
Port 7, Bit 4, PWM 12.
Port 7, Bit 3, PWM 11.
Port 7, Bit 2, PWM 10.
Port 7, Bit 1, PWM 9.
Port 7, Bit 0, PWM 8.
Port 2, Bit 2, PWM 8, E2 Write Disable.
Port 2, Bit 7, PWM 0, Address 4.
Port 2, Bit 6, PWM 2, Address 5.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
Document Number: 38-12036 Rev. *B
Pin
No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Name
Description
DNU
GPort5_Bit1_PWM8
GPort5_Bit0_PWM10
GPort5_Bit4_PWM12
GPort5_Bit5_PWM14
GPort4_Bit7_PWM8
GPort4_Bit6_PWM10
GPort4_Bit5_PWM12
GPort4_Bit4_PWM14
DNU
DNU
XRES
GPort4_Bit3_PWM0
GPort4_Bit2_PWM2
VSS
GPort4_Bit1_PWM4
GPort4_Bit0_PWM6
GPort1_Bit7_PWM0/A4
GPort1_Bit6_PWM2/A5
GPort1_Bit5_PWM4/A6
DNU
GPort1_Bit4_PWM6
DNU
GPort1_Bit3_PWM0
DNU
DNU
GPort1_Bit2_PWM2
DNU
GPort1_Bit1_PWM4
DNU
GPort1_Bit0_PWM6
Vdd
Vdd
VSS
VSS
GPort6_Bit0_PWM0
GPort6_Bit1_PWM1
GPort6_Bit2_PWM2
GPort6_Bit3_PWM3
GPort6_Bit4_PWM4
GPort6_Bit5_PWM5
GPort6_Bit6_PWM6
GPort6_Bit7_PWM7
DNU
GPort0_Bit0_PWM7
DNU
GPort0_Bit1_PWM5
DNU
GPort0_Bit2_PWM3
DNU
DNU = Do Not Use; leave floating.
Port 5, Bit 1, PWM 8.
Port 5, Bit 0, PWM 10.
Port 5, Bit 4, PWM 12.
Port 5, Bit 5, PWM 14.
Port 4, Bit 7, PWM 8.
Port 4, Bit 6, PWM 10.
Port 4, Bit 5, PWM 12.
Port 4, Bit 4, PWM 14.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
Active high external reset with internal pull down.
Port 4, Bit 3, PWM 0.
Port 4, Bit 2, PWM 2.
Ground connection.
Port 4, Bit 1, PWM 4.
Port 4, Bit 0, PWM 6.
Port 1, Bit 7, PWM 0, Address 4.
Port 1, Bit 6, PWM 2, Address 5.
Port 1, Bit 5, PWM 4, Address 6.
DNU = Do Not Use; leave floating.
Port 1, Bit 4, PWM 6.
DNU = Do Not Use; leave floating.
Port 1, Bit 3, PWM 0.
DNU = Do Not Use; leave floating.
DNU = Do Not Use; leave floating.
Port 1, Bit 2, PWM 2.
DNU = Do Not Use; leave floating.
Port 1, Bit 1, PWM 4.
DNU = Do Not Use; leave floating.
Port 1, Bit 0, PWM 6.
Supply voltage.
Supply voltage.
Ground connection.
Ground connection.
Port 6, Bit 0, PWM 0.
Port 6, Bit 1, PWM 1.
Port 6, Bit 2, PWM 2.
Port 6, Bit 3, PWM 3.
Port 6, Bit 4, PWM 4.
Port 6, Bit 5, PWM 5.
Port 6, Bit 6, PWM 6.
Port 6, Bit 7, PWM 7.
DNU = Do Not Use; leave floating.
Port 0, Bit 0, PWM 7.
DNU = Do Not Use; leave floating.
Port 0, Bit 1, PWM 5.
DNU = Do Not Use; leave floating.
Port 0, Bit 2, PWM 3.
DNU = Do Not Use; leave floating.
Page 6 of 24
[+] Feedback
CY8C9520A, CY8C9540A
CY8C9560A
77
76
Vdd
Vdd
GPort1_Bit0_PWM6
DNU
GPort1_Bit1_PWM4
DNU
GPort1_Bit2_PWM2
DNU
87
86
85
84
83
82
81
80
79
78
90
89
88
98
97
96
95
94
93
92
91
GPort6_Bit7_PWM7
GPort6_Bit6_PWM6
GPort6_Bit5_PWM5
GPort6_Bit4_PWM4
GPort6_Bit3_PWM3
GPort6_Bit2_PWM2
GPort6_Bit1_PWM1
GPort6_Bit0_PWM0
Vss
Vss
75
74
TQFP
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
DNU
GPort1_Bit3_PWM0
DNU
GPort1_Bit4_PWM6
DNU
GPort1_Bit5_PWM4/A6
GPort1_Bit6_PWM2/A5
GPort1_Bit7_PWM0/A4
GPort4_Bit0_PWM6
GPort4_Bit1_PWM4
Vss
GPort4_Bit2_PWM2
GPort4_Bit3_PWM0
XRES
DNU
DNU
GPort4_Bit4_PWM14
GPort4_Bit5_PWM12
GPort4_Bit6_PWM10
GPort4_Bit7_PWM8
GPort5_Bit5_PWM14
GPort5_Bit4_PWM12
GPort5_Bit0_PWM10
GPort5_Bit1_PWM8
DNU
DNU
DNU
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GPort7_Bit7_PWM15
GPort7_Bit6_PWM14
GPort7_Bit5_PWM13
GPort7_Bit4_PWM12
GPort7_Bit3_PWM11
GPort7_Bit2_PWM10
GPort7_Bit1_PWM9
GPort7_Bit0_PWM8
GPort2_Bit2_PWM8/WD
INT
GPort2_Bit1_PWM12/A2
GPort2_Bit0_PWM14/A3
DNU
54
53
52
51
26
27
28
29
30
31
32
33
34
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DNU
DNU
I2C Serial Data (SDA)
GPort2_Bit3_PWM11/A1
A0
DNU
Vdd
DNU
Vss
DNU
DNUa
DNU
GPort0_Bit3_PWM1
GPort0_Bit4_PWM7
GPort0_Bit5_PWM5
GPort0_Bit6_PWM3
GPort0_Bit7_PWM1
GPort3_Bit0_PWM7
GPort3_Bit1_PWM5
GPort3_Bit2_PWM3
GPort3_Bit3_PWM1
DNU
DNU
DNU
Vss
GPort3_Bit4_PWM15
GPort3_Bit5_PWM13
GPort3_Bit6_PWM11
GPort3_Bit7_PWM9
GPort5_Bit7_PWM15
GPort5_Bit6_PWM13
GPort5_Bit2_PWM11
GPort5_Bit3_PWM9
I2C Serial Clock (SCL)
DNU
100
99
DNU
GPort0_Bit2_PWM3
DNU
GPort0_Bit1_PWM5
DNU
GPort0_Bit0_PWM7
DNU
Figure 4. CY8C9560A 100-Pin Device
a. DNU = Do Not Use; leave floating.
Document Number: 38-12036 Rev. *B
Page 7 of 24
[+] Feedback
CY8C9520A, CY8C9540A
CY8C9560A
PIN Descriptions
Working with PWMs
Extendable Soft Addressing™
There are four independent PWMs in the CY8C9520A, eight in
the CY8C9540A and sixteen in the CY8C9560A. Each IO pin
can be configured as a PWM output by writing ‘1’ to the corresponding bit of the Select PWM register (see Table 8, “Output
and Select PWM Registers Logic,” on page 11).
The A0 line defines the corresponding bit of the I2C address.
This pin must be pulled up or down. If A0 is a strong pull up or a
strong pull down (wired through 330 or less resistor to Vdd or
Vss), then that is the only address line being specified and the
A1-A6 lines are used as GPIO. If A0 is a weak pull up or a weak
pull down (connected to Vdd or Vss through 75K- 200K ohm
resistor), then A0 is not the only externally defined address bit.
There is a pin assigned to be A1 if it is needed. This pin can be
pulled up or pulled down strong or weak with a resistor. As with
A0, the type of pull determines whether the address bit is the last
externally defined address bit. Differently from A0, A1 is not
dedicated as an address pin. It is only used if A0 is not the only
address bit externally defined. There are also predefined pins for
A2, A3, A4, A5, and A6 that is only used for addressing if needed.
The last address bit in the chain is pulled strong. That way, only
the number of pins needed to assign the address desired for the
part are allocated as address pins, any pins not used for address
bits can be used as GPIO pins. The Table 2, “Device
Addressing,” on page 3 defines the resulting device I2C address.
The next step of PWM configuration is clock source selection
using the Config PWM registers. There are six available clock
sources: 32 kHz (default), 24 MHz, 1.5 MHz, 93.75 kHz, 367.6
Hz or previous PWM output. (see Figure 5)
Figure 5. Clock Sources
32 kHz
24 mHz
1.5 mHz
93.75 kHz
Divider (1-255)
367.6 Hz 93.75 kHz
Interrupt Pin (INT)
The interrupt output (if enabled) is activated if one of these
events occurs:
By default, 32 kHz is selected as the PWM clock.
■
One of the GPIO port pins changes state and the corresponding
bit in the Interrupt Mask register is set low.
PWM Period registers are used to set the output period:
■
When a PWM driven by the slowest clock source (367.6 Hz)
and assigned to a pin changes state and the pin’s corresponding bit in the Interrupt Mask register is set low.
t OUT = Period × t CLK
The interrupt line is deactivated when the master device
performs a read from the corresponding Interrupt Status register.
Write Disable Pin (WD)
If this feature is enabled, ‘0’ allows writes to the EEPROM and
‘1’ blocks any memory writes. This pin is checked immediately
before performing any write to memory. If the EEE bit in the
Enable register is not set (EEPROM disabled) or bit EERO is set
(EEPROM is read-only) then WD line level is ignored.
Allowed values are between 1 and FFh.
The PWM Pulse Width register sets the duration of the PWM
output pulse. Allowed values are between zero and the
(Period-1) value. The duty cycle ratio is computed using thsi
equation:
DutyCycle = PulseWidth
-----------------------------Period
Note that ‘1’ on this line blocks all commands that perform operations with EEPROM (see Table 15, “Available Commands,” on
page 13).
This line may be enabled/disabled by bit 1 of the Enable register
(2Dh): ‘1’ enables WD function, ‘0’ disables.
External Reset Pin (XRES)
A full device reset is caused by pulling the XRES pin high. The
XRES pin has an always-on pull down resistor, so it does not
require an external pull down for operation. It can be tied
directly to ground or left open. Behavior after XRES is similar to
POR.
Document Number: 38-12036 Rev. *B
Page 8 of 24
[+] Feedback
CY8C9520A, CY8C9540A
CY8C9560A
Figure 6. Memory Reading and Writing
Memory Address
Slave Address
R/W
S A6 A5 A4 A3 A2 A1 A0 0
Start
Stop
R/W
A
High(Addr)
ACK from
Slave
A
Low(Addr)
ACK from
Slave
A
S A6 A5 A4 A3 A2 A1 A0 1
ACK from
Slave
A
data(Addr)
ACK from
Slave
A
data(Addr+1)
ACK from
Master
A
...
N
ACK from
Master
P
No ACK
from Master
Reading from EEPROM
Slave Address
Up to the End of Address Space
Memory Address
R/W
S A6 A5 A4 A3 A2 A1 A0 0
Start
Stop
A
High(Addr)
ACK from
Slave
A
Low(Addr)
A
data 1
A
data 2
A
...
A
P
ACK from
Slave
ACK from
Slave
If current address crosses
64-byte block boundary,
then device performs real
writing to EEPROM
Writing to EEPROM
Figure 7. Port Reading and Writing in Multi-Port Device
Slave Address
Register Address = 1
Reading from GPort 2
At this moment, device
performs reading from GPort 1
S A6 A5 A4 A3 A2 A1 A0 0
Start
Stop
R/W
R/W
A
0
0
0
0
0
0
0
ACK from
Slave
1
A
S A6 A5 A4 A3 A2 A1 A0 1
ACK from
Slave
A data from GPort1 A data from GPort 2
A
...
N
P
No ACK
from Master
ACK from
Master
Reading from GPort 1
Slave Address
Register Address = 09h
Output to GPort 2
Output to GPort 3
At this moment, device
performs output to GPort 1
Stop
R/W
S A6 A5 A4 A3 A2 A1 A0 0
Start
A
0
0
ACK from
Slave
0
0
1
0
0
1
A data from GPort1 A data from GPort 2 A data from GPort 3
ACK from
Slave
ACK from
Slave
A
...
P
ACK from
Slave
Writing from GPort 1
Document Number: 38-12036 Rev. *B
Page 9 of 24
[+] Feedback
CY8C9520A, CY8C9540A
CY8C9560A
Register Mapping Table
Table 7. The Device Register Address Map (continued)
The register address is auto-incrementing. If the master device
writes or reads data to or from one register and then continues
data transfer in the same I2C transaction, sequential bytes are
written or read to or from the following registers. For example, if
the first byte is sent to the Output Port 1 register, then the next
bytes are written to Output Port 2, Output Port 3, Output Port 4
etc. The first byte of each write transaction is treated as the
register address.
Address
Register
Default
Register Value
19h
Interrupt Mask
1Ah
Select PWM for Port Output 00h
FFh
1Bh
Inversion
00h
1Ch
Pin Direction - Input/Output
00h
1Dh
Drive Mode - Pull Up
FFh
1Eh
Drive Mode - Pull Down
00h
1Fh
Drive Mode - Open Drain
High
00h
To read a specific register address, the master device must write
the register address byte, then perform a start and read transaction.
20h
Drive Mode - Open Drain
Low
00h
21h
Drive Mode - Strong
00h
See Figure 7, “Port Reading and Writing in Multi-Port Device,” on
page 9.
22h
Drive Mode - Slow Strong
00h
23h
Drive Mode - High-Z
00h
24h
Reserved
None
25h
Reserved
None
26h
Reserved
None
To read data from a seires of registers, the master device must
write the starting register address byte then perform a start and
series of read transactions. If no address was sent, reads start
from address 0.
The device’s register mapping is listed in Table 7.
Table 7. The Device Register Address Map
Address
Register
Default
Register Value
27h
Reserved
None
00h
Input Port 0
None
28h
PWM Select
00h
01h
Input Port 1
None
29h
Config PWM
00h
02h
Input Port 2
None
2Ah
Period PWM
FFh
03h
Input Port 3
None
2Bh
Pulse Width PWM
80h
04h
Input Port 4
None
2Ch
Programmable Divider
FFh
05h
Input Port 5
None
2Dh
Enable WDE, EEE, EERO
00h
06h
Input Port 6
None
2Eh
Device ID/Status
20h/40h/60h
07h
Input Port 7
None
2Fh
Watchdog
00h
08h
Output Port 0
FFh
30h
Command
00h
09h
Output Port 1
FFh
0Ah
Output Port 2
FFh
0Bh
Output Port 3
FFh
0Ch
Output Port 4
FFh
0Dh
Output Port 5
FFh
0Eh
Output Port 6
FFh
0Fh
Output Port 7
FFh
Input Port Registers (00h - 07h)
10h
Interrupt Status Port 0
00h
11h
Interrupt Status Port 1
00h
These registers represent actual logical levels on the pins and
are used for IO port reading operations. They are read only. The
Inversion registers changes the state of reads to these ports.
12h
Interrupt Status Port 2
00h
13h
Interrupt Status Port 3
00h
14h
Interrupt Status Port 4
00h
15h
Interrupt Status Port 5
00h
16h
Interrupt Status Port 6
00h
17h
Interrupt Status Port 7
00h
18h
Port Select
00h
Document Number: 38-12036 Rev. *B
Register Descriptions
The registers for the CY8C95xx are described in the sections
that follow. Note that the PWM registers are located at addresses
28h to 2Bh.
Output Port Registers (08h - 0Fh)
These registers are used for writing data to GPIO ports. By
default, all ports are in the pull up mode allowing quasi-bidirectional IO. To allow input operations without reconfiguration, these
registers have to store ’1’s.
Output register data also affects pin states when PWMs are
enabled. See Table 8. Output and Select PWM Registers Logic
for details.
Page 10 of 24
[+] Feedback
CY8C9520A, CY8C9540A
CY8C9560A
The Inversion registers have no effect on these ports.
The Input registers' logic is presented in Table 9. These registers
have no effect on outputs or PWMs.
Int. Status Port Registers (10h - 17h)
Table 9. Inversion Register Logic
See Figure 7 on page 9 illustrates port read/write procedures.
Each ’1’ bit in these registers signals that there was a change in
the corresponding input line since the last read of that Interrupt
Status register. Each Interrupt (Int.) Status register is cleared
only after a read of that register.
Pin State
Invert
Input
0
0
0
1
0
1
If a PWM is assigned to a pin, then all state changes of the PWM
sets the corresponding bit in the Interrupt Status register. If the
pin's interrupt mask is cleared and the PWM is set to the slowest
possible rate allowed (driven by the programmable clock source
with divide register 2Dh set to FFh), then the INT line also drives
on the PWM state change.
0
1
1
1
1
0
Port Select Register (18h)
This register configures the GPort. Write a value of 0-7 to this
register to select the port to program with registers 19h-23h.
Interrupt Mask Port Register (19h)
The Interrupt Mask register enables or disables activation of the
INT line when GPIO input levels are changed. Each ’1’ in the
Interrupt Mask register masks (disables) interrupts generated
from the corresponding input line of the GPort selected by the
Port Select register (18h).
Select PWM Register (1Ah)
This register allows each port to act as a PWM output. By default,
all ports are configured as GPIO lines. Each ’1’ in this register
connects the corresponding pin of the GPort selected by the Port
Select register (18h) to the PWM output. Output register data
also affects the pin state when a PWM is enabled. See Table 8.
Note that a pin used as PWM output must be configured to the
appropriate drive mode. See Table 10 on page 11 for more information.
Drive Mode Registers (1Dh-23h)
Each port's data pins can be set separately to one of seven
available modes: pull up or down, open drain high/low, strong
drive fast/slow, or high-impedance input. To perform this configuration, the seven drive mode registers are used for the GPort
selected by the Port Select register (18h). Each ’1’ written to this
register changes the corresponding line drive mode. Registers
1Dh through 23h have last register priority meaning that the bit
set to high in which the last register was written overrides those
that came before. Reading these registers reflects the actual
setting, not what was originally written.
Table 10. Drive Mode Register Settings
Reg.
Pin State
Description
Resistive Pull Up
1Eh
Resistive Pull Down Strong High, Resistive Low
1Fh
Open Drain High
Pin State
20h
Open Drain Low
Slow Strong Low, High Z High
21h
Strong Drive
Strong High, Strong Low, Fast
Output Mode
22h
Slow Strong Drive
Strong High, Strong Low,
Slow Output Mode
23h
High Impedance
High Z
Table 8. Output and Select PWM Registers Logic
Select PWM
Each bit in a port is configurable as either an input or an output.
To perform this configuration, the Port Direction register (1Ch) is
used for the GPort selected by the Port Select register (18h). If
a bit in this register is set (written with '1'), the corresponding port
pin is enabled as an input. If a bit in this register is cleared (written
with '0'), the corresponding port pin is enabled as an output.
1Dh
Table 8 describes the logic of the Output and Select PWM
registers.
Output
Port Direction Register (1Ch)
0
0
0
1
0
1
0
1
0
1
1
Current PWM
Resistive High, Strong Low
(default)
Slow Strong High, High Z Low
Inversion Register (1Bh)
This register can invert the logic of the input ports. Each ’1’
written to this register inverts the logic of the corresponding bit in
the Input register of the GPort selected by the Port Select register
(18h).
Document Number: 38-12036 Rev. *B
PWM Select Register (28h)
This register is configures the PWM. Write a value of 00h-0Fh to
this register to select the PWM to program with registers
29h-2Bh.
Page 11 of 24
[+] Feedback
CY8C9520A, CY8C9540A
CY8C9560A
Config (29h)
Divider Register (2Ch)
This register selects the clock source for the PWM selected by
the PWM Select register (28h) and interrupt logic.
This register sets the frequency on the output of the programmable divider:
There are six available clock sources: 32 kHz (default), 24 MHz,
1.5 MHz, 93.75 kHz, 367.6 Hz, or previous PWM output. The
367.6 Hz clock is user programmable. It divides the 93.75 kHz
clock source by the divisor stored in the Divider register (2Ch).
The default divide ratio is 255. (see Table 11 for details). By
default, all PWMs are clocked from 32 kHz.
Table 11. PWM Clock Sources
Config PWM
PWM Clock Source
xxxxx000b
32 kHz (default)
xxxxx001b
24 MHz
xxxxx010b
1.5 MHz
xxxxx011b
93.75 kHz
xxxxx100b
367.6 Hz (programmable)
xxxxx101b
Previous PWM
Frequency =
93.75 kHz
.
Divider
Allowed values are between 1 and 255.
Enable Register (2Dh)
The WDE bit configures the write disable pin to operate either as
a GPIO or as WD. It also enables/disables EEPROM operations
(EEE bit) or makes the EEPROM read-only (EERO bit). Bit
assignments are shown in Table 13 on page 12.
Table 13. Enable Register
Bit
Each PWM can generate an interrupt at the rising or falling edge
of the output pulse. There is a limitation on the clock source for
a PWM to generate an interrupt. Only the slowest speed source
(programmed to 367.6 Hz) with the divider equal to 255 allows
interrupt generation. Consequently, to create a PWM interrupt, it
is necessary to choose the programmable divider output as the
clock source (write xxxxx100b to Config register (29h)), write 255
to the Divide register (2Ch), and select PWM for pin output (1Ah).
Interrupt status is reflected in the Interrupt Status registers
(10h-17h) and can cause INT line activation if enabled by the
corresponding mask bit in the Interrupt Mask register:
7
6
5
4
3
2
1
0
Function
Reserved
EERO
EEE
WDE
Default
Reserved
0
0
0
Each ’1’ enables the corresponding feature, ’0’ disables.
Writes to this register differ from other registers. The write
sequence to modify the Enable register is as follows:
1. Send device I2C address with bit 0.
2. Send register address 2Dh.
3. Send unlock key - the sequence of three bytes: 43h, 4Dh, 53h;
('C', 'M', 'S' in ASCII bytes).
4. Send new Enable register value.
Period Register (2Ah)
This write sequence secures the register from accidental
changes. The register can be read without the use of the unlock
key.
Table 12. Period Register
By default, EERO and EEPROM (EEE bit) are disabled and WD
line (WDE bit) is set to GPIO (WD disabled).
Config PWM
PWM Interrupt on
xxxx0xxxb
Falling pulse edge (default)
xxxx1xxxb
Rising pulse edge
When performing a burst write operation that crosses this
register, the data written to this register is ignored and the
address increments to 2Eh.
Device ID/Status Register (2Eh)
This register sets the period of the PWM counter. Allowed values
are between 1 and FFh. The effective output waveform period of
the PWM is:
tOUT = Period ⋅ tCLK
Pulse Width Register (2Bh)
This register sets the pulse width of the PWM output. Allowed
values are between zero and the (Period - 1) value. The duty
cycle ratio can be computed using the following equation:
This register stores device identifiers (2xh/4xh/6xh) and reflects
which settings were loaded during startup, either factory defaults
(FD) or user defaults (UD). By default during startup, the device
attempts to load the user default block. If it is corrupted then
factory defaults are loaded and the low nibble of this register is
set high to inform which set is active. The high nibble is always
equal to 2 for CY8C9520A, 4 for CY8C9540A, and 6 for
CY8C9560A.
This register is read-only.
Table 14. Device ID Status Register
Bit
DutyCycle =
PulseWidth
.
Period
Document Number: 38-12036 Rev. *B
7
6
5
4
Function Device Family (2, 4,or 6)
3
2
Reserved
1
0
FD/UD
Page 12 of 24
[+] Feedback
CY8C9520A, CY8C9540A
CY8C9560A
Watchdog Register (2Fh)
Write E2 POR Defaults Cmd (03h)
This register controls the internal Watchdog timer. This timer can
trigger a device reset if the device is not responding to I2C
requests due to misconfiguration. Device operation is not
affected when the Watchdog register = 0. If the I2C master writes
any non zero value to the Watchdog register, the countdown
mechanism is activated and each second the register is decremented. Upon transition from 1 to 0, the device is rebooted,
which restores user defaults. After reboot, the Watchdog register
value is reset to zero. Any I2C transaction (addressing the
Expander) resets the Watchdog register to the previously stored
value. Any device reboot (caused by a POR or Watchdog) sets
the Watchdog register to zero (turns off the Watchdog feature).
The Watchdog timer can be disabled by writing zero to the
Watchdog register (2Fh) or by using the Reconfigure Device
Cmd (07h).
This command sends new power up defaults to the CY8C95xx
without changing current settings unless the 07h command is
issued afterwards. This command is followed by 147 data bytes
according to Table 16. The CRC is calculated as the XOR of the
146 data bytes (00h-91h). If the CRC check fails or an incomplete block is sent, then the slave responds with a NAK and the
data does not get saved to EEPROM.
Note The Watchdog timer is not intended to track precise time
intervals. The timer's frequency can vary in range between -50%
on up to +100%. This variation must be taken into account when
selecting the appropriate value for the Watchdog register.
To define new POR defaults the user must:
■
Write command 03h
■
Write 146 data bytes with new values of registers
■
Write 1 CRC byte calculated as XOR of previous 146 data
bytes.
Content of the data block is described in Table 16.
Table 16. POR Defaults Data Structure
Offset
Value
Command Register (30h)
00h – 07h
Output Port 0-7
This register sends commands to the device, including current
configuration as new POR defaults, restore factory defaults,
define POR defaults, read POR defaults, write device configuration, read device configuration, and reconfigure device with
stored POR defaults. The command set is presented in Table 15.
08h – 0Fh
Interrupt mask Port 0-7
10h – 17h
Select PWM Port 0-7
Note Registers are not restored in parallel. Do not assume any
particular order to the restoration process.
28h
Resistive pull up Drive Mode Port 0
29h
Resistive pull down Drive Mode Port 0
2Ah
Open drain high Drive Mode Port 0
2Bh
Open drain low Drive Mode Port 0
2Ch
Strong drive Drive Mode Port 0
2Dh
Slow strong drive Drive Mode Port 0
2Eh
High impedance Drive Mode Port 0
2Fh – 35h
Drive Modes Port 1
Table 15. Available Commands
Command
Description
01h
Store device configuration to EEPROM POR
defaults
02h
Restore Factory Defaults
03h
Write EEPROM POR defaults
04h
Read EEPROM POR defaults
05h
Write device configuration
06h
Read device configuration
07h
Reconfigure device with stored POR defaults
Commands Description
Store Config to E2 POR Defaults Cmd (01h)
The current ports settings (drive modes and output data) and
other configuration registers are saved in the EEPROM by using
the store configuration command (Cmd). These settings are
automatically loaded after the next device power up or if the 07h
command is issued.
18h – 1Fh
Inversion Port 0-7
20h – 27h
Pin Direction Port 0-7
36h – 3Ch
Drive Modes Port 2
3Dh – 43h
Drive Modes Port 3
44h – 4Ah
Drive Modes Port 4
4Bh – 51h
Drive Modes Port 5
52h – 58h
Drive Modes Port 6
59h – 5Fh
Drive Modes Port 7
60h
Config setting PWM0
61h
Period setting PWM0
62h
Pulse Width setting PWM0
63h – 65h
PWM1 settings
…
…
8Dh – 8Fh
PWM15 settings
Restore Factory Defaults Cmd (02h)
90h
Divider
This command replaces the saved user configuration with the
factory default configuration. Current settings are unaffected by
this command. New settings are loaded after the next device
power up or if the 07h command is issued.
91h
Enable
92h
CRC
Document Number: 38-12036 Rev. *B
Page 13 of 24
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CY8C9520A, CY8C9540A
CY8C9560A
Read E2 POR Defaults Cmd (04h)
To read device configuration the user must:
This command reads the POR settings stored in the EEPROM.
■
Write command 06h
To read POR defaults the user must:
■
Read 146 data bytes (see Table 16).
■
Write command 04h
■
Read 1 CRC byte.
■
Read 146 data bytes (see Table 16)
■
Read 1 CRC byte.
Write Device Config Cmd (05h)
Reconfigure Device Cmd (07h)
This command immediately reconfigures the device with actual
POR defaults from EEPROM. It has the same effect on the
registers as a POR.
This command sends a new device configuration to the
CY8C95xx. It is followed by 146 data bytes according to
Table 16. The CRC is calculated as the XOR of the 146 data
bytes (00h-91h). If the CRC check fails or an incomplete block is
sent, then the slave responds with a NAK and the device does
not use the data. This gives the user ‘flat-address-space’ access
to all device settings.
To set the current device configuration the user must:
■
Write command 05h
■
Write 146 data bytes with new values of registers
■
Write 1 CRC byte calculated as XOR of previous 146 data
bytes.
If the CRC check passes, then the device uses the new settings
immediately.
Content of the data block is described in Table 16.
Read Device Config Cmd (06h)
This command reads the current device configuration. It gives
the user ‘flat-address-space’ access to all device settings.
Document Number: 38-12036 Rev. *B
Page 14 of 24
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CY8C9560A
Electrical Specifications
This section lists the DC and AC electrical specifications of the CY8C95xxA device. For the most up to date electrical specifications,
confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted.
Table 17 lists the units of measure that are used in this section.
Table 17. Units of Measure
Symbol
C
kHz
MHz
μs
μV
μVrms
o
Unit of Measure
degree Celsius
kilohertz
megahertz
microsecond
microvolts
microvolts root-mean-square
Symbol
mA
nA
ns
pF
V
Unit of Measure
milli-ampere
nanoampere
nanosecond
picofarad
volts
Absolute Maximum Ratings
Table 18. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
Min
-55
Typ
25
Max
+100
TA
Vdd
VIO
Ambient temperature with power applied
Supply voltage on Vdd relative to Vss
DC input voltage
–
–
–
VIOZ
DC voltage applied to tri-state
IMIO
ESD
LU
Maximum current into any port pin
Electro Static Discharge Voltage
Latch up current
-40
-0.5
Vss 0.5
Vss 0.5
-25
2000
–
+85
+6.0
Vdd +
0.5
Vdd +
0.5
+50
–
200
–
–
–
–
Units
oC
Notes
Higher storage temperatures
reduces data retention time.
Recommended storage temperature is +25oC ± 25oC. Extended
duration storage temperatures
above 65oC degrades reliability.
oC
V
V
V
mA
V
mA
Human Body Model ESD.
Operating Temperature
Table 19. Operating Temperature
Symbol
Description
TA
Ambient temperature
TJ
Junction temperature
Document Number: 38-12036 Rev. *B
Min
-40
-40
Typ
–
–
Max
+85
+100
Units
Notes
oC
o
C
The temperature rise from ambient
to junction is package specific. See
“Thermal Impedances per
Package” on page 22. The user
must limit the power consumption
to comply with this requirement.
Page 15 of 24
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CY8C9560A
DC Electrical Characteristics
DC Chip-Level Specifications
Table 20 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only.
Table 20. CY8C9520A DC Chip-Level Specifications
Symbol
Description
Vdd
Supply voltage
IDD
Supply current Vdd 5V
IDD3
Supply current Vdd 3.3V
Min
3.00
–
–
Typ
–
3.8
2.3
Max
5.25
5
3
Units
V
mA
mA
Typ
–
6
3.3
Max
5.25
9
6
Units
V
mA
mA
Typ
–
15
5
Max
5.25
25
9
Units
V
mA
mA
Notes
Conditions are 5.0V, TA = 25 oC, IOH = 0.
Conditions are 3.3V, TA = 25 oC, IOH = 0.
Table 21. CY8C9540A DC Chip-Level Specifications
Symbol
Description
Vdd
Supply voltage
IDD
Supply current Vdd 5V
IDD3
Supply current Vdd 3.3V
Min
3.00
–
–
Notes
Conditions are 5.0V, TA = 25 oC, IOH = 0.
Conditions are 3.3V, TA = 25 oC, IOH = 0.
Table 22. CY8C9560A DC Chip-Level Specifications
Symbol
Description
Vdd
Supply voltage
IDD
Supply current Vdd 5V
IDD3
Supply current Vdd 3.3V
Min
3.00
–
–
Notes
Conditions are 5.0V, TA = 25 oC, IOH = 0.
Conditions are 3.3V, TA = 25 oC, IOH = 0.
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 23. DC Programming Specifications
Symbol
FlashENPB
FlashENT
FlashDR
a.
Description
Min
Flash (EEPROM) endurance (by block) 10,000
Flash endurance (total)a
1,800,000
Flash data retention
10
Typ
–
–
–
Max
–
–
–
Units
–
–
Years
Notes
Erase/write cycles by block.
Erase/write cycles.
A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles
each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles).
Document Number: 38-12036 Rev. *B
Page 16 of 24
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CY8C9560A
DC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 24. DC GPIO Specifications
Symbol
VOH
Description
High output level
Min
Vdd 1.0
–
–
Units
V
VOL
Low output level
–
–
0.75
V
VIL
VIH
IIL
Input low level
Input high level
Input leakage
(absolute value)
Capacitive load on
pins as input
Capacitive load on
pins as output
–
2.1
–
–
–
1
0.8
–
V
V
nA
Notes
IOH = 10 mA for any one pin, Vdd = 4.75 to 5.25V.
40 mA maximum combined IOH for GPort0; GPort2_Bit3;
GPort3; GPort5_Bit2, 3, 6, 7; GPort6.
40 mA maximum combined IOH for GPort1; GPort2_Bit0, 1,
2; GPort4; GPort5_Bit0, 1, 4, 5; GPort7.
80 mA maximum combined IOH.
IOL = 25 mA for any one pin, Vdd = 4.75 to 5.25V.
100 mA maximum combined IOL for GPort0; GPort2_Bit3;
GPort3; GPort5_Bit2, 3, 6, 7; GPort6.
100 mA maximum combined IOL for GPort1; GPort2_Bit0, 1,
2; GPort4; GPort5_Bit0, 1, 4, 5; GPort7.
200 mA maximum combined IOL.
Vdd = 3.0 to 5.5.
Vdd = 3.0 to 5.5.
Gross tested to 1 μA.
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
–
3.5
10
pF
Package and pin dependent. Temp = 25oC.
CIN
COUT
Document Number: 38-12036 Rev. *B
Typ
Max
Page 17 of 24
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CY8C9560A
AC Electrical Characteristics
AC General Purpose IO Specifications
Table 25 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only or unless otherwise specified.
Table 25. AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise time, normal strong mode, Cload = 50 pF
Fall time, normal strong mode, Cload = 50 pF
Rise time, slow strong mode, Cload = 50 pF
Fall time, slow strong mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
Vdd = 4.75 to 5.25V, 10% - 90%
Vdd = 4.75 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 8. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC PWM Output Jitter Specifications
Table 26 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only or unless otherwise specified.
Table 26. AC PWM Output Jitter Specifications
Symbol
Description
Min
Jitter24MHzPWM 24 MHz based PWM peak-to-peak period –
jitter
Typ
0.1
Max
1.5
Units
%
Jitter32kHzPWM
2.5
5.0
%
32 kHz-based PWM peak-to-peak period –
jitter
Document Number: 38-12036 Rev. *B
Notes
24 MHz, 1.5 MHz, 93.75 kHz and
367.6 Hz (programmable)
sources.
32 kHz clock source.
Page 18 of 24
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AC I2C Specifications
Table 27 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C
≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design
guidance only or unless otherwise specified.
Table 27. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Description
SCL clock frequency
FSCLI2C
THDSTAI2C Hold time (repeated) START condition. After
this period, the first clock pulse is generated.
TLOWI2C
LOW period of the SCL clock
HIGH period of the SCL clock
THIGHI2C
TSUSTAI2C Setup time for a repeated START condition
THDDATI2C Data hold time
TSUDATI2C Data setup time
TSUSTOI2C Setup time for STOP condition
Bus free time between a STOP and START
TBUFI2C
Condition
TSPI2C
Pulse width of spikes are suppressed by the
input filter.
Standard Mode
Fast Mode
Min
Max
Min
Max
0
100
0
–
4.0
–
0.6
–
kHz
μs
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
1.3
0.6
0.6
0
1003
0.6
1.3
–
–
–
–
–
–
–
μs
μs
μs
μs
ns
μs
μs
–
–
0
–
ns
Units
Notes
Figure 9. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
T LOWI2C
T SPI2C
T SUDATI2C
THDSTAI2C
T BUFI2C
SCL
S T HDSTAI2C T HDDATI2C T HIGHI2C
Document Number: 38-12036 Rev. *B
TSUSTAI2C
Sr
T SUSTOI2C
P
S
Page 19 of 24
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CY8C9560A
Packaging Dimensions
This section illustrates the packaging specifications for the CY8C95xxA device, along with the thermal impedances for each package,
the typical package capacitance on crystal pins, and the solder reflow peak temperature.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 10. 28-Pb (210-Mil) SSOP
51-85079 - *C
Document Number: 38-12036 Rev. *B
Page 20 of 24
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CY8C9560A
Figure 11. 48-Pb (300-Mil) SSOP
51-85061 - *C
Figure 12. 100-Pb (14 x 14 x 1.0 mm) TQFP
51-85048 - *C
Document Number: 38-12036 Rev. *B
Page 21 of 24
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Thermal Impedances
Table 28. Thermal Impedances per Package
Typical θJA a
101oC/W
69oC/W
48oC/W
Package
28 SSOP
48 SSOP
100 TQFP
a. TJ = TA + POWER x θJA
Solder Reflow Peak Temperature
Table 29 lists the minimum solder reflow peak temperature to achieve good solderability.
Table 29. Solder Reflow Peak Temperature
Package
Minimum Peak Temperaturea
Maximum Peak Temperature
28 SSOP
240oC
260oC
48 SSOP
220oC
260oC
100 TQFP
220oC
260oC
a. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC with Sn-Pb or 245+/-5oC with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 38-12036 Rev. *B
Page 22 of 24
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CY8C9560A
Features and Ordering Information
Table 30 lists the CY8C95xxA device’s key package features and ordering codes. A definition of the ordering number code follows.
a.
CY8C9520A-24PVXIa
CY8C9520A-24PVXIT1
CY8C9540A-24PVXI1
CY8C9540A-24PVXIT1
CY8C9560A-24AXI1
CY8C9560A-24AXIT1
3K
3K
11K
11K
27K
27K
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
Configurable
IO Pins
PWM
Sources
EEPROM
(Bytes)
Ordering
Code
Package
28 Pin (210 Mil) SSOP
28 Pin (210 Mil) SSOP (Tape and Reel)
48 Pin (300 Mil) SSOP
48 Pin (300 Mil) SSOP (Tape and Reel)
100 Pin TQFP
100 Pin TQFP (Tape and Reel)
Temperature
Range
Table 30. CY8C95xxA Device Key Features and Ordering Information
4
4
8
8
16
16
20
20
40
40
60
60
The A after the existing port expander part number indicates new device firmware.
Ordering Code Definitions
CY 8 C 9 xxx-SPxx
Package Type:
PX = PDIP Pb-Free
SX = SOIC Pb-Free
PVX = SSOP Pb-Free
LFX = QFN Pb-Free
LKX = QFN Pb-Free
AX = TQFP Pb-Free
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Document Number: 38-12036 Rev. *B
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Document History Page
Document Title: CY8C9520A, CY8C9540A, CY8C9560A, 20-, 40-, and 60-Bit IO Expander with EEPROM
Document Number: 38-12036
Revision
ECN
Orig. of
Change
Description of Change
**
346754
HMT
New silicon, document.
*A
392484
HMT
Correct pin 79 on the TQFP. Add AC PWM Output Jitter spec. table. Upgrade to CY Perform logo and update
zip code and trademarks.
*B
1336984
HMT/AESA
Update typical and recommended Storage Temperature per industrial specs. Update copyright and trademarks. Add Watchdog timer details. Add “A” to existing part numbers to indicate new firmware. Fix errors.
Implement CY template.
Distribution: External/Public Posting: None
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12036 Rev. *B
Revised August 03, 2007
Page 24 of 24
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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