NSC PC87317VUL

- February 1998
PC87317VUL/PC97317VUL SuperI/O Plug and Play
Compatible with ACPI Compliant Controller/Extender
Highlights
General Description
The PC87317VUL provides a LED drive output to comply
with PC97 specifications. The chip also provides support for
Power Management (PM), including a WATCHDOG timer,
and standard PC-AT address decoding for on-chip functions.
The PC87317VUL/PC97317VUL are functionally identical
parts that offer a single-chip solution to the most commonly
used ISA, EISA and MicroChannel® peripherals. This fully
Plug and Play (PnP) compatible chip conforms to the Plug
and Play ISA Specification Version 1.0a, May 5, 1994, and
meets specifications defined in the PC97 Hardware Design
Guide. It features a Controller/Extender that is fully compliant with Advanced Configuration and Power Interface (ACPI) Revision 1.0 requirements.
The PC87317VUL Infrared (IR) interface complies with the
HP-SIR and SHARP-IR standards, and supports all four basic protocols for Consumer Remote Control circuitry (RC-5,
RC-5 extended, RECS80 and NEC).
Outstanding Features
Note: All references to the PC87317VUL in this document
also refer to the PC97317VUL, unless otherwise specified.
References which are applicable to the PC97317VUL only
are italicized.
Among the most advanced members of National Semiconductor’s highly successful SuperI/O family, the PC87317VUL
offers:
The PC87317VUL incorporates: an advanced Real-Time
Clock (RTC) device that provides both RTC timekeeping and
Advanced Power Control (APC) functionality, a Floppy Disk
Controller (FDC), a Keyboard and Mouse Controller (KBC),
two enhanced Serial Ports (UARTs) with Infrared (IR) support, a full IEEE 1284 Parallel Port, 24 General-Purpose Input/Output (GPIO) bit ports, three general-purpose chip
select signals that can be programmed for game port control
and a separate configuration register set for each module.
●
Full compatibility with ACPI Revision 1.0 requirements
●
Compliancy with PC97 Hardware Design Guide specifications, including PC97 LED support
●
Advanced RTC, including timekeeping and APC functionality
●
24 GPIO bit ports
●
FDC, KBC, two enhanced UARTs, IR support, IEEE
1284 parallel port
Block Diagram
DMA
IRQ Channels
Plug and Play
(PnP)
Data and
Control Ports
Keyboard + Mouse
Controller (KBC)
(Logical Devices 0 & 1)
Control
Real-Time Clock
(RTC and APC)
(Logical Device 2)
Data
Control
X-Bus
Floppy Drive
Interface
Floppy Disk
Controller (FDC)
(Logical Device 3)
µP Address
Data and
Control
Power
General-Purpose I/O
IEEE 1284
Serial Port
Serial Port
Management (PM)
Parallel Port
with IR (UART2)
(GPIO) Registers
(UART1)
(Logical Device 4) (Logical Devices 5) (Logical Devices 6)
(Logical Device 7) (Logical Device 8)
Data Handshake
Serial Infrared
Interface Interface
Serial
Interface
I/O Ports
Control
TRI-STATE® and WATCHDOG are trademarks of National Semiconductor Corporation.
IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
© 1998 National Semiconductor Corporation
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Highlights
PRELIMINARY
February 1998
Highlights
Features
●
100% compatibility with PnP requirements specified in
the “Plug and Play ISA Specification”, ISA, EISA, and
MicroChannel architectures
●
A special PnP module that includes:
— Flexible IRQs, DMAs and base addresses that meet
the PnP requirements specified by Microsoft® in
their 1995 hardware design guide for Windows® and
PnP ISA Revision 1.0A
— PnP ISA mode (with isolation mechanism – Wait for
Key state)
— Motherboard PnP mode
●
An FDC that provides:
— A modifiable address that is referenced by a 16-bit
programmable register
— Software compatibility with the PC8477, which contains a superset of the floppy disk controller functions in the µDP8473, the NEC µPD765A and the
N82077
— 13 IRQ channel options
— Four 8-bit DMA channel options
— 16-byte FIFO
— Burst and non-burst modes
— A new, high-performance, internal, digital data separator that does not require any external filter components
— Support for standard 5.25" and 3.5" floppy disk
drives
— Automatic media sense support
— Perpendicular recording drive support
— Three-mode Floppy Disk Drive (FDD) support
— Full support for the IBM Tape Drive Register (TDR)
implementation of AT and PS/2 drive types
●
— Customizing by using the PC87323VUL, which includes a RAM-based KBC, as a development platform for keyboard controller code for the
PC87317VUL
A KBC with:
— A modifiable address that is referenced by a 16-bit
programmable register, reported as a fixed address
in resource data
— 13 IRQ options for the Keyboard Controller
— 13 IRQ options for the Mouse Controller
— An 8-bit microcontroller
— Software compatibility with 8042AH and PC87911
microcontrollers
— 2 KB of custom-designed program ROM
— 256 bytes of RAM for data
— Five programmable dedicated open drain I/O lines
for keyboard controller applications
— Asynchronous access to two data registers and one
status register during normal operation
— Support for both interrupt and polling
— 93 instructions
— An 8-bit timer/counter
— Support for binary and BCD arithmetic
— Operation at 8 MHz,12 MHz or 16 MHz (programmable option)
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●
An RTC that has:
— A modifiable address that is referenced by a 16-bit
programmable register
— 13 IRQ options, with programmable polarity
— DS1287, MC146818 and PC87911 compatibility
— 242 bytes of battery backed up CMOS RAM in two
banks
— Selective lock mechanisms for the RTC RAM
— Battery backed up century calendar in days, day of
the week, date of month, months, years and century,
with automatic leap-year adjustment
— Battery backed-up time of day in seconds, minutes
and hours that allows a 12 or 24 hour format and adjustments for daylight savings time
— BCD or binary format for time keeping
— Three different maskable interrupt flags:
• Periodic interrupts - At intervals from 122 msec
to 500 msec
• Time-of-Month alarm - At intervals from once per
second to once per Month
• Updated Ended Interrupt - Once per second
upon completion of update
— Separate battery pin, 2.4 V operation that includes
an internal UL protection resistor
— 2 µA maximum power consumption during power
down
— Double-buffer time registers
●
ACPI Controller/Extender that supports the requirements of the ACPI spec (rev 1.0):
— Power Management Timer
— Power Button
— Real Time Clock Alarm
— Suspend modes via software emulation
— PnP SCI
— Global Lock mechanism
— General Purpose events
— Date of Month Alarm
— Century byte
●
An APC that controls the main power supply to the system, using open-drain output, as follows:
Power turned on when:
— The RTC reaches a pre-determined wake-up century, date and time selection
— A high to low transition occurs on the RI input signals
of the UARTs
— A ring pulse or pulse train is detected on the RING
input signal
— A SWITCH input signal indicates a Switch On event
with a debounce-protection
— Any one of seven programmable Power Management external trigger events occur
Powered turned off when:
— A SWITCH input signal indicates a Switch Off event
Highlights
— A Fail-safe event occurs (power-save mode detected
but the system is hung up)
— Software turns power off
— Any one of 10 programmable Power Management
trigger events occur
●
Two Serial Ports (UART1 and 2) that provide:
— Fully compatible with the 16550A and the 16450
— Extended UART mode
— 13 IRQ channel options
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
●
An enhanced UART with IR interface on the UART2 that
supports:
— IrDA 1.0-SIR
— ASK-IR option of SHARP-IR
— DASK-IR option of SHARP-IR
— Consumer Remote Control circuitry
— DMA handshake signal routing for either 1 or 2 channels
— A PnP compatible external transceiver
●
●
A bidirectional parallel port that includes:
— A modifiable address that is referenced by a 16-bit
programmable register
— Software or hardware control
— 13 IRQ channel options
— Four 8-bit DMA channel options
— Demand mode DMA support
— An Enhanced Parallel Port (EPP) that is compatible
with the new version EPP 1.9, and is IEEE 1284
compliant
— An Enhanced Parallel Port (EPP) that also supports
version EPP 1.7 of the Xircom specification
— Support for an Enhanced Parallel Port (EPP) as
mode 4 of the Extended Capabilities Port (ECP)
— An Extended Capabilities Port (ECP) that is IEEE
1284 compliant, including level 2
— Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
— Reduction of PCI bus utilization by supporting a demand DMA mode mechanism and a DMA fairness
mechanism
— A protection circuit that prevents damage to the parallel port when a printer connected to it powers up or
is operated at high voltages
— Output buffers that can sink and source14 mA
●
24 single-bit GPIO ports:
— Modifiable addresses that are referenced by a 16-bit
programmable register
— Programmable direction for each signal (input or output)
— Programmable drive type for each output pin (opendrain or push-pull)
— Programmable option for internal pull-up resistor on
each input pin
— Configuration-Lock options
— Several signals may be selected as interrupt triggers
— A back-drive protection circuit
●
An X-bus data buffer that connects the 8-bit X data bus
to the ISA data bus
●
Clock source options:
— Source is a 32.768 KHz crystal - an internal frequency multiplier generates all the required internal frequencies.
— Source may be either a 48 MHz or 24 MHz clock input signal.
●
Enhanced Power Management (PM), including:
— Special configuration registers for power down
— WATCHDOG timer for power-saving strategies
— Reduced current leakage from pins
— Low-power CMOS technology
— Ability to shut off clocks to all modules
— LED control powered by VCCH
●
General features include:
— All accesses to the SuperI/O chip activate a Zero
Wait State (ZWS) signal, except for accesses to the
Enhanced Parallel Port (EPP) and to configuration
registers
— Access to all configuration registers is through an Index and a Data register, which can be relocated
within the ISA I/O address space
— 160-pin Plastic Quad Flatpack (PQFP) package
Three general-purpose pins for three separate programmable chip select signals, as follows:
— Can be programmed for game port control
— The Chip Select 0 (CS0) signal produces open drain
output and is powered by the VCCH
— The Chip Select 1 (CS1) and 2 (CS2) signals have
push-pull buffers and are powered by the main VDD
— Decoding of chip select signals depends on the address and the Address Enable (AEN) signals, and
can be qualified using the Read (RD) and Write
(WR) signals.
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Highlights
Basic Configuration
X1
ISA Bus
LED
X-Bus
Parallel
Port
Connector
Configuration
Select Logic
CS2,0
WDO
POR
ONCTL
VCCH
SWITCH
RING
MR
AEN
A15-0
D7-0
RD
WR
IOCHRDY
ZWS
IRQ1
IRQ12-3
IRQ15-14
DRQ3-0
DACK3-0
TC
GPIO37-30
GPIO27-20
MCLK
MDAT
KBDAT
KBCLK
P17,16,12
P21,20
Clock
GPIO17-10
General Purpose I/O
(GPIO)
Keyboard I/O
Interface
Power
Management
(PM)
SIN1
SOUT1
RTS1
DTR1/BOUT1
CTS1
DSR1
DCD1
RI1
PC87317VUL
EIA
Drivers
IRRX2,1
IRTX
Infrared (IR)
IRSL2-0
Interface
ID3-0
SIN2
SOUT2
RTS2
DTR2/BOUT2
CTS2
DSR2
DCD2
RI2
LED
XDRD
XDCS
XD7-0
EIA
Drivers
RDATA
WDATA
WGATE
HDSEL
DIR
STEP
PD7-0
SLIN/ASTRB
STB/WRITE
AFD/DSTRB
INIT
TRK0
INDEX
DSKCHG
WP
MTR1,0
DR1,0
DENSEL
MSEN1,0
DRATE0
ACK
ERR
SLCT
PE
BUSY/WAIT
BADDR1,0
CFG1,0
SELCS
FDC
Connector
VBAT
X1C
X2C
Real-Time Clock (RTC)
Crystal and Power
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Table of Contents
Table of Contents
Highlights ....................................................................................................................................................... 1
1.0
2.0
Signal/Pin Connection and Description
1.1
CONNECTION DIAGRAM ......................................................................................................... 16
1.2
SIGNAL/PIN DESCRIPTIONS ................................................................................................... 17
Configuration
2.1
HARDWARE CONFIGURATION ............................................................................................... 27
2.1.1
Wake Up Options ........................................................................................................ 27
2.1.2
The Index and Data Register Pair ............................................................................... 27
2.1.3
The Strap Pins ............................................................................................................. 28
2.2
SOFTWARE CONFIGURATION ............................................................................................... 28
2.2.1
Accessing the Configuration Registers ........................................................................ 28
2.2.2
Address Decoding ....................................................................................................... 28
2.3
THE CONFIGURATION REGISTERS ....................................................................................... 29
2.3.1
Standard Plug and Play (PnP) Register Definitions .................................................... 30
2.3.2
Configuration Register Summary ................................................................................ 33
2.4
CARD CONTROL REGISTERS ................................................................................................ 37
2.4.1
PC87317 SID Register ................................................................................................ 37
2.4.2
PC97317 SID Register ................................................................................................ 37
2.4.3
SuperI/O Configuration 1 Register (SIOC1) ................................................................ 37
2.4.4
SuperI/O Configuration 2 Register (SIOC2) ................................................................ 38
2.4.5
Programmable Chip Select Configuration Index Register ........................................... 38
2.4.6
Programmable Chip Select Configuration Data Register ............................................ 39
2.4.7
SuperI/O Configuration 3 Register (SIOC3) ................................................................ 39
2.4.8
PC97317 SRID Register .............................................................................................. 39
2.4.9
SuperI/O Configuration F Register (SIOCF), Index 2Fh .............................................. 40
2.5
KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0) .................................................... 40
2.5.1
SuperI/O KBC Configuration Register ......................................................................... 40
2.6
FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 3) .................................................. 40
2.6.1
SuperI/O FDC Configuration Register ......................................................................... 40
2.6.2
Drive ID Register ......................................................................................................... 41
2.7
PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 4) ............................... 41
2.7.1
SuperI/O Parallel Port Configuration Register ............................................................. 41
2.8
UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5) .................... 42
2.8.1
SuperI/O UART2 Configuration Register ..................................................................... 42
2.9
UART1 CONFIGURATION REGISTER (LOGICAL DEVICE 6) ................................................ 42
2.9.1
SuperI/O UART1 Configuration Register ..................................................................... 42
2.10
PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS ...................................... 42
2.10.1 CS0 Base Address MSB Register ............................................................................... 43
2.10.2 CS0 Base Address LSB Register ................................................................................ 43
2.10.3 CS0 Configuration Register ......................................................................................... 43
2.10.4 Reserved ..................................................................................................................... 43
2.10.5 CS1 Base Address MSB Register ............................................................................... 43
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Table of Contents
2.10.6
2.10.7
2.10.8
2.10.9
2.10.10
2.10.11
2.10.12
2.10.13
2.11
3.0
4.0
CS1 Base Address LSB Register ................................................................................ 43
CS1 Configuration Register ......................................................................................... 43
Reserved ..................................................................................................................... 44
CS2 Base Address MSB Register ............................................................................... 44
CS2 Base Address LSB Register ................................................................................ 44
CS2 Configuration Register ......................................................................................... 44
Reserved, Second Level Indexes 0Bh-0Fh ................................................................. 44
Not Accessible, Second Level Indexes 10h-FFh ......................................................... 44
CONFIGURATION REGISTER BITMAPS ................................................................................ 44
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
3.1
SYSTEM ARCHITECTURE ....................................................................................................... 47
3.2
FUNCTIONAL OVERVIEW ....................................................................................................... 48
3.3
DEVICE CONFIGURATION ...................................................................................................... 48
3.3.1
I/O Address Space ...................................................................................................... 48
3.3.2
Interrupt Request Signals ............................................................................................ 48
3.3.3
KBC Clock ................................................................................................................... 49
3.3.4
Timer or Event Counter ............................................................................................... 50
3.4
EXTERNAL I/O INTERFACES .................................................................................................. 50
3.4.1
Keyboard and Mouse Interface ................................................................................... 50
3.4.2
General Purpose I/O Signals ....................................................................................... 50
3.5
INTERNAL KBC - PC87317VUL INTERFACE .......................................................................... 51
3.5.1
The KBC DBBOUT Register, Offset 60h, Read Only .................................................. 52
3.5.2
The KBC DBBIN Register, Offset 60h (F1 Clear) or 64h (F1 Set), Write Only ............ 52
3.5.3
The KBC STATUS Register ........................................................................................ 52
3.6
INSTRUCTION TIMING ............................................................................................................. 52
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
4.1
RTC OVERVIEW ....................................................................................................................... 53
4.1.1
RTC Hardware and Functional Description ................................................................. 53
4.1.2
Timekeeping ................................................................................................................ 54
4.1.3
Power Management .................................................................................................... 55
4.1.4
Interrupt Handling ........................................................................................................ 56
4.2
THE RTC REGISTERS ............................................................................................................. 56
4.2.1
RTC Control Register A (CRA) .................................................................................... 56
4.2.2
RTC Control Register B (CRB) .................................................................................... 57
4.2.3
RTC Control Register C (CRC) ................................................................................... 58
4.2.4
RTC Control Register D (CRD) ................................................................................... 58
4.2.5
Date-of-Month Alarm Register (DMAR ........................................................................ 59
4.2.6
Month Alarm Register (MAR) ...................................................................................... 59
4.2.7
Century Register (CR) ................................................................................................. 59
4.3
APC OVERVIEW ....................................................................................................................... 59
4.3.1
System Power States .................................................................................................. 61
4.3.2
System Power Switching Logic ................................................................................... 62
4.4
APC DETAILED DESCRIPTION ............................................................................................... 62
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Table of Contents
4.4.1
4.4.2
4.4.3
The ONCTL Flip-Flop and Signal ................................................................................ 62
Entering Power States ................................................................................................. 65
System Power-Up and Power-Off Activation Event Description .................................. 67
4.5
APC REGISTERS ...................................................................................................................... 69
4.5.1
APC Control Register 1 (APCR1) ................................................................................ 70
4.5.2
APC Control Register 2 (APCR2) ................................................................................ 70
4.5.3
APC Status Register (APSR) ...................................................................................... 71
4.5.4
Wake up Day of Week Register (WDWR) ................................................................... 71
4.5.5
Wake up Date of Month Register (WDMR) ................................................................. 72
4.5.6
Wake up Month Register (WMR) ................................................................................. 72
4.5.7
Wake up Year Register (WYR) .................................................................................... 72
4.5.8
RAM Lock Register (RLR) ........................................................................................... 72
4.5.9
Wake up Century Register (WCR) .............................................................................. 73
4.5.10 APC Control Register 3 (APCR3) ................................................................................ 73
4.5.11 APC Control Register 4 (APCR4), Bank 2, Index 4Ah ................................................ 74
4.5.12 APC Control Register 5 (APCR5) ................................................................................ 75
4.5.13 APC Control Register 6 (APCR6) ................................................................................ 75
4.5.14 APC Control Register 7 (APCR7) ................................................................................ 76
4.5.15 APC Status Register 1 (APSR1) ................................................................................. 77
4.5.16 Day-of-Month Alarm Address Register (DADDR) ........................................................ 77
4.5.17 Month Alarm Address Register (MADDR) ................................................................... 77
4.5.18 Century Address Register (CADDR) ........................................................................... 77
4.6
ACPI FIXED REGISTERS ......................................................................................................... 78
4.6.1
Power Management 1 Status Low Byte Register (PM1_STS_LOW) .......................... 78
4.6.2
Power Management 1 Status High Byte Register (PM1_STS_HIGH) ........................ 78
4.6.3
Power Management 1 Enable Low Byte Register (PM1_EN_LOW) ........................... 79
4.6.4
Power Management 1 Enable High Byte Register (PM1_EN_HIGH) ......................... 79
4.6.5
Power Management 1 Control Low Byte Register (PM1_CNT_LOW) ........................ 80
4.6.6
Power Management 1 Control High Byte Register (PM1_CNT_HIGH) ....................... 80
4.6.7
Power Management Timer Low Byte Register (PM1_TMR_LOW) ............................. 80
4.6.8
Power Management Timer Middle Byte Register (PM1_TMR_MID) ........................... 81
4.6.9
Power Management Timer High Byte Register (PM1_TMR_HIGH) ............................ 81
4.6.10 Power Management Timer Extended Byte Register (PM1_TMR_EXT) ...................... 81
4.7
GENERAL PURPOSE EVENT REGISTERS ............................................................................ 81
4.7.1
General Purpose 1 Status Register (GP1_STS0) ....................................................... 81
4.7.2
General Purpose 1 Status 1 Register (GP1_STS1), Offset 01h .................................. 82
4.7.3
General Purpose 1 Status 2 Register (GP1_STS2), Offset 02h .................................. 82
4.7.4
General Purpose 1 Status 3 Register (GP1_STS3), Offset 03h .................................. 82
4.7.5
General Purpose 1 Enable 0 Register (GP1_EN0) ..................................................... 82
4.7.6
General Purpose 1 Enable 1 Register (GP1_EN1), Offset 05h ................................... 83
4.7.7
General Purpose 1 Enable 2 Register (GP1_EN2), Offset 06hr ................................. 83
4.7.8
General Purpose 1 Enable 3 Register (GP1_EN3), Offset 07h ................................... 83
4.7.9
General Purpose 2 Enable 0 Register (GP2_EN0) ..................................................... 83
4.7.10 Bit 3 - IRRX2 Enable (IRRX2_E) ................................................................................. 83
4.7.11 SMI Command Register (SMI_CMD), Offset 0Ch ....................................................... 83
4.8
RTC AND APC REGISTER BITMAPS ...................................................................................... 84
4.8.1
RTC Register Bitmaps ................................................................................................. 84
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Table of Contents
4.8.2
4.9
5.0
APC Register Bitmaps ................................................................................................. 84
REGISTER BANK TABLES ....................................................................................................... 89
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
5.1
FDC FUNCTIONS ..................................................................................................................... 92
5.1.1
Microprocessor Interface ............................................................................................. 92
5.1.2
System Operation Modes ............................................................................................ 92
5.2
DATA TRANSFER ..................................................................................................................... 93
5.2.1
Data Rates ................................................................................................................... 93
5.2.2
The Data Separator ..................................................................................................... 93
5.2.3
Perpendicular Recording Mode Support ..................................................................... 94
5.2.4
Data Rate Selection ..................................................................................................... 94
5.2.5
Write Precompensation ............................................................................................... 95
5.2.6
FDC Low-Power Mode Logic ....................................................................................... 95
5.2.7
Reset ........................................................................................................................... 95
5.3
THE FDC REGISTERS ............................................................................................................. 96
5.3.1
Status Register A (SRA) .............................................................................................. 96
5.3.2
Status Register B (SRB) .............................................................................................. 97
5.3.3
Digital Output Register (DOR) ..................................................................................... 97
5.3.4
Tape Drive Register (TDR) .......................................................................................... 99
5.3.5
Main Status Register (MSR) ...................................................................................... 100
5.3.6
Data Rate Select Register (DSR) .............................................................................. 101
5.3.7
Data Register (FIFO) ................................................................................................. 102
5.3.8
Digital Input Register (DIR) ........................................................................................ 103
5.3.9
Configuration Control Register (CCR) ....................................................................... 104
5.4
THE PHASES OF FDC COMMANDS ..................................................................................... 104
5.4.1
Command Phase ....................................................................................................... 104
5.4.2
Execution Phase ........................................................................................................ 104
5.4.3
Result Phase ............................................................................................................. 106
5.4.4
Idle Phase .................................................................................................................. 106
5.4.5
Drive Polling Phase ................................................................................................... 106
5.5
THE RESULT PHASE STATUS REGISTERS ........................................................................ 107
5.5.1
Result Phase Status Register 0 (ST0) ....................................................................... 107
5.5.2
Result Phase Status Register 1 (ST1) ....................................................................... 107
5.5.3
Result Phase Status Register 2 (ST2) ....................................................................... 108
5.5.4
Result Phase Status Register 3 (ST3) ....................................................................... 109
5.6
FDC REGISTER BITMAPS ..................................................................................................... 109
5.6.1
Standard .................................................................................................................... 109
5.6.2
Result Phase Status .................................................................................................. 111
5.7
THE FDC COMMAND SET ..................................................................................................... 112
5.7.1
Abbreviations Used in FDC Commands .................................................................... 113
5.7.2
The CONFIGURE Command .................................................................................... 114
5.7.3
The DUMPREG Command ....................................................................................... 114
5.7.4
The FORMAT TRACK Command ............................................................................. 115
5.7.5
The INVALID Command ............................................................................................ 117
5.7.6
The LOCK Command ................................................................................................ 118
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Table of Contents
5.7.7
5.7.8
5.7.9
5.7.10
5.7.11
5.7.12
5.7.13
5.7.14
5.7.15
5.7.16
5.7.17
5.7.18
5.7.19
5.7.20
5.7.21
5.7.22
5.7.23
5.7.24
5.7.25
5.8
6.0
The MODE Command ............................................................................................... 119
The NSC Command .................................................................................................. 121
The PERPENDICULAR MODE Command ............................................................... 121
The READ DATA Command ..................................................................................... 122
The READ DELETED DATA Command .................................................................... 124
The READ ID Command ........................................................................................... 125
The READ A TRACK Command ............................................................................... 126
The RECALIBRATE Command ................................................................................. 127
The RELATIVE SEEK Command .............................................................................. 127
The SCAN EQUAL, the SCAN LOW OR EQUAL and the SCAN HIGH OR EQUAL
Commands ................................................................................................................ 128
The SEEK Command ................................................................................................ 129
The SENSE DRIVE STATUS Command .................................................................. 129
The SENSE INTERRUPT Command ........................................................................ 130
The SET TRACK Command ...................................................................................... 131
The SPECIFY Command .......................................................................................... 131
The VERIFY Command ............................................................................................. 133
The VERSION Command .......................................................................................... 134
The WRITE DATA Command .................................................................................... 134
The WRITE DELETED DATA Command .................................................................. 135
EXAMPLE OF A FOUR-DRIVE CIRCUIT ............................................................................... 136
Parallel Port (Logical Device 4)
6.1
PARALLEL PORT CONFIGURATION .................................................................................... 137
6.1.1
Parallel Port Operation Modes .................................................................................. 137
6.1.2
Configuring Operation Modes .................................................................................... 137
6.1.3
Output Pin Protection ................................................................................................ 137
6.2
STANDARD PARALLEL PORT (SPP) MODES ...................................................................... 137
6.2.1
SPP Modes Register Set ........................................................................................... 138
6.2.2
SPP Data Register (DTR) .......................................................................................... 138
6.2.3
Status Register (STR) ............................................................................................... 139
6.2.4
SPP Control Register (CTR) ...................................................................................... 140
6.3
ENHANCED PARALLEL PORT (EPP) MODES ...................................................................... 141
6.3.1
EPP Register Set ....................................................................................................... 141
6.3.2
SPP or EPP Data Register (DTR) ............................................................................. 141
6.3.3
SPP or EPP Status Register (STR) ........................................................................... 141
6.3.4
SPP or EPP Control Register (CTR) ......................................................................... 142
6.3.5
EPP Address Register (ADDR) ................................................................................. 142
6.3.6
EPP Data Register 0 (DATA0) .................................................................................. 142
6.3.7
EPP Data Register 1 (DATA1) .................................................................................. 142
6.3.8
EPP Data Register 2 (DATA2) .................................................................................. 142
6.3.9
EPP Data Register 3 (DATA3) .................................................................................. 143
6.3.10 EPP Mode Transfer Operations ................................................................................ 143
6.3.11 EPP 1.7 and 1.9 Zero Wait State Data Write and Read Operations ......................... 144
6.4
EXTENDED CAPABILITIES PARALLEL PORT (ECP) ........................................................... 145
6.4.1
ECP Modes ............................................................................................................... 145
6.4.2
Software Operation .................................................................................................... 145
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Table of Contents
6.4.3
7.0
Hardware Operation .................................................................................................. 145
6.5
ECP MODE REGISTERS ........................................................................................................ 145
6.5.1
Accessing the ECP Registers .................................................................................... 146
6.5.2
Second Level Offsets ................................................................................................ 146
6.5.3
ECP Data Register (DATAR) ..................................................................................... 147
6.5.4
ECP Address FIFO (AFIFO) Register ....................................................................... 147
6.5.5
ECP Status Register (DSR) ....................................................................................... 147
6.5.6
ECP Control Register (DCR) ..................................................................................... 148
6.5.7
Parallel Port Data FIFO (CFIFO) Register ................................................................. 148
6.5.8
ECP Data FIFO (DFIFO) Register ............................................................................. 148
6.5.9
Test FIFO (TFIFO) Register ...................................................................................... 149
6.5.10 Configuration Register A (CNFGA) ........................................................................... 149
6.5.11 Configuration Register B (CNFGB) ........................................................................... 149
6.5.12 Extended Control Register (ECR) ............................................................................. 150
6.5.13 ECP Extended Index Register (EIR) ......................................................................... 151
6.5.14 ECP Extended Data Register (EDR) ......................................................................... 152
6.5.15 ECP Extended Auxiliary Status Register (EAR) ........................................................ 152
6.5.16 Control0 Register ....................................................................................................... 152
6.5.17 Control2 Register ....................................................................................................... 152
6.5.18 Control4 Register ....................................................................................................... 153
6.5.19 PP Confg0 Register ................................................................................................... 153
6.6
DETAILED ECP MODE DESCRIPTIONS ............................................................................... 154
6.6.1
Software Controlled Data Transfer
(Modes 000 and 001) ................................................................................................ 154
6.6.2
Automatic Data Transfer
(Modes 010 and 011) ................................................................................................ 154
6.6.3
Automatic Address and Data Transfers (Mode 100) ................................................. 156
6.6.4
FIFO Test Access (Mode 110) .................................................................................. 156
6.6.5
Configuration Registers Access
(Mode 111) ................................................................................................................ 156
6.6.6
Interrupt Generation .................................................................................................. 156
6.7
PARALLEL PORT REGISTER BITMAPS ............................................................................... 157
6.7.1
EPP Modes ................................................................................................................ 157
6.7.2
ECP Modes ............................................................................................................... 158
6.8
PARALLEL PORT PIN/SIGNAL LIST ...................................................................................... 160
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7.1
FEATURES .............................................................................................................................. 161
7.2
FUNCTIONAL MODES OVERVIEW ....................................................................................... 161
7.2.1
UART Modes: 16450 or 16550, and Extended .......................................................... 161
7.2.2
Sharp-IR, IrDA SIR Infrared Modes ........................................................................... 161
7.2.3
Consumer IR Mode ................................................................................................... 161
7.3
REGISTER BANK OVERVIEW ............................................................................................... 161
7.4
UART MODES – DETAILED DESCRIPTION .......................................................................... 162
7.4.1
16450 or 16550 UART Mode ..................................................................................... 162
7.4.2
Extended UART Mode ............................................................................................... 163
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10
Table of Contents
7.5
SHARP-IR MODE – DETAILED DESCRIPTION ..................................................................... 163
7.6
SIR MODE – DETAILED DESCRIPTION ................................................................................ 163
7.7
CONSUMER-IR MODE – DETAILED DESCRIPTION ............................................................ 164
7.7.1
Consumer-IR Transmission ....................................................................................... 164
7.7.2
Consumer-IR Reception ............................................................................................ 164
7.8
FIFO TIME-OUTS .................................................................................................................... 165
7.8.1
UART, SIR or Sharp-IR Mode Time-Out Conditions ................................................. 165
7.8.2
Consumer-IR Mode Time-Out Conditions ................................................................. 165
7.8.3
Transmission Deferral ............................................................................................... 165
7.9
AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE .......................................... 165
7.11
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS ................................................. 166
7.11.1 Receiver Data Port (RXD) or the Transmitter Data Port (TXD) ................................. 166
7.11.2 Interrupt Enable Register (IER) ................................................................................. 167
7.11.3 Event Identification Register (EIR) ............................................................................ 168
7.11.4 FIFO Control Register (FCR) ..................................................................................... 170
7.11.5 Link Control Register (LCR) and Bank Selection Register (BSR) ............................. 171
7.11.6 Bank Selection Register (BSR) ................................................................................. 172
7.11.7 Modem/Mode Control Register (MCR) ...................................................................... 172
7.11.8 Link Status Register (LSR) ........................................................................................ 174
7.11.9 Modem Status Register (MSR) .................................................................................. 175
7.11.10 Scratchpad Register (SPR) ....................................................................................... 175
7.11.11 Auxiliary Status and Control Register (ASCR) .......................................................... 176
7.12
BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS ......................................... 176
7.12.1 Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), .............................. 177
7.12.2 Link Control Register (LCR) and Bank Select Register (BSR) .................................. 177
7.13
BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................ 177
7.13.1 Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ........................... 178
7.13.2 Extended Control Register 1 (EXCR1) ...................................................................... 179
7.13.3 Link Control Register (LCR) and Bank Select Register (BSR) .................................. 180
7.13.4 Extended Control and Status Register 2 (EXCR2) .................................................... 180
7.13.5 Reserved Register ..................................................................................................... 180
7.13.6 TX_FIFO Current Level Register (TXFLV) ................................................................ 180
7.13.7 RX_FIFO Current Level Register (RXFLV) ............................................................... 181
7.14
BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS .......................................... 181
7.14.1 Module Revision ID Register (MRID) ........................................................................ 181
7.14.2 Shadow of Link Control Register (SH_LCR) ............................................................. 181
7.14.3 Shadow of FIFO Control Register (SH_FCR) ............................................................ 182
7.14.4 Link Control Register (LCR) and Bank Select Register (BSR) .................................. 182
7.15
BANK 4 – IR MODE SETUP REGISTER ................................................................................ 182
7.15.1 Reserved Registers ................................................................................................... 182
7.15.2 Infrared Control Register 1 (IRCR1) .......................................................................... 182
7.15.3 Link Control Register (LCR) and Bank Select Register (BSR) .................................. 182
7.15.4 Reserved Registers ................................................................................................... 182
7.16
BANK 5 – INFRARED CONTROL REGISTERS ..................................................................... 183
7.16.1 Reserved Registers ................................................................................................... 183
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Table of Contents
7.16.2
7.16.3
7.16.4
8.0
(LCR/BSR) Register .................................................................................................. 183
Infrared Control Register 2 (IRCR2) .......................................................................... 183
Reserved Registers ................................................................................................... 183
7.17
BANK 6 – INFRARED PHYSICAL LAYER CONFIGURATION REGISTERS ......................... 183
7.17.1 Infrared Control Register 3 (IRCR3) .......................................................................... 183
7.17.2 Reserved Register ..................................................................................................... 184
7.17.3 SIR Pulse Width Register (SIR_PW) ......................................................................... 184
7.17.4 Link Control Register (LCR) and Bank Select Register (BSR) .................................. 184
7.17.5 Reserved Registers ................................................................................................... 184
7.18
BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS 184
7.18.1 Infrared Receiver Demodulator Control Register (IRRXDC) ..................................... 184
7.18.2 Infrared Transmitter Modulator Control Register (IRTXMC) ...................................... 185
7.18.3 Consumer-IR Configuration Register (RCCFG), ....................................................... 187
7.18.4 Link Control/Bank Select Registers (LCR/BSR) ........................................................ 188
7.18.5 Infrared Interface Configuration Register 1 (IRCFG1) ............................................... 188
7.18.6 Reserved Register ..................................................................................................... 189
7.18.7 Infrared Interface Configuration 3 Register (IRCFG3) ............................................... 189
7.18.8 Infrared Interface Configuration Register 4 (IRCFG4) ............................................... 189
7.19
UART2 WITH IR REGISTER BITMAPS .................................................................................. 190
Enhanced Serial Port - UART1 (Logical Device 6)
8.1
REGISTER BANK OVERVIEW ............................................................................................... 195
8.2
DETAILED DESCRIPTION ...................................................................................................... 195
8.2.1
16450 or 16550 UART Mode ..................................................................................... 196
8.2.2
Extended UART Mode ............................................................................................... 196
8.3
FIFO TIME-OUTS .................................................................................................................... 196
8.4
AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE .......................................... 197
8.4.1
Transmission Deferral ............................................................................................... 197
8.5
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS ................................................. 197
8.5.1
Receiver Data Port (RXD) or the Transmitter Data Port (TXD) ................................. 197
8.5.2
Interrupt Enable Register (IER) ................................................................................. 198
8.5.3
Event Identification Register (EIR) ............................................................................ 199
8.5.4
FIFO Control Register (FCR) ..................................................................................... 200
8.5.5
Line Control Register (LCR) and Bank Selection Register (BSR) ............................. 201
8.5.6
Bank Selection Register (BSR) ................................................................................. 202
8.5.7
Modem/Mode Control Register (MCR) ...................................................................... 203
8.5.8
Line Status Register (LSR) ........................................................................................ 204
8.5.9
Modem Status Register (MSR) .................................................................................. 205
8.5.10 Scratchpad Register (SPR) ....................................................................................... 205
8.5.11 Auxiliary Status and Control Register (ASCR) .......................................................... 205
8.6
BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS ......................................... 206
8.6.1
Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), .............................. 206
8.6.2
Line Control Register (LCR) and Bank Select Register (BSR) .................................. 207
8.7
BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................ 207
8.7.1
Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ........................... 207
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Table of Contents
8.7.2
8.7.3
8.7.4
8.7.5
8.7.6
8.7.7
9.0
10.0
Extended Control Register 1 (EXCR1) ...................................................................... 208
Line Control Register (LCR) and Bank Select Register (BSR) .................................. 209
Extended Control and Status Register 2 (EXCR2) .................................................... 209
Reserved Register ..................................................................................................... 209
TX_FIFO Current Level Register (TXFLV) ................................................................ 209
RX_FIFO Current Level Register (RXFLV) ............................................................... 210
8.8
BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS .......................................... 210
8.8.1
Module Revision ID Register (MRID) ........................................................................ 210
8.8.2
Shadow of Line Control Register (SH_LCR) ............................................................. 210
8.8.3
Shadow of FIFO Control Register (SH_FCR) ............................................................ 211
8.8.4
Line Control Register (LCR) and Bank Select Register (BSR) .................................. 211
8.9
UART1 REGISTER BITMAPS ................................................................................................. 211
General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip
Select Output Signals
9.1
GPIO PORT ACTIVATION ...................................................................................................... 215
9.2
GPIO CONTROL REGISTERS ............................................................................................... 215
9.2.1
Special GPIO Signal Features ................................................................................... 215
9.2.2
Reading and Writing to GPIO Pins ............................................................................ 215
9.2.3
Multiplexed GPIO Signals .......................................................................................... 215
9.2.4
Multiplexed GPIO Signal Selection ............................................................................ 215
9.3
PROGRAMMABLE CHIP SELECT OUTPUT SIGNALS ......................................................... 216
Power Management (Logical Device 8)
10.1
POWER MANAGEMENT OPTIONS ....................................................................................... 218
10.1.1 Configuration Options ................................................................................................ 218
10.1.2 WATCHDOG Feature ................................................................................................ 218
10.2
POWER MANAGEMENT REGISTERS ................................................................................... 218
10.2.1 Power Management Index Register .......................................................................... 218
10.2.2 Power Management Data Register ........................................................................... 219
10.2.3 Function Enable Register 1 (FER1) ........................................................................... 219
10.2.4 Function Enable Register 2 (FER2) ........................................................................... 219
10.2.5 Power Management Control Register (PMC1) .......................................................... 220
10.2.6 Power Management Control 2 Register (PMC2) ....................................................... 221
10.2.7 Power Management Control 3 Register (PMC3) ....................................................... 221
10.2.8 WATCHDOG Time-Out Register (WDTO) ................................................................ 222
10.2.9 WATCHDOG Configuration Register (WDCF) .......................................................... 222
10.2.10 WATCHDOG Status Register (WDST) ...................................................................... 223
10.2.11 PM1 Event Base Address Register (Bits 7-0) ............................................................ 223
10.2.12 PM1 Event Base Address Register (Bits 15-8) .......................................................... 223
10.2.13 PM Timer Base Address (Bits 7-0) ............................................................................ 223
10.2.14 PM Timer Base Address Register (Bits 15-8) ............................................................ 224
10.2.15 PM1 Control Base Address Register (Bits 7-0) ......................................................... 224
10.2.16 PM1 Control Base Address Register (Bits 15-8) ....................................................... 224
10.2.17 General Purpose Status Base Address Register (Bits 7-0) ....................................... 224
10.2.18 General Purpose Status Base Address Register (Bits 15-8) ..................................... 224
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Table of Contents
10.2.19 ACPI Support Register .............................................................................................. 225
10.3
POWER MANAGEMENT REGISTER BITMAPS .................................................................... 226
11.0
X-Bus Data Buffer
12.0
The Internal Clock
13.0
14.0
12.1
THE CLOCK SOURCE ............................................................................................................ 230
12.2
THE INTERNAL ON-CHIP CLOCK MULTIPLIER ................................................................... 230
12.3
SPECIFICATIONS ................................................................................................................... 230
12.4
POWER-ON PROCEDURE WHEN CFG0 = 0 ........................................................................ 230
Interrupt and DMA Mapping
13.1
IRQ MAPPING ......................................................................................................................... 231
13.2
DMA MAPPING ....................................................................................................................... 231
Device Specifications
14.1
GENERAL DC ELECTRICAL CHARACTERISTICS ............................................................... 232
14.1.1 Recommended Operating Conditions ....................................................................... 232
14.1.2 Absolute Maximum Ratings ....................................................................................... 232
14.1.3 Capacitance ............................................................................................................... 232
14.1.4 Power Consumption Under Recommended Operating Conditions ........................... 233
14.2
DC CHARACTERISTICS OF PINS, BY GROUP .................................................................... 233
14.2.1 Group 1 ...................................................................................................................... 233
14.2.2 Group 2 ...................................................................................................................... 234
14.2.3 Group 3 ...................................................................................................................... 234
14.2.4 Group 4 ...................................................................................................................... 235
14.2.5 Group 5 ...................................................................................................................... 235
14.2.6 Group 6 ...................................................................................................................... 235
14.2.7 Group 7 ...................................................................................................................... 236
14.2.8 Group 8 ...................................................................................................................... 236
14.2.9 Group 9 ...................................................................................................................... 237
14.2.10 Group 10 .................................................................................................................... 237
14.2.11 Group 11 .................................................................................................................... 238
14.2.12 Group 12 .................................................................................................................... 238
14.2.13 Group 13 .................................................................................................................... 239
14.2.14 Group 14 .................................................................................................................... 239
14.2.15 Group 15 .................................................................................................................... 240
14.2.16 Group 16 .................................................................................................................... 240
14.2.17 Group 17 .................................................................................................................... 240
14.2.18 Group 18 .................................................................................................................... 240
14.2.19 Group 19 .................................................................................................................... 241
14.2.20 Group 20 .................................................................................................................... 241
14.2.21 Group 21 .................................................................................................................... 241
14.2.22 Group 22 .................................................................................................................... 241
14.2.23 Group 23 .................................................................................................................... 241
14.2.24 Group 24 .................................................................................................................... 242
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Table of Contents
14.2.25
14.2.26
14.2.27
14.2.28
14.3
Group 25
Group 26
Group 27
Group 28
.................................................................................................................... 242
.................................................................................................................... 243
.................................................................................................................... 243
.................................................................................................................... 243
AC ELECTRICAL CHARACTERISTICS .................................................................................. 244
14.3.1 AC Test Conditions TA = 0 °C to 70 °C, VDD = 5.0 V ±10% ...................................... 244
14.3.2 Clock Timing .............................................................................................................. 244
14.3.3 Microprocessor Interface Timing ............................................................................... 245
14.3.4 Baud Output Timing ................................................................................................... 247
14.3.5 Transmitter Timing ..................................................................................................... 248
14.3.6 Receiver Timing ......................................................................................................... 249
14.3.7 UART, Sharp-IR, SIR and Consumer Remote Control Timing .................................. 251
14.3.8 IRSLn Write Timing ................................................................................................... 252
14.3.9 Modem Control Timing .............................................................................................. 252
14.3.10 DMA Timing ............................................................................................................... 253
14.3.11 Reset Timing ............................................................................................................. 256
14.3.12 Write Data Timing ...................................................................................................... 257
14.3.13 Drive Control Timing .................................................................................................. 258
14.3.14 Read Data Timing ...................................................................................................... 258
14.3.15 Parallel Port Timing ................................................................................................... 259
14.3.16 Enhanced Parallel Port 1.7 Timing ............................................................................ 260
14.3.17 Enhanced Parallel Port 1.9 Timing ............................................................................ 261
14.3.18 Extended Capabilities Port (ECP) Timing .................................................................. 262
14.3.19 GPIO Write Timing .................................................................................................... 263
14.3.20 RTC Timing ............................................................................................................... 263
14.3.21 APC Timing ............................................................................................................... 264
14.3.22 Chip Select Timing .................................................................................................... 267
14.3.23 LED Timing ................................................................................................................ 267
Glossary ..................................................................................................................................................... 268
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CONNECTION DIAGRAM
VSS
AFD/DSTRB
SLIN/ASTRB
INIT
ERR
PE
SLCT
ACK
STB/WRITE
BUSY/WAIT
P21
P20
P17
P16/GPIO25
P12/CS0
MDAT
MCLK
KBDAT
KBCLK
VSS
VDD
DSKCHG
WP
INDEX
TRK0
RDATA
DENSEL
WGATE
HDSEL
STEP
DIR
1.1
Signal/Pin Connection and Description
120
VDD
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
VSS
CTS1
DCD1
DSR1
DTR1/BADDR0/BOUT1
RI1
RTS1/BADDR1
SIN1
SOUT1/CFG0
VSS
VDD
GPIO30/CTS2
GPIO31/DCD2
GPIO32/DSR2
DTR2/CFG1/BOUT2
GPIO33/RI2
GPIO34/RTS2
GPIO35/SIN2
GPIO36/SOUT2
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15/PME2
GPIO16/PME1
GPIO17/WDO
GPIO20/IRSL1/ID1
GPIO21/IRSL0/IRSL2/ID2
GPIO22/POR
GPIO23/RING
115
110
105
100
95
WDATA
DR1
DR0
MTR1
MTR0
DRATE0
MSEN1
MSEN0
IRTX
1.0
90
85
81
121
80
125
75
130
70
135
65
140
PC87317VUL
60
145
55
150
50
155
45
160
41
1
5
10
15
20
25
30
35
40
VDD
VSS
D0
D1
D2
D3
D4
D5
D6
D7
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
VDD
VSS
A12
A13
A14
A15
AEN
ZWS
IOCHRDY
RD
WR
TC
IRQ1
IRQ3
IRQ4
IRQ5
VSS
1.0 Signal/Pin Connection and Description
Signal/Pin Connection and Description
PlasticQuad Flatpack (PQFP), EIAJ
Order Number PC87317VUL/PC97317VUL
NS Package Number VUL160A
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16
GPIO24/IRRX1
GPIO37/IRRX2/IRSL0/ID0
IRSL1/ID1/XD7
IRSL2/SELCS/GPIO21/XD6
GPIO27/XD5
GPIO26/XD4
GPIO25/XD3
GPIO24/XD2
CS2/XD1
CS1/XD0/CSOUT-NSC-Test
XDRD/ID3
RING/XDCS
LED/CS0
ONCTL
SWITCH
VCCH
VBAT
X2C
X1C
VDD
VSS
DACK3
DACK2
DACK1
DACK0
DRQ3
DRQ2
DRQ1
DRQ0
MR
X1
IRQ15
IRQ14
IRQ12
IRQ11
IRQ10
IRQ9
IRQ8
IRQ7
IRQ6
Signal/Pin Connection and Description
SIGNAL/PIN DESCRIPTIONS
The Module column indicates the functional module that is
associated with these pins. In this column, the System label
indicates internal functions that are common to more than
one module. The I/O and Group # column describes whether the pin is an input, output, or bidirectional pin (marked as
Input, Output or I/O, respectively).
TABLE 1-1 "Signal/Pin Description Table" lists the signals
of the PC87317VUL in alphabetical order and shows the
pin(s) associated with each. TABLE 1-2 "Multiplexed X-Bus
Data Buffer (XDB) Pins" on page 25 lists the X-Bus Data
Buffer (XDB) signals that are multiplexed and TABLE 1-6
"Pins with a Strap Function During Reset" on page 26 lists
the pins that have strap functions during reset.
TABLE 1-1. Signal/Pin Description Table
Signal/Pin
Name
Pin
Number
A15-0
29-26,
23-12
ACK
Module
I/O and
Function
Group #
ISA-Bus
Input
ISA-Bus Address – A15-0 are used for address decoding on any
Group 1 access except DMA accesses, on condition that the AEN signal is
low.
See Section 2.2.2 on page 28.
113
Parallel Port
Input
Acknowledge – This input signal is pulsed low by the printer to
Group 3 indicate that it has received data from the parallel port. This pin is
internally connected to a weak pull-up.
AFD
119
Parallel Port
I/O
Automatic Feed – When this signal is low the printer should
Group 13 automatically feed a line after printing each line. This pin is in TRISTATE after a 0 is loaded into the corresponding control register bit.
An external 4.7 KΩ pull-up resistor should be attached to this pin.
For Input mode see bit 5 in Section 6.5.16 on page 152.
This signal is multiplexed with DSTRB. See TABLE 6-12 on page 160
for more information.
AEN
30
ISA-Bus
Input
DMA Address Enable – This input signal disables function selection
Group 1 via A15-0 when it is high. Access during DMA transfer is not affected
by this signal.
ASTRB
118
Parallel Port
Output Address Strobe (EPP) – This signal is used in EPP mode as an
Group 13 address strobe. It is active low.
This signal is multiplexed with SLIN.See TABLE 6-12 on page 160 for
more information.
BADDR1,0
136, 134
Configuration
Input
Base Address Strap Pins 0 and 1 – These pins determine the base
Group 5 addresses of the Index and Data registers, the value of the Plug and
Play ISA Serial Identifier and the configuration state immediately after
reset. These pins are pulled down by internal 30 KΩ resistors.
External 10 KΩ pull-up resistors to VDD should be employed.
BADDR1 is multiplexed with RTS1.
BADDR0 is multiplexed with DTR1 and BOUT1.
See TABLE 2-2 on page 28 and Section 2.1 on page 27.
BOUT2,1
148, 138
BUSY
111
UART1,
UART2
Output Baud Output – This multi-function pin provides the associated serial
Group 17 channel Baud Rate generator output signal if test mode is selected,
i.e., bit 7 of the EXCR1 register is set. See “Bit 7 - Baud Generator
Test (BTEST)” on page 180.
After Master Reset this pin provides the SOUT function.
BOUT2 is multiplexed with DTR2 and CFG1.
BOUT1 is multiplexed with DTR1 and BADDR0.
Parallel Port
Input
Busy – This pin is set to high by the printer when it cannot accept
Group 2 another character. It is internally connected to a weak pull-down
resistor.
This signal is multiplexed with WAIT. See TABLE 6-12 on page 160 for
more information.
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SIGNAL/PIN DESCRIPTIONS
1.2
SIGNAL/PIN DESCRIPTIONS
Signal/Pin Connection and Description
Signal/Pin
Name
CFG1-0
Pin
Number
Module
144, 138 Configuration
I/O and
Function
Group #
Input
Configuration Strap Pins 1-0 – These pins determine the default
Group 5 configuration upon power up. These pins are pulled down by internal
30 KΩ resistors. Use external 10 KΩ pull-up resistors to VDD.
CFG1 is multiplexed with DTR2 and BOUT2. CFG0 is multiplexed with
SOUT1. See Table 2-2 on page 28.
CS0
68
106
CS2,1
72, 71
General
Purpose
General
Purpose
Output Programmable Chip Select – CS0, CS1 and CS2 are programmable
Group 21 chip select and/or latch enable and/or output enable signals that have
many uses, for example, as game ports or for I/O port expansion.
Group 12
The decoded address and the assertion conditions are configured via
the chip configuration registers. See Section 2.3 on page 29.
I/O
Group 9 CS0 is multiplexed with LED on pin 68 and with P12 on pin 106. On
pin 68 is an open-drain output that is in TRI-STATE unless VDD is
applied.
CS1 is multiplexed with CSOUT-NSC-Test/XD0.
CS2 is multiplexed with XD1.
CSOUTNSC-Test
71
NSC-use
Output Chip Select Read Output, NSC-Test – National Semiconductor test
Group 21 output. This is an open-drain output signal.
This signal is multiplexed with CS1 and XD0.
CTS2,1
141, 131
UART1,
UART2
Input
UART1 and UART2 Clear to Send – When low, these signals indicate
Group 1 that the modem or other data transfer device is ready to exchange data.
CTS2 is multiplexed with GPIO30.
D7-0
10-3
ISA-Bus
I/O
ISA-Bus Data – Bidirectional data lines to the microprocessor. D0 is
Group 8 the LSB and D7 is the MSB. These signals have 24 mA (sink)
buffered outputs.
DACK3-0
59-56
ISA-Bus
Input
DMA Acknowledge 0,1,2 and 3 – These active low input signals
Group 1 acknowledge a request for DMA services and enable the IOWR and
IORD input signals during a DMA transfer. These DMA signals can be
mapped to the following logical devices: FDC, UART1, UART2 or
parallel port.
DCD2,1
142, 132
UART1,
UART2
Input
UART1 and UART2 Data Carrier Detected – When low, this signal
Group 1 indicates that the modem or other data transfer device has detected
the data carrier.
DCD2 is multiplexed with GPIO31
DENSEL
94
FDC
Output Density Select – Indicates that a high FDC density data rate (500
Group 16 Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is
selected.
DENSELs polarity is controlled by bit 5 of the SuperI/O FDC
Configuration register as described in Section 2.6.1 on page 40.
DIR
90
FDC
Output Direction – This output signal determines the direction of the Floppy
Group 16 Disk Drive (FDD) head movement (active = step in, inactive = step
out) during a seek operation. During reads or writes, DIR is inactive.
DR1,0
88, 87
FDC
Output Drive Select 0 and 1 – These active low output signals are the
Group 16 decoded drive select output signals. DR0 and DR1 are controlled by
Digital Output Register (DOR) bits 0 and 1. They are encoded with
information to control four FDDs when bit 7 of the SuperI/O FDC
Configuration register is 1, as described in Section 2.6.1.
See MTR0,1 for more information.
DRATE0
84
FDC
Output Data Rate 0 – This output signal reflects the value of bit 0 of the
Group 20 Configuration Control Register (CCR) or the Data Rate Select Register
(DSR), whichever was written to last. Output from the pin is totem-pole
buffered (6 mA sink, 6 mA source).
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18
Signal/Pin Connection and Description
Pin
Number
Module
DRQ3-0
55-52
DSKCHG
99
DSR2,1
143, 133
DSTRB
119
DTR2,1
144, 134
ERR
116
GPIO17-15
GPIO14
GPIO13,12
GPIO11
GPIO10
156-154
153
152,151
150
149
General
Purpose
GPIO27,26
GPIO25
GPIO24
GPIO23,22
GPIO21
GPIO20
76,75,
74 or 107,
73 or 80,
160-159,
158 or 77
157.
General
Purpose
I/O and
Function
Group #
ISA-Bus
Output DMA Request 0, 1, 2 and 3 – These active high output signals inform
Group 18 the DMA controller that a data transfer is needed. These DMA signals
can be mapped to the following logical devices: Floppy Disk Controller
(FDC), UART1, UART2 or parallel port.
FDC
Input
Disk Change – This input signal indicates whether or not the drive
Group 1 door has been opened. The state of this pin is available from the
Digital Input Register (DIR). This pin can also be configured as the
RGATE data separator diagnostic input signal via the MODE
command. See the MODE command in Section 5.7.7.
UART1,
UART2
Input
Data Set Ready – When low, this signal indicates that the data
Group 1 transfer device, e.g., modem, is ready to establish a communications
link.
DSR2 is multiplexed with GPIO32.
Parallel Port
Output Data Strobe – This signal is used in EPP mode as a data strobe. It
Group 13 is active low.
DSTRB is multiplexed with AFD. See TABLE 6-12 for more
information.
UART1,
UART2
Output Data Terminal Ready – When low, this output signal indicates to the
Group 17 modem or other data transfer device that the UART1 or UART2 is
ready to establish a communications link.
A Master Reset (MR) deactivates this signal high, and loopback
operation holds this signal inactive.
DTR2 is multiplexed with CFG1 and BOUT2.
DTR1 is multiplexed with BADDR0 and BOUT1.
Parallel Port
Input
Error – This input signal is set active low by the printer when it has
Group 3 detected an error. This pin is internally connected to a weak pull-up.
I/O
Group
Group
Group
Group
Group
10
25
10
24
10
I/O
Group
Group
Group
Group
Group
Group
10
25
10
10
10
10
General Purpose I/O Signals 17-10 – General purpose I/O signals of
I/O Port 1.
GPIO17 is multiplexed with WDO.
GPIO16 is multiplexed with PME1.
GPIO15 is multiplexed with PME2.
General Purpose I/O Signals 27-20 – General purpose I/O port 2
signals.
GPIO27-26 are multiplexed with XD5-4, respectively.
GPIO25 is multiplexed with XD3 on pin 74 and with P16 on pin107.
GPIO24 is multiplexed with XD2 on pin 73 and with IRRX1 on pin 80.
GPIO23 is multiplexed with RING.
GPIO22 is multiplexed with POR.
GPIO21 is multiplexed on pin 158 with IRSL2, IRSL0 and ID2 and on pin
77 with IRSL2, SELCS and XD6. See Bits 4,3 - GPIO21, IRSL2/ID2 or
IRSL0 Pin Select in Section 2.4.4.
GPIO20 is multiplexed with IRSL1 and ID1.
19
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SIGNAL/PIN DESCRIPTIONS
Signal/Pin
Name
SIGNAL/PIN DESCRIPTIONS
Signal/Pin Connection and Description
Signal/Pin
Name
Pin
Number
Module
General
Purpose
I/O and
Function
Group #
I/O
General Purpose I/O Signals 37-30 – General purpose I/O port 3
Group 10 signals.
GPIO37 is multiplexed with IRRX2, IRSL0 and ID0.
GPIO36 is multiplexed with SOUT2.
GPIO35 is multiplexed with SIN2.
GPIO34 is multiplexed with RTS2.
GPIO33 is multiplexed with RI2.
GPIO32 is multiplexed with DSR2.
GPIO31 is multiplexed with DCD2.
GPIO30 is multiplexed with CTS2.
GPIO37-30
79,
148-145,
143-141
HDSEL
92
ID3-0
70, 158,
78 or 157,
79
INDEX
97
FDC
INIT
117
Parallel Port
I/O
Initialize – When this signal is active low, it causes the printer to be
Group 13 initialized. This signal is in TRI-STATE after a 1 is loaded into the
corresponding control register bit.
For Input mode see bit 5 in Section 6.5.16.
An external 4.7 KΩ pull-up resistor should be employed.
IOCHRDY
32
ISA-Bus
Output I/O Channel Ready – This is the I/O channel ready open drain output
Group 22 signal. When IOCHRDY is driven low, the EPP extends the host cycle.
IRQ1
IRQ5-3
IRQ12-6
IRQ15,14
36
39-37
47-41
49,48
ISA-Bus
I/O
Interrupt Requests 1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14 and 15 – IRQ
polarity
and push-pull or open-drain output selection is software
Group 15
configurable by the logical device mapped to the IRQ line.
Keyboard Controller (KBC) or Mouse interrupts can be configured by
the Interrupt Request Type Select 0 register (index 71h) as either
edge or level.
FDC
Output Head Select – This output signal determines which side of the FDD
Group 16 is accessed. Active low selects side 1, inactive selects side 0.
UART2
Input
Identification – These ID signals identify the infrared transceiver for
Group 1 Plug and Play support. These pins are read after reset.
ID3 is multiplexed with XDRD.
ID2 is multiplexed with GPIO21, IRSL2 and IRSL0. ID1 is multiplexed
on pin 78 with IRS L1 and XD7 or pin 78, or on pin 157 with GPIO20
and IRSL1.
ID0 is multiplexed with GPIO37,IRRX2 and IRSL0.
See TABLE 1-2 for more information.
Input
Index – This input signal indicates the beginning of an FDD track.
Group 1
The internal SCI1signal may be routed to these pins.
IRRX2,1
79, 80
UART2
Input
Infrared Reception 1 and 2 – Infrared serial input data. IRRX1
Group 27 and/or IRRX2 may be routed to POR or ONCTL. The pins are
powered by VCCH.
IRRX1 is multiplexed with GPIO24.
IRRX2 is multiplexed with GPIO37,IRSL0 and ID0.
IRSL0
IRSL1
IRSL2
79 or 158
78 or 157
77 or 158
UART2
Output
Pins:
77, 78,79
Group 17
Pins:
157, 158
Group 10
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Infrared Control Signals 0, 1 and 2 – These signals control the
Infrared analog front end. The pins on which these signals are driven
is determined by the SuperI/O Configuration 2 register (index 22h).
See TABLE 1-2 for more information.
IRSL0 is multiplexed on pin 79 with GPIO37, IRRX2 and ID0, or on
pin 158 with GPIO21, IRSL2 and ID2.
IRSL1 is multiplexed on pin 78 with XD7 and ID1, or on pin 157 with
GPIO20 and ID1.
IRSL2 is multiplexed on pin 77 with XD6, SELCS and GPIO21, or on
pin 158 with GPIO21, IRSL0 and ID2.
20
Signal/Pin Connection and Description
Pin
Number
Module
I/O and
Function
Group #
IRTX
81
UART2
Output Infrared Transmit – Infrared serial output data.
Group 19
KBCLK
102
KBC
I/O
Keyboard Clock – This I/O pin transfers the keyboard clock between
Group 11 the SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to the internal TO signal of the KBC.
KBDAT
103
KBC
I/O
Keyboard Data – This I/O pin transfers the keyboard data between
Group 11 the SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to KBC’s P10.
LED
68
APC
OUTPUT LED Control - Drives an externally connected LED, according to the
Group 26 user selection (on, off or a 1 Hz blink). This open-drain output is
powered by VCCH, it is multiplexed with CSO and can sink 16 mA.
MCLK
104
KBC
I/O
Mouse Clock – This I/O pin transfers the mouse clock between the
Group 11 SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to KBC’s T1.
MDAT
105
KBC
I/O
Mouse Data – This I/O pin transfers the mouse data between the
Group 11 SuperI/O chip and the external keyboard using the PS/2 protocol.
When the KBC (logical device 0) is disabled, this signal can be placed
in TRI-STATE.
This pin is connected internally to KBC’s P11.
MR
51
ISA-Bus
Input
Master Reset – An active high MR input signal resets the controller
Group 1 to the idle state, and resets all disk interface output signals to their
inactive states. MR also clears the DOR, DSR and CCR registers,
and resets the MODE command, CONFIGURE command, and LOCK
command parameters to their default values. MR does not affect the
SPECIFY command parameters. MR sets the configuration registers
to their selected default values.
MSEN1,0
83, 82
FDC
Input
Media Sense – These input pins are used for media sensing when bit
Group 4 6 of the SuperI/O FDC Configuration register (at index F0h) is 1. See
TABLE 1-2 for more information.
Each pin has a 40 KΩ internal pull-up resistor.
MTR1,0
86, 85
FDC
Output Motor Select 1,0 – These motor enable lines for drives 0 and 1 are
Group 16 controlled by bits D7-4 of the Digital Output Register (DOR). They are
output signals that are active when they are low. They are encoded with
information to control four FDDs when bit 7 of the SuperI/O FDC
Configuration register is set See TABLE 1-2 for more information. See
DR1,0.
ONCTL
67
APC
Output On/Off Control for the RTC’s Advanced Power Control (APC) –
Group 23 This signal indicates to the main power supply to turn on power.
ONCTL is an open-drain output signal that is powered by VCCH.
P17,16
P12
108, 107
106
KBC
I/O
I/O Port – KBC quasi-bidirectional port for general purpose input and
Group 12 output.
P12 may be routed internally (via APC) to POR and/or SCI1.
P12 is multiplexed with CS0.
P16 is multiplexed with GPIO25.
P21,20
110, 109
KBC
I/O
I/O Port – KBC open-drain signals for general purpose input and
Group 12 output. These signals are controlled by KBC firmware.
21
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SIGNAL/PIN DESCRIPTIONS
Signal/Pin
Name
SIGNAL/PIN DESCRIPTIONS
Signal/Pin Connection and Description
Signal/Pin
Name
Pin
Number
Module
I/O and
Function
Group #
PD7-0
129-122
Parallel Port
I/O
Parallel Port Data – These bidirectional signals transfer data to and
Group 14 from the peripheral data bus and the appropriate parallel port data
register. These signals have a high current drive capability. See
Section 14.1 on page 232.
PE
115
Parallel Port
Paper End – This input signal is set high by the printer when it is out
Input
Group 2 of paper. This pin has an internal weak pull-up or pull-down resistor.
Group 3
PME2,1
154,155
APC
Input
Power Management Event 1 and 2 - These signals indicate that a
Group 28 power Management Event has occurred. They may be routed to POR,
SCI1 or ONCTL. Event characteristics (low/high, rise/fall) are software
configurable. The pins are powered by VCCH.
PME1 is multiplexed with GPIO16.
PME2 is multiplexed with GPIO15.
POR
159
APC
RD
33
ISA-Bus
RDATA
95
FDC
RI2,1
145, 135
UART1, APC
Input
Ring Indicators (Modem) – When low, this signal indicates that a
Group 7 telephone ring signal has been received by the modem.
When enabled, a high to low transition on RI1 or RI2 activates the
ONCTL pin. The RI1 and RI2 pins have schmitt-trigger input buffers.
RI2 is multiplexed with GPIO33.
RING
69 or 160
APC
Input
Ring Indicator (APC) – Detection of an active low RING pulse or
Group 7 pulse train activates the ONCTL signal. The APC’s APCR2 register
determines which pin the RING signal uses. The pins have a schmitttrigger input buffer.
RING is multiplexed on pin 69 with XDCS and on pin 160 with
GPIO23.
RTS2,1
146, 136
UART1,
UART2
Output Request to Send – When low, these output signals indicate to the
Group 17 modem or other data transfer device that the corresponding UART1
or UART2 is ready to exchange data.
A Master Reset (MR) sets RTS to inactive high. Loopback operation
holds it inactive.
RTS2 is multiplexed with GPIO34. RTS1 is multiplexed with BADDR1.
SELCS
77
Configuration
Input
Select CSOUT – During reset, this signal is sampled into bit 1 of the
Group 4 SuperI/O Configuration 1 register (index 21h).
A 40 KΩ internal pull-up resistor (or a 10 KΩ external pull-down
resistor for National Semiconductor testing) controls this pin during
reset. Do not pull this signal low during reset.
This signal is multiplexed with GPIO21, IRSL2 and XD6.
SIN2,1
147, 137
UART1,
UART2
Input
Serial Input – This input signal receives composite serial data from
Group 1 the communications link (peripheral device, modem or other data
transfer device.)
SIN2 is multiplexed with GPIO35.
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Output Power Off Request – This signal is activated by various events,
Group 21 including the APC Switch Off event (regardless of the fail-safe delay).
Selection of edge or level for POR is via the APCR1 register of the
APC. Selection of an output buffer is via GPIO22 output buffer control
bits (in the Port 2 Output Type and Port 2 Pull-up Control registers
described in TABLE 9-2). See Section 4.3.
This signal is multiplexed with GPIO22
Input
I/O Read – An active low RD input signal indicates that the
Group 1 microprocessor has read data.
Input
Read Data – This input signal holds raw serial data read from the
Group 1 Floppy Disk Drive (FDD).
22
Signal/Pin Connection and Description
Pin
Number
Module
I/O and
Function
Group #
SLCT
114
Parallel Port
Input
Select – This input signal is set active high by the printer when the
Group 2 printer is selected. This pin is internally connected to a nominal 25 KΩ
pull-down resistor.
SLIN
118
Parallel Port
I/O
Select Input – When this signal is active low it selects the printer.
Group 13 This signal is in TRI-STATE after a 0 is loaded into the corresponding
control register bit. Use an external 4.7 KΩ pull-up resistor.
For Input mode see bit 5, described in Section 6.5.16.
This signal is multiplexed with ASTRB.
SOUT2,1
148, 138
UART1,
UART2
Output Serial Output – This output signal sends composite serial data to the
Group 17 communications link (peripheral device, modem or other data transfer
device).
The SOUT2,1 signals are set active high after a Master Reset (MR).
SOUT2 is multiplexed with GPIO36.
SOUT1 is multiplexed with CFG0.
STB
112
Parallel Port
I/O
Data Strobe – This output signal indicates to the printer that valid
Group 13 data is available at the printer port.
This signal is in TRI-STATE after a 0 is loaded into the corresponding
control register bit.
An external 4.7 KΩ pull-up resistor should be employed.
For Input mode see bit 5, described in Section 6.5.16.
This signal is multiplexed with WRITE.
STEP
91
FDC
Output Step – This output signal issues pulses to the disk drive at a software
Group 16 programmable rate to move the head during a seek operation.
SWITCH
66
APC
Input
Switch On/Off – A physical momentary switch attached to this pin
Group 7 indicates a user request (to the APC) to switch the power on or off.
(See “The SWITCH Input Signal” on page 67).
The pin has an internal pull-up of 1 MΩ (nominal), a schmitt-trigger
input buffer and debounce protection of at least 16 msec.
TC
35
ISA-Bus
DMA Terminal Count – The DMA controller issues TC to indicate the
Input
Group 1 termination of a DMA transfer. TC is accepted only when a DACK
signal is active.
TC is active high in PC-AT mode, and active low in PS/2 mode.
TRK0
96
FDC
Input
Track 0 – This input signal indicates to the controller that the head of
Group 1 the selected floppy disk drive is at track 0.
VBAT
64
RTC and
APC
Input
Battery Power Supply – Power signal from the battery to the RealTime Clock (RTC) or for Advanced Power Control (APC) when VCCH
is less than VBAT (by at least 0.5V). VBAT includes a UL protection
resistor.
VCCH
65
RTC and
APC
Input
VCC Help Power Supply – This signal provides power to the RTC or
APC when VCCH is higher than VBAT (by at least 0.5V).
VDD
1, 24, 61,
100, 121,
140
Power
Supply
Input
Main 5 V Power Supply – This signal is the 5 V supply voltage for
the digital circuitry.
VSS
2, 11, 25,
40, 60,
101, 120,
130, 139
Power
Supply
Output
WAIT
111
Parallel Port
Ground – This signal provides the ground for the digital circuitry.
Input
Wait – In EPP mode, the parallel port device uses this signal to
Group 2 extend its access cycle. WAIT is active low. This signal is multiplexed
with BUSY. See TABLE 6-12 on page 160 for more information.
23
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SIGNAL/PIN DESCRIPTIONS
Signal/Pin
Name
SIGNAL/PIN DESCRIPTIONS
Signal/Pin Connection and Description
Signal/Pin
Name
Pin
Number
Module
FDC
I/O and
Function
Group #
WDATA
89
Output Write Data (FDC) – This output signal holds the write
Group 16 precompensated serial data that is written to the selected floppy disk
drive. Precompensation is software selectable.
WDO
156
WGATE
93
FDC
Output Write Gate (FDC) – This output signal enables the write circuitry of
Group 16 the selected disk drive. WGATE is designed to prevent glitches during
power up and power down. This prevents writing to the disk when
power is cycled.
WP
98
FDC
Input
Write Protected – This input signal indicates that the disk in the
Group 1 selected drive is write protected.
WR
34
ISA-Bus
Input
I/O Write – WR is an active low input signal that indicates a write
Group 1 operation from the microprocessor to the controller.
WRITE
112
Parallel Port
Output Write Strobe – In EPP mode, this active low signal is a write strobe.
Group 23 This signal is multiplexed with STB. See TABLE 6-12 for more
information.
X1
50
Clock
Input
Clock In – A TTL or CMOS compatible 14.31818MHz, 24 MHz or 48
Group 6 MHz clock. When this pin is fed by the 14.31818MHz clock, the chip
must be configured to work with the on-chip clock multiplier.See
Chapter 12 on page 230.
X1C
62
RTC
Input
X2C
63
RTC
Output
XD7,6,
XD1,0
78, 77
72, 71
X-Bus
XD5-2
76-73
X-Bus
XDCS
69
X-Bus
Input
X-Bus Data Buffer (XDB) Chip Select – This signal enables and
Group 7 disables the bidirectional XD7-0 data buffer signals.
This signal is multiplexed with RING.
XDRD
70
X-Bus
Input
X-Bus Data Buffer (XDB) Read Command – This signal controls the
Group 1 direction of the bidirectional XD7-0 data buffer signals.
This signal is multiplexed with ID3.
ZWS
31
ISA-Bus
Output Zero Wait State – When this open-drain output signal is activated
Group 22 (driven low), it indicates that the access time can be shortened, i.e.,
zero wait states.
ZWS is never activated (driven low) on access to SuperI/O chip
configuration registers (including during the Isolation state) or on
access to the parallel port in SPP or EPP 1.9 mode.
ZWS is always activated (driven low) on access to the parallel port in
ECP mode.
Power ManOutput WATCHDOG Out – This output pin becomes low when a
agement
Group 10 WATCHDOG time-out occurs. See Section 10.1.2 on page 218.This
pin is configured by bit 6 of the SuperI/O Configuration Register 2.
This signal is multiplexed with GPIO17.
Crystal 1 Slow – Input signal to the internal Real-Time Clock (RTC)
crystal oscillator amplifier. Clock source is set by CFG0 during reset.
Crystal 2 Slow – Output signal from the internal Real-Time Clock
(RTC) crystal oscillator amplifier.
I/O
X-Bus Data – These bidirectional signals hold the data in the X Data
Group 9 Buffer (XDB).
XD7 is multiplexed with IRSL1 and ID1.
I/O
XD6 is multiplexed with IRSL2, SELCS and GPIO21.
Group 10
XD5-2 are multiplexed with GPIO27-24, respectively.
XD1 is multiplexed with CS2.
XD0 is multiplexed with CS1/CSOUT-NSC-Test
See TABLE 1-2 on page 25.
1. SCI is an internal signal used to send ACPI-relevant notifications to the host operating system.
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24
Signal/Pin Connection and Description
Pin
X-Bus Data Buffer (XDB)1
Bit 4 of SuperI/O Configuration
Register 1 = 1
I/O
Alternate Functiona
Bit 4 of SuperI/O Configuration 1
Register = 0
I/O
69
XDCS
Input
RING
Input
70
XDRD
Input
ID3
71
XD0
I/O
CS1/CSOUT-NSC-Test
Output
72
XD1
I/O
CS2
Output
73
XD2
I/O
GPIO24
I/O
73
XD3
I/O
GPIO25
I/O
75
XD4
I/O
GPIO26
I/O
76
XD5
I/O
GPIO27
I/O
77
XD6/SELCS
I/O
GPIO21/IRSL2/SELCS
I/O
78
XD7
I/O
IRSL1/ID1
Output
1. Unselected (XDB or alternate function) input signals are internally blocked high.
TABLE 1-3. UART2/GPIO Port 3 Pin Designation
UART2
General Purpose I/O port 3
Pin
Bit 3 of SuperI/O Configuration
Register 1 = 1
I/O
Bit 3 of SuperI/O Configuration
Register 1 = 0
I/O
141
CTS2
Input
GPIO30
I/O
142
DCD2
Input
GPIO31
I/O
143
DSR2
Input
GPIO32
I/O
146
RTS2
Output
GPIO34
I/O
147
SIN2
Input
GPIO35
I/O
148
SOUT2
Output
GPIO36
I/O
TABLE 1-4. APC/Power Management or GPIO/Chip Select Pin Designation
Pin
APC, Power Management
I/O
General Purpose I/O, Chip Select
I/O
154
PME2
Input
GPIO15
I/O
155
PME1
Input
GPIO16
I/O
156
WDO
Output
GPIO17
I/O
159
POR
Output
GPIO22
I/O
160
RING
Input
GPIO23
I/O
68
LED
Output
CS0
Output
25
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SIGNAL/PIN DESCRIPTIONS
TABLE 1-2. Multiplexed X-Bus Data Buffer (XDB) Pins
SIGNAL/PIN DESCRIPTIONS
Signal/Pin Connection and Description
TABLE 1-5. Infrared/KBC or GPIO/Chip-Select Pin Designation
Pin
Infrared, KBC, UART2
I/O
General Purpose I/O, Chip Select
I/O
157
IRSL1/ID1
I/O
GPIO20
I/O
158
IRSL2/IRSL0/ID2
I/O
GPIO21
I/O
80
IRRX1
Input
GPIO24
I/O
107
P16
I/O
GPIO25
I/O
145
RI2
Input
GPIO33
I/O
79
IRRX2/IRSL0/ID0
I/O
GPIO37
I/O
106
P12
I/O
CS0
Output
TABLE 1-6. Pins with a Strap Function During Reset
Strap Function
Pin No.
Symbols
BADDR1,0
134
DTR1/BADDR0/BOUT1
136
RTS1/BADDR1
138
SOUT1/CFG0
144
DTR2/CFG1
77
GPIO21/IRSL2/XD6/SELCS
CFG1,0
SELCS
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26
2.0
Configuration
The BIOS configures the PC87317VUL. Index and Data
register addresses are different from the addresses of
the Plug and Play (PnP) Index and Data registers. Configuration registers can be accessed as if the serial isolation procedure had already been done, and the
PC87317VUL is selected.
The BIOS may switch the addresses of the Index and
Data registers to the PnP ISA addresses of the Index
and Data registers, by using software to modify the base
address bits, as shown in Section 2.4.4 "SuperI/O Configuration 2 Register (SIOC2)" on page 38.
The PC87317VUL is partially configured by hardware, during reset. The configuration can also be changed by software, by changing the values of the configuration registers.
The configuration registers are accessed using an Index
register and a Data register. During reset, hardware strapping options define the addresses of the configuration registers. See Section 2.1.2 "The Index and Data Register
Pair".
After the Index and Data register pair have determined the
addresses of the configuration registers, the addresses of
the Index and Data registers can be changed within the ISA
I/O address space, and a 16-bit programmable register controls references to their addresses and to the addresses of
the other registers.
2.1.2
During reset, a hardware strapping option on the BADDR0
and BADDR1 pins defines an address for the Index and
Data Register pair. This prevents contention between the
registers for I/O address space.
This chapter describes the hardware and software configuration processes. For each, it describes configuration of the
Index and Data register pair first. See Sections 2.1 "HARDWARE CONFIGURATION" and 2.2 "SOFTWARE CONFIGURATION" on page 28.
TABLE 2-1 "Base Addresses" shows the base addresses
for the Index and Data registers that hardware sets for each
combination of values of the Base Address strap pins
(BADDR0 and BADDR1). You can access and change the
content of the configuration registers at any time, as long as
the base addresses of the Index and Data registers are defined.
Section 2.3 "THE CONFIGURATION REGISTERS" on
page 29 presents an overview of the configuration registers
of the PC87317VUL and describes each in detail.
2.1
When BADDR1 is low (0), the Plug and Play (PnP) protocol
defines the addresses of the Index and Data register, and
the system wakes up from reset in the Wait for Key state.
HARDWARE CONFIGURATION
The PC87317VUL supports two Plug and Play (PnP) configuration modes that determine the status of register addresses upon wake up from a hardware reset, Full Plug and
Play ISA mode and Plug and Play Motherboard mode.
2.1.1
When BADDR1 is high (1), the addresses of the Index and
Data register are according to TABLE 2-1 "Base Addresses", and the system wakes up from reset in the Config state.
This configures the PC87317VUL with default values, automatically, without software intervention. After reset, use
software as described in Section 2.2 "SOFTWARE CONFIGURATION" on page 28 to modify the selected base address of the Index and Data register pair, and the defaults
for configuration registers.
Wake Up Options
During reset, strapping options on the BADDR0 and
BADDR1 pins determine one of the following modes.
●
●
The Index and Data Register Pair
Full Plug and Play ISA mode – System wakes up in
Wait for Key state.
Index and Data register addresses are as defined by Microsoft and Intel in the “Plug and Play ISA Specification,
Version 1.0a, May 5, 1994.”
The Plug and Play soft reset has no effect on the logical devices, except for the effect of the Activate registers (index
30h) in each logical device.
The PC87317VUL can wake up with the FDC, the KBC and
the RTC either active (enabled) or inactive (disabled). The
other logical devices and the internal on-chip clock multiplier wake up inactive (disabled).
Plug and Play Motherboard mode – system wakes up
in Config state.
TABLE 2-1. Base Addresses
Address
BADDR1
BADDR0
Configuration Type
Index Register
Data Register
0
x
0279h
Write Only
Write: 0A79h
Read: RD_DATA Port
Full PnP ISA Mode
Wake up in Wait for Key state
1
0
015Ch Read/Write
015Dh Read/Write
PnP Motherboard Mode
Wake up in Config state
1
1
002Eh Read/Write
002Fh Read/Write
PnP Motherboard Mode
Wake up in Config state
27
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2.0 Configuration
Configuration
SOFTWARE CONFIGURATION
Configuration
2.1.3
The Strap Pins
TABLE 2-2. The Strap Pins
Pin
Reset Configuration
Affected
CFG0
0: FDC, KBC and RTC wake up inactive, clock source is 32.768 KHz
with on-chip clock multiplier disabled.
1: FDC, KBC and RTC wake up active, clock source is 48 MHz fed
via X1 pin.
Bit 0 of Activate registers (index
30h) of logical devices 0, 2 and 3
and bit 0 of PMC2 register of Power
Management (logical device 8).
CFG11
0: No X-Bus Data Buffer. (See XDB pins multiplexing in TABLE 1-2.) Bit 4 of SuperI/O Configuration 1
(SIOC1) register (index 21h).
1: X-Bus Data Buffer (XDB) enabled.
BADDR1,0 00:
01:
10:
11:
SELCSa
Full PnP ISA, Wake in Wait For Key state. Index PnP ISA.
Full PnP ISA, Wake in Wait For Key state. Index PnP ISA.
PnP Motherboard, Wake in Config state. Index 015Ch.
PnP Motherboard, Wake in Config state. Index 002Eh.
0: CSOUT-NSC-test on pin 71.
1: CS1 or XD0 on pin 71 (according to CFG1).
Bits 1 and 0 of SuperI/O
Configuration 2 (SIOC2) register
(index 22h)
Bit 1 of SuperI/O Configuration 1
(SIOC1) register (index 21h).
1. SELCS = 0 and CFG1 = 1 is an illegal strap option.
2.2
2.2.1
SOFTWARE CONFIGURATION
2.2.2
In full Plug and Play mode, the addresses of the Index and
Data registers that access the configuration registers are
decoded using pins A11-0, according to the ISA Plug and
Play specification.
Accessing the Configuration Registers
Only two system I/O addresses are required to access any
of the configuration registers. The Index and Data register
pair is used to access registers for all read and write operations.
In Plug and Play Motherboard mode, the addresses of the
Index and Data registers that access the configuration registers are decoded using pins A15-1. Pin A0 distinguishes
between these two registers.
In a write operation, the target configuration register is identified, based on a value that is loaded into the Index register.
Then, the data to be written into the configuration register is
transferred via the Data register.
KBC and mouse register addresses are decoded using pins
A1,0 and A15-3. Pin A2 distinguishes between the device
registers.
Similarly, for a read operation, first the source configuration
register is identified, based on a value that is loaded into the
Index register. Then, the data to be read is transferred via
the Data register.
RTC/APC and Power Management (PM) register addresses are decoded using pins A15-1.
FDC, UART, and GPIO register addresses are decoded using pins A15-3.
Reading the Index register returns the last value loaded into
the Index register. Reading the Data register returns the
data in the configuration register pointed to by the Index
register.
Parallel Port (PP) modes determine which pins are used for
register addresses. In SPP mode, 14 pins are used to decode Parallel Port (PP) base addresses. In ECP and EPP
modes, 13 address pins are used. TABLE 2-3 "Address
Pins Used for Parallel Port" shows which address pins are
used in each mode.
If, during reset, the Base Address 1 (BADDR1) signal is low
(0), the Index and Data registers are not accessible immediately after reset. As a result, all configuration registers of
the PC87317VUL are also not accessible at this time. To
access these registers, you must apply the Plug and Play
(PnP) ISA protocol.
TABLE 2-3. Address Pins Used for Parallel Port
If during reset, the Base Address 1 (BADDR1) signal is high
(1), all configuration registers are accessible immediately
after reset.
It is up to the configuration software to guarantee no conflicts between the registers of the active (enabled) logical
devices, between IRQ signals and between DMA channels.
If conflicts of this type occur, the results are unpredictable.
To maintain compatibility with other SuperI/O‘s, the value of
reserved bits may not be altered. Use read-modify-write.
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Address Decoding
28
PP Mode
Pins Used to
Decode Base
Address
Pins Used to
Distinguish Registers
SPP
A15-2
A1,0
ECP
A9-2 and A15-11
A1,0 and A10
EPP
A15-3
A2-0
Configuration
Parallel Port Mode
SuperI/O Parallel Port
Configuration Register Bits
Decoded Range 1
7
6
5
4
SPP
0
0
x
x
Three registers, from base to base + 02h
EPP (Non ECP Mode 4)
0
1
x
x
Eight registers, from base to base + 07h
ECP, No Mode 4,
No Internal Configuration
1
0
0
0
Six registers, from base to base + 02h and
from base + 400h to base + 402h
ECP with Mode 4,
No Internal Configuration
1
1
1
0
11 registers, from base to base + 07h and
from base + 400h to base + 402h
1
0
0
1
1
1
ECP with Mode 4,
Configuration within Parallel Port
16 registers, from base to base + 07h and
from base + 400h to base + 407h
or
1
1
1. The SuperI/O processor does not decode the Parallel Port outside this range.
2.3
THE CONFIGURATION REGISTERS
The configuration registers control the setup of the
PC87317VUL. Their major functions are to:
●
Identify the chip
●
Enable major functions (such as, the Keyboard Controller (KBC) for the keyboard and the mouse, the RealTime Clock (RTC), including Advanced Power Control
(APC), the Floppy Disc Controller (FDC), UARTs, parallel and general purpose ports, power management and
pin functionality)
●
Define the I/O addresses of these functions
●
Define the status of these functions upon reset
Section 2.3.2 "Configuration Register Summary" on page
33 summarizes information for each register of each function. In addition, the following non-standard, or card control,
registers are described in detail, in Section 2.4 "CARD
CONTROL REGISTERS" on page 37.
●
The Card Control Registers
— SID Register
— SRID Register (only in the PC97317).
— SuperI/O Configuration 1 Register (SIOC1)
— SuperI/O Configuration 2 Register (SIOC2)
— Programmable Chip Select Configuration Index
Register
— Programmable Chip Select Configuration Data Register
29
●
KBC Configuration Register (Logical Device 0)
— SuperI/O KBC Configuration Register
●
FDC Configuration Registers (Logical Device 3)
— SuperI/O FDC Configuration Register
— Drive ID Register
●
Parallel Port Configuration Register (Logical Device 4)
— SuperI/O Parallel Port Configuration Register
●
UART2 and Infrared Configuration Register (Logical
Device 5)
— SuperI/O UART2 Configuration Register
●
UART1 Configuration Register (Logical Device 6)
— SuperI/O UART1 Configuration Register
●
Programmable Chip Select Configuration Registers
— CS0 Base Address MSB Register
— CS0 Base Address LSB Register
— CS0 Configuration Register
— CS1 Base Address MSB Register
— CS1 Base Address LSB Register
— CS1 Configuration Register
— CS2 Base Address MSB Register
— CS2 Base Address LSB Register
— CS2 Configuration Register
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THE CONFIGURATION REGISTERS
TABLE 2-4. Parallel Port Address Range Allocation
THE CONFIGURATION REGISTERS
Configuration
2.3.1
registers, refer the “Plug and Play ISA Specification, Version 1.0a, May 5, 1994”.
Standard Plug and Play (PnP) Register Definitions
TABLES 2-5 through 2-10 describe the standard Plug and
Play registers. For more detailed information on these
TABLE 2-5. Plug and Play (PnP) Standard Control Registers
Index
00h
Name
Definition
Set RD_DATA Port Writing to this location modifies the address of the port used for reading from the
Plug and Play ISA cards. Data bits 7-0 are loaded into I/O read port address bits
9-2.
Reads from this register are ignored. Bits1 and 0 are fixed at the value 11.
01h
Serial Isolation
Reading this register causes a Plug and Play card in the Isolation state to compare
one bit of the ID of the board. This register is read only.
02h
Config Control
This register is write-only. The values are not sticky, that is, hardware automatically
clears the bits and there is no need for software to do so.
Bit 0 - Reset
Writing this bit resets all logical devices and restores the contents of
configuration registers to their power-up (default) values.
In addition, all the logical devices of the card enter their default state and the
CSN is preserved.
Bit 1 - Return to the Wait for Key state.
Writing this bit puts all cards in the Wait for Key state, with all CSNs preserved
and logical devices not affected.
Bit 2 - Reset CSN to 0.
Writing this bit causes every card to reset its CSN to zero.
03h
Wake[CSN]
A write to this port causes all cards that have a CSN that matches the write data
in bits 7-0 to go from the Sleep state to either the Isolation state, if the write data
for this command is zero, or the Config state, if the write data is not zero. It also
resets the pointer to the byte-serial device.
This register is write-only.
04h
Resource Data
This address holds the next byte of resource information. The Status register must
be polled until bit 0 of this register is set to 1 before this register can be read.
This register is read-only.
005
Status
06h
Card Select
Number (CSN)
Writing to this port assigns a CSN to a card. The CSN is a value uniquely assigned
to each ISA card after the serial identification process so that each card may be
individually selected during a Wake[CSN] command.
This register is read/write.
07h
Logical Device
Number
This register selects the current logical device. All reads and writes of memory, I/O,
interrupt and DMA configuration information access the registers of the logical
device written here. In addition, the I/O Range Check and Activate commands
operate only on the selected logical device.
This register is read/write. If a card has only 1 logical device, this location should
be a read-only value of 00h.
20h - 2Fh
Card Level,
Vendor Defined
Vendor defined registers.
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When bit 0 of this register is set to 1, the next data byte is available for reading
from the Resource Data register.
This register is read-only.
30
Configuration
Index
Name
Definition
0030h
Activate
For each logical device there is one Activate register that controls whether or not the
logical device is active on the ISA bus.
This is a read/write register.
Before a logical device is activated, I/O Range Check must be disabled.
Bit 0 - Logical Device Activation Control
0: Do not activate the logical device.
1: Activate the logical device.
Bits 7-1 - Reserved
These bits are reserved and must return 0 on reads.
0031h
I/O Range Check
This register is used to perform a conflict check on the I/O port range programmed
for use by a logical device.
This register is read/write.
Bit 0 - I/O Range Check control
0: The logical device drives 00AAh.
1: The logical device responds to I/O reads of the logical device's assigned I/O
range with a 0055h when I/O Range Check is enabled.
Bit 1 - Enable I/O Range Check
0: I/O Range Check is disabled.
1: I/O Range Check is enabled. (I/O Range Check is valid only when the logical
device is inactive).
Bits 7-2 - Reserved
These bits are reserved and must return 0 on reads.
TABLE 2-7. Plug and Play (PnP) I/O Space Configuration Registers
Index
Name
Definition
60h
Read/write value indicating the selected I/O lower limit address bits 15-8 for I/O
I/O Port Base
Address Bits (15-8) descriptor 0.
Descriptor 0
61h
I/O Port Base
Address Bits (7-0)
Descriptor 0
62h
Read/write value indicating the selected I/O lower limit address bits 15-8 for I/O
I/O Port Base
Address Bits (15-8) descriptor 1.
Descriptor 1
63h
I/O Port Base
Address Bits (7-0)
Descriptor 1
Read/write value indicating the selected I/O lower limit address bits 7-0 for I/O
descriptor 0.
Read/write value indicating the selected I/O lower limit address bits 7-0 for I/O
descriptor 1.
31
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THE CONFIGURATION REGISTERS
TABLE 2-6. Plug and Play (PnP) Logical Device Control Registers
THE CONFIGURATION REGISTERS
Configuration
TABLE 2-8. Plug and Play (PnP) Interrupt Configuration Registers
Index
Name
Definition
70h
Interrupt Request Read/write value indicating selected interrupt level.
Level Select 0 Bits3-0 select the interrupt level used for interrupt 0. A value of 1 selects IRQL 1, a value
of 15 selects IRQL 15. IRQL 0 is not a valid interrupt selection and (represents no
interrupt selection.
71h
Interrupt Request Read/write value that indicates the type and level of the interrupt request level selected in
Type Select 0 the previous register.
If a card supports only one type of interrupt, this register may be read-only.
Bit 0 - Type of the interrupt request selected in the previous register.
0: Edge
1: Level
Bit1 - Level of the interrupt request selected in the previous register. (See also Section
13.1 on page 231).
0: Low polarity. (Implies open-drain output with strong pull-up for a short time, followed
by weak pull-up).
1: High polarity. (Implies push-pull output).
TABLE 2-9. Plug and Play (PnP) DMA Configuration Registers
Index
Name
Definition
74h
DMA Channel
Select 0
Read/write value indicating selected DMA channel for DMA 0.
Bits 2-0 select the DMA channel for DMA 0. A value of 0 selects DMA channel 0; a
value of 7 selects DMA channel 7.
Selecting DMA channel 4, the cascade channel, indicates that no DMA channel is
active.
75h
DMA Channel
Select 1
Read/write value indicating selected DMA channel for DMA 1
Bits 2-0 select the DMA channel for DMA 1. A value of 0 selects DMA channel 0; a
value of 7 selects DMA channel 7.
Selecting DMA channel 4, the cascade channel, indicates that no DMA channel is
active.
TABLE 2-10. Plug and Play (PnP) Logical Device Configuration Registers
Index
F0h-FEh
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Name
Definition
Vendor defined.
Logical Device
Configuration Vendor
Defined
32
Configuration
Configuration Register Summary
The tables in this section specify the Index, type
(read/write), reset values and configuration register or action that controls each register associated with each function.
Soft Reset is related to a Reset executed by utilizing the Reset Bit (Bit 0) of the Config Control Register. (See TABLE
2-5 "Plug and Play (PnP) Standard Control Registers" on
page 30.
When the reset value is not fixed, the table indicates what
controls the value or points to another section that provides
this information.
TABLE 2-11. Card Control Registers
Index Type
Hard Reset
00h
Soft Reset
Configuration Register or Action
00h
W
PnP ISA Set RD_DATA Port.
01h
R
02h
W
PnP ISA
03h
W
00h
04h
R
Resource Data.
05h
R
Status.
06h
R/W
00h
PnP ISA Card Select Number (CSN).
07h
R/W
00h
PnP ISA Logical Device Number.
20h
R
D0h
Serial Isolation.
PnP ISA Configuration Control.
PnP ISA Wake[CSN].
D0h
SID Register.
21h
R/W See Section 2.4.3 on page 37. No Effect SuperI/O Configuration 1 Register (SIOC1).
22h
R/W See Section 2.4.4 on page 38. No Effect SuperI/O Configuration 2 Register (SIOC2).
23h
R/W See Section 2.4.5 on page 38. No Effect Programmable Chip Select Configuration Index Register.
24h
R/W See Section 2.4.6 on page 39. No Effect Programmable Chip Select Configuration Data Register.
27h
R
xx
xx
SRID Register (in PC97317 only).
TABLE 2-12. KBC Configuration Registers for Keyboard - Logical Device 0
Index
R/W
Hard Reset
Soft Reset
Configuration Register or Action
30h
R/W
00h or 01h
See CFG0 in Section.
31h
R/W
00h
00h
I/O Range Check.
60h
R/W
00h
00h
Base Address MSB Register.
61h
R/W
60h
60h
Base Address LSB Register.
Bit 2 (for A2) is read only, 0.
62h
R/W
00h
00h
Command Base Address MSB Register.
63h
R/W
64h
64h
Command Base Address LSB.
Bit 2 (for A2) is read only,1.
70h
R/W
01h
01h
KBC Interrupt (KBC IRQ1 pin) Select.
71h
RW
02h
02h
KBC Interrupt Type.
Bits 1,0 are read/write; others are read only.
74h
R
04h
04h
Report no DMA assignment.
75h
R
04h
04h
Report no DMA assignment.
F0h
R/W
See Section 2.5.1 on page 40.
No Effect
Activate.
00h or 01h
See CFG0 in Section See also FER1 of power management device
(logical device 8).
2.1.3.
33
SuperI/O KBC Configuration Register.
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THE CONFIGURATION REGISTERS
2.3.2
THE CONFIGURATION REGISTERS
Configuration
TABLE 2-13. KBC Configuration Registers for Mouse - Logical Device 1
Index
R/W
Hard Reset
Soft Reset
Configuration Register or Action
30h
R/W
00h
00h
Activate.
When mouse of the KBC mouse is inactive, the IRQ selected by the Mouse
Interrupt Select register (index 70h) is not asserted.
This register has no effect on host KBC commands handling the PS/2 mouse.
70h
R/W
0Ch
0Ch
Mouse Interrupt (KBC IRQ12 pin) Select.
71h
R/W
02h
02h
Mouse Interrupt Type.
Bits 1,0 are read/write; other bits are read only.
74h
R
04h
04h
Report no DMA assignment.
75h
R
04h
04h
Report no DMA assignment.
TABLE 2-14. RTC and APC Configuration Registers - Logical Device 2
Index
R/W
Hard Reset
Soft Reset
Configuration Register or Action
30h
R/W
00h or 01h
See CFG0 in
Section 2.1.3.
00h or 01h
See CFG0 in
Section 2.1.3.
31h
R/W
00h
00h
I/O Range Check.
60h
R/W
00h
00h
Base Address MSB Register.
61h
R/W
70h
70h
Base Address LSB Register.
Bit 0 (for A0) is read only, 0.
70h
R/W
08h
08h
Interrupt Select.
71h
R/W
00h
00h
Interrupt Type.
Bit 1 is read/write, other bits are read only.
74h
R
04h
04h
Report no DMA assignment.
75h
R
04h
04h
Report no DMA assignment.
Activate.
The APC of the RTC is not affected by bit 0.
See also FER1 of logical device 8.
TABLE 2-15. FDC Configuration Registers - Logical Device 3
Index
R/W
Hard Reset
Soft Reset
30h
R/W
00h or 01h
See CFG0 in Section 2.1.3.
00h or 01h
See CFG0 in
Section 2.1.3.
31h
R/W
00h
00h
I/O Range Check.
60h
R/W
03h
03h
Base Address MSB Register.
61h
R/W
F2h
F2h
Base Address LSB Register.
Bits 2 and 0 (for A2 and A0) are read only, 0,0.
70h
R/W
06h
06h
Interrupt Select.
71h
R/W
03h
03h
Interrupt Type.
Bit 1 is read/write; other bits are read only.
74h
R/W
02h
02h
DMA Channel Select.
75h
R
04h
04h
Report no DMA assignment.
F0h
R/W
See Section 2.6.1 on page 40.
No Effect
SuperI/O FDC Configuration Register.
F1h
R/W
See Section 2.6.2 on page 41.
No Effect
Drive ID Register.
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34
Configuration Register or Action
Activate.
See also FER1 of logical device 8.
Configuration
Index
R/W
Hard Reset
Soft Reset
Configuration Register or Action
30h
R/W
00h
00h
Activate.
See also FER1 of the power management device (logical
device 8).
31h
R/W
00h
00h
I/O Range Check.
60h
R/W
02h
02h
Base Address MSB register.
Bits 7-2 (for A15-10) are read only, 000000b.
61h
R/W
78h
78h
Base Address LSB register.
Bits 1,0 (for A1,0) are read only, 00b.
See Section 2.2.2.
70h
R/W
07h
07h
Interrupt Select.
71h
R/W
00h
00h
Interrupt Type.
Bit 0 is read only. It reflects the interrupt type dictated by
the Parallel Port operation mode and configured by the
SuperI/O Parallel Port Configuration register. This bit is
set to 1 (level interrupt) in Extended Mode and cleared
(edge interrupt) in all other modes.
Bit 1 is a read/write bit.
Bits 7-2 are read only.
74h
R/W
04h
04h
DMA Channel Select.
75h
R
04h
04h
Report no DMA assignment.
F0h
R/W
See Section 2.7 on page 41
No Effect SuperI/O Parallel Port Configuration register.
TABLE 2-17. UART2 and Infrared Configuration Registers - Logical Device 5
Index
R/W
Hard Reset
Soft Reset
Configuration Register or Action
30h
R/W
00h
00
Activate.
See also FER1 of the power management device
(logical device 8).
31h
R/W
00h
00h
I/O Range Check.
60h
R/W
02h
02h
Base Address MSB register.
61h
R/W
F8h
F8h
Base Address LSB register.
Bit 2-0 (for A2-0) are read only, 000b.
70h
R/W
03h
03h
Interrupt Select.
71h
R/W
03h
03h
Interrupt Type.
Bit 1 is R/W; other bits are read only.
74h
R/W
04h
04h
DMA Channel Select 0 (RX_DMA).
75h
R/W
04h
04h
DMA Channel Select 1 (TX_DMA).
F0h
R/W
See Section 2.8 on page 42
No Effect
35
SuperI/O UART2 Configuration register.
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THE CONFIGURATION REGISTERS
TABLE 2-16. Parallel Port Configuration Registers - Logical Device 4
THE CONFIGURATION REGISTERS
Configuration
TABLE 2-18. UART1 Configuration Registers - Logical Device 6
Index R/W
Hard Reset
Soft Reset
Configuration Register or Action
30h
R/W
00h
00h
Activate.
See also FER1 of the power management device
(logical device 8).
31h
R/W
00h
00h
I/O Range Check.
60h
R/W
03h
03h
Base Address MSB Register.
61h
R/W
F8h
F8h
Base Address LSB Register.
Bits 2-0 (for A2-0) are read only as 000b.
70h
R/W
04h
04h
Interrupt Select.
71h
R/W
03h
03h
Interrupt Type.
Bit 1 is read/write. Other bits are read only.
74h
R
04h
04h
Report no DMA Assignment.
75h
R
04h
04h
Report no DMA Assignment.
F0h
R/W
See Section 2.9.1 on page 42
No Effect
SuperI/O UART 1 Configuration register.
TABLE 2-19. GPIO Ports Configuration Registers - Logical Device 7
Index
R/W
Hard Reset
Soft Reset
Configuration Register or Action
30h
R/W
00h
00h
Activate.
See also FER2 of the power management device (logical device 8).
31h
R/W
00h
00h
I/O Range Check.
60h
R/W
00h
00h
Base Address MSB Register.
61h
R/W
00h
00h
Base Address LSB Register.
Bit 2-0 (for A2-0) are read only: 000.
74h
R
04h
04h
Report no DMA assignment.
75h
R
04h
04h
Report no DMA assignment.
TABLE 2-20. Power Management Configuration Registers - Logical Device 8
Index
R/W
Hard Reset
Soft Reset
30h
R/W
00
00
Activate.
When bit 0 is cleared, the registers of this logical device are not
accessible. The registers are maintained.
31h
R/W
00h
00h
I/O Range Check.
60h
R/W
00h
00h
Base Address Most Significant Byte.
61h
R/W
00h
00h
Base Address LSB Register.
Bit 0 (for A0) is read only: 0.
74h
R
04h
04h
Report no DMA assignment.
75h
R
04h
04h
Report no DMA assignment.
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Configuration Register or Action
36
Configuration
CARD CONTROL REGISTERS
This section describes the registers at first level indexes in
the range 20h - 2Fh.
7
0
The next section describes the chip select configuration
registers, which are accessed using two index levels. The
first index level accesses the Programmable Chip Select Index register at 23h. The second index level accesses a specific chip select configuration register. See TABLE 2-24
"The Programmable Chip Select Configuration Registers"
on page 43.
2.4.1
6
0
SuperI/O Configuration 1
5 4 3 2 1 0
Register (SIOC1),
0 x 0 1 x 0 Reset
Index 21h
Required
ZWS Enable
CSOUT-NSC-test or CS1/XD0
PC-AT or PS/2 Drive Mode Select
UART2 or GPIO30-36 Select
X-Bus Data Buffer (XDB) Select
Lock Scratch Bit
PC87317 SID Register
This read-only register holds the revision and chip identity
number of the chip. The PC87317VUL is identified by the
value D0h in this register.
General Purpose Scratch Bits
FIGURE 2-3. SIOC1 Register Bitmap
7
1
6
1
PC87317 SID Register
5 4 3 2 1 0
Index 20h
0 1 0 0 0 0 Reset
1
1
0
1
0
0
0
Bit 0 - ZWS Enable
This bit controls assertion of ZWS on any host SuperI/O
chip access, except for configuration registers access
(including Serial Isolation register) and except for Parallel Port access.
For ZWS assertion on host-EPP access, see Section
6.5.17 "Control2 Register" on page 152.
0: ZWS is not asserted.
1: ZWS is asserted.
0 Required
Revision ID
Chip ID
Bit 1 - CSOUT-NSC-test or CS1/XD0 on Pin 71 Select
This bit is initialized with SELCS strap value (see TABLE 2-2 "The Strap Pins" on page 28).
0: CSOUT-NSC-test on pin.
1: CS1 or XD0 on pin (according to bit 4 of SuperI/O
Configuration 1 Register (SIOC1)).
FIGURE 2-1. PC87317 SID Register Bitmap
2.4.2
PC97317 SID Register
This read-only register holds the identity number of the chip.
The PC97317VUL is identified by the value DFh in this register.
7
1
6
1
PC97317 SID Register
5 4 3 2 1 0
Index 20h
0 1 1 1 1 1 Reset
1
1
0
1
1
1
1
Undefined results, when bit 1 of the SuperI/O Configuration
1 register is cleared to zero and bit 4 of the SuperI/O Configuration 1 register is set to one. (see TABLE 2-21).
TABLE 2-21. Signal Assignment for Pin 71
SIOC1 Bits
1 Required
Chip ID
1
0
0
CSOUT-NSC-test
0
1
CS1
1
0
Undefined
1
1
XD0
Bit 2 - PC-AT or PS/2 Drive Mode Select
0: PS/2 drive mode.
1: PC-AT drive mode. (Default)
FIGURE 2-2. PC97317 SID Register Bitmap
2.4.3
Pin 71
4
SuperI/O Configuration 1 Register (SIOC1)
This register can be read or written. It is reset by hardware
to 04h, 06h, 14h or 16h. See SELCS and the CFG1 strap
pin in TABLE 2-2 "The Strap Pins" on page 28.
Bit 3 - UART2 or GPIO30-36 Select
0: GPIO30-32 and GPIO34-36 pins are selected
1: UART2 pins are selected
Upon reset, this bit is initialized to 0.
37
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CARD CONTROL REGISTERS
2.4
CARD CONTROL REGISTERS
Configuration
TABLE 2-22. Signal Assignment for Pins 158 and 77
Bit 4 - X-Bus Data Buffer (XDB) Select
Select X-bus buffer on the XDB pins. This read only bit
is initialized with the CFG1 strap value. See TABLE 2-21
and see also Chapter 11 "X-Bus Data Buffer" on page
229.
0: No XDB buffer. XDB pins have alternate function,
see TABLE 1-2 "Multiplexed X-Bus Data Buffer
(XDB) Pins" on page 25.
1: XDB enabled.
Bits
SuperI/O Configuration 2 Register (SIOC2)
6
0
GPIO21
IRSL2/SELCS
01
IRSL2/ID2
GPIO21/SELCS
10
IRSL0
IRSL2/SELCS
11
Reserved
IRSL2/SELCS
Bit 6 - GPIO17 or WDO Pin Select
This bit determines whether GPIO17 or WDO is routed
to pin 156 when bit 7 of the Port 1 Direction register at
offset 01h of logical device 7 is set to 1. See Section 9.1
"GPIO PORT ACTIVATION" on page 215.
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0: GPIO17 uses the pin. (Default)
1: WDO uses the pin.
This read/write register is reset by hardware to 00h-03h.
See BADDR1,0 strap pins in Section 2.1.3 "The Strap Pins"
on page 28.
7
0
00
Bit 5 - GPIO20, IRSL1 or ID1 Pin Select
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0: The pin is GPIO20.
1: The pin is IRSL1/ID1.
Bits 7,6 - General Purpose Scratch Bits
When bit 5 is set to 1, these bits are read only. After reset they can be read or written. Once changed to readonly, they can be changed back to be read/write bits
only by a hardware reset.
2.4.4
(When Bit 4 of SuperI/O
Config 1 Register = 0)
43
Bit 5 - Lock Scratch Bit
This bit controls bits 7 and 6 of this register. Once this
bit is set to 1 by software, it can be cleared to 0 only by
a hardware reset.
0: Bits 7 and 6 of this register are read/write bits.
1: Bits 7 and 6 of this register are read only bits.
Pin 77
Pin 158
SuperI/O Configuration 2
5 4 3 2 1 0
Register (SIOC2),
0 0 0 0 x x Reset
Index 22h
Bit 7 - GPIO Bank Select
This bit selects the active register bank of GPIO registers.
0: Bank 0 is selected. (Default)
1: Bank 1 is selected.
Required
BADDR1 and BADDR0
GPIO22 or POR Select
2.4.5
Programmable Chip Select Configuration Index
Register
This read/write register is reset by hardware to 00h. It indicates the index of one of the Programmable Chip Select
(CS0, CS1 or CS2) configuration registers described in
Section 2.10 "PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS" on page 42.
The data in the indicated register is in the Programmable
Chip Select Configuration Data register at index 24h.
Bits 7 through 4 are read only and return 0000 when read.
GPIO21, IRSL2/ ID2 or ISL0 Pin Select
GPIO20 or IRSL1 Pin Select
GPIO17 or WDO Pin Select
GPIO Bank Select
FIGURE 2-4. SIOC2 Register Bitmap
Bits 1,0 - BADDR1 and BADDR0
Initialized on reset by BADDR1 and BADDR0 strap pins
(BADDR0 on bit 0). These bits select the addresses of
the configuration Index and Data registers and the Plug
and Play ISA Serial Identifier. See TABLE 2-1 "Base
Addresses" on page 27 and TABLE 2-2 "The Strap
Pins" on page 28.
7
0
6
0
0
0
Programmable Chip Select
5 4 3 2 1 0
Configuration Index
Register,
0 0 0 0 0 0 Reset
Index 23h
0 0
Required
Bit 2 - GPIO22 or POR Pin Select
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers.
0: The pin is GPIO22.
1: The pin is POR.
Index of a Programmable
Chip Select Configuration
Register
Read Only
Bits 4,3 - GPIO21, IRSL2/ID2 or IRSL0 Pin Select
The output buffer of this pin is selected by Port 2 Output
Type and Port 2 Pull-up Control registers as shown in
TABLE 2-22 "Signal Assignment for Pins 158 and 77".
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FIGURE 2-5. Programmable Chip Select Configuration
Index Register Bitmap
38
Configuration
Bit 3 - SCI Polarity Select
0: SCI interrupt is active low.
1: SCI interrupt is active high.
Programmable Chip Select Configuration Data
Register
This read/write register contains the data in the Programmable Chip Select Configuration register (see Section 2.10
"PROGRAMMABLE CHIP SELECT CONFIGURATION
REGISTERS" on page 42) indicated by the Programmable
Chip Select Configuration Index register at index 23h.
7
0
6
0
Bits 7-4 - SCI Plug-and-Play Select
SCI can be routed to one of the following ISA interrupts:
IRQ1, IRQ3-IRQ12, IRQ14-IRQ15.
For details on the SCI signal, refer to Chapter 4 on page 53.
Programmable Chip Select
5 4 3 2 1 0
Configuration Data
Register,
0 0 0 0 0 0 Reset
Index 24h
Required
TABLE 2-23. SCI Routing
Bits
7654
Interrupt
0000
Disable
0001
IRQ1
0010
Invalid
0011
IRQ3
0100
IRQ4
FIGURE 2-6. Programmable Chip Select Configuration
Data Register Bitmap
0101
IRQ5
0110
IRQ6
2.4.7
0111
IRQ7
1000
IRQ8
1001
IRQ9
1010
IRQ10
1011
IRQ11
1100
IRQ12
1101
Invalid
1110
IRQ14
1111
IRQ15
Data in a Programmable
Chip Select Configuration
Register
SuperI/O Configuration 3 Register (SIOC3)
This read/write register enables output-pin designation and
interrupt routing. It is reset by hardware to 00h.
7
0
6
0
SuperI/O Configuration 3
5 4 3 2 1 0
Register (SIOC3),
0 0 0 0 0 0 Reset
Index 25h
Required
P16 or GPIO25 Select
P12 or CS0 Select
Reserved
SCI Polarity Select
Upon reset, these bits are initialized to 0000.
Disable means the SCI is not routed to any ISA interrupt.
Unpredictable results when invalid values are written.
SCI Plug-and-Play Select
FIGURE 2-7. SIOC3 Register Bitmap
2.4.8
PC97317 SRID Register
This read-only register holds the revision number of the
PC97317 chip. SRID is incremented on each tapeout.
Bit 0 - P16 or GPIO25 Pin Select
0: P16 is routed to I/O pin.
1: GPIO25 is routed to I/O pin. The KBC firmware
may write to P16 and read it back as if the pin exist
and left open. Upon reset, this bit is initialized to 0.
7
x
6
x
5 4 3 2 1 0 PC97317 SRID Register
Index 27h
x x x x x x Reset
Required
Bit 1 - P12 or CS0 Pin Select
0: P12 is routed to I/O pin.
1: CS0 is routed to I/O pin. The KBC firmware may
write to P12 and read it back as if the pin exist and
left open. Upon reset, this bit is initialized to 0.
Chip Revision ID
Bit 2 - Reserved
Reserved.
FIGURE 2-8. PC97317 SRID Register Bitmap
39
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CARD CONTROL REGISTERS
2.4.6
KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0)
Configuration
2.4.9
2.6
SuperI/O Configuration F Register (SIOCF),
Index 2Fh
FDC CONFIGURATION REGISTERS (LOGICAL
DEVICE 3)
This register is reserved. Must be written with ‘0’s.
2.6.1
2.5
This read/write register is reset by hardware to 20h.
KBC CONFIGURATION REGISTER (LOGICAL
DEVICE 0)
2.5.1
7
0
SuperI/O KBC Configuration Register
This read/write register is reset by hardware to 40h.
7
0
6
1
5 4 3 2 1 0
0 0 0 0 0 0 Reset
Required
SuperI/O FDC Configuration Register
6
0
Super I/O FDC
Configuration
Register,
Required
Index F0h
5 4 3 2 1 0
1 0 0 0 0 0 Reset
SuperI/O KBC
Configuration
Register,
Index F0h
TRI-STATE Control
Reserved
TRI-STATE Control
DENSEL Polarity Control
TDR Register Mode
Four Drive Control
Reserved
FIGURE 2-10. SuperI/O FDC Configuration Register
Bitmap
KBC Clock Source
Bit 0 - TRI-STATE Control
When set, this bit causes the FDC pins to be in TRISTATE (except the IRQ and DMA pins) when the FDC is
inactive (disabled).
This bit is ORed with a bit of PMC1 register of logical device 8.
0: FDC pins are not put in TRI-STATE.
1: FDC pins are put in TRI-STATE.
FIGURE 2-9. SuperI/O KBC Configuration Register
Bitmap
Bit 0 - TRI-STATE Control
When set, this bit causes the Keyboard and Mouse pins
to be in TRI-STATE (KBCLK, KBDAT, MCLK, and MDAT
pins), when the KBC is inactive (disabled).
This bit is ORed with a bit of PMC1 register of logical device 8.
0: Keyboard and Mouse pins are not put in TRI-STATE
1: Keyboard and Mouse pins are put in TRI-STATE,
when the KBC is inactive.
Bits 4-1 - Reserved
Reserved.
Bit 5 - DENSEL Polarity Control
0: DENSEL is active low for 500 Kbps or 1 Mbps data
rates.
1: DENSEL is active high for 500 Kbps or 1 Mbps
data rates. (Default)
Bits 5-1 - Reserved
Reserved.
Bits 7,6 - KBC Clock Source
Bit 6 is the LSB. The clock source can be changed only
when the KBC is inactive (disabled).
00: 8 MHz
01: 12 MHz
10: 16 MHz. Undefined results when these bits are 10
and the clock source for the chip is 24 MHz on X1.
11: Reserved.
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Bit 6 - TDR Register Mode
0: PC-AT Compatible drive mode (bits 7 through 2 of
TDR are not driven).
1: Enhanced drive mode (bits 7 through 2 of TDR are
driven on TDR read).
Bit 7 - Four Drive Encode
0: Two floppy drives are directly controlled by DR1-0,
MTR1-0.
1: Four floppy drives are controlled with the aid of an
external decoder.
40
Configuration
Bit 0 - TRI-STATE Control
When set, this bit causes the parallel port pins to be in
TRI-STATE (except IRQ and DMA pins) when the parallel port is inactive (disabled). This bit is ORed with a bit
of the PMC1 register of logical device 8.
Drive ID Register
This read/write register is reset by hardware to 00h. These
bits control bits 5 and 4 of the enhanced TDR register.
7
0
6
0
5 4 3 2 1 0
Drive ID Register,
Index F1h
0 0 0 0 0 0 Reset
Bit 1 - Clock Enable
0: Parallel port clock disabled.
ECP modes and EPP time-out are not functional
when the logical device is active. Registers are
maintained.
1: Parallel port clock enabled.
All operation modes are functional when the logical
device is active. This bit is ANDed with a bit of the
PMC3 register of the power management device
(logical device 8).
Required
Drive 0 ID
Drive 1 ID
Reserved
Bit 2 - Reserved
FIGURE 2-11. Drive ID Register Bitmap
Bit 3 - Reported Parallel Port of PnP ISA Resource Data
Report to the ISA PnP Resource Data the device identification.
0: ECP device.
1: SPP device.
Bits 1,0 - Drive 0 ID
These bits are reflected on bits 5 and 4, respectively, of
the Tape Drive Register (TDR) of the FDC when drive 0
is accessed. See Section 5.3.4 "Tape Drive Register
(TDR)" on page 99.
Bit 4 - Configuration Bits within the Parallel Port
0: The registers at base (address) + 403h, base +
404h and base + 405h are not accessible (reads
and writes are ignored).
1: When ECP is selected by bits 7 through 5, the registers at base (address) + 403h, base + 404h and
base + 405h are accessible.
This option supports run-time configuration within
the Parallel Port address space. An 8-byte (and
1024-byte) aligned base address is required to access these registers. See Chapter 6 "Parallel Port
(Logical Device 4)" on page 137 for details.
Bits 3,2 - Drive 1 ID
These bits are reflected on bits 5 and 4, respectively, of
the TDR register of the FDC when drive 1 is accessed.
See Section 5.3.4 "Tape Drive Register (TDR)" on page
99.
Bits 7-4 - Reserved
2.7
PARALLEL PORT CONFIGURATION REGISTER
(LOGICAL DEVICE 4)
2.7.1
SuperI/O Parallel Port Configuration Register
This read/write register is reset by hardware to F2h. For normal operation and to maintain compatibility with future
chips, do not change bits 7 through 4.
7
1
6
1
Bit 7-5 - Parallel Port Mode Select
Bit 5 is the LSB.
Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled
by bit 4 of the Control2 configuration register of the parallel port at offset 02h. See Section 6.5.17 "Control2
Register" on page 152.
000: SPP Compatible mode. PD7-0 are always output
signals.
001: SPP Extended mode. PD7-0 direction controlled
by software.
010:EPP 1.7 mode.
011:EPP 1.9mode.
100:ECP mode (IEEE1284 register set), with no support for EPP mode.
101:Reserved.
110:Reserved.
111:ECP mode (IEEE1284 register set), with EPP
mode selectable as mode 4.
SuperI/O Parallel Port
5 4 3 2 1 0 Configuration Register,
Index F0h
1 1 0 0 1 0 Reset
Required
TRI-STATE Control
Clock Enable
Reserved
PP of PnP ISA Resource Data
Configuration Bits within the Parallel Port
Parallel Port Mode Select
FIGURE 2-12. SuperI/O Parallel Port Configuration
Register Bitmap
41
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PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 4)
2.6.2
UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5)
Configuration
2.8
Bits 6-4 - Reserved
UART2 AND INFRARED CONFIGURATION
REGISTER (LOGICAL DEVICE 5)
2.8.1
Bit 7 - Bank Select Enable
Enables bank switching. If this bit is cleared, all attempts
to access the extended registers are ignored.
SuperI/O UART2 Configuration Register
This read/write register is reset by hardware to 02h.
7
0
6
0
2.9
SuperI/O UART2
5 4 3 2 1 0 Configuration Register,
Index F0h
0 0 0 0 1 0 Reset
UART1 CONFIGURATION REGISTER
(LOGICAL DEVICE 6)
2.9.1
SuperI/O UART1 Configuration Register
This read/write register is reset by hardware to 02h. Its bits function like the bits in the SuperI/O UART2 Configuration register
Required
TRI-STATE Control for
UART2 Signals
Power Mode Control
Busy Indicator
Ring Detection on RI Pin
7
0
6
0
SuperI/O UART1
5 4 3 2 1 0 Configuration Register,
Index F0h
0 0 0 0 1 0 Reset
Required
Reserved
TRI-STATE Control for
UART1 Pins
Power Mode Control
Busy Indicator
Ring Detection on RI Pin
Bank Select Enable
FIGURE 2-13. SuperI/O UART2 Configuration Register
Bitmap
Bit 0 - TRI-STATE Control for UART signals
This bit controls the TRI-STATE status of UART signals
(except IRQ and DMA signals) when the UART is inactive (disabled). This bit is ORed with a bit of the PMC1
register of the power management device (logical device 8).
0: Signals not in TRI-STATE.
1: Signals in TRI-STATE.
Reserved
Bank Select Enable
FIGURE 2-14. SuperI/O UART1 Configuration Register
Bitmap
2.10 PROGRAMMABLE CHIP SELECT
CONFIGURATION REGISTERS
The chip select configuration registers are accessed using
two index levels. The first index level accesses the Programmable Chip Select Index register at 23h. See Section 2.4.5
"Programmable Chip Select Configuration Index Register"
on page 38. The second index level accesses a specific chip
select configuration register as shown in TABLE 2-24 "The
Programmable Chip Select Configuration Registers".
Bit 1 - Power Mode Control
0: Low power mode.
UART Clock disabled. UART output signals are set
to their default state. The RI input signal can be
programmed to generate an interrupt. Registers
are maintained.
1: Normal power mode.
UART clock enabled. The UART is functional when
the logical device is active. This bit is ANDed with a
bit of the PMC3 register of the power management
device (logical device 8)
See also Section 9.3 "PROGRAMMABLE CHIP SELECT
OUTPUT SIGNALS" on page 216 and the description of
each signal in TABLE 1-1 "Signal/Pin Description Table" on
page 17.
Bit 2 - Busy Indicator
This read-only bit can be used by power management
software to decide when to power down the logical device. This bit is also accessed via the PMC3 register of
the power management device (logical device 8).
0: No transfer in progress.
1: Transfer in progress.
Bit 3 - Ring Detection on RI Pin
0: The UART RI input signal uses the RI pin.
1: The UART RI input signal is the RING detection
signal on the RING pin. RING pin is selected by the
APCR2 register of the Advanced Power Control
(APC) module.
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42
Configuration
Second
Level
Index
Register Name
Bit 0 - Mask Address Pin A0
0: A0 is decoded.
1: A0 is not decoded; it is ignored.
Type Reset
00h
CS0 Base Address MSB Register R/W
00h
01h
CS0 Base Address LSB Register R/W
00h
02h
CS0 Configuration Register
R/W
00h
03h
Reserved
-
-
04h
CS1 Base Address MSB Register R/W
00h
05h
CS1 Base Address LSB Register R/W
00h
06h
CS1 Configuration Register
R/W
00h
07h
Reserved
-
-
08h
CS2 Base Address MSB Register R/W
00h
09h
CS2 Base Address LSB Register R/W
00h
0Ah
CS2 Configuration Register
R/W
00h
0Bh-0Fh
Reserved
-
-
10h-FFh
Not Accessible
-
-
Bit 1 - Mask Address Pin A1
0: A1 is decoded.
1: A1 is not decoded (ignored).
Bit 2 - Mask Address Pin A2
0: A2 is decoded.
1: A2 is not decoded; it is ignored.
Bit 3 - Mask Address Pin A3
0: A3 is decoded.
1: A3 is not decoded; it is ignored.
Bit 4 Assert Chip Select Signal on Write
0: Chip select not asserted on address match and
when WR is active (low).
1: Chip select asserted on address match and when
WR is active (low).
Bit 5 - Assert Chip Select Signal on Read
0: Chip select not asserted on address match and
when RD is active (low).
1: Chip select asserted on address match and when
RD is active (low).
Bit 6 - Unaffected by RD/WR
Bits 5 and 4 are ignored when this bit is set.
0: Chip select asserted on address match, qualified
by RD or WR pin state and contents of bits 5 and 4.
1: Chip select asserted on address match, regardless
of RD or WR pin state and regardless of contents
of bits 5 and 4.
2.10.1 CS0 Base Address MSB Register
This read/write register is reset by hardware to 00h. Same
as Plug and Play ISA base address register at index 60h.
See TABLE 2-7 "Plug and Play (PnP) I/O Space Configuration Registers" on page 31.
2.10.2 CS0 Base Address LSB Register
This read/write register is reset by hardware to 00h. It is the
same as the Plug and Play ISA base address register at index 61h. See TABLE 2-7 "Plug and Play (PnP) I/O Space
Configuration Registers" on page 31.
Bit 7 - Mask Address Pins A11-A0
0: A11 are decoded.
1: A11 are not decoded; they are ignored.
2.10.3 CS0 Configuration Register
2.10.4 Reserved
This read/write register is reset by hardware to 00h. It controls activation of the CS0 signal upon an address match,
when AEN is inactive (low) and the non-masked address
pins match the corresponding base address bits.
7
0
6
0
Attempts to access this register produce undefined results.
2.10.5 CS1 Base Address MSB Register
This read/write register is reset by hardware to 00h. Same
as Plug and Play ISA base address register at index 60h.
See TABLE 2-7 "Plug and Play (PnP) I/O Space Configuration Registers" on page 31.
5 4 3 2 1 0
CS0 Configuration
Register,
0 0 0 0 0 0 Reset
Second Level
Required
Index 02h
2.10.6 CS1 Base Address LSB Register
This read/write register is reset by hardware to 00h. Same
as Plug and Play ISA base address register at index 61h.
See TABLE 2-7 "Plug and Play (PnP) I/O Space Configuration Registers" on page 31.
Mask Address Pin A0
Mask Address Pin A1
Mask Address Pin A2
Mask Address Pin A3
Assert Chip Select Signal on Write
Assert Chip Select Signal on Read
Unaffected by RD/WR
Mask Address Pins A11
2.10.7 CS1 Configuration Register
This read/write register is reset by hardware to 00h. It functions like the CS0 Configuration Register described in Section 2.10.3 "CS0 Configuration Register" on page 43.
FIGURE 2-15. SuperI/O CS0 Configuration Register
Bitmap
43
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PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS
TABLE 2-24. The Programmable Chip Select
Configuration Registers
CONFIGURATION REGISTER BITMAPS
Configuration
2.11 CONFIGURATION REGISTER BITMAPS
7
0
6
0
5 4 3 2 1 0
CS1 Configuration
Register,
0 0 0 0 0 0 Reset
Second Level
Required
Index 06h
Mask Address Pin A0
Mask Address Pin A1
Mask Address Pin A2
Mask Address Pin A3
Assert Chip Select Signal on Write
Assert Chip Select Signal on Read
Unaffected by RD/WR
Mask Address Pins A11
7
1
6
1
5 4 3 2 1 0
0 1 0 0 0 0 Reset
1
1
0
1
0
0
0
SID (In PC87317)
Register,
Index 20h
0 Required
Revision ID
Chip ID
FIGURE 2-16. SuperI/O CS1 Configuration Register
Bitmap
2.10.8 Reserved
SID (In PC97317)
Register,
Index 20h
1 Required
Attempts to access this register produce undefined results.
7
1
6
1
5 4 3 2 1 0
0 1 1 1 1 1 Reset
2.10.9 CS2 Base Address MSB Register
1
1
0
1
1
1
1
This read/write register is reset by hardware to 00h. It functions like the Plug and Play ISA base address register at index 60h. See TABLE 2-7 "Plug and Play (PnP) I/O Space
Configuration Registers" on page 31.
2.10.10 CS2 Base Address LSB Register
Chip ID
This read/write register is reset by hardware to 00h. It functions like the Plug and Play ISA base address register at index 61h. See TABLE 2-7 "Plug and Play (PnP) I/O Space
Configuration Registers" on page 31.
2.10.11 CS2 Configuration Register
This read/write register is reset by hardware to 00h. It functions like the CS0 Configuration register.
7
0
6
0
7
0
6
0
SuperI/O Configuration 1
5 4 3 2 1 0
Register (SIOC1),
0 x 0 1 x 0 Reset
Index 21h
Required
5 4 3 2 1 0
CS2 Configuration
Register,
0 0 0 0 0 0 Reset
Second Level
Required
Index 0Ah
ZWS Enable
CSOUT or CS0 Select
PC-AT or PS/2 Drive Mode Select
UART2 or GPIO30-36 Select
X-Bus Data Buffer (XDB) Select
Lock Scratch Bit
Mask Address Pin A0
Mask Address Pin A1
Mask Address Pin A2
Mask Address Pin A3
Assert Chip Select Signal on Write
Assert Chip Select Signal on Read
Unaffected by RD/WR
Mask Address Pins A11
General Purpose Scratch Bits
7
0
FIGURE 2-17. SuperI/O CS2 Configuration Register
Bitmap
6
0
SuperI/O Configuration 2
5 4 3 2 1 0
Register (SIOC2),
Index 22h
0 0 0 0 x x Reset
Required
2.10.12 Reserved, Second Level Indexes 0Bh-0Fh
Attempts to access these registers produce undefined results.
BADDR1 and BADDR0
GPIO22 or POR Select
2.10.13 Not Accessible, Second Level Indexes 10h-FFh
GPIO21, IRSL2, ID2 or ISL0 Pin Select
GPIO20 or IRSL1 Pin Select
GPIO17 or WDO Pin Select
GPIO Bank Select
Not accessible because bits 7-4 of the Index register are 0.
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44
Configuration
6
0
0
0
Programmable Chip Select
5 4 3 2 1 0
Configuration Index
Register,
0 0 0 0 0 0 Reset
Index 23h
0 0
Required
7
0
6
1
5 4 3 2 1 0
0 0 0 0 0 0 Reset
Required
SuperI/O KBC
Configuration
Register,
Index F0h
TRI-STATE Control
Index of a Programmable
Chip Select Configuration
Register
Reserved
Read Only
7
0
6
0
KBC Clock Source
Programmable Chip Select
5 4 3 2 1 0
Configuration Data
Register,
0 0 0 0 0 0 Reset
Index 24h
Required
7
0
6
0
5 4 3 2 1 0
1 0 0 0 0 0 Reset
Required
SuperI/O FDC
Configuration
Register,
Index F0h
TRI-STATE Control
Reserved
Data in a Programmable
Chip Select Configuration
Register
7
0
6
0
DENSEL Polarity Control
TDR Register Mode
Four Drive Control
SuperI/O Configuration 3
5 4 3 2 1 0
Register (SIOC3),
0 0 0 0 0 0 Reset
Index 25h
7
0
6
0
5 4 3 2 1 0
Drive ID Register,
Index F1h
0 0 0 0 0 0 Reset
Required
Required
P16 or GPIO25 Select
P12 or CS0 Select
Reserved
SCI Polarity Select
Drive 0 ID
Drive 1 ID
SCI Plug-and-Play Select
7
x
6
x
Reserved
5 4 3 2 1 0 SRID (In the 97317 only)
Register,
x x x x x x Reset
Index 27h
7
0
Required
6
0
5 4 3 2 1 0
CS0 Configuration
Register,
0 0 0 0 0 0 Reset
Second Level
Required
Index 02h
Mask Address Pin A0
Mask Address Pin A1
Mask Address Pin A2
Mask Address Pin A3
Assert Chip Select Signal on Write
Assert Chip Select Signal on Read
Unaffected by RD/WR
Mask Address Pins A11-4
Chip Revision ID
45
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CONFIGURATION REGISTER BITMAPS
7
0
CONFIGURATION REGISTER BITMAPS
Configuration
7
0
6
0
5 4 3 2 1 0
CS1 Configuration
Register,
0 0 0 0 0 0 Reset
Second Level
Required
Index 06h
Mask Address Pin A0
Mask Address Pin A1
Mask Address Pin A2
Mask Address Pin A3
Assert Chip Select Signal on Write
Assert Chip Select Signal on Read
Unaffected by RD/WR
Mask Address Pins A11-4
7
0
6
0
5 4 3 2 1 0
CS2 Configuration
Register,
0 0 0 0 0 0 Reset
Second Level
Required
Index 0Ah
Mask Address Pin A0
Mask Address Pin A1
Mask Address Pin A2
Mask Address Pin A3
Assert Chip Select Signal on Write
Assert Chip Select Signal on Read
Unaffected by RD/WR
Mask Address Pins A11-4
7
1
6
1
SuperI/O Parallel Port
5 4 3 2 1 0 Configuration Register,
Index F0h
1 1 0 0 1 0 Reset
Required
TRI-STATE Control
Clock Enable
Reserved
PP of PnP ISA Resource Data
Configuration Bits within the Parallel Port
Parallel Port Mode Select
7
0
6
0
SuperI/O UART1,2
5 4 3 2 1 0 Configuration Register,
Index F0h
0 0 0 0 0 0 Reset
Required
TRI-STATE Control for
UART Pins
Power Mode Control
Busy Indicator
Ring Detection on RI Pin
Reserved
Bank Select Enable
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46
3.0
Keyboard (and Mouse) Controller
(KBC) (Logical Devices 0 and 1)
3.1
SYSTEM ARCHITECTURE
The KBC is a general purpose microcontroller, with an 8-bit
internal data bus. See FIGURE 3-1 "KBC System Functional Block Diagram". It includes these functional blocks:
The Keyboard Controller (KBC) is a functionally independent programmable device controller. It is implemented
physically as a single hardware module on the
PC87317VUL multi-I/O chip and houses two separate logical devices: a keyboard controller and a mouse controller.
Serial Open-collector Drivers: Four open-collector bi-directional serial lines enable serial data exchange with
the external devices (keyboard and mouse) using the
PS/2 protocol.
The KBC accepts user input from the keyboard or mouse,
and transfers this input to the host PC via the common
PC87317VUL-PC interface.
Program ROM: 2 Kbytes of ROM store program machine
code in non-erasable memory. The code is copied to
this ROM during manufacture, from customer-supplied
code.
The KBC is functionally equivalent to the industry standard
8042A keyboard controller, which may serve as a detailed
technical reference for the KBC.
Data RAM: A 256-byte data RAM enables run-time internal data storage, and includes an 8-level stack and 16
8-bit registers.
The KBC is delivered preprogrammed with customer-supplied code. KBC firmware code is identical to 8042 code,
and to code of the keyboard controller of the PC87323VUL
chip. The PC87323VUL is recommended as a development
platform for the KBC since it uses identical code and includes internal program RAM that enables software development.
Timer/Counter: An internal 8-bit timer/counter can count
external events or pre-divided system clock pulses. An
internal time-out interrupt may be generated by this device.
I/O Ports: Two 8-bit ports (Port 1 and Port 2) serve various
I/O functions. Some are for general purpose use, others
are utilized by the KBC firmware.
Program
Address
Data
RAM
256 x 8
(including
registers
and stack)
Program
ROM
8-Bit
2Kx8
CPU
TEST1
8-Bit Internal Bus
Timer
Overflow
I/O PORT 1
8-Bit
8-Bit Timer
or Counter
I/O Port 2
8-Bit
P25
P11,10
P24
STATUS
P27, P26, P23, P22
Serial Open-Collector
Drivers
DBBIN
DBBOUT
IBF
TEST0
P21-20
To PnP
Interrupt Matrix KBDAT KBCLK MDAT MCLK
P17, P16, P12
RD WR A2
D7-0
PC87317VUL Interface
I/O Interface
FIGURE 3-1. KBC System Functional Block Diagram
47
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3.0 Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
FUNCTIONAL OVERVIEW
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
PC87317VUL
SA15-0
A15-0
D7-0
AEN
PC
Internal Interface Bus
XD7-0
KBC Device
STATUS
P16
DBBIN
P17
DBBOUT
P20
P21
P26
TEST0
Chip Set
RD
P27
P10
WR
MR
P23
KBC IRQ
IRQn
Plug and
Play
Matrix
P12
P24
TEST1
P22
Mouse IRQ P25
P11
KBCLK
Keyboard Clock
KBDAT
Keyboard Data
MCLK
Mouse Clock
MDAT
Mouse Data
FIGURE 3-2. System Interfaces
3.2
FUNCTIONAL OVERVIEW
The KBC clock is generated from the main clock of the chip,
which may come from an external clock source or from the
internal frequency multiplier. (See Section 3.3 "DEVICE
CONFIGURATION" and FIGURE 3-5 "Timing Generation
and Timer Circuit" on page 50.) The KBC clock rate is configured by the SIO Configuration Registers.
The KBC supports two external devices — a keyboard and
a mouse. Each device communicates with the KBC via two
bidirectional serial signals. Five additional external generalpurpose I/O signals are provided.
KBC operation involves three signal interfaces:
●
External I/O interface
●
Internal KBC - PC87317VUL interface
●
PC87317VUL - PC chip set interface.
3.3
DEVICE CONFIGURATION
The KBC hardware contains two logical devices—the KBC
(logical device 0) and the mouse (logical device 1).
3.3.1
These system interfaces are shown in FIGURE 3-2 "System Interfaces".
I/O Address Space
The KBC has two I/O addresses and one IRQ line (KBC
IRQ) and can operate without the companion mouse.
The KBC uses two data registers (for input and output) and
a status register to communicate with the PC87317VUL
central system. Data exchange between these units may be
based on programmed I/O or interrupt-driven.
The mouse cannot operate without the KBC device. It has
one IRQ line (mouse IRQ) but has no I/O address. It utilizes
the KBC I/O addresses.
The KBC has two internal interrupts: the Input Buffer Full
(IBF) interrupt and Timer Overflow interrupt (see FIGURE
3-1 "KBC System Functional Block Diagram" on page 47).
These two interrupts can be independently enabled or disabled by KBC firmware. Both are disabled by a hard reset.
These two interrupts only affect the execution flow of the
KBC firmware, and have no connection with the external interrupts requested by this logical device.
3.3.2
The KBC can generate two external interrupt requests.
These request signals are controlled by the KBC firmware
which generates them by manipulating I/O port signals. See
Section 3.3.2 "Interrupt Request Signals".
The Interrupt Select registers (index 70h for each logical device) select the IRQ pin to which the corresponding interrupt
request is routed. The interrupt may also be disabled by not
routing its request signal to any IRQ pin.
The PC87317VUL supports the KBC and handles interactions with the PC chip set. In addition to data transfer, these
interactions include KBC configuration, activation and status monitoring. The PC87317VUL interconnects with the
host via one interface that is shared by all chip devices.
Bit 0 of the Interrupt Type registers (index 71h for each logical device) determines whether the interrupts are passed
(bit 0 = 0) or latched (bit 0 = 1). If bit 0 = 0, interrupt request
signals (P24 and P25) are passed directly to the selected
IRQ pin. If bit 0 = 1, interrupt request signals that become
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Interrupt Request Signals
The KBC IRQ and Mouse IRQ interrupt request signals are
identical to (or functions of) the P24 and P25 signals of the
8042. These interrupt request signals are routed internally
to the Plug and Play interrupt Matrix and may be routed to
user-programmable IRQ pins. Each logical device is independently controlled.
48
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
“1”
From KBC IRQ
KBC IRQ Feedback
Interrupt Enable
RD
AEN
A15-0
Q
1
CLK
CLR
Plug and
Play Matrix
0
MUX
1 MUX
Port 60
Address Read
Decoder
Interrupt
Type
(1 = Latch)
MR
“1”
From Mouse IRQ
Q
1
CLK
CLR
Mouse IRQ Feedback
Interrupt Enable
Address
Decoder
Interrupt
Polarity
(0 = Invert)
0
PR
D
RD
AEN
A15-0
MR
Plug and
Play Matrix
0
PR
D
Interrupt
Polarity
(0 = Invert)
To Selected KBC IRQ Pin
Interrupt
Type
(1 = Latch)
To Selected Mouse IRQ Pin
trates the internal interrupt request logic.
0
MUX
Port 60
Read
1 MUX
Note:
The EN FLAGS command (used for routing OBF and IBF onto P24 and P25 in the 8042) causes unpredictable results
and should not be issued.
FIGURE 3-3. Interrupt Request Logic
3.3.3
See Section 2.5.1 "SuperI/O KBC Configuration Register"
on page 40. The clock source and frequency may only be
changed when the KBC is disabled.
KBC Clock
The KBC clock frequency is selected by the Super I/O KBC
Configuration Register at index F0h of logical device 0 to be
either 8, 12 or 16 MHz. 16 MHz is not available when the
clock source on pin X1 is 24 MHz. This clock is generated
from a 32.768 KHz crystal connected to pins X1C and X2C,
or from either a 24 MHz or a 48 MHz clock input at pin X1.
For details regarding the configuration of each device, refer
to TABLES 2-12 "KBC Configuration Registers for Keyboard - Logical Device 0" and 2-13 "KBC Configuration
Registers for Mouse - Logical Device 1" on page 34.
+VCC
External
Clock
Standard or
Open-Collector
TTL Driver
X1
PC87317VUL
FIGURE 3-4. External Clock Connection
49
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DEVICE CONFIGURATION
active are latched on their rising edge, and held until read
from the KBC output buffer (port 60h). FIGURE 3-3 illus-
EXTERNAL I/O INTERFACES
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
External
24 or 48 MHz X1
Clock
External
32768 Hz
Crystal
X1C
X2C
Frequency
Multiplier
(1465)
48 MHz
Clock
Source
Select
÷2
÷
2 or 3
Frequency
Select
KBC Clock
3-State
Counter
Stop
5-Cycle
Counter
32-Bit
Timer
Prescaler
Timer
8-Bit Timer
or Counter
Overflow
Flag
Counter
TEST1 External Event Input
(MCLK)
Interrupt
FIGURE 3-5. Timing Generation and Timer Circuit
3.3.4
3.4.1
Timer or Event Counter
Four serial I/O signals interface with the external keyboard
and mouse. These signals are driven by open-collector drivers with signals derived from two I/O ports residing on the
internal bus. Each output can drive 16 mA, making them
suitable for driving the keyboard and mouse cables. The
signals are named KBCLK, KBDAT, MCLK and MDAT, and
they are the logical complements of P26, P27, P23 and
P22, respectively.
The keyboard controller includes an 8-bit counter, which
can be used as a timer or an event counter, as selected by
the firmware.
Timer Operation
When the internal clock is chosen as the counter input, the
counter functions as a timer. The clock fed to the timer consists of the KBC instruction cycle clock, divided by 32. (See
FIGURES 3-9 "Instruction Timing" on page 52 and 3-5
"Timing Generation and Timer Circuit".) The divisor is reset
only by a hardware reset or when the timer is started by an
STRT T instruction.
TEST0 and TEST1 are dedicated test pins, internally connected to KBCLK and MCLK, respectively, as shown in FIGURES 3-1 "KBC System Functional Block Diagram" on
page 47 and 3-2 "System Interfaces" on page 48. These
pins may be used as logical conditions for conditional jump
instructions, which directly check the logical levels at the
pins.
Event Counter Operation
When the clock input of the counter is switched to the external input (MCLK), it becomes an event counter. The falling
edge of the signal on the MCLK pin causes the counter to
increment. Timer Overflow Flag and Timer interrupt operate
as in the timer mode.
3.4
KBDAT and MDAT are connected to pins P10 and P11, respectively.
MCLK also provides input to the event counter.
When the KBC is disabled, the KBCLK, KBDAT, MCLK and
MDAT pins can be put in TRI-STATE. The KBC can be disabled via the Activate register in logical device 0 or via bit 0
of FER1 register in logical device 8. The above pins can be
put in TRI-STATE via bit 0 of the SuperI/O KBC Configuration register in logical device 0 or via bit 0 of the PMC1 register in logical device 8. The Activate register in logical
device 1 has no effect on these pins.
EXTERNAL I/O INTERFACES
The PC chip set interfaces with the PC87317VUL as illustrated in FIGURE 3-2 "System Interfaces" on page 48.
All data transactions between the KBC and the PC chip set
are handled by the PC87317VUL.
The PC87317VUL decodes all I/O device chip-select functions from the address bus. The KBC chip-select codes are,
traditionally, 60h or 64h, as described in TABLE 3-1 "System Interface Operations" on page 51. (These addresses
are user-programmable.)
3.4.2
General Purpose I/O Signals
The P12, P16, P17, P20 and P21 general purpose I/O signals interface to two I/O ports (port1 and port2). P12, P16
and P17 are mapped to port 1 and P20 and P21 are
mapped to port 2.
The external interface includes two sets of signals: the keyboard and mouse interface signals, and the general-purpose I/O signals.
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Keyboard and Mouse Interface
P12 port’s output can be routed internally to POR and/or
SCI. (See Section 4.4.3 "System Power-Up and Power-Off
Activation Event Description" on page 67)
50
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
lines used for input is recommended to limit the surge current during the strong pull-up. See FIGURE 3-7 "Current
Limiting Resistor".
If a 1 is asserted, an externally applied signal may pull down
the output. Therefore, input from this quasi-bidirectional circuit can be correctly read if preceded by a 1 written to output.
During output, a 1 written to output is strongly pulled up for
the duration of a (short) write pulse, and thereafter maintained by a high impedance “weak” active pull-up (implemented by a degenerated transistor employed as a
switchable pull-up resistor). A series resistor to those port
P20 and P21 are driven by open-drain drivers.
When the KBC is reset, all port data bits are initialized to 1.
ORL, ANL
+VCC
MR
Q1
P
Q3
Q
D
PORT
F/F
PAD
Q
Port
Write
Q2
IN
Internal Bus
FIGURE 3-6. Quasi-Bidirectional Driver
R
Port Pin
R: current limiting resistor
100 – 500Ω
A small-value series current limiting
resistor is recommended when
port pins are used for input.
PC87317VUL
R
Port Pin
100 – 500Ω
FIGURE 3-7. Current Limiting Resistor
3.5
INTERNAL KBC - PC87317VUL INTERFACE
TABLE 3-1. System Interface Operations
The KBC interfaces internally with the PC87317VUL via
three registers: an input (DBBIN), output (DBBOUT) and
status (STATUS) register. See FIGURE 3-1 "KBC System
Functional Block Diagram" on page 47 and TABLE 3-1
"System Interface Operations".
RD WR
TABLE 3-1 "System Interface Operations" illustrates the
use of address line A2 to differentiate between data and
commands. The device is selected by chip identification of
default address 60h (when A2 is 0) or 64h (when A2 is 1).
After reset, these addresses can be changed by software.
51
Default
Addresses
Operation
0
1
60h
Read DBBOUT
1
0
60h
Write DBBIN, F1 Clear (Data)
0
1
64h
Read STATUS
1
0
64h
Write DBBIN, F1 Set (Command)
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INTERNAL KBC - PC87317VUL INTERFACE
P12, P16 and P17 are driven by quasi-bidirectional drivers.
(See FIGURE 3-6 "Quasi-Bidirectional Driver".) These signals are called quasi-bidirectional because the output buffer
cannot be turned off (even when the I/O signal is used for
input).
INSTRUCTION TIMING
Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)
3.5.1
Bit 0 - OBF, Output Buffer Full
A 1 indicates that data has been written into the DBBOUT register by the KBC. It is cleared by a system
read operation from DBBOUT.
The KBC DBBOUT Register, Offset 60h,
Read Only
The DBBOUT register transfers data from the keyboard
controller to the PC87317VUL. It is written to by the keyboard controller and read by the PC87317VUL for transfer
to the PC. The PC may be notified of the need to read data
from the KBC by an interrupt request or by polling the Output Buffer Full (OBF) bit (bit 0 of the KBC STATUS register
described in Section 3.5.3 "The KBC STATUS Register").
3.5.2
Bit 1 - IBF, Input Buffer Full
When a write operation is performed by the host system,
this bit is set to 1, which may be set up to trigger the IBF
interrupt. Upon executing an IN A, DBB instruction, it is
cleared.
The KBC DBBIN Register, Offset 60h (F1 Clear)
or 64h (F1 Set), Write Only
Bit 2 - F0, General Purpose Flag
A general purpose flag that can be cleared or toggled by
the keyboard controller firmware.
The DBBIN register transfers data from the PC87317VUL
system to the keyboard controller. (This transaction is transparent to the user, who should program the device as if direct access to the registers were in effect.)
Bit 3 - F1, Command/Data Flag
This flag holds the state of address line A2 while a write
operation is performed by the host system. It distinguishes between commands and data from the host
system. In this device, a write with A2 = 1 (hence F1 =
1) is defined as a command, and A2 = 0 (hence F1 = 0)
is data.
When data is received in this manner, an Input Buffer Full
(IBF) internal interrupt may be generated in the KBC, to deal
with this data. Alternatively, reception of data in this manner
can be detected by the KBC polling the Input Buffer Full bit
(IBF, bit 1 of the KBC STATUS register).
3.5.3
The KBC STATUS Register
Bits 7-4, General Purpose Flags
These flags may be modified by KBC firmware.
The STATUS register holds information regarding the system interface status.The bitmap below shows the bit definition of this register. This register is controlled by the KBC
firmware and hardware, and is read-only for the system.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
3.6
INSTRUCTION TIMING
The KBC clock is first divided by 3 to generate the state timing, then by 5 to generate the instruction timing. Thus each
instruction cycle consists of five states and 15 clock cycles.
KBC Status Register
Offset 64h
0 Reset
Read Only
0
Most keyboard controller instructions require only one instruction cycle, while some require two cycles. Refer to the
8042 or PC87323VUL instruction set for details.
OBF Output Buffer Full
IBF Input Buffer Full
F0 General Purpose Flag
F1 Command or Data Flag
General Purpose
Flags
FIGURE 3-8. KBC STATUS Configuration Register Bitmap
S1
S2
S3
S4
1 Instruction Cycle = 15 Clock Cycles
KBC CLK
FIGURE 3-9. Instruction Timing
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52
S5
S1
4.0
●
Real-Time Clock (RTC) and
Advanced Power Control (APC)
(Logical Device 2)
Bank 2 uses the upper 64 bytes for functions specific
to the APC activity.
The active bank is selected by setting RTC Control Register
A (CRA) bits 6-4 (DV2-0). (See TABLE 4-3 "Divider Chain
Control and Bank Selection" on page 57.)
The RTC logical device contains two major functions: the
Real-Time Clock (RTC) and Advanced Power Control
(APC).
All RTC register are accessed by an Index and a Data register (at base address and base address+1). The Index register points to the register location being accessed, and the
Data register contains the data to be transferred to or from
the register. An additional 128 bytes of battery-backed RAM
(also called upper RAM) may be accessed via a second level address: the second level uses the upper RAM Index register at index 50h of bank 1 and the upper RAM Data
register at index 53h of bank 1.
The RTC is a timekeeping module that provides a time of
day clock and a multi-century calendar, alarm facilities and
three programmable timer interrupts. It maintains valid timekeeping and retains RAM contents during power-down using external battery backup power and offers RAM-Lock
schemes and Power Management options.
RTC software module is compatible with the DS1287 and
MC146818 clock chips. (The RTC module differs from
these two chips in the following feature: Port 70 is read/write
in this module, and is write-only in the DS1287 and
MC146818.)
Access to the three register banks and RAM may be locked.
For details see Section 4.5.8 "RAM Lock Register (RLR)" on
page 72.
The APC function enables automatic PC system powerstate control in response to external events, adding power
management ability to the PC host system.
RTC operation is controlled using the control registers listed
in TABLE 4-1 "RTC Control Registers" below. These registers appear in all the RTC register banks. See Section 4.9
"REGISTER BANK TABLES" on page 89.
4.1
Automatic Power-Up switching enables efficient use of the
PC system in applications which are typically powered up at
all times, such as telephone answering machines or fax receivers. Automatic Power-Down switching enables a controlled power-down sequence when switched off by the
user.
TABLE 4-1. RTC Control Registers
The PC87317VUL APC module supports a variety of external General Purpose Power Management interrupts, giving
the user software - selectable input signal definition for each
individual input. It maintains a specific Power Management
Timer for implementing operational logic and generating the
appropriate interrupt request.
The module complies with the ACPI (Rev 1.0) standard definition.
Battery-Backed Register Banks and RAM
The RTC and APC module has three battery-backed register banks. Two are used by the logical units themselves.
The host system uses the third for general purpose batterybacked storage.
Bank 0 - General Purpose Register Bank
Bank 1 - RTC Register Bank
●
Bank 2 - APC Register Bank
Bank 1 uses the upper 64 bytes for functions specific
to the RTC activity and for addressing Upper RAM.
CRA
RTC Control Register A
0Bh
CRB
RTC Control Register B
0Ch
CRC
RTC Control Register C
0Dh
CRD
RTC Control Register D
rel1
DMAR
Day-of-Month Alarm Register
rel1
MAR
Month Alarm Register
rel1
CR
Century Register
4.1.1
RTC Hardware and Functional Description
Bus Interface
The RTC function is initially mapped to the default I/O registers at addresses 70h (index) and 71h (data) within the
PC87317VUL. These registers may be reassigned, in compliance with the Plug and Play requirements. See Section
2.2 "SOFTWARE CONFIGURATION" on page 28.
The upper 64 bytes of bank addresses are utilized as follows:
●
0Ah
Local battery-backed RAM serves as storage for all timekeeping functions.
The lower 64-byte locations of the three banks are shared.
The first 14 bytes store time and alarm data and contain
control registers. The next 50 bytes are general purpose
memory.
Bank 0 supplies an additional 64 bytes of memory
backed RAM.
Description
The RTC employs an external crystal connected to an internal oscillator circuit or an optional external clock input, as
the basic clock for timekeeping.
The memory maps and register content for each of the three
banks are illustrated in Section 4.9 "REGISTER BANK TABLES" on page 89.
●
Name
RTC configuration registers within the PC87317VUL store
the settings for all interface, configuration and power management options. These registers are described in detail in
Section 2.3 "THE CONFIGURATION REGISTERS" on
page 29.
The banks are:
●
Index
1. These registers have relocatable indexes.
See register descriptions.
Battery-backup power enables information retention during
system power down.
●
RTC OVERVIEW
53
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4.0 Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
RTC OVERVIEW
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
External Clock and Timing Generation
Start-up time for this oscillator may vary from two to seven
seconds due to the high Q of the crystal. The parameters
below describe the crystal requirements:
The RTC can use one of the following timekeeping input
clock options:
●
●
Parallel, resonant, tuning fork (N cut) or XY bar
A 32768 Hz crystal connected externally at the X1C
and X2C pins completes an oscillator circuit and generates the 32768 Hz input clock. (See FIGURE 4-1
"Oscillator Internal and External Circuitry" on page
54.)
Q ≥ 35000
Load Capacitance (CL) 9 to 13 pF
Accuracy and temperature coefficients are user defined.
4.1.2
An external clock may be connected to pin X1C.
The time generation function divides the 32.768 KHz by 215
to derive a 1 Hz signal which serves as the input for timekeeping functions. Bits 6-4 of RTC Control Register A
(CRA) control the activity and location of the divider chain in
memory. Bits 3-0 of the CRA register select one of fifteen
taps from the divider chain to be used as a periodic interrupt. See Section 4.2.1 "RTC Control Register A (CRA)" on
page 56 for a description of divider configurations and rate
selections.
Time is kept in BCD or binary format as determined by bit 2
(DM) of Control Register B (CRB). Either 12 or 24 hour representation for the hours can be maintained as determined
by bit 1 of CRB. When changing formats, the time registers
must be re-initialized to the corresponding data format.
Daylight savings time and leap year exceptions are handled
by the timekeeping function. When bit 0 (the Daylight Saving Enable bit, DSE) of CRB is set to 1, time advances from
1:59:59 AM to 3:00:00 on the first Sunday in April, and
changes from 1:59:59 to 1:00:00 on the last Sunday of October. In leap years, February is extended to 29 days.
The divider chain is reset to 0 by bits 6-4 of the CRA register. An update occurs 500 msec after the divider chain is activated by setting normal operational mode (bits 6-4 of CRA
= 010). The periodic flag becomes active one half of the programmed period after the divider chain is activated.
Updating
Timekeeping is performed by hardware updating a pre-programmed time value once per second. The preprogrammed
values are written by the user to the following locations:
FIGURE 4-1 "Oscillator Internal and External Circuitry" illustrates the internal and external circuitry that comprise the
oscillator.
20 MΩ
C1
The values for seconds, minutes, hours, day of week, date
of Month, month and year are located in the common storage area in all three memory banks (See TABLE 4-19
"Banks 0, 1 and 2 - Common 64-Byte Memory Map" on
page 89). The century value is located in the Century Register (See Section 4.2.7 on page 59).
X2C Internal
External
X1C
Users must ensure that reading or writing to the time storage registers does not coincide with a system update of
these registers, which would cause invalid and unpredictable results.
REXT
C2
REXT = 120 KΩ
C1 = 10 pF
C2 = 33 pF
CPARASITIC = 8 pF
There are several ways to avoid this contention. Four options follow:
Method 1 - Set the SET bit (bit 7 of the CRB register) to 1.
This takes a “snapshot” of the internal time registers and
loads it into the user copy. If user copy registers have
been updated, the user copy updates the internal registers when the SET bit goes from 1 to 0. This mechanism
enables loading new time parameters into the RTC.
FIGURE 4-1. Oscillator Internal and External Circuitry
This oscillator is active under normal power or during power
down. It stops only in the event of a power failure with the
oscillator disabled (see “Oscillator Activity” on page 56), or
when battery backup power drops below VBAT(Min) (see
TABLE 14-1 "Recommended Operating Conditions" on
page 232).
Method 2 - Access after detection of an Update-Ended interrupt.
This implies that an update has just completed and
there are 999 msec remaining until the next occurrence.
If oscillator input is from an external source, input should be
driven rail to rail and should have a nominal 50% duty cycle.
In this case, oscillator output X2C should be disconnected
and internal oscillator should be disabled.
Method 3 - Poll Update-In-Progress (UIP) (bit 7 in Control
Register A).
The update occurs 244 µsec after the update-inprogress bit goes high. Therefore if a 0 is read, there is
a minimum of 244µs in which the time is guaranteed to
remain stable.
External capacitor values should be chosen to provide the
manufacturer’s specified load capacitance for the crystal
when combined with the parasitic capacitance of the trace,
socket, and package, which can vary from 0 to 8 pF. The
rule of thumb in choosing these capacitors is:
Method 4 - Use a periodic interrupt to determine if an update cycle is in progress.
The periodic interrupt is first set to a desired period. Periodic interrupt appearance then indicates there is a period of (Period of periodic interrupt ÷ 2 + 244 µsec)
remaining until another update occurs.
CL = (C1 * C2) ÷ (C1 + C2) + CPARASITIC
C2 > C1
C1 can be trimmed to achieve precisely 32768.0 Hz after insertion.
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Timekeeping
54
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
RTC OVERVIEW
Power Supply Module
VDD
Power
Host PC
VDD
PC87317VUL
External AC Power
VDD Sense
RTC
and
APC
Modules
ONCTL
VCCH Power
VCCH
VBAT Power
Backup
Battery
FIGURE 4-2. PC87317VUL Power Supplies
A battery backup voltage VBAT maintains RTC/APC timekeeping and backup memory storage when the VCCH voltage is absent, due to power failure or disconnection of the
external AC input power supply.
Alarms
The timekeeping function may generate an alarm when the
current time reaches a stored alarm time. After each RTC
time update, the seconds, minutes, hours, day-of-month
and month storage registers are compared with their counterparts in the alarm storage registers.
The APC function produces the ONCTL signal, which controls the VDD power supply voltage. (See Section 4.4.1 "The
ONCTL Flip-Flop and Signal" on page 62.)
If equal, the alarm flag is set in Control Register C (CRC). If
the Alarm Interrupt Enable bit is set in Control Register B,
then setting the Alarm flag generates an RTC interrupt.
To ensure proper operation, a 500 mV differential is needed
between VCCH and VBAT.
See FIGURE 4-3 "Typical Battery Configuration". No external diode is required to meet the UL standard, due to the internal serial resistor.
Any alarm register may be set to a “Don’t Care” state by setting bits 7,6 to 11. This results in periodic alarm activation at
an increased rate whose period is that of the Don’t Care
register, e.g., if bits 7,6 of the hours register is set to 11(its
”Don’t care” value), the alarm will be activated every hour. If
the day-of-month register is set to its ”Don’t care” value, the
alarm will be activated daily at the time defined by the remaining alarm values.
VCCH
1µF
The seconds, minutes and hours alarm registers are shared
with the wake-up function, and are located at indexes 01h,
03h and 05h of banks 0, 1 and 2, respectively. The day-ofmonth alarm register is configurable. It may reside in bank
0 or bank 1. Upon first power-on, it resides in bank 1, Index
49h. The register is configured via the DADDR register in
bank 2. The month alarm register is also configurable and
may reside in bank 0 or bank 1. Upon first power-on, it resides in bank 1, Index 4Ah. The register is configured via
the MADDR register in bank 2. For more details, see the
RTC and APC Registers.
PC87317VUL
VBAT
FIGURE 4-3. Typical Battery Configuration
System Bus Lockout
As the RTC switches to battery power, all input signals are
locked out so that the internal registers can not be modified
externally.
The century register is configurable. It may reside in bank 0
or bank 1. Upon first power-on, it resides in bank 1, Index
48h. The register is configured via the CADDR register in
bank 2. For more details, see the RTC and APC Registers.
4.1.3
VCCH
Power Up Detection
When system power is restored after a power failure, the
power failure lock condition continues for a delay of 62
msec (minimum) to 125 msec (maximum) after the RTC
switches from battery power to system power.
Power Management
The host PC and PC87317VUL power is supplied by the
system power supply voltage, VDD. See FIGURE 4-2
"PC87317VUL Power Supplies".
The power failure lock condition is switched off immediately
in the following situations:
●
A trickle voltage (VCCH) from the external AC power supply
powers the RTC and APC under normal conditions. The
VDD voltage reaches the RTC/APC as a sense signal, to determine the presence or absence of a valid VDD supply.
55
If the Divider Chain Control bits (DV2-0, bits 6-4 in Control Register A) specify any mode other than 010, 100 or
011, all input signals are enabled immediately upon detection of system voltage above that of the battery voltage.
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THE RTC REGISTERS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
●
●
4.2.1
When battery voltage is below 1 volt and MR is 1, all input signals are enabled immediately upon detection of
system voltage above that of battery voltage. This also
initializes registers at indexes 00h through 0Dh.
The CRA register controls periodic interrupt rate selection
and bank selection.
Bits 3-0 - Periodic Interrupt Rate Select (RS3-0)
These read/write bits select one of fifteen output taps
from the clock divider chain to control the rate of the periodic interrupt. See TABLE 4-2 "Periodic Interrupt Rate
Encoding" below and FIGURE 4-5 "Interrupt/Status Timing" on page 57.
Master reset does not affect these bits.
If the VRT bit (bit 7 in Control Register D) is 0, all input
signals are enabled immediately upon detection of system voltage above that of battery voltage.
Oscillator Activity
The RTC internal oscillator circuit is active whenever power
is supplied to the RTC with the following exceptions:
●
●
RTC Control Register A (CRA)
Software wrote 000 or 001 to the Divider Chain Control bits (DV2-0), i.e., bits 6-4, of Control Register A,
and the RTC is supplied by VBAT, or
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0 Power-Up
Reset
Required
The RTC is supplied by VBAT and the VRT bit of Control Register D is 0.
RS0
RS1
RS2
RS3
DV0
DV1
DV2
UIP
These conditions disables the oscillator.
When the oscillator becomes inactive, the APC is disabled.
4.1.4
RTC Control
Register A
(CRA)
Index 0Ah
Interrupt Handling
The RTC logic device has a single Interrupt Request line,
IRQ, which handles three interrupt conditions. The Periodic,
Alarm, and Update-Ended interrupts are generated (IRQ is
driven low) if the respective enable bits in Control Register
B are set when an interrupt event occurs.
TABLE 4-2. Periodic Interrupt Rate Encoding
Reading RTC Control Register C (CRC) clears all interrupt
flags. Thus, it is recommended that when multiple interrupts
are enabled, the interrupt service routine should first read
and store the CRC register, then deal with all pending interrupts by referring to this stored status.
RS3-0
3210
Periodic Interrupt Rate
0000
none
If an interrupt is not serviced before a second occurrence of
the same interrupt condition, the second interrupt event is
lost. FIGURE 4-5 "Interrupt/Status Timing" on page 57 illustrates interrupt and status timing in the PC87317VUL.
0001
3.90625
msec
0010
7.8125
msec
0011
122.070
µsec
4.2
0100
244.141
µsec
0101
488.281
µsec
0110
976.562
µsec
0111
1.953125
msec
1000
3.90625
msec
1001
7.8125
msec
1010
15.625
msec
1011
31.25
msec
1100
62.5
msec
1101
125
msec
1110
250
msec
1111
500
msec
THE RTC REGISTERS
The RTC registers can be accessed at any time during nonbattery backed operation. The registers are listed in TABLE
4-1 "RTC Control Registers" on page 53 and described in
detail in the sections that follow.
The RTC registers and the RAM cannot be written to before
reading the VRT bit (bit 7 of the Section 4.2.4 "RTC Control
Register D (CRD)" on page 58), thus preventing bank selection and other functions. The user must read the VRT bit as
part of the startup activity in order to be able to access the
RTC/APC registers.
For registers with reserved bits, the “Read-Modify-Write”
technique should be used.
Bits 6-4 - Divider Chain Control (DV2-0)
These read/write bits control the configuration of the divider chain for timing generation and memory bank selection, as shown in TABLE 4-3 "Divider Chain Control
and Bank Selection" on page 57.
Master reset does not affect these bits.
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56
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
DV2-0
This register enables the selection of various time and date
options, as well as the use of interrupts.
Selected
Bank
Configuration
0 0 0
Bank 0
Oscillator Disabled1
0 0 1
Bank 0
Oscillator Disabled1
0 1 0
Bank 0
Normal Operation
0 1 1
Bank 1
Normal Operation
1 0 0
Bank 2
Normal Operation
1 0 1
Undefined
Test
1 1 0
Bank 0
Divider Chain Reset
1 1 1
Bank 0
Divider Chain Reset
6
5 4
RTC Control Register B (CRB)
7
6
5
4
3
0
0
0
0
2
1
0
Power-Up
Reset
0
Required
RTC Control
Register B
(CRB)
Index 0Bh
DSE
24 or 12 Hour Mode
DM
Unused
UIE
AIE
PIE
SET
1. The oscillator stops in this case only in the event
of a power failure.
FIGURE 4-4. CRB Register Bitmap
Bit 0 - Daylight Savings Enable (DSE)
Master reset does not affect this read/write bit.
0: Disables the daylight savings feature.
1: Enables daylight savings feature, as follows:
In the spring, time advances from 1:59:59 to
3:00:00 on the first Sunday in April.
In the fall, time returns from 1:59:59 to 1:00:00 on
the last Sunday in October.
Bit 7 - Update in Progress (UIP)
This read only bit is not affected by reset.
0: An update will not occur within the next 244 µsec.
Bit 7 (the SET bit) of Control Register B (CRB) is 1.
1: Timing registers are updated within 244 µsec.
Bit 1 - 24 or 12 Hour Mode
This is a read/write bit that is not affected by reset.
0: Enables 12 hour format.
1: Enables 24 hour format.
Bit 2 - Data Mode (DM)
This is a read/write bit that is not affected by reset.
0: Enables BCD format.
1: Enables binary format.
A
B
UIP bit of CRA
C
UF bit of CRC
D
PF bit of CRC
E
AF bit of CRC
A-B
D-C
C-E
Update In Progress (UIP) bit high before update occurs = 244 µsec
Periodic interrupt to update = Period (periodic int) / 2 + 244 µsec
Update to Alarm Interrupt = 30.5 µs
UIP
UF
PF
AF
Update In Progress status bit
Update-Ended Interrupt Flag (Update-Ended Interrupt if enabled)
Periodic Flag (Periodic Interrupt if enabled)
Alarm Flag (Alarm Interrupt if enabled)
Flags (and IRQ) are reset at the conclusion of Control Register C (CRC) read or by reset.
FIGURE 4-5. Interrupt/Status Timing
57
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THE RTC REGISTERS
4.2.2
TABLE 4-3. Divider Chain Control and Bank Selection
THE RTC REGISTERS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Bit 5 - Alarm Interrupt Flag (AF)
Master reset forces this read-only bit to 0.
0: No alarm was detected since the last read.
1: An alarm condition was detected. This bit is reset
to 0 when this register is read.
Bit 3 - Unused
This bit is defined as “Square Wave Enable” by the
MC146818 and is not supported by the RTC. This bit is
always read as 0.
Bit 4 - Update-Ended Interrupt Enable (UIE)
Master reset forces this read/write bit to 0.
0: Disables generation of the Update-Ended interrupt.
1: Enables generation of the Update-Ended interrupt.
This interrupt is generated at the time an update
occurs.
Bit 6 - Periodic Interrupt Flag (PF)
Master reset forces this read-only bit to 0. In addition,
this bit is reset to 0 when this register is read.
0: Indicates no transition occurred on the selected tap
since the last read.
1: A transition occurred on the selected tap of the divider chain.
Bit 5 - Alarm Interrupt Enable (AIE)
Master reset forces this read/write bit to 0.
0: Disables generation of the alarm interrupt.
1: Enables generation of the Alarm interrupt. The
alarm interrupt is generated immediately after a
time update in which the Seconds, Minutes, Hours
Day-of-month and Month time equal their respective alarm counterparts.
Bit 7 - Interrupt Request Flag (IRQF)
This read-only bit is the inverse of the value on the IRQ
output signal of the RTC/APC.
0: IRQ is inactive (high).
1: IRQ is active (low) and any of the following conditions exists: both PIE and PF are 1; both AIE and
AF are 1; both UIE and UF are 1. (PIE, AIE and
UIE are bits 6, 5 and 4, respectively of the CRB
register.)
Bit 6 - Periodic Interrupt Enable (PIE)
Master reset forces this read/write bit to 0.
0: Disables generation of the Periodic interrupt.
1: Enables generation of the Periodic interrupt. Bits 30 of Control Register A (CRA) determine the rate of
the Periodic interrupt.
4.2.4
This register indicates the validity of the RTC RAM data.
Bit 7 - Set Mode (SET)
Master reset does not affect this read/write bit.
0: The timing updates occur normally.
1: The user copy of time is “frozen”, allowing the time
registers to be accessed without regard for an occurrence of an update.
4.2.3
RTC Control Register D (CRD)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 Power-Up
Reset
0 Required
RTC Control Register C (CRC)
Reserved
This register indicates the status of interrupt request flags.
7
RTC Control
Register D
(CRD)
Index 0Dh
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0 Power-Up
Reset
0 Required
RTC Control
Register C
(CRC)
Index 0Ch
VRT
FIGURE 4-7. CRD Register Bitmap
Bits 6-0 - Reserved
These bits are reserved and always return 0.
Reserved
Bit 7 - Valid RAM and Time (VRT)
The VRT bit senses the voltage that feeds this logical
device (VCCH or VBAT) and indicates whether or not it
was too low since the last time this bit was read. If it was
too low, the RTC and RAM data are not valid.
This read-only bit is set to 1 when this register is read.
0: The voltage that feeds the APC/RTC logical device
was too low.
1: The RTC and RAM data are valid.
UF
AF
PF
IRQF
FIGURE 4-6. CRC Register Bitmap
Bits 3-0 - Reserved
These bits are reserved and always return 0000.
WARNING:
If VCCH ramps down at a rate exceeding 1 V/msec, it
may reset this bit.
Bit 4 - Update-Ended Interrupt Flag (UF)
Master reset forces this read-only bit to 0. In addition,
this bit is reset to 0 when this register is read.
0: No update has occurred since the last read.
1: Time registers have been updated.
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58
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Date-of-Month Alarm Register (DMAR
This register contains the Day-of-Month alarm setting and
its “don’t care” enable bits. Upon first power-up it is located
at Bank 1, Index 49h and is initialized to C0h.
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0 Power-Up
Reset
Required
This register can be relocated anywhere in bank 0 or bank
1. Its location is programmed via the Section 4.5.16 "Dayof-Month Alarm Address Register (DADDR)" on page 77.
Master Reset does not affect the Day-of-Month Alarm register.
7
6
5
4
3
2
1
1
1
0
0
0
0
0
Month Alarm
Register
(MAR)
Relocatable Index
in Bank0 or Bank1
Month
Alarm Bits
0
Date-of-Month Alarm
Register
0 Power-Up
Reset
(DMAR)
Required
Relocatable Index
in Bank0 or Bank1
“Don’t Care” control bits
FIGURE 4-9. MAR Register Bitmap
Bits 5-0 - Day-of-Month Alarm Bits
These read/write bits hold the month alarm value. These six
bits are set to the value of 0 upon first power-up, and are unaffected by system resets. The legal values for these six bits
are, 01 to 12 in BCD format, and 00 to 0C in binary format.
Other values may cause unpredictable results. The BCD or
Binary format is set by the DM bit of the CRB Register, as
explained in Section 4.2.2 "RTC Control Register B (CRB)"
on page 57.
Day-of-Month
Alarm Bits
“Don’t Care” control bits
FIGURE 4-8. DMAR Register Bitmap
Bits 5-0 - Date-of-Month Alarm Bits
Bits 7,6 - “Don’t Care” Control Bits
These read/write bits hold the Day-of-Month alarm value.
These six bits are set to the value of 0 upon first power-up,
and are unaffected by system resets. The legal values for
these six bits are, 00 to 31 in BCD format, and 00 to 1F in
binary format. Other values may cause unpredictable results. The BCD or Binary format is set by the DM bit, explained in Section 4.2.2 "RTC Control Register B (CRB)" on
page 57.
The Month Alarm is “Don’t Care” when bits 6 and 7 are set
to 11.
4.2.7
This register holds the century.
Upon first power on, the Century Register resides in Bank
1, Index 48h and holds 00h.This register can be relocated
anywhere in bank 0 or bank 1. Its location is programmed
via the CADDR Register, as described in Section 4.5.18
"Century Address Register (CADDR)" on page 77.
Bits 7,6 - “Don’t Care” Control Bits
The Day-of-Month Alarm is “Don’t Care” when bits 6 and 7
are set to 11.
4.2.6
Century Register (CR)
Master Reset does not affect this register.
Month Alarm Register (MAR)
This register contains the Month Alarm setting and its “don’t
care” enable bits.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Power-Up
Reset
Century
Register
(CR)
Required
Upon first power on, the Month Alarm register is located at
bank 1, Index 4Ah and is initialized to C0h. The default value is not guaranteed to any other location of the Month
Alarm Register.
Relocatable Index
in Bank0 or Bank1
This register can be relocated anywhere in bank 0 or bank
1. Its location is programmed via the MADDR Register, as
explained in Section 4.5.17 "Month Alarm Address Register
(MADDR)" on page 77.
Century
Bits
Master Reset does not affect the Month Alarm register.
FIGURE 4-10. MAR Register Bitmap
Bits 7 - 0
These read/write bits hold the century value.
4.3
APC OVERVIEW
Advanced Power Supply Control (APC) is implemented
within the RTC logical device. It enables the PC to power up
automatically in response to pre-programmed external
59
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APC OVERVIEW
4.2.5
APC OVERVIEW
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
ACPI Compliance
events, or to power down in an orderly, controlled manner.
The APC assumes the function of the physical power supply
On/Off switch, which is replaced by a momentary switch
that enables the user to signal requests for power-state
changes to the APC.
The PC87317 supports all the minimum requirements of the
ACPI spec (Rev 1.0):
The APC device is powered at all times that external AC
power or battery backup power are connected to the RTC
device. This is true even though the PC may be switched off
or disconnected from the external AC power outlet, in which
case the APC device is active but does not activate system
power. The APC device controls the power state of the entire PC system in response to various events (including the
power-on or power-off switch event).
The APC function produces four output signals:
the ONCTL signal - to activate the system power supply
●
the Power-Off-Request (POR) - an interrupt request
signal designed to enable software-controlled power
off activity
●
the SCI interrupt request - to comply with ACPI specifications for system power management.
●
The LED signal - to drive an external LED status indicator
Power Management Timer.
●
Power Button.
●
Real Time Clock Alarm.
●
Suspend modes via software emulation.
●
Plug-and-Play SCI.
The following optional features are also supported:
WARNING:
The APC device does not function if the 32.768 KHz oscillator is not running.
●
●
●
Global Lock mechanism.
●
General Purpose events.
●
Day-of-Month Alarm.
●
Century byte.
Several programmable General Purpose Power Managements events may be utilized to wake-up the system or to
generate interrupts, as listed in “General Purpose Power
Management Events” on page 68. The module includes a
Power Management timer that can generate interrupt requests.
TABLE 4-4 "APC Control and Status Register List" lists the
registers used for Automatic Power Supply Control (APC) in
the PC87317VUL.
ONCTL: The ONCTL signal is intended to activate or deactivate the system power supply.
TABLE 4-4. APC Control and Status Register List
The ONCTL’s value depends on the following:
Index
Mnemonic
Programmable parameter settings
40h
APCR1
APC Control Register 1
●
The system’s state when an external event occurs
41h
APCR2
APC Control Register 2
●
The state of the system’s power supply.
49h
APCR3
APC Control Register 3
4Ah
APCR4
APC Control Register 4
4Bh
APCR5
APC Control Register 5
4Ch
APCR6
APC Control Register 6
4Dh
APCR7
APC Control Register 7
42h
APSR
APC Status Register
4Eh
APSR1
APC Status Register 1
47h
RLR
4Fh
DADDR
Day-of-Month Alarm Address
Register
50h
MADDR
Month Alarm Address Register
51h
CADDR
Century Address Register
43h
WDW
Wake up Day of Week
44h
WDM
Wake up Date of Month
45h
WM
Wake up Month
46h
WY
Wake up Year
48h
WC
Wake up Century
●
External events
●
POR: The APC generates a Power-Off-Request (POR) (as
an interrupt request signal) in response to various “Power
Off events”, including the “Switch Off event” generated
when the power switch is manually toggled. This enables
various user-selectable choices of system response when
returning from a power Failure, or a software controlled exit
procedure (analogous to the autoexec.bat startup procedure in DOS operating systems) with automatic activation
of preprogrammed features such as system status backup,
system activity logging, file closing and backup, remote
communications termination, print completion, etc.
SCI: The APC meets ACPI requirements, with additional
optional features (see “ACPI Compliance” below). An SCI
interrupt is generated to send ACPI-relevant notifications to
the host operating system. (See “The SCI Signal” on page
69.)
LED: The APC supplies a programmable LED signal output
that may directly drive an external LED to indicate system
status under various power states (See TABLE 4-7 "LED
signal outputs" on page 68).
NOTE: The APC can distinguish between two events of the
same type if a minimum time of 2.5 periods of the 32Khz
clock passed between their arrivals. Thus, if the APC detects an event, and another event of the same nature occurs
once again in less than 70us from the previous event, the
APC might not detect the second event, i.e., the event will
be lost.
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Description
RAM Lock Register
The ACPI Fixed Registers include four groups of registers,
as listed below.
60
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Offset
Mnemonic
from triggering interrupt requests, and monitoring them via
the status bits.
The Offsets indicated in the ACPI Fixed Register list are the
address offset values to be added to the Base Address values, to obtain the real addresses of the registers. The Base
Addresses are user-defined, at the following locations:
Description
PM1 Event Registers (Status and Enable registers)
00h
PM1_STS_LOW PM 1 Status Low Byte Register
01h
PM1_STS_HIGH PM 1 Status High Byte Register
02h
PM1_EN_LOW
PM 1 Enable Low Byte Register
03h
PM1_EN_HIGH
PM 1 Enable High Byte Register
PM1 Event Registers (Status and Enable registers) base
address is located at the PM1 Event Base Address Bits 7-0
register and PM1 Event Base Address Bits 15-8 register of
the Power Management device (Logical Device 8).
PM1 Control Registers base address is located at the PM1
Control Base Address Bits 7-0 register and PM1 Control
Base Address Bits 15-8 register of the Power Management
device (Logical Device 8)
PM1 Control Registers
00h
PM1_CNT_LOW PM 1 Control Low Byte Register
01h
PM1_CNT_HIGH PM 1 Control High Byte Register
PM TImer Registers base address is located at the PM
Timer Base Address Bits 7-0 register and PM Timer Base
Address Bits 15-8 register of the Power Management device (Logical Device 8)
PM TImer Registers
00h
PM1_TMR_LOW PM Timer Low Byte Register
01h
PM1_TMR_MID
02h
PM1_TMR_HIGH PM Timer High Byte Register
03h
PM1_TMR_EXT PM Timer Extended Byte Register
General Purpose Event Registers base address is located at the General Purpose Status Base Address Bits 7-0
register and General Purpose Status Base Address Bits 158 register of the Power Management device (Logical Device
8)
PM Timer Middle Byte Register
User Selectable Parameters
General Purpose Event Registers
The APC function allows tailoring the system response to
power up, power down, power failure and battery operation
and other events.
00h
GP1_STS0
General Purpose 1 Status 0 Reg.
01h
GP1_STS1
General Purpose 1 Status 1 Reg.
02h
GP1_STS2
General Purpose 1 Status 2 Reg.
03h
GP1_STS3
General Purpose 1 Status 3 Reg.
04h
GP1_EN0
General Purpose 1 Enable 0 Reg.
05h
GP1_EN1
General Purpose 1 Enable 1 Reg.
06h
GP1_EN2
General Purpose 1 Enable 2 Reg.
07h
GP1_EN3
General Purpose 1 Enable 3 Reg.
08h
GP2_EN0
General Purpose 2 Enable 0 Reg.
09h0Bh
Reserved
0Ch
SMI_CMD
0Dh0Fh
Reserved
User-selectable parameters include:
●
Enabling various external events to wake up the system. See Section 4.4.2 "Entering Power States" on
page 65.
●
Wake-up time for an automatic system wake-up. See
“Predetermined Wake-Up” on page 68.
●
Type of system recovery after a Power Failure state.
See “The MOAP Bit” on page 62 and APCR6 bit 6 and
7 in “Bits 7,6 - Extended Wakeup options after Power
Failure.” on page 76.
●
Immediate or delayed Switch Off shutdown. See “The
SWITCH Input Signal” on page 67.
●
5 or 21 second time-out fail-safe shutdown. See “The
SWITCH Input Signal” on page 67.
●
LED signal response.
●
Mechanism for recognizing system power states. See
Section 4.3.2 "System Power Switching Logic" on
page 62.
●
Trigger characteristics for General Purpose events.
SMI Command Register
The Power Management events are user-controlled via the
PM1 Event Registers: the enable bits in these registers give
the user the ability to tailor system response by enabling or
disabling Power Management options, and monitoring them
via the status bits. (e.g. Power Button, Real-Time Clock
Alarm or Wake State enabling or monitoring).
4.3.1
System Power States
The system power state may be one of: No Power, Power
On, Power Off (suspended) or Power Failure. These states
are illustrated in FIGURE 4-11 "APC State Diagram" on
page 64. TABLE 4-6 "System Power States" on page 62 indicates the power-source combinations for each state. No
other power-source combinations are valid.
The PM Control registers enable control of system operation options (such as Power Button or Real-TIme CLock enabling, or reading Power Button override status).
The Power Management Timer registers house the values
of the Power Management Timer, which enables elapsedtime detection for power-state control.
In addition, the power sources and distribution for the entire
PC system are described in FIGURE 4-2 "PC87317VUL
Power Supplies" on page 55.
The General Purpose Event registers give the user control
over the General Purpose Power Management events: the
enable bits in these registers give the user the ability to tailor system response by enabling or disabling the events
WARNING:
It is illegal for VDD to be present when VCCH is absent.
61
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APC OVERVIEW
TABLE 4-5. ACPI Fixed Register List.
APC DETAILED DESCRIPTION
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
TABLE 4-6. System Power States
VDD
VCCH
VBAT
Power State
−
−
−
No Power
−
−
+
Power Failure
−
+
+ or -
Power Off
+
+
+ or -
Power On
+
−
+ or -
Illegal State
Knowing the system’s state is important for the correct detection of the Switch Events. The PC87317 distinguishes
between Power On and Power Off as follows:
VCCH exists and VDD does not implies Power Off.
If VBAT falls below 2V with VCCH absent, the oscillator, the
timekeeping functions and the APC all stop functioning.
If no external or battery-backup power is available, the system enters a No Power state. Upon leaving this state, the
system is initialized.
This state exists when no external or battery power is connected to the device. This condition will not occur once a
backup battery has been connected, except in the case of a
malfunction. The APC undergoes initialization only when
leaving this state.
4.4
APC DETAILED DESCRIPTION
4.4.1
The ONCTL Flip-Flop and Signal
The APC checks when activation or deactivation conditions
are met, and drives the ONCTL signal accordingly. This signal activates the system power supply. ONCTL is physically
generated as the output of the ONCTL set-reset flip-flop.
The state of the ONCTL flip-flop depends on the following:
Power On
This is the normal state when the PC is active. This state
may be initiated by various events in addition to the normal
physical switching on of the system. In this state, the PC
power supply is powered by external AC power and produces VDD and VCCH. The PC system and the PC87317VUL
device are powered by VDD, with the exception of the RTC
logical device, which is powered by VCCH.
Power Off (Suspended)
This is the normal state when the PC has been switched off
and is not required to be active, but is still connected to a
live external AC input power source. This state may be initiated directly or by software, and causes the PC system to
be powered down. The RTC logical device remains active,
powered by VCCH.
●
Presence of activation conditions
●
The status of the Mask ONCTL Activation (MOAP) bit
and APCR6 bits 6 and 7
●
Power source condition
●
The preceding state of ONCTL
The Preceding State of the ONCTL Signal
A power failure may occur when the system is active or inactive. The ONCTL flip-flop maintains the state of the
ONCTL signal at the time of the power failure. When power
is restored, the ONCTL signal returns the system to a state
determined by the saved status of ONCTL and the saved
value of the MOAP bit if this option is selected via APCR6
bits 6 and 7.
Power Failure
This state occurs when the external power source to the PC
stops supplying power, due to disconnection or power failure on the external AC input power source. The RTC continues to maintain timekeeping and RAM data under battery
power (VBAT), unless the oscillator stop bit was set in the
RTC. In this case, the oscillator stops functioning if the system goes to battery power, and timekeeping data becomes
invalid.
The MOAP Bit
The Mask ONCTL Activation in Power Failure (MOAP) bit
(bit 4 of APCR1) is controlled by software. It makes it possible to choose the desired system response upon return
from a power failure and decide whether the system remains inactive until it is manually switched on, or resumes
the state that prevailed at the time of the power failure, including enabling of “wake-up” events, as described in the
next section.
System Power Switching Logic
In the Power On state, the PC host is powered by the power-supply voltage VDD. From this state the system enters
the Power Off state if the conditions for this state occur (See
Section 4.4.3 on page 67), or the Power Failure state if external power is removed.
Logical Conditions that Define the Status of the ONCTL
Flip-Flop
The logical conditions described here set or reset the
ONCTL flip-flop. They reflect the events described in Section 4.4.3 on page 67.
In the Power Off state, the PC hosts does not receive power
from the system power supply, except for RTC and APC
which receive VCCH. The system may enter the Power On
state if the conditions for this state occur (see Section 4.4.3
on page 67), or the Power Failure state if external power is
removed.
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VDD exists implies power On
●
VDD must be at least VBAT +500 mvolt, to prevent the possibility of the APC entering the Power Failure state and
switching to battery power.
No Power
4.3.2
●
Conditions that put the ONCTL flip-flop in a 0 state (active
ONCTL signal):
62
●
Switch On event occurred.
●
RTC Alarm Status bit (bit 2 of PM1_STS_HIGH) and
RTC Alarm Enable bit (bit 2 of PM1_EN_HIGH)are set
●
Match Enable bit is 1 (APCR2 bit 0) and there is a
match between the real-time clock and the time specified in the pre-determined date and time registers.
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
●
The RING enable bit (bit 3 of APCR2) is 1 and one of
the following occurs:
— Bit 2 of APCR2 is 0, and a high-to-low transition is
detected on the RING input pin.
— Bit 2 of APCR2 is 1 and a train of pulses is detected
on the RING input pin.
●
RI1,2 Enable bits (bits 3 and 4 of APCR2) are 1 and a
high to low transition is detected on the RI1,2 input
pin(s).
●
Software On Command by asserting bit 7 of APCR2
●
PME1 Status bit (GP1_STS0 bit 0) and PME1 Enable
bit (GP1_EN0 bit 0) are set.
●
PME2 Status bit (GP1_STS0 bit 1) and PME2 Enable
bit (GP1_EN0 bit 1) are set.
●
IRRX1 Status bit (GP1_STS0 bit 2) and IRRX1 Enable
(GP1_EN0 bit 2) bit are set.
●
IRRX2 Status bit (GP1_STS0 bit 3) and IRRX2 Enable
(GP1_EN0 bit 3) bit are set.
●
GPIO10 Status bit (GP1_STS0 bit 6) and GPIO10 Enable bit (GP1_EN0 bit 6) are set.
●
The SWITCH pin is 0 for more than 3.95 seconds or 4
seconds. See detailed description above.
●
For the last 500 msec ONCTL is asserted but Vdd
does not exist. See detailed description above.
When bit 4 of APCR7 register is 0, ONCTL can be asserted
only after 1 second passed since it was deasserted. A wake
up event that happens during this 1 second, will activate the
ONCTL signal at the end of the 1 second. Off events are ignored during the 1 second period.
When bit 4 of APCR7 register is 1, ONCTL can be asserted
immediately after it was deasserted. (i.e., a wake-up event
can activate ONCTL immediately after ONCTL was deasserted.)
The tONH (see TABLE 14-69 "RING Trigger and ONCTL
Timing" on page 265) delay on power-up, when power returns after power failure, always occurs, regardless of bit 4
of APCR7 register.
Conditions that put the ONCTL flip-flop in a 1 state (inactive
ONCTL signal):
●
Switch Off Delay Enable bit is 0 and Switch Off event
occurred. (The Switch-Off event can inactivate ONCTL
only when SCI/POR bit is 0 - see PM1_CNT_LOW
register in the ACPI Fixed registers). The Power Button Enable bit has no effect - see PM1_EN_HIGH register in the ACPI Fixed registers.
●
Switch Off Delay Enable bit is 1 and Fail-safe Timer
reached terminal count. (The Failsafe Timer’s terminal
count can inactivate ONCTL only when SCI/POR bit is
0 - see PM1_CNT_LOW register in the ACPI Fixed
registers). The Power Button Enable bit has no effect see PM1_EN_HIGH register in the ACPI Fixed registers.
●
Software Off Command by asserting bit 5 of APCR1.
Power Override
When the debounced SWITCH is 0 and Vdd exists (both)
for more than 3.95 seconds or 4 seconds (the time is selected via bit 3 of the APCR7 register), ONCTL is deasserted
regardless of the Fail-safe Timer state. Once a power button override is detected, the ONCTL can be asserted again
only after Vdd does not exist.
For the last 500 msec ONCTL is asserted but Vdd does not
exist. This reset condition overrides any set condition of the
ONCTL flip-flop. This condition can reset the ONCTL flipflop, only if enabled via bit 4 of APCR7 register.
63
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APC DETAILED DESCRIPTION
When Activate and Inactivate conditions of the ONCTL flipflop occur at the same time, the Activate overrides the Inactivate. Exception to this are the following Inactivate conditions. They override any Activate condition that occurs at
the same time:
User software must ensure unused date/time fields are
coherent, to ensure the comparison of valid bits gives
the correct results.
APC DETAILED DESCRIPTION
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
VBAT
Power
Failure
T
BA
V
H∗
∗
CC
H
C
AT
AT
VB
∗ VB
V CCH
H
C
VC
V
A
V CCH
VC
APC Inactive
No
Power
VBAT
VCCH∗ VBAT
Power
On
A
Power
Off
Switch On Event
Switch Off Event or
Software Off Command
Pr
ming
ram
t
Prog
is no
APC
V DD
)
r if
CTL
occu
y ON
(can
d b
rolle
cont
C
AP
g
in
m
m
ra
og
APC Active
Initial Values
VCCH∗ VBAT
A
∗V
T
BA
CH
VC
nly
ent O
Power
On
Ev
h On
led W
ake
Off E
vent
witc
S
Enab
Power
Off
Up E
vent
Power
Off
1
VCCH∗ VBAT
V
CC
H∗
V
BA
2
∗V
V
T
BA
H
CC
T
3
4
APC Active
Programmed Values
Power
Failure
VCCH∗ VBAT
A
1
VCCH ∗ MOAP ∗ (Power Failure Bit = 0)
(can occur if VDD is not controlled by ONCTL)
2
VCCH ∗ ( (MOAP ∗ (APCR6 bits 7,6 = 0,0) ∗ (Power was On) ) or
(MOAP ∗ (APCR6 bits 7,6 = 0,0) ∗ (Time Match During Power Failure) ) or
( (APCR6 bits 7,6 = 1,0) ∗ (Time Match During Power Failure) ) )
3
VCCH ∗ ( (MOAP ∗ (APCR6 bits 7,6 = 0,0) ∗ (Power was Off) ) or
( (APCR6 bits 7,6 = 1,0) ∗ (No Time Match During Power Failure) ) or
(APCR6 bits 7,6 = 0,1) )
4
VCCH ∗ MOAP ∗ (APCR6 bits 7,6 = 0,0) ∗ (Power Failure Bit = 1)
FIGURE 4-11. APC State Diagram
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64
VCCH∗ VBAT
A
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
The PC87317 supports the Global Lock mechanism of the
ACPI. Thus, when bit 2 (status) and bit 3 (enable) of the
ACPI Support register are set to 1, POR is asserted (see
Power Management registers, Logical Device 8). This is the
ACPI Global Lock Release event. It is initiated by the ACPI
OS that writes a 1 to the ACPI Global Lock Release bit in
the PM1_CNT_LOW register (see Fixed ACPI registers).
Entering Power States
Power Up
When power is first applied to the RTC, (referred to as first
Power on) the APC registers are initialized to the default
values defined in the register descriptions. (See TABLE
4-22 "Bank 2 Registers - APC Memory Bank" on page 90).
This situation is defined by the appearance of VBAT or VCCH
with no previous power.
The system can enter suspend modes via software emulation. When bit 0 (status) and bit 1 (enable) of the ACPI Support register are set to 1, POR is asserted (see Power
Management registers, Logical Device 8). This is the Sleep
Enable event. It is initiated by the ACPI OS that writes a 1
to the Sleep Enable bit in the PM1_CNT_HIGH register (see
Fixed ACPI registers).
The APC powers up when the RTC supply is applied from
any source and is always in an active state. The RTC may
be powered up, but inactive; this occurs if bit 0 of the register at index 30h (see Section 2.3 "THE CONFIGURATION
REGISTERS" on page 29) of this logical device is not set.
In this situation, the APC registers are not accessible, since
they are only accessed via the RTC. This is also true of the
general-purpose battery-backed RAM.
The Power Button (Switch-Off Event) can assert the POR
pin, only when the SCI/POR bit is 0 (see PM1_CNT_LOW
register in the ACPI Fixed registers). It will assert the POR
pin, when a Switch-Off event is detected, regardless of the
Power Button Enable bit (see PM1_EN_HIGH register in
the ACPI Fixed registers).
Power Off Request (POR)
The APC allows a maskable or non-maskable interrupt on
the POR pin. This interrupt enables the user to perform an
orderly exit procedure, automatically performing housekeeping functions such as file backups, printout completion
and communications terminations, before powering down.
See FIGURE 4-12 "POR, SCI and ONCTL Generation" on
page 66.
When POR is in level mode (bit 2 of APCR1 register is 1), it
is asserted until the corresponding event’s status bit or enable bit is cleared. The exception to this is the Switch-Off
event. For that event, POR will be deasserted by the Level
POR Clear Command bit (bit 3 of the APCR1 register). Note
that if level events are configured, the POR must be configured to level mode. When any of the following events is enabled, POR must also be configured to level mode:
The POR signal can be asserted by the following events:
●
Power Button (Switch-Off Event).
●
Writes to the SMI Command register.
●
ACPI Global Lock Release.
●
●
Sleep Enable.
Write 1 to the ACPI Global Lock Release bit of the
PM1_CNT_LOW register
●
SMI Command.
●
●
PME1 Event.
Write 1 to the Sleep
PM1_CNT_HIGH register.
●
PME2 Event.
●
IRRX1 Event.
Power Failure
●
IRRX2 Event.
●
GPIO12 Event.
The APC is in a Power Failure state when it is powered by
VBAT, without VCCH.
●
GPIO13 Event.
Upon entering a Power Failure state, the following occurs:
●
GPIO10 Event.
●
All APC inputs are masked (high).
●
P12 Event.
●
These signals remain masked until one second after
exit from the Power Failure state, i.e., one second after
switching from VBAT to VCCH.
The ONCTL pin state is internally saved, and ONCTL is
forced inactive. System Recovery after Power Failure
Enable
bit
of
the
Upon Master Reset, the POR signal is in TRI-STATE.
An event will assert POR, only if its corresponding status
and enable bits are set.
Each of the events (PME1 to P12, in the list above) has a
corresponding status bit in the GP1_STS0 register. The
events can be enabled via two registers. When bit 0 of the
PM1_CNT_LOW register is 0, the events can be enabled
via their corresponding bit in the GP1_EN0 register. A bit in
the GP2_EN0 register can always enable its corresponding
event (All registers referred to in this paragraph are in the
ACPI Fixed registers).
The nature of the system recovery after power failure is set
by bits 6 and 7 of the APCR6 control register (See Section
4.5.13 "APC Control Register 6 (APCR6)" on page 75).
In all cases, the system can be switched on manually after
power returns.
Three selectable automatic options exist:
The PC87317 also supports the SMI Command of the ACPI. Thus, when bit 5 (status) and bit 6 (enable) of the ACPI
Support register are '1', POR is asserted (see Power Management registers, Logical Device 8). This is the SMI Command event. It is initiated by the ACPI OS that writes to the
SMI Command register.
65
●
the system response is controlled by the MOAP bit
●
the system remains inactive after power returns until
an enabled “wake-up” event occurs
●
the system is awakened when power returns by a new
enabled wake-up event, or by an enabled “match
event” that occurred while power was down.
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APC DETAILED DESCRIPTION
4.4.2
APC DETAILED DESCRIPTION
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
RTC Alarm
SCI
Generator
Power
Management
Timer
BIOS
Global Lock
Release
SMI
Command
ACPI
Global Lock
Release
POR
Generator
SLEEP
Enable
SELECT
rising/falling
high/low
GPIO 12,13
P12
SELECT
rising/falling
high/low
PME2,1
IRRX2,1
GPIO10
Restart
Fail-Safe
Timer
Stop
SWITCH
SWITCH
Event Type
VDD
EXISTS
RING
SWITCH OFF EVENT
SWITCH ON EVENT
ONCTL
Generator
Pulse/train
SELECT
MATCH
RI2,1
FIGURE 4-12. POR, SCI and ONCTL Generation
A "wake-up" event is any event that can activate the ONCTL
signal. The "wake-up" events are masked for one second
upon return from Power Failure, except the Match event
and the RTC Alarm event. These two events are not
masked but if they occur during Power Failure or during the
one second period after return from Power Failure, they will
assert ONCTL only at the end of that one second period.
One second after power returns, the ONCTL signal reverts to its saved state, if the MOAP bit is cleared to 0. If the
MOAP bit is set to 1, ONCTL remains inactive. If MOAP = 0
when the one second delay expires, new events can activate ONCTL, unless a time match occurs during Power Failure, in which case the APC “remembers” to activate ONCTL
at the end of the one second delay.
If the system is selected to respond to the MOAP bit value
(Mask ONCTL Activation in Power Failure, i.e., bit 4 of the
APCR1 register - see Section 4.5.1 "APC Control Register
1 (APCR1)" on page 70) via the APCR6 bit 6 and 7 settings,
the following occurs:
If the MOAP bit (bit 4 of APCR1) and the Power Failure
bit (bit 7 of APCR1) are both 1, then only the Switch On
event can activate ONCTL.
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66
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
When the Switch-Off Delay Enable bit is 1, occurrence of a
Switch-Off event will trigger a Fail-safe Timer countdown of
5 or 21 seconds. (Countdown length is set by bit 1 of the
APCR1 register. See Section 4.5.1 "APC Control Register
1 (APCR1)" on page 70.) If it is allowed to complete this
countdown (i.e., no reset or retrigger occurs while counting
down), the Fail-safe Timer sets the ONCTL signal high (inactive). This Fail-safe Timer countdown may also be triggered (or retriggered if a countdown is already in progress)
by writing a 1 to bit 0 of APCR1. Triggering sets the timer to
its initial countdown value and starts the countdown sequence. Switch-Off events occurring while a countdown is
in progress will not affect the countdown.
System Power-Up and Power-Off Activation
Event Description
The APC may activate the host power supply when the following “wake-up” events occur:
●
Physical On/Off switch is depressed and VDD is absent.
●
Preprogrammed wake-up time arrives.
●
Communications input is detected on a modem.
●
Ring signal is detected at a telephone input jack.
●
General Purpose Power Management wake-up event
occurs.
Switch-Off Event detection activates the Power-Off Request (POR) that triggers a user-defined interrupt routine to
conduct housekeeping activities prior to powering down.
(The user may also detect the Switch-Off Event by polling
the Switch-Off Detect bit, rather than by using the interrupt
routine). The user must ensure that the power-off routine
duration does not exceed the 5 or 21 second Switch-Off Delay. If required, a user routine may deactivate the countdown by setting the Fail-safe Timer Reset Command bit, (bit
6 of APCR1). Setting this bit will stop and reset the Fail-safe
Timer, thus preventing the fail-safe timer from causing power off before completion.
The PC may be powered down by the following events:
●
Physical On/Off switch is depressed with VDD present,
or depressed continuously for longer than 4 seconds.
●
Software controlled power down.
●
Fail-safe power down in the event of power-down software hang-up. (See “Switch-Off Event” below.)
●
ONCTL is active but VDD doesn’t exist for 500 ms
(See ONCTL description).
If the power-off routine gets “hung up”, and the timer was
not stopped and reset, then after the delay time has elapsed
the timer will conclude its countdown and activate power off
(deactivate ONCTL).
The SWITCH Input Signal
This signal provides two events: Switch On and Switch Off.
In both, the physical switch line is debounced, i.e., the signal state is transferred only after 14 to 16 msec without transitions, which ensures the switch is no longer bouncing. See
FIGURE 4-13.
The Fail-safe Timer is stopped, and reset, by writing 1 to the
Fail-safe Timer reset bit (bit 6 of APCR1). Switch-off events
detected while the timer is already counting are ignored. If,
VDD goes down while the Fail-safe Timer is counting, the
timer is stopped and reset, and ONCTL is not deactivated.
Switch-On Event - Detection of a high to low transition on
the debounced SWITCH input pin, when VDD does not
exist. The Switch-On event is masked (not detected) for
one to two seconds after VDD is removed.
The Switch-On event sets the Switch-On event detect
bit to 1 (bit 2 of APSR1).
POR may be asserted on a Switch-Off Event. It can be configured as either edge or level triggered, according to the
APCR1 register, bit 2. In edge mode, it is a negative pulse,
and in level mode it remains asserted until cleared by a level
POR Clear Command (bit 3 of the APCR1 register, see FIGURE 4-12 "POR, SCI and ONCTL Generation" on page
66). Selection of POR on the GPIO22/POR pin is via the SuperI/O Configuration 2 register (at index 22h). Selection of
the POR output buffer is via GPIO22 output buffer control
bits (Port 2 Output Type and Port 2 Pull-up Control registers). See TABLE 9-2 "The GPIO Registers, Bank 0" on
page 216.
Switch-Off Event - Detection of a high to low transition on
the debounced SWITCH input pin, when VDD exists.
The Switch-Off event sets the Switch-Off Event Detect
bit (bit 5 in APSR) to 1.
Switch-Off Delay - When the Switch-Off Delay Enable bit
(bit 6 in register APCR2) is 0, the Switch-Off event powers the system off immediately, i.e., the ONCTL output
pin is deactivated immediately.
VCCH
VDD
SWITCH
VDD Exists
Debounce
Switch-On Event
Falling
Edge
Detector
Edge or Trigger POR Select
APCR1 Register, Bit 2
Switch-Off Event
POR
Level POR Clear
APCR1 Register, Bit 3
FIGURE 4-13. Switch Event Detector
67
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APC DETAILED DESCRIPTION
4.4.3
APC DETAILED DESCRIPTION
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Predetermined Wake-Up
The following events may generate an interrupt if the system is in the Power On state:
The second, minute, and hour values of the pre-determined
wake-up times are contained in the Seconds Alarm, Minutes Alarm, and Hours alarm registers, respectively (indexes 01h, 03h and 05h of banks 0, 1 and 2). The Day-ofWeek, Day-of-Month, Month, Year and Century of the predetermined date are held in bank 2, registers indexes 43h46h and 48h. These eight registers are compared with the
corresponding Seconds, Minutes, Hours, Day-of-Week,
Day-of-Month, Month and Year, in all banks, register indexes 00, 02, 04, 06, 07, 08, 09 and the Century register which
can be located anywhere in bank 0 or bank 1 - its location
is programmed via the Century Address Register in bank 2.
(The Century bit value - bit 6 0f RTC Control Register d - is
not used for this function).
●
GPIO12 Event defined by bits 2-0 of the APCR6 register.
●
GPIO13 Event defined by bits 5-3 of the APCR6 register.
●
GPIO10 Event defined by bits 7-5 of the APCR3 register.
●
P12 Event defined by bits 2-0 of the APCR7 register.
Each of the events has a corresponding status bit in the
GP1_STS0 register. The events can be enabled via two
registers: GP1_EN0 register and GP2_EN0 register.
An event will wake up the system or generate an interrupt,
only if its corresponding status and enable bits are set.
LED Signal
Any Wake Up register in bank 2 (Index 43h-46h and 48h)
may be set to a "Don't Care" state by setting bits 7,6 to 11.
This results in periodic Match Event activation at an increased rate whose period is that of the Don’t Care location,
e.g., if the Wake Up Day-of-Week location and the Wake Up
Month are both set to a Don’t Care, a Match Event will be
activated once a month during the specified year.
This output signal enables an external LED to be driven directly by the PC87317, and may be programmed to give
various responses under various power conditions.
Three signal outputs may be selected:
●
High - Impedance (HI-Z)
●
Drive 0 level
●
a 1 hz “blink” signal, alternating between the previous
two outputs.
Ring Signal Event
An incoming telephone call is an event that may activate a
transfer from the Power-Off state to a Power-On state, in order to deal with the pending incoming voice, fax or modem
communication.
The High Impedance output will leave the LED unlit. The
Drive 0 value will switch on an external LED connected to
an external power source and grounded by the LED signal
output.
The PC87317VUL can detect a RING pulse falling edge or
a RING pulse train with a frequency of at least 16 Hz, that
lasts at least 0.19 seconds.
The outputs of this signal depend on programmed values
selected at bits 6 and 7 of APCR4, and on the prevailing
power state.
During RING pulse train detection, the existence of falling
edges on RING is monitored during time slots of 62.5 msec
(16 Hz cycle time). A RING pulse train detect event occurs
if falling edge(s) of RING were detected in three consecutive time slots, following a time slot in which no falling edge
of RING was detected.
Signal outputs under all conditions are listed in the following
table:
TABLE 4-7. LED signal outputs
This method of detecting a RING pulse train filters out (does
not detect) a RING pulse train of less then 11 Hz, might detect a RING pulse train of 11 Hz to 16 Hz, and guarantees
detection of a RING pulse train of at least 16 Hz.
APCR4
Bits
76
LED State
VCCH
VBAT only
RI1,2 Event
00
HI-Z
HI-Z
High to Low transitions on RI1 or RI2 indicate communications activity on the UART inputs, and these conditions may
be used as events to “wake-up” the system.
01
Drive 0
HI-Z
10
1 Hz blink
HI-Z
11
Reserved
HI-Z
General Purpose Power Management Events
The LED signal is functional, when VDD and VCCH exist or
when only VCCH exists. When only VBAT exists, the LED signal is not functional (output is set to HI-Z) but its control bits
are saved. Thus, when VCCH is applied again, the LED signal returns to the previous state. Upon first power-on (application of one of the voltages VBAT or VCCH when no
previous voltage was present), the LED signal is configured
to be in the high-impedance state. The One Hz blink requires a 32.768 KHz clock.
The APC supports additional events that can wake-up the
system from the power off state, or generate an interrupt if
the system is in the power on state.
An event is defined as the detection of falling edge, rising
edge, low level, or high level on a specific signal. Each signal’s event is configurable via software.
The following events may wake up the system from the
Power Off state, or generate an interrupt if the system is in
the Power On state:
●
PME1 Event defined by bits 2-0 of the APCR4 register.
●
PME2 Event defined by bits 5-3 of the APCR4 register.
●
IRRX1 Event defined by bits 2-0 of the APCR5 register.
●
IRRX2 Event defined by bits 5-3 of the APCR5 register.
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68
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
The SCI interrupt is used to send ACPI relevant notifications
to the host Operating System. The following events assert
the SCI signal:
RTC alarm
●
Power Button (Switch-Off event)
●
Timer Carry
●
BIOS Global Lock Release
ONCTL
POR
The following table summarizes the various events and
their connection to ONCTL, POR and SCI
●
●
PME1 Event
RTC Alarm
+
+
●
PME2 Event
Power Button
+
+
●
IRRX1 Event
IRRX2 Event
Power Management Timer
Carry
+
●
●
GPIO12 Event
BIOS Global Lock Release
+
●
GPIO13 Event
ACPI Global Lock Release
+
●
GPIO10 Event
Sleep Enable
+
●
P12 Event.
Power Management
Trigger Event
An event will assert SCI, only if its corresponding status and
enable bits are set. Exception to this is the Switch-Off event,
as explained below.
Each of the general purpose events (PME1 to P12, in the
list above) has a corresponding status bit in the GP1_STS0
register. When bit 0 of the PM1_CNT_LOW register is 1, the
events can be enabled via their corresponding bit in the
GP1_EN0 register.
The Timer status bit is in the PM1_STS_LOW register. It is
enabled via the PM1_EN_LOW register. The RTC alarm
status bit and the Power Button status bit are in the
PM1_STS_HIGH register. They are enabled via the
PM1_EN_HIGH register. Note that the Power Button status
bit holds two events: Switch-Off and Switch-On. Only the
Switch-Off event can assert SCI. The Switch-On events
have no effect. During the suspended state (defined in the
Wake Status bit of the PM1_STS_HIGH register), SwitchOff events always assert SCI, regardless of the Power Button Enable bit.
SCI
TABLE 4-8. Trigger Events for ONCTL, POR and SCI
+
PME2,1 Event
+
+
+
IRRX2,1 Event
+
+
+
GPIO10 Event
+
+
+
GPIO12/13 Events
+
+
P12 Event
+
+
SMI Command
+
Power Management Timer
The Power Management Timer is a 24-bit fixed rate running
count-up timer that runs off a 3.579545 MHz clock (derived
from the 14.31818 MHz clock input). Upon Master Reset,
the timer is disabled since its clock is disabled (bit 0 of the
PMC3 register, logical device 8). It is functional only when
VDD exists.
The Power Management Timer operates only if a 14.31818
MHz clock is fed via the X1 pin and the chip is configured to
work with the on-chip clock multiplier.
When bit 5 of the PM1_STS_LOW register and bit 5 of the
PM1_EN_LOW register are set to 1, SCI is asserted (see
the ACPI Fixed registers). This is the BIOS Global Lock Release event. It is initiated by the BIOS that writes a 1 to the
BIOS Global Lock Release bit in the ACPI Support register
(see Power Management registers, Logical Device 8).
When the most significant bit (bit #23) of the timer changes
from either high to low or low to high, the Timer status bit
(PM1_STS_LOW register) is set to 1. An SCI interrupt is
generated, when both the Timer status bit and the Timer enable bit (PM1_EN_LOW register) are set to 1.
SCI is a level interrupt. Its polarity is software programmable (see Section 2.4.7 "SuperI/O Configuration 3 Register
(SIOC3)" on page 39). It is asserted until the corresponding
event’s status bit are both set to 1. Exception to this is the
Switch-Off event during suspend mode that asserts (or
deasserts) SCI according to its status bit, regardless of its
enable bit.
The Power Management Timer can be read via four byte
registers,
placed
in
consecutive
addresses:
PM1_TMR_LOW, PM1_TMR_MID, PM1_TMR_HIGH and
PM1_TMR_EXT registers. For proper operation, the
PM1_TMR_LOW register should be placed on a doubleword boundary.
Upon Master Reset, the SCI signal is not configured to any
IRQ pin. At that time, SCI can be active due to the RTC
alarm or Switch-Off event.
Whenever the PM1_TMR_LOW register is read, the
PM1_TMR_LOW, PM1_TMR_MID and PM1_TMR_HIGH
registers are updated with the internal timer’s value. The
PM1_TMR_EXT register always reads 0. This scheme
guarantees that a coherent time is read.
The SCI signal can be routed (via software) to one of the following IRQ pins: IRQ1, IRQ3-IRQ12, IRQ14-IRQ15 (see
Section 2.4.7 "SuperI/O Configuration 3 Register (SIOC3)"
on page 39). Note that the SCI is a shareable interrupt, i.e.,
it can share the IRQ pin with another device (and the two interrupt sources can be enabled at the same time). The SCI
can share the IRQ pin with another device provided they are
configured in the same manner (e.g., both are configured as
4.5
APC REGISTERS
The APC registers reside in the APC bank 2 memory. The
RAM Lock register also resides in this bank. See TABLE
4-22 "Bank 2 Registers - APC Memory Bank" on page 90.
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APC REGISTERS
active high level interrupts). This IRQ pin should be configured as an open-drain output. It is the software’s responsibility to share the correct device with the SCI.
The SCI Signal
APC REGISTERS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
0: Ignored.
1: Fail-safe timer is stopped and reset.
The APC registers are not affected by Master Reset. They
are initialized to 0 only when power is applied for the first
time, i.e., application of one of the voltages VBAT or VCCH
when no previous voltage was present.
4.5.1
7
0
Bit 7 - Power Failure
Set to 1 when RTC/APC switches from VCCH to VBAT.
Cleared to 0 by writing 1 to this bit. Writing 0 to this bit
has no effect.
APC Control Register 1 (APCR1)
6
5
4
3
2
1
0
0
0
0
0
0
0
0 Power-Up
Reset
APC Control
Register 1
(APCR1)
Bank 2
Required
Index 40h
Failsafe Timer Trigger Cmd.
Switch Off Delay Option
POR Edge or Level Select
Level POR Clear Command
MOAP
SOC
Fail-safe Timer Reset Command
Power Failure
4.5.2
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0 Power-Up
Reset
Required
APC Control
Register 2
(APCR2)
Bank 2
Index 41h
TME
RSS
RPTDM
RE
R1E
R2E
SODE
Software On Command
FIGURE 4-14. APCR1 Register Bitmap
Bit 0 - Fail-safe Timer Trigger Command
This write-only bit returns 0 when read. Writing a 1 to
this bit resets the failsafe timer and triggers a 5 or 21
second countdown, as selected by bit 1 of this register.
0: Ignored.
1: 5 or 21 second failsafe countdown triggered.
FIGURE 4-15. APCR2 Register Bitmap
Bit 0 - Timer Match Enable (TME)
0: Pre-determined date or time event is ignored.
1: Match between the RTC and the pre-determined
date and time activates the ONCTL output signal.
See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for
an overriding case.
Bit 1 - Switch Off Delay Option
0: 5 seconds.
1: 21 seconds.
Bit 1 - RING Source Select (RSS)
0: RING source is RING/XDCS signal, regardless of
X-bus Data Buffer (XDB) select bit of SuperI/O
Configuration 1 register.
1: RING source is GPIO23/RING signal.
Bit 2 - POR Edge or Level Select
0: Edge POR.
1: Level POR. Once POR is asserted, it remains asserted until cleared by Level POR Clear Command
(bit 3).
Bit 2 - RING Pulse or Train Detection Mode (RPTDM)
0: Detection of RING pulse falling edge.
1: Detection of RING pulse train above 16 Hz for 0.19
sec.
Bit 3 - Level POR Clear Command
This is a write-only non-sticky bit. Read returns 0.
0: Ignored.
1: POR output signal is deactivated.
Bit 3 - RING Enable (RE)
0: RING input signal is ignored.
1: RING detection activates the ONCTL output signal,
unless it is overridden by the MOAP bit, bit 4 of the
APCR1 register and bits 6,7 0f APCR6.
Bit 4 - Mask ONCTL Activation if Power Fail (MOAP)
The function of this bit is enabled by extended wakeup
options settings in APCR6, bits 6 and 7.
0: When power returns and APCR6 bit 6 and 7 are
00, sets the system to the power state that existed
when power failed.
1: While the Power Failure bit (bit 7 of APCR1) is set,
mask ONCTL activation, except as a result of a
Switch On Event.
Bit 4 - RI1 Enable (R1E)
0: RI1 input signal is ignored.
1: A high to low transition on the RI1 input pin activates the ONCTL output pin.
See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for
an overriding case.
Bit 5 - Software Off Command (SOC)
This bit is write-only and non-sticky. Read returns 0.
0: Ignored.
1: ONCTL output signal is deactivated.
Bit 5 - RI2 Enable (R2E)
0: RI2 input signal is ignored.
1: A high to low transition on the RI2 input pin activates the ONCTL output pin.
Bit 6 - Fail-safe Timer Reset Command
This bit is write-only and non-sticky. Read returns 0.
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APC Control Register 2 (APCR2)
70
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Bit 6 - Switch Off Delay Enable (SODE)
0: ONCTL output pin is deactivated immediately after
the Switch Off event.
1: After the Switch Off event, ONCTL output signal is
deactivated after the 5 or 21 seconds Switch Off
delay.
Bit 6 - Reserved
Bit 7 - RING Status Bit (RS)
Holds the instantaneous value of the selected RING pin.
4.5.4
Bit 7 - Software On Command
This bit is write-only and non-sticky. Read returns 0.
0: Ignored
1: ONCTL output signal is activated.
4.5.3
This register contains the Wake up Day of Week settings.
APC Status Register (APSR)
Bits 5-0 in this register are cleared to 0, when this register
is read.
7
6
5
4
3
2
1
0
0
0
0
0
0
Power-Up
1 Reset
Required
Wake up Day of Week Register (WDWR)
APC Status
Register
(APSR)
Bank 2,
Index 42h
7
6
5
4
3
2
1
1
0
0
0
0
Wake up Day of Week Register
1 0
(WDWR)
Bank 2
0 0 Power-Up
Reset
Index 43h
Required
Wake up Day-of-Week Bits
TMD
RID
RI1 Detect
RI2 Detect
FTD
SOED
Reserved
“Don’t Care” control bits
FIGURE 4-17. WDWR Register Bitmap
Bits 5-0 Wake up Day of Week Bits
These bits contain the day of week setting. Values may
be 01 to 07 in BCD format or 01 to 07 in Binary format.,
where sunday = 01. See “Predetermined Wake-Up” on
page 68.
RS
FIGURE 4-16. APSR Register Bitmap
Bit 0 - Timer Match Detect (TMD)
This bit is set to 1 when the RTC reaches the pre-determined date, regardless of the Timer Match Enable bit
(bit 0 of APCR2). After first Power-Up, the RTC and the
pre-determined date, are 0 and so this bit is set. It is recommended to clear this bit by reading this register after
first Power-Up.
Bits 7,6 - Don’t Care control bits
When both bits are set to 11, these bits set the Wake up Day
of Week field to a “don’t care” state
Bit 1 - RING Detect (RID)
This bit is set to 1 when a high to low transition is detected on the RING input pin and bit 2 of APCR2 is 0, or
when a RING pulse train is detected on the RING input
pin and bit 2 of APCR2 is 1, regardless of the status of
the RING enable bit.
Bit 2 - RI1 Detect
This bit is set to 1 when a high to low transition is detected on the RI1 input signal, regardless of the RI1 Enable
bit.
Bit 3 - RI2 Detect
This bit is set to 1 when a high to low transition is detected on the RI2 input pin, regardless of the RI2 Enable bit.
Bit 4 - Fail-Safe Timer Detect (FTD)
This bit is set to 1 when the Fail-safe timer reaches terminal count.
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APC REGISTERS
Bit 5 - Switch Off Event Detect (SOED)
This bit is set to 1 when a Switch Off event is detected,
regardless of the Switch Off Delay Enable bit.
See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for
an overriding case.
APC REGISTERS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
4.5.5
Wake up Date of Month Register (WDMR)
This register contains the Wake up Date of Month settings.
7
6
5
4
3
2
1
1
1
0
0
0
0
0
Wake up Date-of-Month
Register
0
(WDMR)
0 Power-Up
Reset
Bank 2
Index 44h
Required
7
6
5
4
3
2
1
1
1
0
0
0
0
0
Wake up Year
Register
(WYR)
0 Power-Up
Reset
Bank 2
Index 46h
Required
0
Wake up Year Bits
Wake up Date of Month Bits
“Don’t Care” control bits
FIGURE 4-20. WYR Register Bitmap
“Don’t Care” control bits
Bits 5-0 - Wake up Year Bits
FIGURE 4-18. WDMR Register Bitmap
These bits contain the Year setting. Values may be 01
to 99 in BCD format or 01 to 63 in Binary format. See “Predetermined Wake-Up” on page 68.
Bits 5-0 Wake up Date of Month Bits
These bits contain the Date of Month setting. Values
may be 01 to 31 in BCD format or 01 to 1F in Binary format.
See “Predetermined Wake-Up” on page 68.
Bits 7,6 - Don’t Care control bits
When both bits are set to 11, these bits set the Wake up
Year field to a “don’t care” state.
Bits 7,6 - Don’t Care control bits
When both bits are set to 11, these bits set the Wake up
Date of Month field to a “don’t care” state
4.5.6
4.5.8
Once a non-reserved bit is set to 1 it can be cleared only by
hardware (MR pin) reset.
Wake up Month Register (WMR)
This register contains the Wake up Month settings.
7
6
5
4
3
2
1
1
1
0
0
0
0
0
RAM Lock Register (RLR)
Wake up Month
Register
Power-Up
(WMR)
0
Reset
Bank 2
Index 45h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0 Power-Up
Reset
0
Required
0
RAM Lock
Register
(RLR)
Bank 2,
Index 47h
Reserved
Reserved
Reserved
Upper RAM Block
RAM Block Read
RAM Block Write
RAM Mask Write
RAM Lock
Wake up Month Bits
FIGURE 4-21. RLR Register Bitmap
“Don’t Care” control bits
Bit 2-0 - Reserved
FIGURE 4-19. WMR Register Bitmap
Bit 3 - Upper RAM Block
Controls access to the upper 128 RAM bytes, accessed
via the Upper RAM Address and Data Ports of bank 1
0: This bit has no effect on upper RAM access.
1: Upper RAM Data Port of bank 1 is blocked: writes
are ignored and reads return FFh.
Bits 5-0 Wake up Month Bits
These bits contain the Month setting. Values may be 01
to 12 in BCD format or 01 to 0C in Binary format. See “Predetermined Wake-Up” on page 68.
Bits 7,6 - Don’t Care control bits
Bit 4 - RAM Block Read
This bit controls reads from RAM bytes 80h-9Fh (00h1Fh of upper RAM).
0: This bit has no effect on upper RAM access.
1: Reads from bytes 00h-1Fh of upper RAM return
FFh.
When both bits are set to 11, these bits set the Wake up
Month field to a “don’t care” state
4.5.7
Wake up Year Register (WYR)
This register contains the Wake up Year settings.
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72
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
7
1
Bit 6 - RAM Mask Write
This bit controls writes to all RTC RAM.
0: This bit has no effect on RAM access.
1: Writes to bank 0 RAM and to upper RAM are ignored.
5
4
3
2
1
1
1
0
0
0
0
0
3
0
2
0
1
0
0
0 Power-Up
Reset
APC Control
Register 3
(APCR3)
Bank 2,
Required
Index 49h
PME1 or GPIO16 select
PME2 or GPIO15 select
LED or CS0 select
GPIO24 or IRRX1 select
GPIO37 or IRRX2/IRSL0/ID0 Select
Bit 0 - PME1 or GPIO16 Pin Select
This bit selects PME1 or GPIO16 to be connected to I/O
pin.
When PME1 is not selected, its enable bit (bit 0 of
GP1_EN) should be cleared to 0.
0: GPIO16 selected.
1: PME1 selected.
Wake up Century Register (WCR)
6
4
0
FIGURE 4-23. APCR3 Register Bitmap
This register contains the Wake up Century settings.
7
5
1
GPIO10 Event Polarity/Edge select
Bit 7 - RAM Lock
0: This bit has no effect on RAM access.
1: Read and write to locations 38h-3Fh of all banks
are blocked. Writes are ignored, and reads return
FFh.
4.5.9
6
0
Wake up Century
Register
(WCR)
0 Power-Up
Reset
Bank 2
Index 48h
Required
0
Bit 1 - PME2 or GPIO15 pin select
This bit selects PME2 or GPIO15 to be connected to I/O
pin.
When PME2 is not selected, its enable bit (bit 1 of
GP1_EN) should be cleared to 0.
0: GPIO15 selected.
1: PME2 selected.
Wake up Century Bits
Bit 2 - LED or CS0 Pin select
This bit selects LED or CS0 to be connected to I/O pin.
0: CS0 selected.
1: LED selected.
“Don’t Care” control bits
FIGURE 4-22. WCR Register Bitmap
Bit 3 - GPIO24 or IRRX1 Pin Select
This bit selects GPIO24 or IRRX1 to be connected to I/O
pin.
When IRRX1 is not selected, its enable bit (bit 2 of
GP1_EN) must be cleared to 0.
0: IRRX1 selected.
1: GPIO24 selected.
Bits 5-0 Wake up Century Bits
These bits contain the Century setting. Values may be
01 to 99 in BCD format or 01 to 63 in Binary format. See
“Predetermined Wake-Up” on page 68.
Bits 7,6 - Don’t Care control bits
When both bits are set to 11, these bits set the Wake up
Century field to a “don’t care” state
Bit 4 - GPIO37 or IRRX2/IRSL0/ID0 Pin Select
This bit selects GPIO37 or IRRX2/IRSL0/ID0 to be connected to I/O pin. Selection between IRRX2/IRSL0/ID0
is described in the UART2 registers (device 5).
When IRRX2 is not selected, its enable bit must be
cleared to 0.
0: IRRX2/IRSL0/ID0 selected.
1: GPIO37 selected.
4.5.10 APC Control Register 3 (APCR3)
This register defines device I/O pin designations, and
GPIO10 event polarity/edge settings.
This register in not affected by Master reset. Upon first Power-Up, it is initialized to A0h.
Bits 7-5 - GPIO10 Event Polarity/Edge Select
These bits determine the physical conditions that trigger the GPIO10 General Purpose Event.
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APC REGISTERS
Bit 5 - RAM Block Write
This bit controls writes to bytes 80h-9Fh (00h-1Fh of upper RAM).
0: This bit has no effect on upper RAM access.
1: Writes to bytes 00h-1Fh of upper RAM are ignored.
APC REGISTERS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
TABLE 4-10. PME1 Event settings select
TABLE 4-9. GPIO10 Event settings select
APCR3 bits
765
APCR4 bits
Physical trigger condition
210
000
Low level
000
Low level
001
High level
001
High level
010
010
011
Reserved
011
100
101
Falling Edge
101
Falling Edge
110
Rising Edge
110
Rising Edge
111
Falling or Rising Edge
111
Falling or Rising Edge
Bits 5-3 - PME2 Event Polarity/Edge Select
These bits determine the physical conditions that trigger
the PME2 Power Management Event.
These bits are unaffected by Master Reset.
This register configures the LED output signal operational
mode and PME2,1 event polarity/edge settings.
Upon first Power-Up, this register is initialized to 2Dh. The
bit settings are unaffected by Master Reset.
TABLE 4-11. PME2 Event settings select
APCR4 bits
6
0
5
1
Reserved
100
4.5.11 APC Control Register 4 (APCR4), Bank 2, Index
4Ah
7
0
Physical trigger condition
4
0
3
1
2
1
1
0
0
1 Power-Up
Reset
Required
APC Control
Register 4
(APCR4)
Bank 2,
Index 4Ah
543
Physical trigger condition
000
Low level
001
High level
010
PME1 Event Polarity/Edge select
011
Reserved
100
PME2 Event Polarity/Edge select
101
Falling Edge
LED configuration
110
Rising Edge
FIGURE 4-24. APCR4 Register Bitmap
111
Falling or Rising Edge
Bits 7,6 - LED Configuration
These bits determine the LED output signal.
Bits 2-0 - PME1 Event Polarity/Edge Select
These bits determine the physical conditions that trigger
the PME1 Power Management Event.
These bits are unaffected by Master Reset.
TABLE 4-12. LED Configuration settings
APCR4 bits
LED output
76
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74
00
High Impedance
01
Drive 0
10
One Hz blink
11
Reserved
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
APCR5 bits
This register contains the IRRX2,1 event polarity/edge settings and configures I/O pin designations.
543
Upon first Power-Up this register is reset to 2Dh. The bit settings are unaffected by Master Reset.
7
0
6
0
5
1
4
0
3
1
2
1
1
0
0
1 Power-Up
Reset
Required
APC Control
Register 5
(APCR5)
Bank 2,
Index 4Bh
Physical trigger condition
101
Falling Edge
110
Rising Edge
111
Falling or Rising Edge
Bit 6 - GPIO33 or RI2 Pin select
This pin routes signal GPIO33 or RI2 to I/O pin.
0: RI2 selected
IRRX1 Event Polarity/Edge select
1: GPIO33 selected
Bit 7 - Reserved
IRRX2 Event Polarity/Edge select
GPIO33 or RI2 select
Reserved
4.5.13 APC Control Register 6 (APCR6)
This register contains the GPIO13,12 event polarity/edge
settings and setting for extended wakeup options after power failure.
FIGURE 4-25. APCR5 Register Bitmap
Upon first Power-Up this register is reset to 2Dh. The bit settings are unaffected by Master Reset.
Bits 2-0 - IRRX1 Event Polarity/Edge Select
These bits determine the physical conditions that trigger the IRRX1 Event.
These bits are unaffected by Master Reset.
7
0
6
0
5
1
4
0
3
1
2
1
TABLE 4-13. IRRX1 Event settings select
APCR5 bits
210
Low level
001
High level
APC Control
Register 6
(APCR6)
Bank 2,
Index 4Ch
GPIO12 Event Polarity/Edge
select
GPIO13 Event Polarity/Edge select
010
011
0
1 Power-Up
Reset
Required
Physical trigger condition
000
1
0
Extended wake-up options after Power failure
Reserved
FIGURE 4-26. APCR6 Register Bitmap
100
101
Falling Edge
110
Rising Edge
111
Falling or Rising Edge
Bits 2-0 - GPIO12 Event Polarity/Edge Select
These bits determine the physical conditions that trigger the GPIO12 Event.
These bits are unaffected by Master Reset.
TABLE 4-15. GPIO12 Event settings select
Bits 5-3 - IRRX2 Event Polarity/Edge Select
These bits determine the physical conditions that trigger
the IRRX2 Event.
These bits are unaffected by Master Reset.
APCR6 bits
210
TABLE 4-14. IRRX2 Event settings select
APCR5 bits
543
Low level
001
High level
011
Low level
001
High level
Reserved
100
010
011
000
010
Physical trigger condition
000
Physical trigger condition
Reserved
101
Falling Edge
110
Rising Edge
111
Falling or Rising Edge
100
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APC REGISTERS
4.5.12 APC Control Register 5 (APCR5)
APC REGISTERS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Bits 5-3 -GPIO13 Event Polarity/Edge Select
These bits determine the physical conditions that trigger
the GPIO13 Event.
These bits are unaffected by Master Reset.
7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
1 Power-Up
Reset
Required
TABLE 4-16. GPIO13 Event settings select
APCR6 bits
543
P12 Event Polarity/Edge select
PWRBTNOR
Power Supply Protect Mode
Physical trigger condition
000
Low level
001
High level
APC Control
Register 7
(APCR7)
Bank 2,
Index 4Dh
Reserved
010
011
FIGURE 4-27. APCR7 Register Bitmap
Reserved
100
101
Falling Edge
110
Rising Edge
111
Falling or Rising Edge
Bits 2-0 - P12 Event Polarity/Edge Select
These bits determine the physical conditions that trigger
the P12 event.
Note that P12 is multiplexed with the CS0. In any case,
it is the internal P12 port’s output that is detected.
TABLE 4-18. P12 Event settings select
Bits 7,6 - Extended Wakeup options after Power Failure.
These bits determine the system wake-up behavior after return from Power failure, as follows:
APCR7 bits
210
TABLE 4-17. Extended Wake-up Option settings
APCR6
Bits
Wake up Option
01
While the Power Failure bit (bit 7, APCR1) is
set, mask ONCTL activation except if a new
enabled event occurs after power returns.
11
Low level
001
High level
011
The MOAP bit (bit 4, APCR1) determines
system response upon return from power failure
10
000
010
76
00
if a MATCH event occurred during power
failure
●
if a new enabled event occurs after power
returns
101
Falling Edge
110
Rising Edge
111
Falling or Rising Edge
Bit 3 - Power Button Override Time Select
(PWRBTNOR)
This bit selects the Power Button Override time.
0: 4 seconds override time select.
1: 3.95 seconds override time select
Reserved
Bit 4 - Power Supply Protect Mode
0: ONCTL can be asserted only after 1 second
passed since it was deasserted.
When for the last 500 msec ONCTL is asserted but
Vdd does not exist, ONCTL is deasserted.
1: ONCTL can be asserted immediately after it was
deasserted.
The case in which Vdd does not exist for 500 msec
has no affect on ONCTL.
4.5.14 APC Control Register 7 (APCR7)
This register contains the P12 event polarity/edge settings,
the Power Button Override time and the Power Supply Protect Mode bit.
Upon first Power-Up this register is reset to 05h. The bit settings are unaffected by Master Reset.
Bits 7-5 - Reserved
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Reserved
100
While the Power Failure bit (bit 7, APCR1) is
set, mask ONCTL activation except:
●
Physical trigger condition
76
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Upon first power on, it is initialized to C9h.
This is read-only register. The bit settings are unaffected by
Master Reset.
4.5.17 Month Alarm Address Register (MADDR)
7
6
5
4
3
2
1
0
0
Power-Up
X Reset
This register defines the Month Alarm register location. The
bit settings are unaffected by Master Reset.
APC Status
Register 1
(APSR1)
Bank 2,
Required
Index 4Eh
SWITCH pin status
Switch-On Event detect
7
6
5
4
3
2
1
1
1
0
0
1
0
1
Month Alarm Address
Register
0 Power-Up
(MADDR)
Reset
Bank 2
Required
Index 50h
0
Month
Alarm Address
Reserved
FIGURE 4-28. APSR1 Register Bitmap
Bank Select
Bit 0 - Switch Pin Status
This bit is holds the value of the SWITCH pin (before the
debouncer).
FIGURE 4-30. MADDR Register Bitmap
Bits 6-0 - Offset Address of the Month Alarm Register
Bit 0 is the least significant bit of the address.
Bit 1 - Switch On event Detect
This bit is set to 1 when a Switch On event is detected,
regardless of the Power Button Enable bit (See “Bit 0 Power Button Enable (PWRBTN_EN)” on page 79). It is
cleared to 0 when the register is read.
Bit 7 - Bank Select
0: Bank 0.
1: Bank 1.
Upon first power on, it is initialized to CAh.
Bits 7-2 - Reserved
4.5.18 Century Address Register (CADDR)
This register defines the Century register location. The bit
settings are unaffected by Master Reset.
4.5.16 Day-of-Month Alarm Address Register
(DADDR)
This register defines the Day-of-Month Alarm register location. The bit settings are unaffected by Master Reset.
7
6
5
4
3
2
1
1
0
0
1
0
Day-of-Month Alarm Address
Register
1 0
(DADDR)
0 1 Power-Up
Bank 2
Reset
Index 4Fh
Required
7
6
5
4
3
2
1
1
1
0
0
1
0
0
Century Address
Register
(CADDR)
Power-Up
0
Bank 2
Reset
Index 51h
Required
0
Century Address
Day-of-Month
Alarm Address
Bank Select
FIGURE 4-31. CADDR Register Bitmap
Bank Select
Bits 6-0 - Offset Address of the Century Register
FIGURE 4-29. DADDR Register Bitmap
Bit 0 is the least significant bit of the address.
Bits 6-0 - Offset Address of the Day-of-Month Alarm
Register
Bit 7 - Bank Select
0: Bank 0.
1: Bank 1.
Upon first power on, it is initialized to C8h.
Bit 0 is the least significant bit of the address.
Bit 7 - Bank Select
0: Bank 0.
1: Bank 1.
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APC REGISTERS
4.5.15 APC Status Register 1 (APSR1)
ACPI FIXED REGISTERS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
4.6
POWER MANAGEMENT REGISTERS
ACPI FIXED REGISTERS
The APCI fixed registers are divided into four groups:
●
PM1 Event registers
●
PM1 Control registers
●
PM TImer registers
●
General Purpose Event registers
4.6.2
Power Management 1 Status High Byte
Register (PM1_STS_HIGH)
All implemented bits are “sticky” bits: they are set to 1 by a
hardware event, and are reset to 0 only by software writing
a 1 to the bit location.Reserved bits are read-only, and will
always return 0. Set overrides reset.
These registers, their base address locations and their address offsets are listed in TABLE 4-5 "ACPI Fixed Register
List." on page 61. These registers are accessed using their
base address and the offset from the base address.
The APCI Fixed registers are reset to 0 upon first Power Up,
and are unaffected by Master Reset (unless specifically
mentioned otherwise).
7
6
5
4
3
0
0
0
0
0
Required
Access to these registers is disabled by default and must be
enabled via FER2 (see Section 10.2.4 on page 219). The
access is not controlled by the Active register (Index 30h) of
Logical Device 2 (RTC/APC) or by the Active register (Index
30h) of Logical Device 8 (Power Management).
PWRBTN_STS
Reserved
RTC_STS
PWRBTNOR_STS
PM1 EVENT REGISTERS
4.6.1
Reserved
Power Management 1 Status Low Byte Register
(PM1_STS_LOW)
WAK_STS
FIGURE 4-33. PM1_STS_HIGH Register Bitmap
All implemented bits are “sticky” bits: they are set to 1 by a
hardware event, and are reset to 0 only by software writing
a 1 to the bit location. (Set overrides reset in the event of
conflict).
Bit 0 - Power Button Status (PWRBTN_STS)
This bit is set to 1 when a high to low transition is detected on the SWITCH, regardless of the Power Button Enable bit (bit 0 of the PM1_EN_HIGH register). This bit
may be cleared to 0 by either software (as described
above) or by hardware, when the SWITCH input signal
is 0 for over 3.95 or 4 seconds (as selected by bit 3 of
APCR7). A high to low transition on the SWITCH input
pin that occurs while the Power Button Status bit is being cleared by software may be lost. The SWITCH state
is detected after the debouncer.
Reserved bits are read-only, and will always return 0.
7
6
5
4
3
2
0
0
0
0
0
0
Power Management 1 Status
High Byte Register
2 1 0
(PM1_STS_HIGH)
Power-Up
Offset 01h
X 0 0 Reset
Power Management 1 Status
0
Low Byte Register
Power-Up
0 0 Reset
(PM1_STS_LOW)
Required
Offset 00h
1
Bit 1- Reserved
TMR_STS
Bit 2 - Real Time Clock Status (RTC_STS)
This bit is set to 1 when the real time clock detects an
alarm condition (even if bit 5 of the RTC Control Register C is already set to 1). It is set to 1 regardless of the
Real Time Clock Enable bit (bit 2 of PM1_EN_HIGH
register). It is reset by software, as described above.
Upon first power up, this bit may be 1
Reserved
GBL_STS
Reserved
FIGURE 4-32. PM1_STS_LOW Register Bitmap
Bit 3 - Power Button Override Status
(PWRBTNOR_STS)
This bit is set to 1 when the SWITCH input pin is 0 for
over 3.95 or 4 seconds (as selected by bit 3 of APCR7),
i.e., when the user presses the power button for more
than 3.95 o r4 seconds. The SWITCH state is detected
after the debouncer.
Bit 0 - Timer Status (TMR_STS)
This bit is set to 1 when the most significant bit of the
Power Management Timer (bit 23 - See
PM1_TMR_HIGH) changes from low to high or from
high to low.
Bits 4-1 - Reserved
Bit 6-4 - Reserved
Bit 5 - Global Lock Status (GBL_STS)
This bit is set to 1 when a 1 is written to the BIOS Global
Lock Release bit (See ACPI Support register, Power
Management registers, in Logical device 8).
Bits 7-6 - Reserved
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
4.6.3
Reserved bits are read-only, and will always return 0.
5
4
3
2
0
0
0
0
0
0
6
5
4
3
0
0
0
0
Reserved
FIGURE 4-35. PM1_EN_HIGH Register Bitmap
Bit 0 - Power Button Enable (PWRBTN_EN)
This pin is reset to 0 upon Master Reset.
0: Power Button Status bit is ignored (bit 0 of
PM1_STS_HIGH)
1: Activate the SCI pin when the Power Button Status
bit is set to 1.
Reserved bits are read-only. Read returns 0.
6
7
0
Power Management 1 Enable
High Byte Register
2 1 0 Power-Up
Reset (PM1_EN_HIGH)
0 0 0
Offset 03h
Required
PWRBTN_EN
Reserved
RTC_EN
Power Management 1 Enable Low Byte
Register (PM1_EN_LOW)
7
Power Management 1 Enable High Byte
Register (PM1_EN_HIGH)
Power Management 1 Enable
Low Byte Register
0
Power-Up
0 0 Reset
(PM1_EN_LOW)
Offset 02h
Required
1
Bit 1 - Reserved
TMR_EN
Bit 2 - Real Time Clock Alarm Enable (RTC_EN)
0: Real Time Clock Alarm status bit is ignored (bit 2 of
PM1_STS_HIGH)
1: Activate the ONCTL pin and the SCI signal when
the Real Time Clock Status bit is set to 1.
Reserved
GBL_EN
Bits 7-3 - Reserved
Reserved
FIGURE 4-34. PM1_EN_LOW Register Bitmap
Bit 0 - Timer Enable (TMR_EN)
This pin is reset to 0 upon Master Reset.
0: Timer Status bit is ignored (bit 0 of the
PM1_STS_LOW register)
1: Activate the SCI signal, when the Timer Status bit
is set to 1.
Bits 4-1 - Reserved
Bit 5 - Global Lock Enable (GBL_EN)
This pin is reset to 0 upon Master Reset.
0: Global Lock Status bit is ignored (bit 5 of the
PM1_STS_LOW register)
1: Activate the SCI signal, when the Global Lock Status bit is set to 1.
Bits 7-6 - Reserved
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ACPI FIXED REGISTERS
4.6.4
Bit 7 - Wake Status (WAK_STS)
This bit is set to 1, when the system is in the suspended
state and an enabled Power Management event occurs.
Exception to this is the Switch-Off event that can set this
bit to '1', regardless of the Power Button Enable bit. Unlike the other status bits of this register, reset overrides
set.
Suspend state starts when Sleep Enable bit (of
PM1_CNT_HIGH register) is written with a 1.
Suspend
state
ends
when
PM1_STS_LOW,
PM1_STS_HIGH, PM1_EN_LOW, PM1_EN_HIGH,
PM1_CNT_LOW,
PM1_CNT_HIGH,
GP1_STS0,
GP1_EN0,
GP2_EN0,
PM1_TMR_LOW,
PM1_TMR_MID, PM1_TMR_HIGH or PM1_TMR_EXT is
accessed while Wake Status bit (of PM1_STS_HIGH register) is set. It ends on first access to any of these registers.
Power Management events that affect this bit: RTC
Alarm, Power Button, PME1, PME2, IRRX1, IRRX2,
GPIO10, GPIO12, GPIO13, P12 (enabled by the
GP1_EN0 register).
ACPI FIXED REGISTERS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
4.6.5
4.6.6
Power Management 1 Control Low Byte
Register (PM1_CNT_LOW)
Reserved bits are read-only, and will always return 0.
Reserved bits are read-only, and will always return 0.
7
6
5
4
3
0
0
0
0
0
Power Management 1 Control High Byte
Register (PM1_CNT_HIGH)
Power Management 1 Control
Low Byte Register
2 1 0 Power-Up
Reset (PM1_CNT_LOW)
0 0 0
Offset 00h
Required
7
6
5
4
3
2
0
0
0
0
0
0
Power Management 1 Control
High Byte Register
0
Power-Up
0 0 Reset
(PM1_CNT_HIGH)
Offset 01h
Required
1
Reserved
SCI_EN
Reserved
GBL_RLS
SLP_TYP
SLP_EN
Reserved
Reserved
FIGURE 4-37. PM1_CNT_HIGH Register Bitmap
FIGURE 4-36. PM1_CNT_LOW Register Bitmap
Bits 0,1 - Reserved
Bit 0 - SCI/POR Select (SCI_EN)
This pin routes Power Management events to either the
POR or the SCI.
The power management events affected are Power Button, PME2,1, IRRX2,1, GPIO10/12/13 or P12.
Upon Master Reset, this bit is initialized to 0.
0: Power management events are routed to POR.
1: Power management events are routed to SCI
(which is routed to an IRQ assignment).
Bits 4-2 - Sleep Type (SLP_TYP)
These read/write bits do not affect the PC87317. They are
implemented only for compliance with the ACPI standard.
In the ACPI standard they define the type of suspend mode the
system should enter (when the Sleep Enable bit is set to 1).
Bit 5 - Sleep Enable (SLP_EN)
This bit is a write-only non-sticky bit. Read returns 0.
0: Ignored
1: Sleep Enable Status bit in the ACPI Support register is
set to 1 (See Logical device 8). This can assert POR.
Bit 1 - Reserved
Bit 2 - ACPI Global Lock Release (GBL_RLS)
When a 1 is written to this bit, the ACPI GLobal Lock
Status bit is set to 1 (See ACPI Support register, Logical
device 8). This can assert POR. Writing a 0 to this bit
has no effect on POR.
Upon Master Reset, this bit is initialized to 0.
Bits 7,6 - Reserved
PM TIMER REGISTERS
4.6.7
Power Management Timer Low Byte Register
(PM1_TMR_LOW)
This is a read-only register.
Bits 7-3 - Reserved
7
6
5
4
3
x
x
x
x
x
Power Management Timer
Low Byte Register
2 1 0 Power-Up
Reset (PM1_TMR_LOW)
x x x
Offset 00h
Required
Power Management Timer Low Byte
FIGURE 4-38. PM1_TMR_LOW Register Bitmap
Bits 7-0 - Power Management Low Byte Bits
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80
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Power Management Timer Middle Byte Register
(PM1_TMR_MID)
4.6.10 Power Management Timer Extended Byte
Register (PM1_TMR_EXT)
This is a read-only register.
This read-only register always returns 00h.
.
7
6
5
4
3
2
1
x
x
x
x
x
x
x
Power Management Timer
Middle Byte Register
Power-Up
x Reset
(PM1_TMR_MID)
Offset 01h
Required
0
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
Power Management Timer
Extended Byte Register
2 1 0 Power-Up
Reset (PM1_TMR_EXT)
0 0 0
Offset 03h
Required
0 0 0
Power Management Timer Middle Byte
Power Management Timer
Extended Byte
FIGURE 4-39. PM1_TMR_MID Register Bitmap
FIGURE 4-41. PM1_TMR_EXT Register Bitmap
Bits 7-0 - Power Management Timer Middle Byte bits.
4.6.9
.Bits 7-0 - Power Management Timer extended Byte bits.
Power Management Timer High Byte Register
(PM1_TMR_HIGH)
4.7
This is a read-only register.
GENERAL PURPOSE EVENT REGISTERS
4.7.1
.
7
6
5
4
3
2
1
x
x
x
x
x
x
x
Power Management Timer
High Byte Register
x Power-Up
Reset (PM1_TMR_HIGH)
Offset 02h
Required
General Purpose 1 Status Register (GP1_STS0)
All implemented bits are “sticky” bits: they are set to 1 by a
hardware event, and are reset to 0 only by software writing
a 1 to the bit location. Set overrides reset. Read returns 0.
0
Upon first power Up, these bits are initialized to 0. Upon
Master Reset, bits 4 to 7 are reset to 0.
Power Management Timer High Byte
7
6
5
4
3
2
1
0
0
0
0
0
0
0
General Purpose 1
Status Register
0 Power-Up
(GP1_STS0)
Reset
Offset 00h
Required
0
PME1_S
PME2_S
IRRX1_S
IRRX2_S
GPIO12_S
GPIO13_S
GPIO10_S
P12_S
FIGURE 4-40. PM1_TMR_HIGH Register Bitmap
Bits 7-0 - Power Management Timer High Byte bits.
FIGURE 4-42. GP1_STS0 Register Bitmap
Bit 0 - PME1 Status (PME1_S)
This bit is set to 1, when a PME1 event occurs, regardless of the PME1 Enable bit setting (bit 0 of the
GP1_EN0 and GP2_EN0 registers). PME1 Event is defined by bits 2-0 of the APCR4 register.
Bit 1 - PME2 Status (PME2_S)
This bit is set to 1, when a PME2 event occurs, regardless of the PME2 Enable bit setting (bit 1 of the
GP1_EN0 and GP2_EN0 registers). PME2 Event is defined by bits 5-3 of the APCR4 register.
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GENERAL PURPOSE EVENT REGISTERS
4.6.8
GENERAL PURPOSE EVENT REGISTERS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Bit 2 - IRRX1 Status (IRRX1_S)
This bit is set to 1, when an IRRX1 event occurs, regardless of the IRRX1 Enable bit setting (bit 2 of the
GP1_EN0 and GP2_EN0 registers). IRRX1 Event is defined by bits 2-0 of the APCR5 register.
Bit 3 - IRRX2 Status (IRRX2_S)
This bit is set to 1, when an IRRX2 event occurs, regardless of IRRX2 Enable bit (bit 3 of the GP1_EN0 and
GP2_EN0 registers). IRRX2 Event is defined by bits 53 of the APCR5 register.
Note that if bit 3 of the GP1_EN0 register and bit 3 of the
GP2_EN0 register are both cleared to 0, spurious
IRRX2 events may be detected by this bit.
3
2
1
0
0
0
0
0
0
0
General Purpose 1
Enable 0 Register
0 Power-Up
(GP1_EN0)
Reset
Offset 04h
Required
0
Bit 1 - PME2 Enable (PME2_E)
0: PME2 Status bit is ignored (bit 1 of the GP1_STS0
register).
1: When the PME2 Status bit is 1:
- Activate the ONCTL pin.
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When PME2 is not selected on its corresponding
pin, this bit should be 0.
Bit 7 - P12 Status (P12_S)
This bit is set to 1, when a P12 event occurs, regardless
of the P12 Enable bit setting (bit 7 of the GP1_EN0 and
GP2_EN0 registers). P12 Event is defined by bits 2-0 of
the APCR7 register. Note that P12 is multiplexed with
CS0. In any case, the internal P12 port’s output is detected.
Bit 2 - IRRX1 Enable (IRRX1_E)
0: IRRX1 Status bit is ignored (bit 2 of the GP1_STS0
register).
1: When the IRRX1 Status bit is 1:
- Activate the ONCTL pin.
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When IRRX1 is not selected on its corresponding
pin, this bit should be 0.
General Purpose 1 Status 1 Register
(GP1_STS1), Offset 01h
This register is reserved. Read returns 0.
General Purpose 1 Status 2 Register
(GP1_STS2), Offset 02h
This register is reserved. Read returns 0.
Bit 3 - IRRX2 Enable (IRRX2_E)
0: IRRX2 Status bit is ignored (bit 3 of the GP1_STS0
register).
1: When the IRRX2 Status bit is 1:
- Activate the ONCTL pin.
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When IRRX2 is not selected on its corresponding
pin, this bit should be 0.
General Purpose 1 Status 3 Register
(GP1_STS3), Offset 03h
This register is reserved. Read returns 0.
4.7.5
4
Bit 0 - PME1 Enable (PME1_E)
0: PME1 Status bit is ignored (bit 0 of the GP1_STS0
register).
1: When the PME1 Status bit is 1:
- Activate the ONCTL pin.
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
When PME1 is not selected on its corresponding
pin, this bit should be 0.
Bit 6 - GPIO10 Status (GPIO10_S)
This bit is set to 1, when a GPIO10 event occurs, regardless of the GPIO10 Enable bit setting (bit 6 of the
GP1_EN0 and GP2_EN0 registers). GPIO10 Event is
defined by bits 7-5 of the APCR3 register.
4.7.4
5
FIGURE 4-43. GP1_EN0 Register Bitmap
Bit 5 - GPIO13 Status (GPIO13_S)
This bit is set to 1, when a GPIO13 event occurs, regardless of the GPIO13 Enable bit setting (bit 5 of the
GP1_EN0 and GP2_EN0 registers). GPIO13 Event is
defined by bits 5-3 of the APCR6 register.
4.7.3
6
PME1_E
PME2_E
IRRX1_E
IRRX2_E
GPIO12_E
GPIO13_E
GPIO10_E
P12_E
Bit 4 - GPIO12 Status (GPIO12_S)
This bit is set to 1, when a GPIO12 event occurs, regardless of the GPIO12 Enable bit setting (bit 4 of the
GP1_EN0 and GP2_EN0 registers). GPIO12 Event is
defined by bits 2-0 of the APCR6 register.
4.7.2
7
General Purpose 1 Enable 0 Register
(GP1_EN0)
Upon first power Up, these bits are initialized to 0. Upon
Master Reset, bits 4 to 7 are reset to 0.
Bit 4 - GPIO12 Enable (GPIO12_E)
0: GPIO12 Status bit is ignored (bit 4 of the
GP1_STS0 register).
1: When the GPIO12 Status bit is 1:
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
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82
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Bit 6 - GPIO10 Enable (GPIO10_E)
0: GPIO10 Status bit is ignored (bit 6 of the
GP1_STS0 register).
1: When the GPIO10 Status bit is 1:
- Activate the ONCTL pin.
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
Bit 2 - IRRX1 Enable (IRRX1_E)
0: IRRX1 Status bit is ignored (bit 2 of the GP1_STS0
register).
1: Activate the POR pin, when the IRRX1 Status bit
is 1, regardless of bit 0 of the PM1_CNT_LOW
register.
When IRRX1 is not selected on its corresponding pin,
this bit should be 0.
Bit 7 - P12 Enable (P12_E)
0: P12 Status bit is ignored (bit 7 of the GP1_STS0
register).
1: When the P12 Status bit is 1:
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
4.7.6
4.7.10 Bit 3 - IRRX2 Enable (IRRX2_E)
0: IRRX2 Status bit is ignored (bit 3 of the GP1_STS0
register)
1: Activate the POR pin, when the IRRX2 Status bit
is 1, regardless of bit 0 of the PM1_CNT_LOW
register.
When IRRX2 is not selected on its corresponding pin,
this bit should be 0.
General Purpose 1 Enable 1 Register
(GP1_EN1), Offset 05h
This register is reserved. Read returns 0.
4.7.7
General Purpose 1 Enable 2 Register
(GP1_EN2), Offset 06hr
Bit 4 - GPIO12 Enable (GPIO12_E)
0: GPIO12 Status bit is ignored (bit 4 of the
GP1_STS0 register).
1: Activate the POR pin, when the GPIO12 Status bit is
1, regardless of bit 0 of the PM1_CNT_LOW register.
This register is reserved. Read returns 0.
4.7.8
General Purpose 1 Enable 3 Register
(GP1_EN3), Offset 07h
This register is reserved. Read returns 0.
4.7.9
Bit 5 - GPIO13 Enable (GPIO13_E)
0: GPIO13 Status bit is ignored (bit 5 of the
GP1_STS0 register)
1: Activate the POR pin, when the GPIO13 Status bit is
1, regardless of bit 0 of the PM1_CNT_LOW register.
General Purpose 2 Enable 0 Register
(GP2_EN0)
Upon first power Up and Master Reset, these bits are initialized to 0.
.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Bit 6 - GPIO10 Enable (GPIO10_E)
0: GPIO10 Status bit is ignored (bit 6 of the
GP1_STS0 register).
1: Activate the POR pin, when the GPIO10 Status bit is
1, regardless of bit 0 of the PM1_CNT_LOW register.
General Purpose 2
Enable Register
0 Power-Up
(GP2_EN0)
Reset
Offset 08h
Required
0
PME1_E
PME2_E
IRRX1_E
IRRX2_E
GPIO12 Enable
GPIO13_E
GPIO10_E
P12_E
Bit 7 - P12 Enable (P12_E)
0: P12 Status bit is ignored (bit 7 of the
GP1_STS0 register).
1: Activate the POR pin, when the P12 Status bit is 1,
regardless of bit 0 of the PM1_CNT_LOW register.
4.7.11 SMI Command Register (SMI_CMD), Offset 0Ch
This is an 8-bit read/write register. The data held in this register has no affect on the PC87317. Any write to this register
sets bit 5 of the ACPI Support register (see Logical Device
8). This can assert POR.
FIGURE 4-44. GP2_EN0 Register Bitmap
Bit 0 - PME1 Enable (PME1_E)
0: PME1 Status bit is ignored (bit 0 of the GP1_STS0
register).
1: Activate the POR pin, when the PME1 Status bit is 1,
regardless of bit 0 of the PM1_CNT_LOW register.
When PME1 is not selected on its corresponding pin,
this bit should be 0.
83
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GENERAL PURPOSE EVENT REGISTERS
Bit 1 - PME2 Enable (PME2_E)
0: PME2 Status bit is ignored (bit 1 of the GP1_STS0
register).
1: Activate the POR pin, when the PME2 Status bit
is 1, regardless of bit 0 of the PM1_CNT_LOW
register.
When PME2 is not selected on its corresponding pin,
this bit should be 0.
Bit 5 - GPIO13 Enable (GPIO13_E)
0: GPIO13 Status bit is ignored (bit 5 of the
GP1_STS0 register).
1: When the GPIO13 Status bit is 1:
- Activate the SCI signal or the POR pin (according
to bit 0 of the PM1_CNT_LOW register).
RTC AND APC REGISTER BITMAPS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
4.8
RTC AND APC REGISTER BITMAPS
4.8.1
4.8.2
7
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0 Power-Up
Reset
Required
6
5
4
3
2
1
0
0
0
0
0
Power-Up
Reset
0
Required
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0 Power-Up
Reset
0 Required
7
RTC Control
Register B
(CRB)
Index 0Bh
6
5
APC Control
Register 1
(APCR1)
index 40h
4
3
2
1
0
APC Control
Register 2
(APCR2)
Index 41h
RE
R1E
R2E
SODE
Software On Command
RTC Control
Register C
(CRC)
Index 0Ch
7
6
5
4
3
2
1
0
0
0
0
0
0
Power-Up
1 Reset
Required
APC Status
Register
(APSR)
Index 42h
TMD
RID
RI1 Detect
RI2 Detect
FTD
SOED
Reserved
PF
IRQF
0
0
TME
RSS
RPTDM
UF
5
1
Required
AF
6
2
Power-Up
Reset
Reserved
7
3
Failsafe Timer Trigger Cmd.
Switch Off Delay Option
POR Edge or Level Select
Level POR Clear Command
MOAP
SOC
Fail-safe Timer Reset Command
Power Failure
AIE
5
4
Required
PIE
SET
6
5
Power-Up
Reset
DSE
24 or 12 Hour Mode
DM
Unused
UIE
7
6
RTC Control
Register A
(CRA)
Index 0Ah
RS0
RS1
RS2
RS3
DV0
DV1
DV2
UIP
7
APC Register Bitmaps
RTC Register Bitmaps
RS
4
3
2
1
0
0 Power-Up
Reset
0 Required
0
0
0
0
0
0
0
0
0
0
0
0
RTC Control
Register D
(CRD)
Index 0Dh
7
6
5
4
3
2
1
1
1
0
0
0
0
0
Wake up Day of Week
Power-Up
Register
0
Reset
(WDWR)
Index 43h
Required
0
Wake up Day-of-Week Bits
Reserved
“Don’t Care” control bits
VRT
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84
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
6
5
4
3
2
1
1
1
0
0
0
0
0
Wake up Date-of-Month
Register
(WDMR)
0 Power-Up
Reset
Bank 2
Index 44h
Required
0
7
6
5
4
3
2
1
1
1
0
0
0
0
0
Wake up Date of Month Bits
Wake up Century Bits
“Don’t Care” control bits
7
6
5
4
3
2
1
1
1
0
0
0
0
0
“Don’t Care” control bits
Wake up Month
Register
Power-Up
(WMR)
0
Reset
Bank 2
Index 45h
Required
0
7
1
6
0
5
1
4
0
5
4
3
2
1
1
1
0
0
0
0
0
2
0
1
0
0
0 Power-Up
Reset
APC Control
Register 3
(APCR3)
Index 49h
PME1 or GPIO16 select
PME2 or GPIO15 select
LED or CS0 select
GPIO24 or IRRX1 select
GPIO37 or IRRX2/IRSL0/ID0 Select
GPIO10 Event Polarity/Edge select
“Don’t Care” control bits
6
3
0
Required
Wake up Month Bits
7
Wake up Century
Register
(WCR)
0 Power-Up
Reset
Bank 2
Index 48h
Required
0
Wake up Year
Register
Power-Up
(WYR)
0
Reset
Bank 2
Index 46h
Required
7
0
0
6
0
5
1
4
0
3
1
2
1
1
0
0
1 Power-Up
Reset
Required
APC Control
Register 4
(APCR4)
Index 4Ah
PME1 Event Polarity/Edge select
Wake up Year Bits
PME2 Event Polarity/Edge select
LED configuration
“Don’t Care” control bits
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0 Power-Up
Reset
0
Required
RAM Lock
Register
(RLR)
Index 47h
7
0
6
0
5
1
4
0
3
1
2
1
1
0
0
1 Power-Up
Reset
Required
Reserved
Reserved
Reserved
Upper RAM Block
RAM Block Read
RAM Block Write
RAM Mask Write
RAM Lock
APC Control
Register 5
(APCR5)
Index 4Bh
IRRX1 Event Polarity/Edge select
IRRX2 Event Polarity/Edge select
GPIO33 or RI2 select
Reserved
85
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RTC AND APC REGISTER BITMAPS
7
RTC AND APC REGISTER BITMAPS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
7
0
6
0
5
1
4
0
3
1
2
1
1
0
0
1 Power-Up
Reset
Required
APC Control
Register 6
(APCR6)
Index 4Ch
7
6
5
4
3
2
1
1
1
0
0
0
0
0
GPIO12 Event Polarity/Edge
select
0
Date-of-Month Alarm
Register
0 Power-Up
Reset
(DMAR)
Required
Relocatable Index
in Bank0 or Bank1
Day-of-Month
Alarm Bits
GPIO13 Event Polarity/Edge select
Extended wake-up options after Power failure
7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
1 Power-Up
Reset
Required
“Don’t Care” control bits
APC Control
Register 7
(APCR7)
Index 4Dh
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0 Power-Up
Reset
Month Alarm
Register
(MAR)
Required
Relocatable Index
in Bank0 or Bank1
P12 Event Polarity/Edge select
Power Button Override Select time
Power Supply Protect Mode
Month
Alarm Bits
Reserved
7
6
5
4
3
“Don’t Care” control bits
2
1
0
0
Power-Up
X Reset
Required
APC Status
Register 1
(APSR1)
Index 4Eh
7
6
5
4
3
2
1
1
1
0
0
1
0
1
Month Alarm Address
Register
Power-Up
0
(MADDR)
Reset
Bank 2
Required
Index 50h
0
SWITCH pin status
Switch -On Event detect
Month
Alarm Address
Reserved
Bank Select
7
6
5
4
3
2
1
1
0
0
1
0
Day-of-Month Alarm Address
Register
0
(DADDR)
Power-Up
0 1
Bank 2
Reset
Index 4Fh
Required
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Power-Up
Reset
1
Century
Register
(CR)
Required
Relocatable Index
in Bank0 or Bank1
Century
Bits
Day-of-Month
Alarm Address
Bank Select
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7
86
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
6
5
4
3
2
1
1
1
0
0
1
0
0
7
6
5
4
3
0
0
0
0
0
Power Management 1 Enable High
Byte Register
1 0
Power-Up
0 0 0
Reset (PM1_EN_HIGH)
Offset 01h
Required
2
PWRBTN_EN
Reserved
RTC_EN
Century Address
Reserved
Bank Select
7
6
5
4
3
2
0
0
0
0
0
0
Power Management 1 Status
Low Byte Register
0
Power-Up
0 0 Reset
(PM1_STS_LOW)
Offset 00h
Required
1
7
6
5
4
3
2
0
0
0
0
0
0
TMR_STS
Power Management 1 Control
Low Byte Register
0
Power-Up
0 0 Reset
(PM1_CNT_LOW)
Offset 00h
Required
1
SCI_EN
Reserved
GBL_RLS
Reserved
GBL_STS
Reserved
Reserved
7
6
5
4
3
0
0
0
0
0
Power Management 1 Status High
2 1 0
Byte Register
Power-Up
0 0 0 Reset
(PM1_STS_HIGH)
Offset 01h
Required
7
6
5
4
3
2
0
0
0
0
0
0
PWRBTN_STS
Reserved
RTC_STS
PWRBTNOR_STS
Power Management 1 Control
High Byte Register
0
Power-Up
0 0 Reset
(PM1_CNT_HIGH)
Offset 01h
Required
1
Reserved
SLP_TYP
SLP_EN
Reserved
WAK_STS
Reserved
7
6
5
4
3
0
0
0
0
0
Power Management 1 Enable Low
2 1 0
Byte Register
Power-Up
0 0 0 Reset
(PM1_EN_LOW)
Offset 02h
Required
7
6
5
4
3
2
0
0
0
0
0
0
Power Management Timer Low
1 0
Byte Register
Power-Up
0 0 Reset
(PM1_TMR_LOW)
Offset 00h
Required
TMR_EN
Reserved
Power Management Timer Low Byte
GBL_EN
Reserved
87
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RTC AND APC REGISTER BITMAPS
7
Century Address
Register
0
(CADDR)
Power-Up
0
Bank 2
Reset
Index 51h
Required
RTC AND APC REGISTER BITMAPS
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
7
6
5
4
3
0
0
0
0
0
Power Management Timer Middle
1 0
Byte Register
0 0 0 Power-Up
Reset
(PM1_TMR_MID)
Offset 00h
Required
2
7
6
5
4
3
2
1
0
0
0
0
0
0
0
PME1_E
PME2_E
IRRX1_E
IRRX2_E
GPIO12_E
GPIO13_E
GPIO10_E
P12_E
Power Management Timer Middle Byte
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Power Management Timer
High Byte Register
0 Power-Up
Reset (PM1_TMR_HIGH)
Offset 02h
Required
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Power Management Timer
Extended Byte Register
Power-Up
0 Reset
(PM1_TMR_EXT)
0 Required
Offset 00h
0
Power Management Timer
Extended Byte
7
6
5
4
3
2
1
0
0
0
0
0
0
0
General Purpose 1
Status Register
0 Power-Up
(GP1_STS0)
Reset
Offset 00h
Required
0
PME1_S
PME2_S
IRRX1_S
IRRX2_S
GPIO12_S
GPIO13_S
GPIO10_S
P12_S
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7
6
5
4
3
2
1
0
0
0
0
0
0
0
General Purpose 2
Enable Register
0 Power-Up
(GP2_EN0)
Reset
Offset 08h
Required
0
PME1_E
PME2_E
IRRX1_E
IRRX2_E
GPIO12_E
GPIO13_E
GPIO10_E
P12_E
Power Management Timer High Byte
7
General Purpose 1
Enable Register
0 Power-Up
(GP1_EN0)
Reset
Offset 04h
Required
0
88
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
REGISTER BANK TABLES
TABLE 4-19. Banks 0, 1 and 2 - Common 64-Byte Memory Map
Index
FUNCTION
BCD FORMAT
BINARY FORMAT
COMMENTS
00h
Seconds
00-59
00-3b
R/W
01h
Seconds Alarm
00-59
00-3b
R/W
02h
Minutes
00-59
00-3b
R/W
00-59
00-3b
R/W
12hr = 01-12 (AM)
01-0c (AM)
R/W
12hr = 81-92 (PM)
81-8c (PM)
R/W
24hr = 00-23
00-17
R/W
12hr = 01-12 (AM)
01-0c (AM)
R/W
12hr = 81-92 (PM)
81-8c (PM)
R/W
24hr = 00-23
00-17
R/W
03h
Minutes Alarm
04h
Hours
05h
Hours Alarm
06h
Day-of-Week
01-07
01-07 (Sunday = 1)
R/W
07h
Day-of-Month
01-31
01-1f
R/W
08h
Month
01-12
01-0c
R/W
09h
Year
00-99
00-63
R/W
0Ah
Control Register A
R/W (bit 7 is read only)
0Bh
Control Register B
R/W (bit 3 is read only)
0Ch
Control Register C
All bits read only
0Dh
Control Register D
All bits read only
0Eh-3Fh General Purpose RAM
R/W
TABLE 4-20. Bank 0 Registers - General Purpose Memory Bank
Register
Index
Type
Power-on Value
The first 14 RTC registers and the first 50 RTC
RAM bytes are shared among banks 0, 1 and 2.
00h-3Fh
40h - 7Fh
Function
R/W
General Purpose 64-Byte Battery-Backed RAM.
TABLE 4-21. Bank 1 Registers - RTC Memory Bank
Register
Century
Index
Type
Power-on Value
Function
00h-3Fh
Banks 0, 1 and 2 share the first 14 RTC registers and the
first 50 RTC RAM bytes.
40h-47h
Reserved. Writes have no effect and reads return 00h
48h(relocatable)
R/W
00h
BCD Format: 00-99. Binary Format: 00-63
Date 0f Month
Alarm
49h
R/W
C0h
BCD Format: 01-31. Binary Format 01-1F. Bits 6,7 are
“don’t care” control
Month Alarm
4Ah
R/W
C0h
BCD Format: 01-12. Binary Format 01-0c. Bits 6,7 are
“don’t care” control
4Bh-4Fh
Reserved
89
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REGISTER BANK TABLES
4.9
REGISTER BANK TABLES
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Register
Index
Type
50h
R/W
Upper RAM
Address Port
Power-on Value
Bits 6-0: Address of the upper 128 RAM bytes.
Bit 7: Reserved
51h-52h
Upper RAM Data
Port
53h
Function
Reserved
The byte pointed by the Upper RAM Address Port is
accessed via this register.
R/W
54h-7Fh
Reserved
TABLE 4-22. Bank 2 Registers - APC Memory Bank
Register
Index
Type
Power-On Value
00h - 3Fh
Function
Banks 0, 1 and 2 share the first 14 RTC
registers and the first 50 bytes of RTC RAM.
APC Control Register 1
(APCR1)
40h
R/W
00h
See Section 4.5.1
APC Control Register 2
(APCR2)
41h
R/W
00h
See Section 4.5.2
APC Status Register (APSR)
42h
R
Wake Up Day-of-Week
43h
R/W
BCD Format: 01-07
Binary Format: 01-07 (Sunday = 1)
Wake Up Day-of-Month
44h
R/W
BCD Format: 01-31
Binary Format: 01-1F
Wake Up Month
45h
R/W
BCD Format: 01-12
Binary Format: 01-0C
Wake Up Year
46h
R/W
BCD Format: 00-99
Binary Format: 00-63
RAM Lock
47h
R/W
Wake Up Century
48h
R/W
APC Control Register 3
(APCR3)
49h
R/W
A0h
See Section 4.5.10
APC Control Register 4
(APCR4)
4Ah
R/W
2Dh
See Section 4.5.11
APC Control Register 5
(APCR5)
4Bh
R/W
2Dh
See Section 4.5.12
APC Control Register 6
(APCR6)
4Ch
R/W
2Dh
See Section 4.5.13
APC Control Register 7
(APCR7)
4Dh
R/W
05h
See Section 4.5.14
APC Status Register 1
(APSR1)
4Eh
R
X
See Section 4.5.15
Date of Month Alarm
Address Register
4Fh
R/W
C9h
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1000001 (binary)
See Section 4.5.3
(bit 7 is indeterminate)
00h
initialized also on
MR pin reset.
See Section 4.5.8
BCD Format: 00-99
Binary Format: 00-63
90
Contains the Date of Month Alarm Relocatable
index within bank 0 or 1
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Index
Type
Power-On Value
Month Alarm Address
Register
50h
R/W
CAh
Contains the Month Alarm Relocatable index
within bank 0 or 1
Century Address Register
51h
R/W
C8h
Contains the Century Relocatable index within
bank 0 or 1
52h-7Fh
Function
Reserved
TABLE 4-23. Available General Purpose Bytes
Index
Bank
Number of Bytes
0Eh - 3Fh
All
50
40h - 7Fh
Bank 0
64
50h, 53h
Bank 1
128
Total
Notes
Indirect access via 50h for address and 53h for data.
242
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REGISTER BANK TABLES
Register
5.0
The Digital Floppy Disk Controller
(FDC) (Logical Device 3)
The Floppy Disk Controller (FDC) is suitable for all PC-AT,
EISA, PS/2, and general purpose applications. DP8473 and
N82077 software compatibility is provided. Key features include a 16-byte FIFO, PS/2 diagnostic register support, perpendicular recording mode, CMOS disk input and output
logic, and a high performance Digital Data Separator
(DDS).
FIGURE 5-1 "FDC Functional Block Diagram" shows a
functional block diagram of the FDC. The rest of this chapter
describes the FDC functions, data transfer, the FDC registers, the phases of FDC commands, the result phase status
registers and the FDC commands, in that order.
5.1
FDC FUNCTIONS
FDC functions are enabled when the FDC Function Enable
bit (bit 3) of the Function Enable Register 1 (FER1) at offset
00h in logical device 8 is set to 1. See Section 10.2.3 "Function Enable Register 1 (FER1)" on page 219.
The PC87317 is software compatible with the DP8473 and
82077 Floppy Disk Controllers (FDCs). Upon a power-on
reset, the 16-byte FIFO is disabled. Also, the disk interface
output signals are configured as active push-pull output signals, which are compatible with both CMOS input signals
and open-collector resistor terminated disk drive input signals.
The FIFO can be enabled with the CONFIGURE command.
The FIFO can be very useful at high data rates, with systems that have a long DMA bus latency, or with multi-tasking systems such as the EISA or MCA bus structures.
The FDC supports all the DP8473 MODE command features as well as some additional features. These include
control over the enabling of the FIFO for read and write operations, disabling burst mode for the FIFO, a bit that will
configure the disk interface outputs as open-drain output
signals, and programmability of the DENSEL output signal.
5.1.1
Microprocessor Interface
The Floppy Disk Controller (FDC) receives commands,
transfers data, and returns status information via an FDC
microprocessor interface. This interface consists of the
A9-3, AEN, RD, and WR signals, which access the chip for
read and write operations; the data signals D7-0; the address lines A2-0, which select the appropriate register (see
TABLE 5-1 "The FDC Registers and Their Addresses" on
page 96) an IRQ signal, and the DMA interface signals
DRQ, DACK, and TC.
5.1.2
System Operation Modes
The FDC operates in PC-AT or PS/2 drive mode, depending
on the value of bit 2 of the SuperI/O Configuration 1 register
at index 21h. See Section 2.4.3 "SuperI/O Configuration 1
Register (SIOC1)" on page 37.
Internal Control and Data Bus
RD
WR
FDC Chip
Select
A2-0
Reset
Interface
Logic
Main Status
Register
(MSR)
Status
Register A
DIR
Address
Decoder
FDC DMA
Acknowledge
16-Byte
DMA
Interrupt
FDC Clock
Logic
DR0
PC8477B
Micro-Engine
and
Timing/Control
Logic
Digital Input
Register
(DIR)
Digital Output
Register
(DOR)
Disk
Input
and
Output
Logic
HDSEL
MTR0
MTR1
STEP
WGATE
WDATA
DSKCHG
Data Rate
Selection
Register
(DSR)
Configuration
Control
Register
(CCR)
Write
Precompensator
2 KB x 16
Micro-Code
92
INDEX
RDATA
TRK0
Digital
Data
Separator
(DDS)
FIGURE 5-1. FDC Functional Block Diagram
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DR1
FIFO
Enable
FDC DMA
Request
DENSEL
Status
Register B
D7-0
TC
DRATE0
WP
MSEN1,0
To Floppy Disk Interface Cable
5.0 The Digital Floppy Disk Controller (FDC) (Logical Device 3)
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
The PC-AT register set is enabled. The DMA enable bit in
the Digital Output Register (DOR) becomes valid (the appropriate IRQ and DRQ signals can be put in TRI-STATE).
TC and DENSEL become active high signals (default to a
5.25" floppy disk drive).
250,300, 500 Kbps and 1 Mbps
80
Window Margin Percentage
PS/2 Drive Mode
This drive mode supports the PS/2 models 50/60/80 configuration and register set. The value of the DMA enable bit in
the Digital Output Register (DOR) becomes unimportant
(the IRQ and DRQ signals assigned to the FDC are always
valid). TC and DENSEL become active low signals (default
to 3.5" floppy drive).
5.2
5.2.1
DATA TRANSFER
Data Rates
The FDC supports the standard PC data rates of 250, 300
and 500 Kbps, as well as 1 Mbps. High performance tape
and floppy disk drives that are currently emerging in the PC
world, transfer data at 1 Mbps. The FDC also supports the
perpendicular recording mode, a new format used for some
high capacity disk drives at 1 Mbps.
60
50
40
30
20
10
-14-12-10 -8 -6 -4 -2 0 2 4 4 8 10 12 14
Motor Speed Variation (% of Nominal)
The internal digital data separator needs no external components. It improves the window margin performance standards of the DP8473, and is compatible with the strict data
separator requirements of floppy disk drives and tape
drives.
Typical Performance at 500 Kbps,
VDD = 5.0 V, 25 C
FIGURE 5-2. PC87317 Dynamic Window Margin
Performance
The FDC contains write precompensation circuitry that defaults to 125 nsec for 250, 300, and 500 Kbps (41.67 nsec
at 1 Mbps). These values can be overridden in software to
disable write precompensation or to provide levels of precompensation up to 250 nsec.
The x axis measures MSV. MSV is translated directly to the
actual rate at which the data separator reads data from the
disk. In other words, a faster than nominal motor results in
a higher data rate.
The FDC has internal 24 mA data bus buffers which allow
direct connection to the system bus. The internal 40 mA totem-pole disk interface buffers are compatible with both
CMOS drive input signals and 150 resistor terminated disk
drive input signals.
5.2.2
70
The dynamic window margin performance curve also indicates how much bit jitter (or window margin) can be tolerated by the data separator. This parameter is shown on the yaxis of the graph. Bit jitter is caused by the magnetic interaction of adjacent data pulses on the disk, which effectively
shifts the bits away from their nominal positions in the middle of the bit window. Window margin is commonly measured as a percentage. This percentage indicates how far a
data bit can be shifted early or late with respect to its nominal bit position, and still be read correctly by the data separator. If the data separator cannot correctly decode a shifted
bit, then the data is misread and a CRC error results.
The Data Separator
The internal data separator is a fully digital PLL. The fully
digital PLL synchronizes the raw data signal read from the
disk drive. The synchronized signal is used to separate the
encoded clock and data pulses. The data pulses are broken
down into bytes, and then sent to the microprocessor by the
controller.
The dynamic window margin performance curve supplies
two pieces of information:
The FDC supports data transfer rates of 250, 300, 500 Kbps
and 1 Mbps in Modified Frequency Modulation (MFM) format.
The FDC has a dynamic window margin and lock range performance capable of handling a wide range of floppy disk
drives. In addition, the data separator operates under a variety of conditions, including high fluctuations in the motor
speed of tape drives that are compatible with floppy disk
drives.
●
The maximum range of MSV (also called “lock range”)
that the data separator can handle with no read errors.
●
The maximum percentage of window margin (or bit jitter)
that the data separator can handle with no read errors.
Thus, the area under the dynamic window margin curves in
FIGURE 5-2 "PC87317 Dynamic Window Margin
Performance" is the range of MSV and bit jitter that the FDC
can handle with no read errors. The internal digital data separator of the FDC performs much better than comparable
digital data separator designs, and does not require any external components.
The dynamic window margin is the primary indicator of the
quality and performance level of the data separator. It indicates the toleration of the data separator for Motor Speed
Variation (MSV) of the drive spindle motor and bit jitter (or
window margin).
FIGURE 5-2 "PC87317 Dynamic Window Margin
Performance" shows the dynamic window margin in the
performance of the FDC at different data rates, generated
93
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DATA TRANSFER
using a FlexStar FS-540 floppy disk simulator and a proprietary dynamic window margin test program written by
National Semiconductor.
PC-AT Drive Mode
DATA TRANSFER
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
can write to the disk surface. The pre-erase head is activated during disk write operations only, i.e. FORMAT and
WRITE DATA commands.
The controller maximizes the internal digital data separator
by implementing a read algorithm that enhances the lock
characteristics of the fully digital Phase-Locked Loop (PLL).
The algorithm minimizes the effect of bad data on the synchronization between the PLL and the data.
In 2.88 MB drives, the pre-erase head leads the read/write
head by 200 µm, which translates to 38 bytes at 1 Mbps (19
bytes at 500 Kbps).
It does this by forcing the fully digital PLL to re-lock to the
clock reference frequency any time the data separator attempts to lock to a non-preamble pattern. See the state diagram of this read algorithm in FIGURE 5-3 "Read
Algorithm State Diagram".
Read/
Write
Head
Read Gate = 0
PLL idle
locked
to clock.
Read Gate = 1
PLL
locking
to data.
Wait six bits.
Not
sixth bit.
Bit is
preamble.
Operation
completed.
Three address
marks found.
Not third
address mark.
Because of the 38-byte spacing between the read/write
head and the pre-erase head at 1 Mbps, the gap 2 length of
22 bytes used in the standard IBM disk format is not long
enough. The format standard for 2.88 MB drives at 1 Mbps
called the Perpendicular Format, increases the length of
gap 2 to 41 bytes. See FIGURE 5-19 "IBM, Perpendicular,
and ISO Formats Supported by the FORMAT TRACK Command" on page 118.
Perpendicular Recording Mode Support
The FDC is fully compatible with perpendicular recording
mode disk drives at all data transfer rates. These perpendicular drives are also called 4 Mbyte (unformatted) or 2.88
Mbyte (formatted) drives. This refers to their maximum storage capacity.
The PERPENDICULAR MODE command puts the Floppy
Disk Controller (FDC) into perpendicular recording mode,
which allows it to read and write perpendicular media. Once
this command is invoked, the read, write and format commands can be executed in the normal manner. The perpendicular mode of the FDC functions at all data rates,
adjusting format and write data parameters accordingly.
See Section 5.7.9 "The PERPENDICULAR MODE Command" on page 121 for more details.
Perpendicular recording orients the magnetic flux changes
(which represent bits) vertically on the disk surface, allowing for a higher recording density than conventional longitudinal recording methods. This increased recording density
increases data rate by up to 1 Mbps, thereby doubling the
storage capacity. In addition, the perpendicular 2.88 MB
drive is read/write compatible with 1.44 MB and 720 KB diskettes (500 Kbps and 250 Kbps respectively).
The 2.88 MB drive has unique format and write data timing
requirements due to its read/write head and pre-erase head
design. This is illustrated in FIGURE 5-4 "Perpendicular Recording Drive Read/Write Head and Pre-Erase Head".
5.2.4
Data Rate Selection
The FDC sets the data rate in two ways. For PC compatible
software, the Configuration Control Register (CCR) at offset
07h programs the data rate for the FDC. The lower bits D1
and D0 in the CCR set the data rate. The other bits should
be set to zero. TABLE 5-6 "Data Transfer Rate Encoding"
on page 101 shows how to encode the desired data rate.
Unlike conventional disk drives which have only a
read/write head, the 2.88 MB drive has both a pre-erase
head and read/write head. With conventional disk drives,
the read/write head, itself, can rewrite the disk without problems. 2.88 MB drives need a pre-erase head to erase the
magnetic flux on the disk surface before the read/write head
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Preamble
With 2.88 MB drives, since the preamble must be erased
before it is rewritten, WGATE should be asserted when the
pre-erase head is located at the beginning of the preamble
to the data field. This means that WGATE should be asserted when the read/write head is at least 38 bytes (at 1 Mbps)
before the preamble. TABLES 5-15 "Effect of Drive Mode
and Data Rate on FORMAT TRACK and WRITE DATA
Commands" on page 122 and 5-16 "Effect of GDC Bits on
FORMAT TRACK and WRITE DATA Commands" on page
122 show how the perpendicular format affects gap 2 and,
consequently, WGATE timing, for different data rates.
FIGURE 5-3. Read Algorithm State Diagram
5.2.3
Data Field
For both conventional and perpendicular drives, WGATE is
asserted with respect to the position of the read/write head.
With conventional drives, this means that WGATE is asserted when the read/write head is located at the beginning of
the preamble to the data field.
Check for
three address
mark bytes.
Bit is not
preamble.
Intersector
= 41 x 4Eh
Gap 2
PreErase
Head
FIGURE 5-4. Perpendicular Recording Drive
Read/Write Head and Pre-Erase Head
Read ID
field or
data field.
Three address
marks not found.
Wait for
first bit that
is not a
preamble
bit.
End of
ID Field
200 µm
(38 bytes @ 1 Mbps)
94
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
Manual low power can also be triggered by the MODE command. Manual low power mode functions as a logical OR
function between the DSR low power bit and the LOW PWR
option of the MODE command.
The data rate is determined by the last value written to either the CCR or the DSR. Either the CCR or the DSR can
override the data rate selection of the other register. When
the data rate is selected, the micro-engine and data separator clocks are scaled appropriately.
Automatic low-power mode switches the controller to low
power 500 msec (at the 500 Kbps MFM data rate) after it
has entered the Idle state. Once automatic low-power mode
is set, it does not have to be set again, and the controller automatically goes into low-power mode after entering the Idle
state.
5.2.5
Automatic Low-Power Mode
Write Precompensation
Automatic low-power mode can only be set with the LOW
PWR option of the MODE command.
Write precompensation enables the WDATA output signal
to adjust for the effects of bit shift on the data as it is written
to the disk surface.
Recovery from Low-Power Mode
Bit shift is caused by the magnetic interaction of data bits as
they are written to the disk surface. It shifts these data bits
away from their nominal position in the serial MFM data pattern. Bit shift makes it much harder for a data separator to
read data and can cause soft read errors.
There are two ways the FDC section can recover from the
power-down state.
Power up is triggered by a software reset via the DOR or
DSR. Since a software reset requires initialization of the
controller, this method might be undesirable.
Write precompensation predicts where bit shift could occur
within a data pattern. It then shifts the individual data bits
early, late, or not at all so that when they are written to the
disk, the shifted data bits are back in their nominal position.
Power up is also triggered by a read or write to either the
Data Register (FIFO) or Main Status Register (MSR). This
is the preferred way to power up since all internal register
values are retained. It may take a few milliseconds for the
clock to stabilize, and the microprocessor will be prevented
from issuing commands during this time through the normal
MSR protocol. That means that bit 7, the Request for Master (RQM) bit, in the MSR will be a 0 until the clock has stabilized. When the controller has completely stabilized after
power up, the RQM bit in the MSR is set to 1 and the controller can continue where it left off.
The FDC supports software programmable write precompensation. Upon power up, the default write precompensation values shown in TABLE 5-8 "Default Precompensation
Delays" on page 102, are used. In addition, the default starting track number for write precompensation is track zero
You can use the DSR to change the write precompensation
using any of the values in TABLE 5-7 "Write Precompensation Delays" on page 102. Also, the CONFIGURE command
can change the starting track number for write precompensation.
5.2.6
5.2.7
Reset
The FDC can be reset by hardware or software.
A hardware reset consists of pulsing the Master Reset (MR)
input signal. A hardware reset sets all of the user addressable registers and internal registers to their default values.
The SPECIFY command values are unaffected by reset, so
they must be initialized again.
FDC Low-Power Mode Logic
The FDC of the PC87317 supports two low-power modes,
manual and automatic.
In low-power mode, the micro-code is driven from the clock.
Therefore, it is disabled while the clock is off. Upon entering
the power-down state, bit 7, the RQM (Request For Master)
bit, in the Main Status Register (MSR) of the FDC is cleared
to 0.
The major default conditions affected by reset are:
For details about entering and exiting low-power mode by
setting bit 6 of the Data rate Select Register (DSR) or by executing the LOW PWR option of the FDC MODE command,
see “Recovery from Low-Power Mode” later in this section,
Section 5.3.6 "Data Rate Select Register (DSR)" on page
101 and Section 5.7.7 "The MODE Command" on page
119.
●
FIFO disabled
●
DMA disabled
●
Implied seeks disabled
●
Drive polling enabled
A software reset can be triggered by bit 2 of the Digital Output Register (DOR) or bit 7 of the Data rate Select Register
(DSR). Bit 7 of DSR clears itself, while bit 2 of DOR does
not clear itself.
The DSR, Digital Output Register (DOR), and the Configuration Control Register (CCR) are unaffected and remain
active in power-down mode. Therefore, you should make
sure that the motor and drive select signals are turned off.
If the LOCK bit in the LOCK command was set to 1 before
the software reset, the FIFO, THRESH, and PRETRK parameters in the CONFIGURE command will be retained. In
addition, the FWR, FRD, and BST parameters in the MODE
command will be retained if LOCK is set to 1. This function
eliminates the need for total initialization of the controller after a software reset.
If the power to an external clock driving the PC87317 will be
independently removed while the FDC is in power-down
mode, it must not be done until 2 msec after the LOW PWR
option of the FDC MODE command is issued.
After a hardware (assuming the FDC is enabled in the FER)
or software reset, the Main Status Register (MSR) is immediately available for read access by the microprocessor. It
will return a 00h value until all the internal registers have
been updated and the data separator is stabilized.
Manual Low-Power Mode
Manual low power is enabled by writing a 1 to bit 6 of the
DSR. The chip will power down immediately. This bit will be
cleared to 0 after power up.
95
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DATA TRANSFER
The lower two bits of the Data rate Select Register (DSR) at
offset 04h can also set the data rate. These bits are encoded like the corresponding bits in the CCR. The remainder of
the bits in the DSR have other functions. See the description of the DSR in Section 5.3.6 "Data Rate Select Register
(DSR)" on page 101 for more details.
THE FDC REGISTERS
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
When the controller is ready to receive a command byte, the
MSR returns a value of 80h (Request for Master (RQM, bit
7) bit is set). The MSR is guaranteed to return the 80h value
within 250 µsec after a hardware or software reset.
SRA can be read at any time while PS/2 drive mode is active. In PC-AT drive mode, all bits are in TRI-STATE during
a microprocessor read.
All other user addressable registers other than the Main
Status Register (MSR) and Data Register (FIFO) can be accessed at any time, even during software reset.
7
0
5.3
THE FDC REGISTERS
0
4
3
0
PS/2 Drive Mode
2 1 0
0 Reset
Status Register
A (SRA)
Offset 00h
Head Direction
WP
INDEX
Head Select
TRK0
Step
Reserved
IRQ Pending
TABLE 5-1. The FDC Registers and Their Addresses
Offset
Description
R/W
A2 A1 A0
FIGURE 5-5. SRA Register Bitmap
SRA
Status Register A
0
0
0
R
SRB
Status Register B
0
0
1
R
DOR
Digital Output Register
0
1
0
R/W
TDR
Tape Drive Register
0
1
1
R/W
MSR
Main Status Register
1
0
0
R
DSR
Data Rate Select Register 1
0
0
W
FIFO
Data Register (FIFO)
1
0
1
R/W
(Bus in TRI-STATE)
1
1
0
X
DIR
Digital Input Register
1
1
1
R
CCR
CCR Configuration
Control Register
1
1
1
W
-
5
Required
The FDC registers are mapped to the offset address shown
in TABLE 5-1 "The FDC Registers and Their Addresses",
with the base address range provided by the on-chip address decoder. For PC-AT or PS/2 applications, the offset
address range of the diskette controller is 00h through 07h
from the index of logical device 3.
Symbol
6
Bit 0 - Head Direction
This bit indicates the direction of the head of the Floppy
Disk Drive (FDD). Its value is the inverse of the value of
the DIR interface output signal.
0: DIR is not active, i.e., the head of the FDD steps
outward. (Default)
1: DIR is active, i.e., the head of the FDD steps inward.
Bit 1 - Write Protect (WP)
This bit indicates whether or not the selected Floppy
Disk Drive (FDD) is write protected. Its value reflects the
status of the WP disk interface input signal.
0: WP is active, i.e., the FDD in the selected drive is
write protected.
1: WP is not active, i.e., the FDD in the selected drive
is not write protected.
The FDC supports two system operation modes: PC-AT
drive mode and PS/2 drive mode (MicroChannel systems).
Section 5.1.2 "System Operation Modes" on page 92 describes each mode and “Bit 2 - PC-AT or PS/2 Drive Mode
Select” on page 37 describes how each is enabled.
Bit 2 - Beginning of Track (INDEX)
This bit indicates the beginning of a track. Its value reflects the status of the INDEX disk interface input signal.
0: INDEX is active, i.e., it is the beginning of a track.
1: INDEX is not active, i.e., it is not the beginning of a
track.
Unless specifically indicated otherwise, all fields in all registers are valid in both drive modes.
The FDC supports plug and play, as follows:
●
The FDC interrupt can be routed on one of the following
ISA interrupts: IRQ3-IRQ7, IRQ9-IRQ12 and IRQ15
(see PNP2 register).
●
The FDC DMA signals can be routed to one of three 8bit ISA DMA channels (see PNP2 register); and its base
address is software configurable (see FBAL and FBAH
registers).
●
Upon reset, the DMA of the FDC is routed to the DRQ2
and DACK2 pins.
5.3.1
Bit 3 - Head Select
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected by the head. Its value is the inverse of
the HDSEL disk interface output signal.
0: HDSEL is not active, i.e., the head of the FDD selects side 0. (Default)
1: HDSEL is active, i.e., the head of the FDD selects
side 1.
Bit 4 - At Track 0 (TRK0)
This bit indicates whether or not the head of the Floppy
Disk Drive (FDD) is at track 0. Its value reflects the status of the TRK0 disk interface input signal.
0: TRK0 is active, i.e., the head of FDD is at track 0.
1: TRK0 is not active, i.e., the head of FDD is not at
track 0.
Status Register A (SRA)
Status Register A (SRA) monitors the state of assigned IRQ
signal and some of the disk interface signals. SRA is a readonly register that is valid only in PS/2 drive mode.
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96
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
Bit 3 - Read Data Status (RDATA)
If read data was sent, this bit indicates whether an odd
or even number of bits was sent.
Every inactive edge transition of the RDATA disk interface output signal causes this bit to change state.
0: Either no read data was sent or an even number of
bits of read data was sent. (Default)
1: An odd number of bits of read data was sent.
Bit 6 - Reserved
Bit 7 - IRQ Pending
This bit signals the completion of the execution phase of
certain FDC commands. Its value reflects the status of
the IRQ signal assigned to the FDC.
0: The IRQ signal assigned to the FDC is not active.
1: The IRQ signal assigned to the FDC is active, i.e.,
the FDD has completed execution of certain FDC
commands.
5.3.2
Bit 4 - Write Data Status (WDATA)
If write data was sent, this bit indicates whether an odd
or even number of bits was sent.
Every inactive edge transition of the WDATA disk interface output signal causes this bit to change state.
0: Either no write data was sent or an even number of
bits of write data was sent. (Default)
1: An odd number of bits of write data was sent.
Status Register B (SRB)
Status Register B (SRB) is a read-only diagnostic register
that is valid only in PS/2 drive mode.
SRB can be read at any time while PS/2 drive mode is active. In PC-AT drive mode, all bits are in TRI-STATE during
a microprocessor read.
7
6
5
4
3
PS/2 Drive Mode
2 1 0
1
1
0
0
0
0
1
1
0
0 Reset
Bit 5 - Drive Select 0 Status
This bit reflects the status of drive select bit 0 in the Digital Output Register (DOR). See Section 5.3.3 "Digital
Output Register (DOR)".
It is cleared after a hardware reset and unaffected by a
software reset.
0: Either drive 0 or 2 is selected. (Default)
1: Either drive 1 or 3 is selected.
SRB Register
Offset 01h
Required
MTR0
MTR1
WGATE
RDATA
WDATA
Drive Select 0 Status
Reserved
Reserved
Bits 7,6 - Reserved
These bits are reserved and are always 1.
5.3.3
Digital Output Register (DOR)
DOR is a read/write register that can be written at any time.
It controls the drive select and motor enable disk interface
output signals, enables the DMA logic and contains a software reset bit.
Bit 0 - Motor 0 Status (MTR0)
This bit indicates the complement of the MTR0 output
pin.
This bit is cleared to 0 by a hardware reset and unaffected by a software reset.
0: MTR0 not active; motor 0 off
1: MTR0 active; motor 0 on (default)
The contents of the DOR is set to 00h after a hardware reset, and is unaffected by a software reset.
TABLE 5-2 "Drive and Motor Pin Encoding for Four Drive
Configurations and Drive Exchange Support" shows how
the bits of DOR select a drive and enable a motor when the
FDC is enabled (bit 3 of the Function Enable Register 1
(FER1) at offset 00h of logical device 8 is 1) and bit 7 of the
SuperI/O FDC Configuration register at index F0h is 1. Bit
patterns not shown produce states that should not be decoded to enable any drive or motor.
Bit 1 - Motor 1 Status (MTR1)
This bit indicates the complement of the MTR1 output
pin.
This bit is cleared to 0 by a hardware reset and unaffected by a software reset.
0: MTR0 not active; motor 1 off
1: MTR0 active.; motor 1 on (default)
When the FDC is enabled and bit 7 of the of the SuperI/O
FDC Configuration register at index F0h is 1, MTR1 presents a pulse that is the inverse of WR. This pulse is active
whenever an I/O write to address 02h occurs. This pulse is
delayed for between 25 and 80 nsec after the leading edge
of WR. The leading edge of this pulse can be used to clock
data into an external latch (e.g., 74LS175).
97
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THE FDC REGISTERS
Bit 2 - Write Circuitry Status (WGATE)
This bit indicates the complement of the WGATE output
pin.
0: WGATE not active. The write circuitry of the selected FDD is enabled.
1: WGATE active. The write circuitry of the selected
FDD is disabled. (Default))
Bit 5 - Step
This bit indicates whether or not the head of the Floppy
Disk Drive (FDD) should move during a seek operation.
Its value is the inverse of the STEP disk interface output
signal.
0: STEP is not active, i.e., the head of the FDD
moves. (Default)
1: STEP is active (low), i.e., the head of the FDD does
not move.
THE FDC REGISTERS
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
TABLE 5-2. Drive and Motor Pin Encoding for Four
Drive Configurations and Drive Exchange Support
Digital Output
Register Bits
Control
Signals
MTR DR
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
Digital Output
Register (DOR)
Offset 02h
Required
Decoded Functions
Drive Select
Reset Controller
DMAEN
Motor Enable 0
Motor Enable 1
Motor Enable 2
Motor Enable 3
7 6 5 4 3 2 1 0 1 0 1 0
x x x 1 x x 0 0 - 0 0 0
Activate Drive 0
and Motor 0
x x 1 x x x 0 1 - 0 0 1
Activate Drive 1
and Motor 1
x 1 x x x x 1 0 - 0 1 0
Activate Drive 2
and Motor 2
1 x x x x x 1 1 - 0 1 1
Activate Drive 3
and Motor 3
FIGURE 5-6. DOR Register Bitmap
Bits 1,0 - Drive Select
These bits select a drive, so that only one drive select
output signal is active at a time.
See “Bit 7 - Four Drive Encode” on page 40 and “Bits 3,2
- Logical Drive Control (Enhanced TDR Mode Only)” on
page 100 for more information.
00: Drive 0 is selected. (Default)
01: Drive 1 is selected.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11: If four drives are supported, drive 3 is selected.
Activate Drive 0 and
x x x 0 x x 0 0 - 1 0 0
Deactivate Motor 0
x x 0 x x x 0 1 - 1 0 1
Activate Drive 1 and
deactivate Motor 1
x 0 x x x x 1 0 - 1 1 0
Activate Drive 2 and
Deactivate Motor 2
0 x x x x x 1 1 - 1 1 1
Activate Drive 3 and
Deactivate Motor 3
Usually, the motor enable and drive select output signals for
a particular drive are enabled together. TABLE 5-3 "Drive
Enable Hexadecimal Values" shows the DOR hexadecimal
values that enable each of the four drives.
Bit 2 - Reset Controller
This bit can cause a software reset. The controller remains in a reset state until this bit is set to 1.
A software reset affects the CONFIGURE and MODE
commands. See Sections 5.7.2 "The CONFIGURE
Command" on page 114 and 5.7.7 "The MODE Command" on page 119, respectively. A software reset does
not affect the Data rate Select Register (DSR), Configuration Control Register (CCR) and other bits of this register (DOR).
This bit must be low for at least 100 nsec. There is
enough time during consecutive writes to the DOR to reset software by toggling this bit.
0: Reset controller. (Default)
1: No reset.
TABLE 5-3. Drive Enable Hexadecimal Values
Drive
DOR Value (Hex)
0
1C
1
2D
2
4E
3
8F
The motor enable and drive select signals for drives 2 and
3 are only available when four drives are supported, i.e., bit
7 of the SuperI/O FDC Configuration register at index F0h
is 1, or when drives 2 and 0 are exchanged. These signals
require external logic.
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7
Bit 3 - DMA Enable (DMAEN)
In PC-AT drive mode, this bit enables DMA operations
by controlling DACK, TC and the appropriate DRQ and
IRQ DMA signals. In PC-AT mode, this bit is set to 0 after reset.
In PS/2 drive mode, this bit is reserved, and DACK, TC
and the appropriate DRQ and IRQ signals are enabled.
During reset, these signals remain enabled.
0: In PC-AT drive mode, DMA operations are disabled. DACK and TC are disabled, and the appropriate DRQ and IRQ signals are put in TRI-STATE.
(Default)
1: In PC-AT drive mode, DMA operations are enabled,
i.e., DACK, TC and the appropriate DRQ and IRQ
signals are all enabled.
98
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
In this mode, the TDR assigns a drive number to the tape
drive support mode of the data separator. All other logical
drives can be assigned as floppy drive support. Bits 7-2 are
in TRI-STATE during read operations.
Enhanced TDR Mode
In this mode, all the bits of the TDR define operations with
Enhanced floppy disk drives.
AT Compatible TDR Mode
7
6
Bit 5 - Motor Enable 1
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 0, depending on
the remaining bits of this register. See TABLE 5-2.
If two drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 0), this bit controls
the motor output signal for drive 1.
0: The motor signal for drive 1 is not active.
1: The motor signal for drive 1 is active.
4
3
2
1
1
0
0
0 Reset
Tape Drive
Register (TDR)
Offset 03h
Required
Tape Drive Select 1,0
Not Used
TRI-STATE During Read Operations
Bit 6 - Motor Enable 2
If drives 2 and 0 are exchanged (see "Bits 3,2 - Logical
Drive Control (Enhanced TDR Mode Only)" on page
100), or if four drives are supported (bit 7 of the SuperI/O FDC Configuration register at index F0h is 1), this
bit controls the motor output signal for drive 2. See TABLE 5-2.
0: The motor signal for drive 2 is not active.
1: The motor signal for drive 2 is active.
FIGURE 5-7. TDR Register Bitmap, AT Compatible
TDR Mode
Enhanced TDR Mode
7 6 5 4 3 2 1 0
Tape Drive
Register (TDR)
1
0 0 Reset
Offset 03h
Required
Bit 7 - Motor Enable 3
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 3, depending on
the remaining bits of this register. See TABLE 5-2.
0: The motor signal for drive 3 is not active.
1: The motor signal for drive 3 is active.
5.3.4
5
Tape Drive Select 1,0
Logical Drive Exchange
Drive ID0 Information
Drive ID1 Information
High Density
Extra Density
Tape Drive Register (TDR)
FIGURE 5-8. TDR Register Bitmap, Enhanced TDR
Mode
The TDR register is a read/write register that acts as the
Floppy Disk Controller’s (FDC) media and drive type register.
The TDR functions differently, depending on the mode set
by bit 6 the SuperI/O FDC Configuration register at index
F0h. See “Bit 6 - TDR Register Mode” on page 40.
TABLE 5-4. TDR Bit Utilization and Reset Values in Different Drive Modes
Bits of TDR
TDR Mode
Bit 6 of SuperI/O
FDC Configuration
Register
At Compatible
0
Enhanced
1
Extra
Density
High
Density
7
6
Drive ID1 Drive ID0
5
4
Logical Drive
Exchange
3
2
Not used. Floated in TRI-STATE during read operations.
Not Reset Not Reset
99
1
1
0
0
Drive Select
1
0
0
0
0
0
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THE FDC REGISTERS
AT Compatible TDR Mode
Bit 4- Motor Enable 0
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 0, depending on
the remaining bits of this register. See TABLE 5-2
"Drive and Motor Pin Encoding for Four Drive Configurations and Drive Exchange Support" on page 98.
If two drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 0), this bit controls
the motor output signal for drive 0.
0: The motor signal for drive 0 is not active.
1: The motor signal for drive 0 is active.
THE FDC REGISTERS
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
5.3.5
Bits 1,0 - Tape Drive Select 1,0
These bits assign a logical drive number to a tape drive.
Drive 0 is not available as a tape drive and is reserved
as the floppy disk boot drive.
00: No drive selected.
01: Drive 1 selected.
10: Drive 2 selected.
11: Drive 3 selected.
This read-only register indicates the current status of the
Floppy Disk Controller (FDC), indicates when the disk controller is ready to send or receive data through the Data
Register (FIFO) and controls the flow of data to and from the
Data Register (FIFO).
The MSR can be read at any time. It should be read before
each byte is transferred to or from the Data Register (FIFO)
except during a DMA transfer. No delay is required when
reading this register after a data transfer.
Bits 3,2 - Logical Drive Control (Enhanced TDR Mode
Only)
These read/write bits control logical drive exchange between drives 0 and 2, only.
They enable software to exchange the physical floppy
disk drive and motor control signals assigned to pins.
Drive 3 is never exchanged for drive 2.
When four drives are configured, i.e., bit 7 of SuperI/O
FDC Configuration register at index F0h is 1, logical
drives are not exchanged.
00: No logical drive exchange.
01: Disk drive and motor control signal assignment to
pins exchanged between logical drives 0 and 1.
10: Disk drive and motor control signal assignment to
pins exchanged between logical drives 0 and 2.
11: Reserved. Unpredictable results when configured.
The microprocessor can read the MSR immediately after a
hardware or software reset, or recovery from a power down.
The MSR contains a value of 00h, until the FDC clock has
stabilized and the internal registers have been initialized.
When the FDC is ready to receive a new command, it reports a value of 80h for the MSR to the microprocessor.
System software can poll the MSR until the MSR is ready.
The MSR must report an 80h value (RQM set to 1) within
2.5 msec after reset or power up.
0
0
5.25"
0
1
2.88 M
1
0
1.44 M
1
1
720 K
4
3
0
0
0
0
0
Read Operations
2 1 0
0
0
0 Reset
Main Status
Register (MSR)
Offset 04h
Bit 0 - Drive 0 Busy
This bit indicates whether or not drive 0 is busy.
It is set to 1 after the last byte of the command phase of
a SEEK or RECALIBRATE command is issued for drive
0.
This bit is cleared to 0 after the first byte in the result
phase of the SENSE INTERRUPT command is read for
drive 0.
0: Not busy.
1: Busy.
Bit 1 - Drive 1 Busy
This bit indicates whether or not drive 1 is busy.
It is set to 1 after the last byte of the command phase of
a SEEK or RECALIBRATE command is issued for drive
1.
This bit is cleared to 0 after the first byte in the result
phase of the SENSE INTERRUPT command is read for
drive 1.
0: Not busy.
1: Busy.
Bit 7 - Extra Density (Enhanced TDR Mode Only)
Together with bit 6, this bit indicates the type of media
currently in the active floppy disk drive. The value of this
bit reflects the state of the MSEN1 signal.
TABLE 5-5 shows how these bits encode media type.
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5
FIGURE 5-9. MSR Register Bitmap
TABLE 5-5. Media Type (Density) Encoding
Media Type
6
Drive 0 Busy
Drive 1 Busy
Drive 2 Busy
Drive 3 Busy
Command in Progress
Non-DMA Execution
Data I/O Direction
RQM
Bit 6 - High Density (Enhanced TDR Mode Only)
Together with bit 7, this bit indicates the type of media
currently in the active floppy disk drive. The value of this
bit reflects the state of the MSEN0 signal.
TABLE 5-5 "Media Type (Density) Encoding" shows
how these bits encode media type.
Bit 6 (MSEN0)
7
Required
Bits 5,4 - Drive ID1,0 Information
If the value of bits 1,0 of the Digital Output Register
(DOR) are 00, these bits reflect the ID of drive 0, i.e., the
value of bits 1,0, respectively, of the Drive ID register at
index F1h. See “Bits 1,0 - Drive 0 ID” on page 41.
If the value of bits 1,0 of the Digital Output Register
(DOR) are 01, these bits reflect the ID of drive 1, i.e., the
value of bits 3,2, respectively, of the Drive ID register at
index F1h. See “Bits 3,2 - Drive 1 ID” on page 41.
Bit 7 (MSEN1)
Main Status Register (MSR)
100
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
Data Rate Select Register (DSR)
This write-only register is used to program the data transfer
rate, amount of write precompensation, power down mode,
and software reset.
The data transfer rate is programmed via the CCR, not the
DSR, for PC-AT, PS/2 and MicroChannel applications. Other applications can set the data transfer rate in the DSR.
The data rate of the floppy controller is determined by the
most recent write to either the DSR or CCR.
The DSR is unaffected by a software reset. A hardware reset sets the DSR to 02h, which corresponds to the default
precompensation setting and a data transfer rate of 250
Kbps.
Bit 3 - Drive 3 Busy
This bit indicates whether or not drive 3 is busy.
It is set to 1 after the last byte of the command phase of
a SEEK or RECALIBRATE command is issued for drive
3.
This bit is cleared to 0 after the first byte in the result
phase of the SENSE INTERRUPT command is read for
drive 3.
0: Not busy.
1: Busy.
7
6
5
4
3
0
0
0
0
0
Write Operations
2 1 0
Data Rate Select
Register (DSR)
0 1 0 Reset
Offset 04h
Required
Data Transfer Rate Select
Bit 4:
Command in Progress
This bit indicates whether or not a command is in
progress. It is set after the first byte of the command
phase is written. This bit is cleared after the last byte of
the result phase is read.
If there is no result phase in a command, the bit is
cleared after the last byte of the command phase is written.
0: No command is in progress.
1: A command is in progress.
Precompensation Delay Select
Undefined
Low Power
Software Reset
FIGURE 5-10. DSR Register Bitmap
Bits 1,0 - Data Transfer Rate Select
These bits determine the data transfer rate for the Floppy Disk Controller (FDC), depending on the supported
speeds. TABLE 5-6 "Data Transfer Rate Encoding"
shows the data transfer rate selected by each value of
this field.
These bits are unaffected by a software reset, and are
set to 10 (250 Kbps) after a hardware reset.
Bit 5:
Non-DMA Execution
This bit indicates whether or not the controller is in the
execution phase of a byte transfer operation in nonDMA mode.
This bit is used for multiple byte transfers by the microprocessor in the execution phase through interrupts or
software polling.
0: The FDC is not in the execution phase.
1: The FDC is in the execution phase.
TABLE 5-6. Data Transfer Rate Encoding
DSR Bits
Data Transfer Rate
Bit 6 - Data I/O (Direction)
Indicates whether the controller is expecting a byte to be
written or read, to or from the Data Register (FIFO).
0: Data will be written to the FIFO.
1: Data will be read from the FIFO.
1
0
0
0
500 Kbps
0
1
300 Kbps
1
0
250 Kbps
Bit 7 - Request for Master (RQM)
This bit indicates whether or not the controller is ready
to send or receive data from the microprocessor through
the Data Register (FIFO). It is cleared to 0 immediately
after a byte transfer and is set to 1 again as soon as the
disk controller is ready for the next byte.
During a Non-DMA execution phase, this bit indicates
the status of the interrupt.
0: Not ready. (Default)
1: Ready to transfer data.
1
1
1 Mbps
Bits 4-2 - Precompensation Delay Select
This field sets the write precompensation delay that the
Floppy Disk Controller (FDC) imposes on the WDATA
disk interface output signal, depending on the supported
speeds. TABLE 5-7 "Write Precompensation Delays"
on page 102 shows the delay for each value of this field.
In most cases, the default delays shown in TABLE 5-8
"Default Precompensation Delays" on page 102 are adequate. However, alternate values may be used for specific drive and media types.
101
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THE FDC REGISTERS
5.3.6
Bit 2 - Drive 2 Busy
This bit indicates whether or not drive 2 is busy.
It is set to 1 after the last byte of the command phase of
a SEEK or RECALIBRATE command is issued for drive
2.
This bit is cleared to 0 after the first byte in the result
phase of the SENSE INTERRUPT command is read for
drive 2.
0: Not busy.
1: Busy.
THE FDC REGISTERS
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
5.3.7
Track 0 is the default starting track number for precompensation. The starting track number can be changed
using the CONFIGURE command.
Data Register (FIFO)
The Data Register of the FDC is a read/write register that is
used to transfer all commands, data and status information
between the microprocessor and the FDC.
TABLE 5-7. Write Precompensation Delays
During the command phase, the microprocessor writes
command bytes into the Data Register after polling the
RQM (bit 7) and DIO (bit 6) bits in the MSR. During the result phase, the microprocessor reads result bytes from the
Data Register after polling the RQM and DIO bits in the
MSR.
DSR Bits
Duration of Delay
4
3
2
0
0
0
Default (TABLE 5-8)
0
0
1
41.7 nsec
0
1
0
83.3 nsec
0
1
1
125.0 nsec
Use of the FIFO buffer lengthens the interrupt latency period and, thereby, reduces the chance of a disk overrun or
underrun error occurring. Typically, the FIFO buffer is used
at a 1 Mbps data transfer rate or with multi-tasking operating
systems.
1
0
0
166.7 nsec
Enabling and Disabling the FIFO Buffer
1
0
1
208.3 nsec
1
1
0
250.0 nsec
The 16-byte FIFO buffer can be used for DMA, interrupt, or
software polling type transfers during the execution of a
read, write, format or scan command.
1
1
1
0.0 nsec
The FIFO buffer is enabled and its threshold is set by the
CONFIGURE command.
When the FIFO buffer is enabled, only execution phase byte
transfers use it. If the FIFO buffer is enabled, it is not disabled after a software reset if the LOCK bit is set in the
LOCK command.
TABLE 5-8. Default Precompensation Delays
Data Rate
Precompensation Delay
1 Mbps
41.7 nsec
500 Kbps
125.0 nsec
300 Kbps
125.0 nsec
250 Kbps
125.0 nsec
The FIFO buffer is always disabled during the command
and result phases of a controller operation. A hardware reset disables the FIFO buffer and sets its threshold to zero.
The MODE command can also disable the FIFO for read or
write operations separately.
After a hardware reset, the FIFO buffer is disabled to maintain compatibility with PC-AT systems.
Bit 5 - Undefined
Should be set to 0.
Burst Mode Enabled and Disabled
Bit 6 - Low Power
This bit triggers a manual power down of the FDC in
which the clock and data separator circuits are turned
off. A manual power down can also be triggered by the
MODE command.
After a manual power down, the FDC returns to normal
power after a software reset, or an access to the Data
Register (FIFO) or the Main Status Register (MSR).
0: Normal power.
1: Trigger power down.
In burst mode, the DRQ or IRQ signal assigned to the FDC
remains active until all of the bytes have been transferred to
or from the FIFO buffer.
The FIFO buffer can be used with burst mode enabled or
disabled by the MODE command.
When burst mode is disabled, the appropriate DRQ or IRQ
signal is deactivated for 350 nsec to allow higher priority
transfer requests to be processed.
FIFO Buffer Response Time
During the execution phase of a command involving data
transfer to or from the FIFO buffer, the maximum time the
system has to respond to a data transfer service request is
calculated by the following formula:
Max_Time = (THRESH + 1) x 8 x tDRP – (16 x tICP)
Bit 7 - Software Reset
This bit controls the same kind of software reset of the
FDC as bit 2 of the Digital Output Register (DOR). The
difference is that this bit is automatically cleared to 0 (no
reset) 100 nsec after it was set to 1.
See also “Bit 2 - Reset Controller” on page 98.
0: No reset. (Default)
1: Reset.
This formula applies for all data transfer rates, whether the
FIFO buffer is enabled or disabled. THRESH is a 4-bit value
programmed by the CONFIGURE command, which sets
the threshold of the FIFO buffer. If the FIFO buffer is disabled, THRESH is zero in the above formula. The last term
in the formula, (16 x tICP) is an inherent delay due to the microcode overhead required by the FDC. This delay is also
data rate dependent. TABLE 14-43 "Nominal tICP, tDRP
Values" on page 245 specifies minimum and maximum values for tDRP and tICP.
The programmable FIFO threshold (THRESH) is useful in
adjusting the FDC to the speed of the system. A slow system with a sluggish DMA transfer capability requires a high
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102
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
7
6
5
4
3
2
1
0
Reset
7
6
1
Read Operations, PS/2 Drive Mode
5 4 3 2 1 0
Digital Input
Register (DIR)
1 1 1
1 Reset
Offset 07h
Required
Data Register
(FIFO)
Offset 05h
High Density
DRATE0 Status
DRATE1 Status
Required
Reserved
DSKCHG
Data
FIGURE 5-13. DIR Register Bitmap, Read Operations,
PS/2 Drive Mode
Bit 0 - High Density (PS/2 Drive Mode Only)
In PC-AT drive mode, this bit is reserved, in TRI-STATE
and used by the status register of the hard disk.
In PS/2 drive mode, this bit indicates whether the data
transfer rate is high or low.
0: The data transfer rate is high, i.e., 1 Mbps or 500 Kbps.
1: The data transfer rate is low, i.e., 300 Kbps or 250 Kbps.
FIGURE 5-11. FDC Data Register Bitmap
5.3.8
Digital Input Register (DIR)
This read-only diagnostic register is used to detect the state
of the DSKCHG disk interface input signal and some diagnostic signals. DIR is unaffected by a software reset.
The bits of the DIR register function differently depending
on whether the FDC is operating in PC-AT drive mode or in
PS/2 drive mode. See Section 5.1.2 "System Operation
Modes" on page 92.
Bits 2,1 - Data Rata Select 1,0 (DRATE1,0)
(PS/2 Drive Mode Only)
In PC-AT drive mode, these bits are reserved, in TRISTATE and used by the status register of the hard disk.
In PS/2 drive mode, these bits indicate the status of the
DRATE1,0 bits programmed in DSR or CCR, whichever
is written last.
The significance of each value for these bits depends on
the supported speeds. See TABLE 5-6 "Data Transfer
Rate Encoding" on page 101.
00: Data transfer rate is 500 Kbps.
01: Data transfer rate is 300 Kbps.
10: Data transfer rate is 250 Kbps.
11: Data transfer rate is 1 Mbps.
In PC-AT drive mode, bits 6 through 0 are in TRI-STATE to
prevent conflict with the status register of the hard disk at
the same address as the DIR.
Read Operations, PC-AT Drive Mode
7 6 5 4 3 2 1 0
Digital Input
Register (DIR)
1 1 1 1
1 Reset
Offset 07h
Required
Reserved, In TRI-STATE
Bits 6-3: Reserved
These bits are reserved and are always 1. In PC-AT
mode these bits are also in TRI-STATE. They are used
by the status register of the fixed hard disk.
DSKCHG
FIGURE 5-12. DIR Register Bitmap, Read Operations,
PC-AT Drive Mode
Bit 7 - Disk Changed (DSKCHG)
This bit reflects the status of the DSKCHG disk interface
input signal.
During power down this bit is invalid, if it is read by the
software.
0: DSKCHG is not active.
1: DSKCHG is active.
103
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THE FDC REGISTERS
value for THRESH. this gives the system more time to respond to a data transfer service request (DRQ for DMA
mode or IRQ for interrupt mode). Conversely, a fast system
with quick response to a data transfer service request can
use a low value for THRESH.
THE PHASES OF FDC COMMANDS
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
5.3.9
Prior to performing the command phase, the Digital Output
Register (DOR) should be set and the data rate should be
set with the Data rate Select Register (DSR) or the Configuration Control Register (CCR).
Configuration Control Register (CCR)
This write-only register can be used to set the data transfer
rate (in place of the DSR) for PC-AT, PS/2 and MicroChannel applications. Other applications can set the data transfer rate in the DSR. See Section 5.3.6 "Data Rate Select
Register (DSR)" on page 101.
The Main Status Register (MSR) controls the flow of command bytes, and must be polled by the software before writing each command phase byte to the Data Register (FIFO).
Prior to writing a command byte, bit 7 of MSR (RQM, Request for Master) must be set and bit 6 of MSR (DIO, Data
I/O direction) must be cleared.
This register is not affected by a software reset.
The data rate of the floppy controller is determined by the
last write to either the CCR register or to the DSR register.
After the first command byte is written to the Data Register
(FIFO), bit 4 of MSR (CMD PROG, Command in Progress)
is also set and remains set until the last result phase byte is
read. If there is no result phase, the CMD PROG bit is
cleared after the last command byte is written.
Write Operations
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
Configuration Control
Register (CCR)
0 Reset
Offset 07h
Required
A new command may be initiated after reading all the result
bytes from the previous command. If the next command requires selection of a different drive or a change in the data
rate, the DOR and DSR or CCR should be updated, accordingly. If the command is the last command, the software
should deselect the drive.
DRATE0
DRATE1
Normally, command processing by the controller core and
updating of the DOR, DSR, and CCR registers by the microprocessor are operations that can occur independently of
one another. Software must ensure that the these registers
are not updated while the controller is processing a command.
Reserved
FIGURE 5-14. CCR Register Bitmap
5.4.2
Bits 1,0 - Data Transfer Rate Select 1,0 (DRATE 1,0)
These bits determine the data transfer rate for the Floppy Disk Controller (FDC), depending on the supported
speeds.
TABLE 5-6 "Data Transfer Rate Encoding" on page 101
shows the data transfer rate selected by each value of
this field.
These bits are unaffected by a software reset, and are
set to 10 (250 Kbps) after a hardware reset.
During the execution phase, the Floppy Disk Controller
(FDC) performs the desired command.
Commands that involve data transfers (e.g., read, write and
format operations) require the microprocessor to write or
read data to or from the Data Register (FIFO) at this time.
Some commands, such as SEEK or RECALIBRATE, control the read/write head movement on the disk drive during
the execution phase via the disk interface signals. Execution of other commands does not involve any action by the
microprocessor or disk drive, and consists of an internal operation by the controller.
Bits 7-2 - Reserved
These bits are reserved and should be set to 0.
5.4
Data can be transferred between the microprocessor and
the controller during execution in DMA mode, interrupt
transfer mode or software polling mode. The last two modes
are non-DMA modes. All data transfer modes work with the
FIFO enabled or disabled.
THE PHASES OF FDC COMMANDS
FDC commands may be in the command phase, the execution phase or the result phase. The active phase determines
how data is transferred between the Floppy Disk Controller
(FDC) and the host microprocessor. When no command is
in progress, the FDC may be either idle or polling a drive.
5.4.1
DMA mode is used if the system has a DMA controller. This
allows the microprocessor to do other tasks while data
transfer takes place during the execution phase.
If a non-DMA mode is used, an interrupt is issued for each
byte transferred during the execution phase. Also, instead
of using the interrupt during a non-DMA mode transfer, the
Main Status Register (MSR) can be polled by software to indicate when a byte transfer is required.
Command Phase
During the command phase, the microprocessor writes a
series of bytes to the Data Register (FIFO). The first command byte contains the opcode for the command, which the
controller can interpret to determine how many more command bytes to expect. The remaining command bytes contain the parameters required for the command.
DMA Mode - FIFO Disabled
DMA mode is selected by writing a 0 to the DMA bit in the
SPECIFY command and by setting bit 3 of the DOR (DMA
enabled) to 1.
The number of command bytes varies for each command.
All command bytes must be written in the order specified in
the Command Description Table in Section 5.7 "THE FDC
COMMAND SET" on page 112. The execution phase starts
immediately after the last byte in the command phase is
written.
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Execution Phase
In the execution phase when the FIFO is disabled, each
time a byte is ready to be transferred, a DMA request (DRQ)
is generated in the execution phase. The DMA controller
should respond to the DRQ with a DMA acknowledge
(DACK) and a read or write pulse. The DRQ is cleared by
104
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
Whenever the number of bytes in the FIFO is less than or
equal to THRESH, a DRQ is generated. This is the trigger
condition for the FIFO write data transfers from the microprocessor to the FDC.
During DMA operations, FDC address signals are ignored
since AEN input signal is 1. The DACK signal acts as the
chip select signal for the FIFO, in this case, and the state of
the address lines A2-0 is ignored. The Terminal Count (TC)
signal can be asserted by the DMA controller to terminate
the data transfer at any time. Due to internal gating, TC is
only recognized when DACK is low.
Burst Mode Enabled - DRQ remains active until enough
bytes have been written to the controller to completely
fill the FIFO.
Burst Mode Disabled - DRQ is deactivated after each
write transfer. If the FIFO is not full, DRQ is asserted
again after a 350 nsec delay. Deactivation of DRQ allows other higher priority DMA transfers to take place
between floppy disk transfers.
PC-AT Drive Mode
In PC-AT drive mode when the FIFO is disabled, the controller is in single byte transfer mode. That is, the system
has the time it takes to transfer one byte, to service a DMA
request (DRQ) from the controller. DRQ is deactivated between bytes.
The FIFO has a byte counter which monitors the number of
bytes being transferred to the FIFO during write operations
whether burst mode is enabled or disabled. When the last
byte of a sector is transferred to the FIFO, DRQ is deactivated even if the FIFO has not been completely filled. Thus,
the FIFO is cleared after each sector is written. Only after
the FDC has determined that another sector is to be written,
is DRQ asserted again. Also, since DRQ is deactivated immediately after the last byte of a sector is written to the
FIFO, the system will not be delayed by deactivation of
DRQ and is free to do other operations.
PS/2 Drive Mode
In PS/2 drive mode, for DMA transfers with the FIFO disabled, instead of single byte transfer mode, the FIFO is enabled with THRESH = 0Fh. Thus, DRQ is asserted when
one byte enters the FIFO during a read, and when one byte
can be written to the FIFO during a write. DRQ is deactivated by the leading edge of the DACK input signal, and is asserted again when DACK becomes inactive high. This
operation is very similar to burst mode transfer with the
FIFO enabled except that DRQ is deactivated between
bytes.
Read and Write Data Transfers
The DACK input signal from the DMA controller may be held
active during an entire burst, or a pulse may be issued for
each byte transferred during a read or write operation. In
burst mode, the FDC deactivates DRQ as soon as it recognizes that the last byte of a burst was transferred.
DMA Mode - FIFO Enabled
Read Data Transfers
If a DACK pulse is issued for each byte, the leading edge of
this pulse is used to deactivate DRQ. If a DACK pulse is issued, RD or WR is not required. This is the case during the
read-verify mode of the DMA controller.
Whenever the number of bytes in the FIFO is greater than
or equal to (16 − THRESH), a DRQ is generated. This is the
trigger condition for the FIFO read data transfers from the
floppy controller to the microprocessor.
If DACK is held active during the entire burst, the trailing
edge of the RD or WR pulse is used to deactivate DRQ.
DRQ is deactivated within 50 nsec of the leading edge of
DACK, RD, or WR. This quick response should prevent the
DMA controller from transferring extra bytes in most applications.
When the last byte in the FIFO has been read, DRQ becomes inactive. DRQ is asserted again when the FIFO trigger condition is satisfied. After the last byte of a sector is
read from the disk, DRQ is again generated even if the FIFO
has not yet reached its threshold trigger condition. This
guarantees that all current sector bytes are read from the
FIFO before the next sector byte transfer begins.
Overrun Errors
Burst Mode Enabled - DRQ remains active until enough
bytes have been read from the controller to empty the
FIFO.
An overrun or underrun error terminates the execution of a
command, if the system does not transfer data within the allotted data transfer time. (See Section 5.3.7 "Data Register
(FIFO)" on page 102.) This puts the controller in the result
phase.
Burst Mode Disabled - DRQ is deactivated after each
read transfer. If the FIFO is not completely empty, DRQ
is asserted again after a 350 nsec delay. This allows
other higher priority DMA transfers to take place between floppy disk transfers.
In addition, this mode allows the controller to work correctly in systems where the DMA controller is put into a
read verify mode, where only DACK signals are sent to
the FDC, with no RD pulses. This read verify mode of
the DMA controller is used in some PC software. When
burst mode is disabled, a pulse from the DACK input
signal may be issued by the DMA controller, to correctly
clocks data from the FIFO.
During a read overrun, the microprocessor is required to
read the remaining bytes of the sector before the controller
asserts the appropriate IRQ signifying the end of execution.
During a write operation, an underrun error terminates the
execution phase after the controller has written the remaining bytes of the sector with the last correctly written byte to
the FIFO. Whether there is an error or not, an interrupt is
generated at the end of the execution phase, and is cleared
by reading the first result phase byte.
DACK asserted alone, without a RD or WR pulse, is also
counted as a transfer. If pulses of RD or WR are not being
issued for each byte, a DACK pulse must be issued for each
byte so that the Floppy Disk Controller(FDC) can count the
number of bytes correctly.
105
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THE PHASES OF FDC COMMANDS
Write Data Transfers
the leading edge of the active low DACK input signal. After
the last byte is transferred, an interrupt is generated, indicating the beginning of the result phase.
THE PHASES OF FDC COMMANDS
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
The VERIFY command, allows easy verification of data
written to the disk without actually transferring the data on
the data bus.
signal. Otherwise, the data transfer is similar to the interrupt
mode described above, whether the FIFO is enabled or disabled.
Interrupt Transfer Mode - FIFO Disabled
5.4.3
If interrupt transfer (non-DMA) mode is selected, the appropriate IRQ signal is asserted instead of DRQ, when each
byte is ready to be transferred.
During the result phase, the microprocessor reads a series
of result bytes from the Data Register (FIFO). These bytes
indicate the status of the command. They may indicate
whether the command executed properly, or may contain
some control information.
The Main Status Register (MSR) should be read to verify
that the interrupt is for a data transfer. The RQM and NON
DMA bits (bits 7 and 5, respectively) in the MSR are set to
1. The interrupt is cleared when the byte is transferred to or
from the Data Register (FIFO). To transfer the data in or out
of the Data register, you must use the address bits of the
FDC together and RD or WR must be active, i.e., A2-0 must
be valid. It is not enough to just assert the address bits of
the FDC. RD or WR must also be active for a read or write
transfer to be recognized.
Result Phase
See the specific commands in Section 5.7 "THE FDC COMMAND SET" on page 112 or Section 5.3.7 "Data Register
(FIFO)" on page 102 for details.
These result bytes are read in the order specified for that
particular command. Some commands do not have a result
phase. Also, the number of result bytes varies with each
command. All result bytes must be read from the Data Register (FIFO) before the next command can be issued.
The microprocessor should transfer the byte within the data
transfer service time (see Section 5.3.7 "Data Register
(FIFO)" on page 102). If the byte is not transferred within the
time allotted, an overrun error is indicated in the result
phase when the command terminates at the end of the current sector.
As it does for command bytes, the Main Status Register
(MSR) controls the flow of result bytes, and must be polled
by the software before reading each result byte from the
Data Register (FIFO). The RQM bit (bit 7) and DIO bit (bit 6)
of the MSR must both be set before each result byte can be
read.
An interrupt is also generated after the last byte is transferred. This indicates the beginning of the result phase. The
RQM and DIO bits (bits 7 and 6, respectively) in the MSR
are set to 1, and the NON DMA bit (bit 5) is cleared to 0. This
interrupt is cleared by reading the first result byte.
After the last result byte is read, the Command in Progress
bit (bit 4) of the MSR is cleared, and the controller is ready
for the next command.
For more information, see Section 5.5 "THE RESULT
PHASE STATUS REGISTERS" on page 107.
Interrupt Transfer Mode - FIFO Enabled
5.4.4
Interrupt transfer (non-DMA) mode with the FIFO enabled is
very similar to interrupt transfer mode with the FIFO disabled. In this case, the appropriate IRQ signal is asserted
instead of DRQ, under the same FIFO threshold trigger conditions.
After a hardware or software reset, after the chip has recovered from power-down mode or when there are no commands in progress the controller is in the idle phase. The
controller waits for a command byte to be written to the Data
Register (FIFO). The RQM bit is set, and the DIO bit is
cleared in the MSR.
The MSR should be read to verify that the interrupt is for a
data transfer. The RQM and non-DMA bits (bits 7 and 5, respectively) in the MSR are set. To transfer the data in or out
of the Data register, you must use the address bits of the
FDC together and RD or WR must be active, i.e., A2-0 must
be valid. It is not enough to just assert the address bits of
the FDC. RD or WR must also be active for a read or write
transfer to be recognized.
After receiving the first command (opcode) byte, the controller enters the command phase. When the command is
completed the controller again enters the idle phase. The
Digital Data Separator (DDS) remains synchronized to the
reference frequency while the controller is idle. While in the
idle phase, the controller periodically enters the drive polling
phase.
Burst mode may be used to hold the IRQ signal active during a burst, or burst mode may be disabled to toggle the IRQ
signal for each byte of a burst. The Main Status Register
(MSR) is always valid to the microprocessor. For example,
during a read command, after the last byte of data has been
read from the disk and placed in the FIFO, the MSR still indicates that the execution phase is active, and that data
needs to be read from the Data Register (FIFO). Only after
the last byte of data has been read by the microprocessor
from the FIFO does the result phase begin.
5.4.5
Drive Polling Phase
National Semiconductor’s FDC supports the polling mode
of old 8-inch drives, as a means of monitoring any change
in status for each disk drive present in the system. This support provides backward compatibility with software that expects it.
In the idle phase, the controller enters a drive polling phase
every 1 msec, based on a 500 Kbps data transfer rate. In
the drive polling phase, the controller checks the status of
each of the logical drives (bits 0 through 3 of the MSR). The
internal ready line for each drive is toggled only after a hardware or software reset, and an interrupt is generated for
drive 0.
The overrun and underrun error procedures for non-DMA
mode are the same as for DMA mode. Also, whether there
is an error or not, an interrupt is generated at the end of the
execution phase, and is cleared by reading the first result
phase byte.
At this point, the software must issue four SENSE INTERRUPT commands to clear the status bit for each drive, unless drive polling is disabled via the POLL bit in the
CONFIGURE command. See “Bit 4 - Disable Drive Polling
(POLL)” on page 114. The CONFIGURE command must be
issued within 500 µsec (worst case) of the hardware or software reset to disable drive polling.
Software Polling
If non-DMA mode is selected and interrupts are not suitable,
the microprocessor can poll the MSR during the execution
phase to determine when a byte is ready to be transferred.
The RQM bit (bit 7) in the MSR reflects the state of the IRQ
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Idle Phase
106
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
The controller also uses the drive polling phase to automatically trigger power down. When the specified time that the
motor may be off expires, the controller waits 512 msec,
based on data transfer rates of 500 Kbps and 1 Mbps, before powering down, if this function is enabled via the
MODE command.
Bit 3 - Not used.
This bit is not used and is always 0.
Bit 4 - Equipment Check
After a RECALIBRATE command, this bit indicates
whether the head of the selected drive was at track 0,
i.e., whether or not TRK0 was active. This information is
used during the SENSE INTERRUPT command.
0: Head was at track 0, i.e., a TRK0 pulse occurred
after a RECALIBRATE command.
1: Head was not at track 0, i.e., no TRK0 pulse occurred after a RECALIBRATE command.
If a new command is issued while the FDC is in the drive
polling phase, the MSR does not indicate a ready status for
the next parameter byte until the polling sequence completes the loop. This can cause a delay between the first
and second bytes of up to 500 µsec at 250 Kbps.
5.5
THE RESULT PHASE STATUS REGISTERS
In the result phase of a command, result bytes that hold status information are read from the Data Register (FIFO) at
offset 05h. These bytes are the result phase status registers.
Bit 5 - SEEK End
This bit indicates whether or not a SEEK, RELATIVE
SEEK, or RECALIBRATE command was completed by
the controller. Used during a SENSE INTERRUPT command.
0: SEEK, RELATIVE SEEK, or RECALIBRATE command not completed by the controller.
1: SEEK, RELATIVE SEEK, or RECALIBRATE command was completed by the controller.
The result phase status registers may only be read from the
Data Register (FIFO) during the result phase of certain
commands, unlike the Main Status Register (MSR), which
is a read only register that is always valid.
5.5.1
Result Phase Status Register 0 (ST0)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Result Phase Status
Register 0 (ST0)
0 Reset
Bits 7,6 - Interrupt Code (IC)
These bits indicate the reason for an interrupt.
00: Normal termination of command.
01: Abnormal termination of command. Execution of
command was started, but was not successfully
completed.
10: Invalid command issued. Command issued was not
recognized as a valid command.
11: Internal drive ready status changed state during the
drive polling mode. This only occurs after a hardware or software reset.
Required
Logical Drive Selected
(Execution Phase)
Head Selected (Execution Phase)
Not Used
Equipment Check
SEEK End
Interrupt Code
5.5.2
FIGURE 5-15. ST0 Result Phase Register Bitmap
Bits 1,0 - Logical Drive Selected
These two binary encoded bits indicate the logical drive
selected at the end of the execution phase.
The value of these bits is reflected in bits 1,0 of the SR3
register, described in Section 5.5.4 "Result Phase Status Register 3 (ST3)" on page 109.
00: Drive 0 selected.
01: Drive 1 selected.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11: If four drives are supported, drive 3 is selected.
Result Phase Status Register 1 (ST1)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Result Phase Status
Register 1 (ST1)
0 Reset
Required
Missing Address Mark
Drive Write Protected
Missing Data
Not Used
Overrun or Underrun
CRC Error
Not Used
End of Track
Bit 2 - Head Selected
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected. It reflects the status of the HDSEL
signal at the end of the execution phase.
FIGURE 5-16. ST1 Result Phase Register Bitmap
107
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THE RESULT PHASE STATUS REGISTERS
The value of this bit is reflected in bit 2 of the ST3 register, described in Section 5.5.4 "Result Phase Status
Register 3 (ST3)" on page 109.
0: Side 0 is selected.
1: Side 1 is selected.
Even if drive polling is disabled, drive stepping and delayed
power-down occur in the drive polling phase. The controller
checks the status of each drive and, if necessary, it issues
a pulse on the STEP output signal with the DIR signal at the
appropriate logic level.
THE RESULT PHASE STATUS REGISTERS
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
Bit 7 - End of Track
This bit is set to 1 when the FDC transfers the last byte
of the last sector without the TC signal becoming active.
The last sector is the End of Track sector number programmed in the command phase.
0: The FDC did not transfer the last byte of the last
sector without the TC signal becoming active.
1: The FDC transferred the last byte of the last sector
without the TC signal becoming active.
Bit 0 - Missing Address Mark
This bit indicates whether or not the Floppy Disk Controller (FDC) failed to find an address mark in a data field
during a read, scan, or verify command.
0: No missing address mark.
1: Address mark missing.
Bit 0 of the result phase Status register 2 (ST2) indicates the when and where the failure occurred.
See Section 5.5.3 "Result Phase Status Register 2
(ST2)" on page 108.
5.5.3
Bit 1 - Drive Write Protected
When a write or format command is issued, this bit indicates whether or not the selected drive is write protected, i.e., the WP signal is active.
0: Selected drive is not write protected, i.e., WP is not
active.
1: Selected drive is write protected, i.e., WP is active.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Result Phase Status
Register 2 (ST2)
0 Reset
Required
Missing Address
Mark Location
Bad Track
Scan Not Satisfied
Scan Equal Hit
Wrong Track
CRC Error in Data Field
Control Mark
Not Used
Bit 2 - Missing Data
This bit indicates whether or not data is missing for one
of the following reasons:
— Controller cannot find the sector specified in the
command phase during the execution of a read,
write, scan, or VERIFY command. An Address Mark
(AM) was found however, so it is not a blank disk.
— Controller cannot read any address fields without a
CRC error during a READ ID command.
— Controller cannot find starting sector during execution of READ A TRACK command.
0: Data is not missing for one of these reasons.
1: Data is missing for one of these reasons.
FIGURE 5-17. ST2 Result Phase Register Bitmap
Bit 0 - Missing Address Mark Location
If the FDC cannot find the address mark of a data field
or of an address field during a read, scan, or verify command, i.e., bit 0 of ST1 is 1, this bit indicates when and
where the failure occurred.
0: The FDC failed to detect an address mark for the
address field after two disk revolutions.
1: The FDC failed to detect an address mark for the
data field after it found the correct address field.
Bit 3 - Not Used
This bit is not used and is always 0.
Bit 4 - Overrun or Underrun
This bit indicates whether or not the FDC was serviced
by the microprocessor soon enough during a data transfer in the execution phase. For read operations, this bit
indicates a data overrun. For write operations, it indicates a data underrun.
0: FDC was serviced in time.
1: FDC was not serviced fast enough. Overrun or underrun occurred.
Bit 1 - Bad Track
This bit indicates whether or not the FDC detected a bad
track
0: No bad track detected.
1: Bad track detected.
The desired sector is not found. If the track number
recorded on any sector on the track is FFh and this
number is different from the track address specified
in the command phase, then there is a hard error in
IBM format.
Bit 5 - CRC Error
This bit indicates whether or not the FDC detected a Cyclic Redundancy Check (CRC) error.
0: No CRC error detected.
1: CRC error detected.
Bit 5 of the result phase Status register 2 (ST2) indicates when and where the error occurred. See
Section 5.5.3 "Result Phase Status Register 2
(ST2)".
Bit 2 - Scan Not Satisfied
This bit indicates whether or not the value of the data
byte from the microprocessor meets any of the conditions specified by the scan command used.
Section
5.7.16
"The
SCAN
EQUAL,
the SCAN LOW OR EQUAL and the SCAN HIGH OR
EQUAL Commands" on page 128 and TABLE 5-21
"The Effect of Scan Commands on the ST2 Register" on
page 129 describe the conditions.
0: The data byte from the microprocessor meets at
least one of the conditions specified.
1: The data byte from the microprocessor does not
meet any of the conditions specified.
Bit 6 - Not Used
This bit is not used and is always 0.
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Result Phase Status Register 2 (ST2)
108
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
Bit 2 - Head Selected
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected. It reflects the status of the HDSEL
signal at the end of the command phase.
The value of this bit is the same as bit 2 of the SR0 register, described in Section 5.5.1 "Result Phase Status
Register 0 (ST0)" on page 107.
0: Side 0 is selected.
1: Side 1 is selected.
Bit 4 - Wrong Track
This bit indicates whether or not there was a problem
finding the sector because of the track number.
0: Sector found.
1: Desired sector not found.
The desired sector is not found. The track number
recorded on any sector on the track is different
from the track address specified in the command
phase.
Bit 3 - Not Used
This bit is not used and is always 1.
Bit 5 - CRC Error in Data Field
When the FDC detected a CRC error in the correct sector (bit 5 of the result phase Status register 1 (ST1) is 1),
this bit indicates whether it occurred in the address field
or in the data field.
0: The CRC error occurred in the address field.
1: The CRC error occurred in the data field.
Bit 4 - Track 0
This bit Indicates whether or not the head of the selected drive is at track 0.
0: The head of the selected drive is not at track 0, i.e.,
TRK0 is not active.
1: The head of the selected drive is at track 0, i.e.,
TRK0 is active.
Bit 6 - Control Mark
When the controller tried to read a sector, this bit indicates whether or not it detected a deleted data address
mark during execution of a READ DATA or scan commands, or a regular address mark during execution of a
READ DELETED DATA command.
0: No control mark detected.
1: Control mark detected.
Bit 5 - Not Used
This bit is not used and is always 1.
Bit 6 - Drive Write Protected
This bit indicates whether or not the selected drive is
write protected, i.e., the WP signal is active (low).
0: Selected drive is not write protected, i.e., WP is not
active.
1: Selected drive is write protected, i.e., WP is active.
Bit 7 - Not Used
This bit is not used and is always 0.
5.5.4
Bit 7 - Not Used
This bit is not used and is always 0.
Result Phase Status Register 3 (ST3)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
5.6
Result Phase Status
Register 3 (ST3)
0 Reset
FDC REGISTER BITMAPS
5.6.1
Standard
Required
PS/2 Drive Mode
Logical Drive Selected
(Command Phase)
Head Selected (Command Phase)
Not Used
Track 0
Not Used
Drive Write Protected
Not Used
7
0
6
5
0
4
3
0
2
1
0
0 Reset
Status Register
A (SRA)
Offset 00h
Required
Head Direction
WP
INDEX
Head Select
TRK0
Step
Reserved
IRQ Pending
FIGURE 5-18. ST3 Result Phase Register Bitmap
Bits 1,0 - Logical Drive Selected
These two binary encoded bits indicate the logical drive
selected at the end of the command phase.
The value of these bits is the same as bits 1,0 of the SR0
register, described in Section 5.5.1 "Result Phase Status Register 0 (ST0)" on page 107.
109
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FDC REGISTER BITMAPS
00: Drive 0 selected.
01: Drive 1 selected.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11: If four drives are supported, drive 3 is selected.
Bit 3 - Scan Satisfied
This bit indicates whether or not the value of the data
byte from the microprocessor was equal to a byte on the
floppy disk during any scan command.
0: No equal byte was found.
1: A byte whose value is equal to the byte from the
microprocessor was found on the floppy disk.
FDC REGISTER BITMAPS
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
PS/2 Drive Mode
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0 Reset
1
1
Status Register
B (SRB)
Offset 01h
7
6
5
4
3
0
0
0
0
0
0
6
0
0
0
0 Reset
5
0
4
0
3
0
2
0
1
0
0
0 Reset
Main Status
Register (MSR)
Offset 04h
Required
Required
Drive 0 Busy
Drive 1 Busy
Drive 2 Busy
Drive 3 Busy
Command in Progress
Non-DMA Execution
Data I/O Direction
RQM
MTR0
MTR1
WGATE
RDATA
WDATA
DR0
Reserved
Reserved
7
Read Operations
2 1 0
Digital Output
Register (DOR)
Offset 02h
Required
7
6
5
4
3
0
0
0
0
0
Drive Select
Reset Controller
DMAEN
Motor Enable 0
Motor Enable 1
Motor Enable 2
Motor Enable 3
Write Operations
2 1 0
0
1
Data Rate Select
Register (DSR)
Offset 04h
Required
0 Reset
DRATE0
DRATE1
Precompensation Delay Select
Undefined
Low Power
Software Reset
PC-AT Compatible Drive Mode
7
6
5
4
1
3
2
1
0
0
0 Reset
Tape Drive
Register (TDR)
Offset 03h
7
6
5
4
3
2
1
0
Reset
Required
Data Register
(FIFO)
Offset 05h
Required
Tape Drive Select 1,0
Data
Not Used
TRI-STATE During Read Operations
7
6
5
4
1
Enhanced Drive Mode
3 2 1 0
Tape Drive
Register (TDR)
0 0 Reset
Offset 03h
Required
7
6
1
Read Operations, PC-AT Drive Mode
5 4 3 2 1 0
Digital Input
Register (DIR)
1 1 1
1 Reset
Offset 07h
Required
Tape Drive Select 1,0
Logical Drive Exchange
Drive ID0 Information
Drive ID1 Information
High Density
Extra Density
Reserved, In TRI-STATE
DSKCHG
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110
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
7
6
5
4
3
1
1
1
1
2
1
0
1 Reset
Digital Input
Register (DIR)
Offset 07h
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Result Phase Status
Register 1 (ST1)
0 Reset
Required
Required
Missing Address Mark
Drive Write Protected
Missing Data
Not Used
Overrun or Underrun
CRC Error
Not Used
End of Track
High Density
DRATE0 Status
DRATE1 Status
Reserved
DSKCHG
Write Operations
7
6
5
4
3
2
1
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Result Phase Status
Register 2 (ST2)
0 Reset
0
Configuration Control
Register (CCR)
0 Reset
Offset 07h
Required
Required
Missing Address
Mark Location
Bad Track
Scan Not Satisfied
Scan Equal Hit
Wrong Track
CRC Error in Data Field
Control Mark
Not Used
DRATE0
DRATE1
Reserved
5.6.2
0
Result Phase Status
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Result Phase Status
Register 3 (ST3)
0 Reset
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Result Phase Status
Register 0 (ST0)
0 Reset
Logical Drive Selected
(Command Phase)
Head Selected (Command Phase)
Not Used
Track 0
Not Used
Drive Write Protected
Not Used
Required
Logical Drive Selected
(Execution Phase)
Head Selected (Execution Phase)
Not Used
Equipment Check
SEEK End
Interrupt Code
111
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FDC REGISTER BITMAPS
Read Operations, PS/2 Drive Mode
THE FDC COMMAND SET
5.7
THE FDC COMMAND SET
TABLE 5-9. FDC Command Set Summary
The first command byte for each command in the FDC command set is the opcode byte. The FDC uses this byte to determine how many command bytes to expect.
Opcode
Command
7
6
5
4 3 2 1 0
CONFIGURE
0
0
0
1 0 0 1 1
TABLE 5-9 "FDC Command Set Summary" shows the FDC
commands in alphabetical order with the opcode, i.e., the
first command byte, for each.
DUMPREG
0
0
0
0 1 1 1 0
FORMAT TRACK
0
MFM
0
0 1 1 0 1
In this table:
INVALID
If an invalid command byte is issued to the controller, it immediately enters the result phase and the status is 80h, signifying an invalid command.
●
MT is a multi-track enable bit (See “Bit 7 - Multi-Track
(MT)” on page 122.)
●
MFM is a modified frequency modulation parameter
(See “Bit 6 - Modified Frequency Modulation (MFM)”
on page 116.)
●
Invalid Opcode
LOCK
SK is a skip control bit. (See “Bit 5 - Skip Control (SK)”
on page 122.)
Section 5.7.1 "Abbreviations Used in FDC Commands" on
page 113 explains some symbols and abbreviations you will
encounter in the descriptions of the commands.
0
0
1 0 1 0 0
MODE
0
0
0
0 0 0 0 1
NSC
0
0
0
1 1 0 0 0
PERPENDICULAR
MODE
0
0
0
1 0 0 1 0
READ DATA
MT
MFM
SK
0 0 1 1 0
READ DELETED
DATA
MT
MFM
SK
0 1 1 0 0
All phases of each command are described in detail, starting with Section 5.7.2 "The CONFIGURE Command" on
page 114, with bitmaps of each byte in each phase.
READ ID
0
MFM
0
0 1 0 1 0
READ TRACK
0
MFM
0
0 0 0 1 0
Only named bits and fields are described in detail. When a
bitmap shows a value (0 or 1) for a bit, that bit must have
that value and is not described.
RECALIBRATE
0
0
0
0 0 1 1 1
RELATIVE SEEK
1
DIR
0
0 1 1 1 1
SCAN EQUAL
MT
MFM
SK
1 0 0 0 1
SCAN HIGH OR
EQUAL
MT
MFM
SK
1 1 1 0 1
SCAN LOW OR
EQUAL
MT
MFM
SK
1 1 0 0 1
SEEK
0
0
0
0 1 1 1 1
SENSE DRIVE
STATUS
0
0
0
0 0 1 0 0
SENSE INTERRUPT
0
0
0
0 1 0 0 0
SET TRACK
0
1
0 0 0 0 1
SPECIFY
0
0
0
0 0 0 1 1
MT
MFM
SK
1 0 1 1 0
0
0
0
1 0 0 0 0
WRITE DATA
MT
MFM
0
0 0 1 0 1
WRITE DELETED
DATA
MT
MFM
0
0 1 0 0 1
VERIFY
VERSION
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112
BFR
BST
IPS
Abbreviations Used in FDC Commands
Buffer enable bit set in the MODE command. Enables open-collector output buffers.
LOCK Lock enable bit in the LOCK command. Used to
prevent certain parameters from being affected by
a software reset.
Burst mode disable control bit set in MODE command. Disables burst mode for the FIFO, if the
FIFO is enabled.
LOW PWR
Low Power control bits set in the MODE command.
DC3-0 Drive Configuration for drives 3-0. Used to configure a logical drive to conventional or perpendicular
mode in the PERPENDICULAR MODE command.
MFM Modified Frequency Modulation parameter used in
FORMAT TRACK, read, VERIFY and write commands.
DENSEL
Density Select control bits set in the MODE command.
DIR
Direction control bit used in RELATIVE SEEK command to indicate step in or out.
DMA DMA mode enable bit set in the SPECIFY command.
EIS
EOT
ETR
Enable Count control bit set in the VERIFY command. When this bit is 1, SC (Sectors to read
Count) command byte is required.
Enable Implied Seeks. Set in the CONFIGURE
command.
Motor Off Time. Now called Delay After Processing
time. This delay is set by the SPECIFY command.
MNT
Motor On Time. Now called Delay Before Processing time. This delay is set by the SPECIFY command.
MT
Multi-Track enable bit used in read, write, scan and
VERIFY commands.
OW
Overwrite control bit set in the PERPENDICULAR
MODE command.
POLL Enable Drive Polling bit set in the CONFIGURE
command.
End of Track parameter set in read, write, scan,
and VERIFY commands.
PRETRK
Precompensation Track Number set in the CONFIGURE command
Extended Track Range set in the MODE command.
FIFO First-In First-Out buffer. Also a control bit set in the
CONFIGURE command to enable or disable the
FIFO.
FRD
MFT
MSB Most Significant Byte controls which whether the
most or least significant byte is read or written in
the SET TRACK command.
DS1-0 Drive Select for bits 1,0 used in most commands.
Selects the logical drive.
EC
PTR
FIFO Read Disable control bit set in the MODE
command
Gap 2 The length of gap 2 in the FORMAT TRACK command and the portion of it that is rewritten in the
WRITE DATA command depend on the drive mode,
i.e., perpendicular or conventional. FIGURE 5-19
"IBM, Perpendicular, and ISO Formats Supported
by the FORMAT TRACK Command" on page 118
illustrates gap 2 graphically. For more details, see
“Bits 1,0 - Group Drive Mode Configuration (GDC)”
on page 121.
Gap 3 Gap 3 is the space between sectors, excluding the
synchronization field. It is defined in the FORMAT
TRACK command. See FIGURE 5-19.
RTN
Relative Track Number used in the RELATIVE
SEEK command.
SC
Sector Count control bit used in the VERIFY command.
SK
Skip control bit set in read and scan and VERIFY
operations.
SRT
Step Rate Time set in the SPECIFY command. Determines the time between STEP pulses for SEEK
and RECALIBRATE operations.
ST0-3
Result phase Status registers 3-0 that contain status information about the execution of a command.
See Sections 5.5.1 "Result Phase Status Register
0 (ST0)" on page 107 through 5.5.4 "Result Phase
Status Register 3 (ST3)" on page 109.
GDC Group Drive Configuration for all drives. Configures
all logical drives as conventional or perpendicular.
Used in the PERPENDICULAR MODE command.
Formerly, GAP2 and WG.
Head Select control bit used in most commands.
Selects Head 0 or 1 of the disk.
IAF
Index Address Field control bit set in the MODE
command. Enables the ISO Format during the
FORMAT command.
Present Track number. Contains the internal 8-bit
track number or the least significant byte of the 12bit track number of one of the four logical disk
drives. PTR is set in the SET TRACK command.
R255 Recalibration control bit set in MODE command.
Sets maximum number of STEP pulses during
RECALIBRATE command to 255.
FWR FIFO Write disable control bit set in the MODE
command.
HD
Implied Seek enable bit set in the MODE, read,
write, and scan commands.
THRESH
FIFO threshold parameter set in the CONFIGURE
command
TMR
113
Timer control bit set in the MODE command. Affects the timers set in the SPECIFY command.
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THE FDC COMMAND SET
5.7.1
THE FDC COMMAND SET
WG
0: FIFO enabled for read and write operations.
1: FIFO disabled. (Default)
Formerly, the Write Gate control bit. Now included
in the Group Drive mode Configuration (GDC) bits
in the PERPENDICULAR MODE command.
Bit 6 - Enable Implied Seeks (EIS)
This bit enables or disables implied seek operations. A
software reset disables implied seeks, i.e., clears this bit
to 0.
Bit 5 of the MODE command (Implied Seek (IPS) can
override the setting of this bit and enable implied seeks
even if they are disabled by this bit.
When implied seeks are enabled, a seek or sense interrupt operation is performed before execution of the read,
write, scan, or verify operation.
0: Implied seeks disabled. The MODE command can
still enable implied seek operations. (Default)
1: Implied seeks enabled for read, write, scan and
VERIFY operations, regardless of the value of the
IPS bit in the MODE command.
WLD Wildcard bit in the MODE command used to enable
or disable the wildcard byte (FFh) during scan commands.
WNR Write Number controls whether to read an existing
track number or to write a new one in the SET
TRACK command.
5.7.2
The CONFIGURE Command
The CONFIGURE command controls some operation
modes of the controller. It should be issued during the initialization of the FDC after power up.
The bits in the CONFIGURE registers are set to their default
values after a hardware reset.
Command Phase
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
EIS
FIFO POLL
Fourth Command Phase Byte, Bits 7-0,
Precompensation Track Number (PRETRK)
This byte identifies the starting track number for write
precompensation. The value of this byte is programmable from track 0 (00h) to track 255 (FFh).
If the LOCK bit (bit 7 of the opcode of the LOCK command) is 0, after a software reset this byte indicates
track 0 (00h).
If the LOCK bit is 1, PRETRK retains its previous value
after a software reset.
Threshold (THRESH)
Precompensation Track Number (PRETRK)
Third Command Phase Byte
Execution Phase
Bits 3-0 - The FIFO Threshold (THRESH)
These bits specify the threshold of the FIFO during the
execution phase of read and write data transfers.
This value is programmable from 00h to 0Fh. A software
reset sets this value to 00 if the LOCK bit (bit 7 of the opcode of the LOCK command) is 0. If the LOCK bit is 1,
THRESH retains its value.
Use a high value of THRESH for systems that respond
slowly and a low value for fast systems.
Internal registers are written.
Result Phase
None.
5.7.3
The DUMPREG command supports system run-time diagnostics, and application software development and debugging.
Bit 4 - Disable Drive Polling (POLL)
This bit enables and disabled drive polling. A software
reset clears this bit to 0.
When drive polling is enabled, an interrupt is generated
after a reset.
When drive polling is disabled, if the CONFIGURE command is issued within 500 msec of a hardware or software reset, then an interrupt is not generated. In
addition, the four SENSE INTERRUPT commands to
clear the Ready Changed State of the four logical drives
is not required.
0: Enable drive polling. (Default)
1: Disable drive polling.
DUMPREG has a one-byte command phase (the opcode)
and a 10-byte result phase, which returns the values of parameters set in other commands. See the commands that
set each parameter for a detailed description of the parameter.
Command Phase
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
0
Execution Phase
Internal registers read.
Bit 5 - Enable FIFO (FIFO)
This bit enables and disables the FIFO for execution
phase data transfers.
If the LOCK bit (bit 7 of the opcode of the LOCK command) is 0, a software reset disables the FIFO, i.e., sets
this bit to 1.
If the LOCK bit is 1, this bit retains its previous value after a software reset.
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The DUMPREG Command
114
7
6
5
4
3
2
1
0
Byte of Present Track Number (PTR) Drive 0
Byte of Present Track Number (PTR) Drive 1
Byte of Present Track Number (PTR) Drive 2
Byte of Present Track Number (PTR) Drive 3
Step Rate Time (SRT)
Delay After Processing
Delay Before Processing
Ninth and Tenth Result Phase Bytes
These bytes reflect the values in the third and fourth
command phase bytes of the CONFIGURE command.
See Section 5.7.2 "The CONFIGURE Command" on
page 114.
DMA
Sectors per Track or End of Track (EOT) Sector #
LOCK
0
0
EIS
DC3
DC2
FIFO POLL
DC1
DC0
GDC
THRESH
5.7.4
Precompensation Track Number (PRETRK)
The FORMAT TRACK Command
This command formats one track on the disk in IBM, ISO, or
Toshiba perpendicular format.
After a hardware or software reset, parameters in this phase
are reset to their default values. Some of these parameters
are unaffected by a software reset, depending on the state
of the LOCK bit.
After a pulse from the INDEX signal is detected, data patterns are written on the disk including all gaps, Address
Marks (AMs), address fields and data fields. See FIGURE
5-19 "IBM, Perpendicular, and ISO Formats Supported by
the FORMAT TRACK Command" on page 118.
See the command that determines the setting for the bit
or field for details.
The format of the track is determined by the following parameters:
First through Fourth Result Phase Bytes, Bits 7-0,
Present Track Number (PTR) Drives 3-0
Each of these bytes contains either the internal 8-bit
track number or the least significant byte of the 12-bit
track number of the corresponding logical disk drive.
Fifth and Sixth Result Phase Bytes, Bits 7-0,
Step Rate Time, Motor Off Time, Motor On Time and
DMA
These fields are all set by the SPECIFY command. See
Section 5.7.21 "The SPECIFY Command" on page 131.
Seventh Result Phase Byte Sectors Per Track or End of Track (EOT)
This byte varies depending on what commands have
been previously executed.
If the last command issued was a FORMAT TRACK
command, and no read or write commands have been
issued since then, this byte contains the sectors per
track value.
If a read or a write command was executed more recently than a FORMAT TRACK command, this byte specifies the number of the sector at the End of the Track
(EOT).
●
The MFM bit in the opcode (first command) byte, which
indicates the type of the disk drive and the data transfer
rate and determines the format of the address marks
and the encoding scheme.
●
The Index Address Format (IAF) bit (bit 6 in the second
command phase byte) in the MODE command, which
selects IBM or ISO format.
●
The Group Drive Configuration (GDC) bits in the PERPENDICULAR MODE command, which select either
conventional or Toshiba perpendicular format.
●
A bytes-per-sector code, which determines the sector
size. See TABLE 5-11 "Bytes per Sector Codes" on
page 116.
●
A sectors per track parameter, which specifies how
many sectors are formatted on the track.
●
The data pattern byte, which is used to fill the data field
of each sector.
TABLE 5-10 "Typical Values for PC Compatible Diskette
Media" on page 116 shows typical values for these parameters for specific PC compatible diskettes.
To allow flexible formatting, the microprocessor must supply the four address field bytes (track number, head number, sector number, bytes-per-sector code) for each sector
formatted during the execution phase. This allows non-sequential sector interleaving.
Eighth Result Phase Byte
Bits 5-0 - DC3-0, GDC
Bits 5-0 of the second command phase byte of the PERPENDICULAR MODE command set bits 5-0 of this byte.
See “Bits 5-2 -Drive 3-0 Mode Configuration (DC3-0)”
on page 121.
This transfer of bytes from the microprocessor to the controller can be done in DMA or non-DMA mode (See Section
5.4.2 "Execution Phase" on page 104), with the FIFO enabled or disabled.
The FORMAT TRACK command terminates when a pulse
from the INDEX signal is detected a second time, at which
point an interrupt is generated.
115
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THE FDC COMMAND SET
Bit 7 - LOCK
This bit controls how the other bits in this command respond to a software reset. See Section 5.7.6 "The
LOCK Command" on page 118.
The value of this is determined by bit 7 of the opcode of
the LOCK command.
0: Bits in this command are set to their default values
after a software reset. (Default)
1: Bits in this command are unaffected by a software
reset.
Result Phase
THE FDC COMMAND SET
Command Phase
First Command Phase Byte, Opcode
7
6
5
4
3
2
1
0
0
MFM
0
0
1
1
0
1
X
X
X
X
X
HD
DS1
DS0
Bit 6 - Modified Frequency Modulation (MFM)
This bit indicates the type of the disk drive and the data
transfer rate, and determines the format of the address
marks and the encoding scheme.
0: FM mode, i.e., single density.
1: MFM mode, i.e., double density.
Bytes-Per-Sector Code
Sectors per Track
Bytes in Gap 3
Data Pattern
TABLE 5-10. Typical Values for PC Compatible Diskette Media
Bytes-Per-Sector End of Track (EOT) Bytes in Gap 2 1 Bytes in Gap 3 2
Code (hex)
Sector # (hex)
(hex)
(hex)
Media Type
Bytes in Data
Field (decimal)
360 KB
512
02
09
2A
50
1.2 MB
512
02
0F
1B
54
720 KB
512
02
09
1B
50
1.44 MB
512
02
12
1B
6C
3
512
02
24
1B
53
2.88 MB
1. Gap 2 is specified in the command phase of read, write, scan, and verify commands. Although this is the
recommended value, the FDC ignores this byte in read, write, scan and verify commands.
2. Gap 3 is the suggested value for the programmable GAP3 that is used in the FORMAT TRACK command and is illustrated in FIGURE 5-19 "IBM, Perpendicular, and ISO Formats Supported by the FORMAT TRACK Command" on page 118.
3. The 2.88 MB diskette media is a barium ferrite media intended for use in perpendicular recording drives
at the data rate of up to 1 Mbps.
Second Command Phase Byte
1: HDSEL is active, i.e., the head of the FDD selects
side 1.
Bits 1,0 - Logical Drive Select (DS1,0)
These bits indicate which logical drive is active. They reflect the values of bits 1,0 of the Digital Output Register
(DOR) described in “Bits 1,0 - Drive Select” on page 98
and of result phase status registers 0 and 3 (ST0 and
ST3) described in Sections 5.5.1 "Result Phase Status
Register 0 (ST0)" on page 107 and 5.5.4 "Result Phase
Status Register 3 (ST3)" on page 109.
00: Drive 0 is selected. (Default)
01: Drive 1 is selected.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11: If four drives are supported, drive 3 is selected.
Third Command Phase Byte -Bytes-Per-Sector Code
This byte contains a code in hexadecimal format that indicates the number of bytes in a data field.
TABLE 5-11 "Bytes per Sector Codes" shows the number of bytes in a data field for each code.
TABLE 5-11. Bytes per Sector Codes
Bit 2 - Head Select (HD)
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected by the head. Its value is the inverse of
the HDSEL disk interface output signal.
This bit reflects the value of bit 3 of Status Register A
(SRA) described in Section 5.3.1 "Status Register A
(SRA)" on page 96 and bit 2 of result phase status registers 0 and 3 (ST0 and ST3) described in Sections
5.5.1 "Result Phase Status Register 0 (ST0)" on page
107 and 5.5.4 "Result Phase Status Register 3 (ST3)"
on page 109, respectively.
0: HDSEL is not active, i.e., the head of the FDD selects side 0. (Default)
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Bytes-Per-Sector Code (hex)
Bytes in Data Field
00
128
01
256
02
512
03
1024
04
2048
05
4096
06
8192
07
16384
Fourth Command Phase Byte - Sectors Per Track
The value in this byte specifies how many sectors there
are in the track.
116
Execution Phase
The system transfers four ID bytes (track number, head
number, sector number and bytes-per-sector code) per sector to the Floppy Disk Controller (FDC) in either DMA or
non-DMA mode. Section 5.4.2 "Execution Phase" on page
104 describes these modes.
The entire track is formatted. The data block in the data field
of each sector is filled with the data pattern byte.
Only the first three status bytes in this phase are significant.
TABLE 5-12. Typical Gap 3 Values
Drive Type and
Bytes in Data Bytes-Per-Sector End of Track (EOT) Bytes in Gap 2 1 Bytes in Gap 3 2
Data Transfer Rate Field (decimal)
Code (hex)
Sector # (hex)
(hex)
(hex)
256
01
12
0A
0C
256
01
10
20
32
250 Kbps
512
02
08
2A
50
MFM
512
02
09
2A
50
1024
03
04
80
F0
2048
04
02
C8
FF
4096
05
01
C8
FF
500 Kbps
256
010
1A
0E
36
MFM
512
02
0F
1B
54
512
02
12
1B
6C
1024
03
08
35
74
2048
04
04
99
FF
4096
05
02
C8
FF
8192
06
01
C8
FF
1. Gap 2 is specified in the command phase of read, write, scan, and verify commands. Although this is the recommended value, the FDC ignores this byte in read, write, scan and verify commands.
2. Gap 3 is the suggested value for use in the FORMAT TRACK command. This is the programmable Gap 3
illustrated in FIGURE 5-19 "IBM, Perpendicular, and ISO Formats Supported by the FORMAT TRACK
Command" on page 118.
Result Phase
7
6
5.7.5
5
4
3
2
1
The INVALID Command
If an invalid command (illegal opcode byte in the command
phase) is received by the Floppy Disk Controller (FDC), the
controller responds with the result phase Status register 0
(ST0) in the result phase. See Section 5.5.1 "Result Phase
Status Register 0 (ST0)" on page 107.
0
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
The controller does not generate an interrupt during this
condition. Bits 7 and 6 in the MSR (see Section 5.3.6 "Data
Rate Select Register (DSR)" on page 101) are both set to 1,
indicating to the microprocessor that the controller is in the
result phase and the contents of ST0 must be read.
Result Phase Status Register 2 (ST2)
Undefined
Undefined
Undefined
Undefined
117
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THE FDC COMMAND SET
Sixth Command Phase Byte - Data Pattern
This byte contains the contents of the data field.
Fifth Command Phase Byte - Bytes in Gap 3
The number of bytes in gap 3 is programmable. The
number to program for Gap 3 depends on the data
transfer rate and the type of the disk drive. TABLE 5-12
"Typical Gap 3 Values" shows some typical values to
use for Gap 3.
FIGURE 5-19 "IBM, Perpendicular, and ISO Formats
Supported by the FORMAT TRACK Command" on
page 118 illustrates the track format for each of the formats recognized by the FORMAT TRACK command.
THE FDC COMMAND SET
Command Phase
7
6
Result Phase
5
4
3
2
1
0
7
Invalid Opcodes
6
5
4
3
2
1
0
Result Phase Status Register 0 (STO) (80h)
The system reads the value 80h from ST0 indicating that an
invalid command was received.
Execution Phase
None.
Index Pulse
IBM
Format
(MFM)
AM
Gap 0 SYNC
IAM
Gap 1 SYNC
80 of 12 of
50 of 12 of
4E
00 3 of
4E
00
3 of
A1* FE
C2* FC
T
r
a
c
k
H
e
a
d
S
e
c
t
o
r
# C Gap 2 SYNC
AM
B R 22 of 12 of
y C 4E
00
FB
t
3 of or
e
A1* F8
s
Data
C
Gap 3 Gap 4
R ProgramC
able
Toshiba
Perpendicular
Format
AM
Gap 0 SYNC
IAM
Gap 1 SYNC
80 of 12 of
50 of 12 of
4E
00 3 of
4E
00
3 of
A1* FE
C2* FC
T
r
a
c
k
H
e
a
d
S
e
c
t
o
r
# C Gap 2 SYNC
AM
B R 41 of 12 of
y C 4E
00
FB
t
3 of or
e
A1* F8
s
Data
C
Gap 3 Gap 4
R ProgramC
able
T
r
a
c
k
H
e
a
d
S
e
c
t
o
r
# C Gap 2 SYNC
AM
B R 22 of 12 of
y C 4E
00
FB
t
3 of or
e
A1* F8
s
Data
C
Gap 3 Gap 4
R ProgramC
able
Index
Field
Address
AM
Gap 1 SYNC
32 of 12 of
4E
00
3 of
A1* FE
ISO
Format
(MFM)
Address Field
Data Field
Repeated for each sector
A1* = Data Pattern of A1, Clock Pattern of 0A. All other data rates use gap 2 = 22 bytes.
C2* = Data Pattern of C2, Clock Pattern of 14
FIGURE 5-19. IBM, Perpendicular, and ISO Formats Supported by the FORMAT TRACK Command
5.7.6
Command Phase
The LOCK Command
The LOCK command can be used to keep the FIFO enabled and to retain the values of some parameters after a
software reset.
After the command byte of the LOCK command is written,
its result byte must be read before the opcode of the next
command can be read. The LOCK command is not executed until its result byte is read by the microprocessor.
7
6
5
4
3
2
1
0
LOCK
0
0
1
0
1
0
0
Bit 7 - Control Reset Effect (LOCK)
This bit determines how the FIFO, THRESH, and
PRETRK bits in the CONFIGURE command and, the
FWR, FRD, and BST bits in the MODE command are affected by a software reset.
0: Set default values after a software reset. (Default)
1: Values are unaffected by a software reset.
If the part is reset after the command byte of the LOCK command is written but before its result byte is read, then the
LOCK command is not executed. This prevents accidental
execution of the LOCK command.
Execution Phase
Internal register is written.
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118
7
6
5
4
3
2
1
0
0
0
0
LOCK
0
0
0
0
Bit 4 - Control Reset Effect (LOCK)
Same as bit 7 of opcode in command phase.
5.7.7
The MODE Command
This command selects the special features of the controller.
The bits in the command bytes of the MODE command are
set to their default values after a hardware reset.
Command Phase
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
TMR
IAF
IPS
0
0
ETR
FWR
FRD
BST
R255
0
0
BFR
WLD
0
0
DENSEL
0
0
LOW PWR
0
0
Bit 6 - Index Address Format (IAF)
This bit determines whether the controller formats
tracks with or without an index address field.
A software reset clears this bit to its default value of 0.
0: The controller formats tracks with an index address
field. (IBM and Toshiba Perpendicular format).
1: The controller formats tracks without an index address field. (ISO format).
Head Settle Factor
0
0
0
0
Bit 7 - Motor Timer Values (TMR)
This bit determines which group of values to use to calculate the Delay Before Processing and Delay After Processing times. The value of each is programmed using
the SPECIFY command, which is described in TABLES
5-24 "Constant Multipliers for Delay After Processing
Factor and Delay Ranges" on page 132 and 5-25 "Constant Multipliers for Delay Before Processing Factor and
Delay Ranges" on page 132.
A software reset clears this bit to its default value of 0.
0: Use the TMR = 0 group of values. (Default)
1: Use the TMR = 1 group of values.
Second Command Phase Byte
Bit 0 - Extended Track Range (ETR)
This bit determines how the track number is stored. It is
cleared to 0 after a software reset.
0: Track number is stored as a standard 8-bit value
compatible with the IBM, ISO, and Toshiba Perpendicular formats.
This allows access of up to 256 tracks during a
seek operation. (Default)
1: Track number is stored as a 12-bit value.
The upper four bits of the track value are stored in
the upper four bits of the head number in the sector
address field.
This allows access of up to 4096 tracks during a
seek operation. With this bit set, an extra byte is required in the SEEK command phase and SENSE
INTERRUPT result phase.
Third Command Phase Byte
Bit 4 - RECALIBRATE Step Pulses (R255)
This bit determines the maximum number of RECALIBRATE step pulses the controller issues before terminating with an error, depending on the value of the
Extended Track Range (ETR) bit, i.e., bit 0 of the second command phase byte in the MODE command.
A software reset clears this bit to its default value of 0.
0: If ETR (bit 0) = 0, the controller issues a maximum
of 85 recalibration step pulses.
If ETR (bit 0) = 1, the controller issues a maximum
of 3925 recalibration step pulses. (Default)
1: If ETR (bit 0) = 0, the controller issues a maximum
of 255 recalibration step pulses.
If ETR (bit 0) = 1, the controller issues a maximum
of 4095 recalibration step pulses.
Bits 3,2 - Low-Power Mode (LOW PWR)
These bits determine whether or not the FDC powers
down and, if it does, they specific how long it will take.
These bits disable power down, i.e., are cleared to 0, after a software reset.
00: Disables power down. (Default)
01: Automatic power down.
At a 500 Kbps data transfer rate, the FDC goes into
low-power mode 512 msec after it becomes idle.
At a 250 Kbps data transfer rate, the FDC goes into
low-power mode 1 second after it becomes idle.
10: Manual power down.
The FDC powers down mode immediately.
11: Not used.
Bit 5 - Burst Mode Disable (BST)
This bit enables or disables burst mode, if the FIFO is
enabled (bit 5 in the CONFIGURE command is 0). If the
FIFO is not enabled in the CONFIGURE command, then
the value of this bit is ignored.
119
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THE FDC COMMAND SET
Bit 5 - Implied Seek (IPS)
This bit determines whether the Implied Seek (IPS) bit
in a command phase byte of a read, write, scan, or verify
command is ignored or READ.
A software reset clears this bit to its default value of 0.
0: The IPS bit in the command byte of a read, write,
scan, or verify is ignored. (Default)
Implied seeks can still be enabled by the Enable
Implied Seeks (EIS) bit (bit 6 of the third command
phase byte) in the CONFIGURE command.
1: The IPS bit in the command byte of a read, write,
scan, or verify is read.
If it is set to 1, the controller performs seek and
sense interrupt operations before executing the
command.
Result Phase
THE FDC COMMAND SET
TABLE 5-13. Multipliers and Head Settle Time Ranges
for Different Data Transfer Rates
A software reset enables burst mode, i.e., clears this bit
to its default value of 0, if the LOCK bit (bit 7 of the opcode of the LOCK command) is 0. If it is 1, BST retains
its value after a software reset.
0: Burst mode enabled for FIFO execution phase data
transfers. (Default)
1: Burst mode disabled.
The FDC issues one DRQ or IRQ6 pulse for each
byte to be transferred while the FIFO is enabled.
Bit 6 - FIFO Read Disable (FRD)
This bit enables or disables the FIFO for microprocessor
read transfers from the controller, if the FIFO is enabled
(bit 5 in the CONFIGURE command is 0). If the FIFO is
not enabled in the CONFIGURE command, then the value of this bit is ignored.
A software reset enables the FIFO for reads, i.e., clears
this bit to its default value of 0, if the LOCK bit (bit 7 of
the opcode of the LOCK command) is 0. If it is 1, FRD
retains its value after a software reset.
0: Enable FIFO. Execution phase of microprocessor
read transfers use the internal FIFO. (Default)
1: Disable FIFO. All read data transfers take place
without the FIFO.
Multiplier
Head Settle
Time Range (msec)
250
8
0 - 120
300
6.666
0 - 100
500
4
0 - 60
1000
2
0 - 30
Bit 4 - Scan Wild Card (WLD)
This bit determines whether or not a value of FFh from
either the microprocessor or the disk is recognized during a scan command as a wildcard character.
0: A value of FFh from either the microprocessor or
the disk during a scan command is interpreted as a
wildcard character that always matches. (Default)
1: The scan commands do not recognize a value of
FFh as a wildcard character.
Bit 5 - CMOS Disk Interface Buffer Enable (BFR)
This bit configures drive output signals.
0: Drive output signals are configured as standard 4
mA push-pull output signals (40 mA sink, 4 mA
source). (Default)
1: Drive output signals are configured as 40 mA opendrain output signals.
Bit 7 - FIFO Write Enable or Disable (FWR)
This bit enables or disables write transfers to the controller, if the FIFO is enabled (bit 5 in the CONFIGURE
command is 0). If the FIFO is not enabled in the CONFIGURE command, then the value of this bit is ignored.
A software reset enables the FIFO for writes, i.e., clears
this bit to its default value of 0, if the LOCK bit (bit 7 of
the opcode of the LOCK command) is 0. If it is 1, FWR
retains its value after a software reset.
0: Enable FIFO. Execution phase microprocessor
write transfers use the internal FIFO. (Default)
1: Disable FIFO. All write data transfers take place
without the FIFO.
Bits 7,6 - Density Select Pin Configuration (DENSEL)
This field can configure the polarity of the Density Select
output signal (DENSEL) as always low or always high,
as shown in Table 4-3. This allows the user more flexibility with new drive types.
This field overrides the DENSEL polarity defined by the
DENSEL polarity bit of the SuperI/O FDC configuration
register at index F0h and described in Section 2.6.1 "SuperI/O FDC Configuration Register" on page 40.
00: The DENSEL signal is always low.
01: The DENSEL signal is always high.
10: The DENSEL signal is undefined.
11: The polarity of the DENSEL signal is defined by the
DENSEL Polarity bit (bit 5) of the SuperI/O FDC
configuration register. See page “Bit 5 - DENSEL
Polarity Control” on page 40. (Default)
Fourth Command Phase Byte
Bits 3-0 - Head Settle Factor
This field is used to specify the maximum time allowed
for the read/write head to settle after a seek during an
implied seek operation.
The value specified by these bits (the head settle factor)
is multiplied by the multiplier for selected data rate to
specify a head settle time that is within the range for that
data rate.
Use the following formula to determine the head settle
factor that these bits should specify:
Head Settle Factor x Multiplier = Head Settle Time
TABLE 5-13 "Multipliers and Head Settle Time Ranges
for Different Data Transfer Rates" shows the multipliers
and head settle time ranges for each data transfer rate.
The default head settle factor, i.e., value for these bits,
is 8.
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Data Transfer
Rate (Kbps)
TABLE 5-14. DENSEL Encoding
120
Bit 7
Bit 6
DENSEL Pin Definition
0
0
DENSEL low
0
1
DENSEL high
1
0
undefined
1
1
Set by bit 5 of the SuperI/O FDC
configuration register at offset F0h.
Internal registers are written.
Result Phase
None.
5.7.8
The NSC Command
Also, during WRITE DATA operations to a perpendicular
drive, a portion of gap 2 must be rewritten by the controller
to guarantee that the data field preamble has been preerased. See TABLE 5-15.
The NSC command can be used to distinguish between the
FDC versions and the 82077.
Command Phase
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
Command Phase
Execution Phase
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
0
OW
0
DC3
DC2
DC1
DC0
GDC
Result Phase.
Second Command Phase Byte
7
6
5
4
3
2
1
0
0
1
1
1
0
0
1
1
A hardware reset clears all the bits to zero (conventional
mode for all drives). PERPENDICULAR MODE command
bits may be written at any time.
The settings of bits 1 and 0 in this byte override the logical
drive configuration set by bits 5 through 2. If bits 1 and 0 are
both 0, bits 5 through 2 configure the logical disk drives as
conventional or perpendicular. Otherwise, bits 2 and 0 configure them. See TABLE 5-16 "Effect of GDC Bits on FORMAT TRACK and WRITE DATA Commands" on page 122.
The result phase byte of the NSC command identifies the
module as the floppy disk controller (FDC) of NSC by returning a value of 73h.
The 82077 and DP8473 return the value 80h, signifying an
invalid command.
Bits 3-0 of this result byte are subject to change by NSC,
and specify the version of the Floppy Disk Controller (FDC)
5.7.9
Bits 1,0 - Group Drive Mode Configuration (GDC)
These bits configure all the logical disk drives as conventional or perpendicular. If the Overwrite bit (OW, bit
7) is 0, this setting may be overridden by bits 5-2.
It is not necessary to issue the FORMAT TRACK command if all drives are conventional.
These bits are cleared to 0 by a software reset.
00: Conventional. (Default)
01: Perpendicular. (500 Kbps)
10: Conventional.
11: Perpendicular. (1 or 2 Mbps)
The PERPENDICULAR MODE Command
The PERPENDICULAR MODE command configures each
of the four logical disk drives for perpendicular or conventional mode via the logical drive configuration bits 1,0 or 52, depending on the value of bit 7. The default mode is conventional. Therefore, if the drives in the system are conventional, it is not necessary to issue a PERPENDICULAR
MODE command.
This command supports the unique FORMAT TRACK and
WRITE DATA requirements of perpendicular (vertical) recording disk drives with a 4 MB unformatted capacity.
Bits 5-2 -Drive 3-0 Mode Configuration (DC3-0)
If bits 1,0 are both 0, and bit 7 is 1, these bits configure
logical drives 3-0 as conventional or perpendicular. Bits
5-2 (DC3–0) correspond to logical drives 3-0, respectively.
These bits are not affected by a software reset.
0: Conventional drive. (Default)
It is not necessary to issue the FORMAT TRACK
command for conventional drives.
1: Perpendicular drive.
Perpendicular recording drives operate in extra high density
mode at 1 or 2 Mbps, and are downward compatible with
1.44 MB and 720 KB drives at 500 kbps (high density) and
250 kbps (double density), respectively.
If the system includes perpendicular drives, this command
should be issued during initialization of the FDC. Then,
when a drive is accessed for a FORMAT TRACK or WRITE
DATA command, the FDC adjusts the command parameters based on the data rate. See TABLE 5-15 "Effect of
Drive Mode and Data Rate on FORMAT TRACK and
WRITE DATA Commands" on page 122.
Precompensation is set to zero for perpendicular drives at
any data rate.
Bit 7 - Overwrite (OW)
This bit enables or disables changes in the mode of the
logical drives by bits 5-2.
0: Changes in mode of logical drives via bits 5-2 are
ignored. (Default)
1: Changes enabled.
Perpendicular recording type disk drives have a pre-erase
head that leads the read or write head by 200 µm, which
translates to 38 bytes at a 1 Mbps data transfer rate (19
bytes at 500 Kbps).
121
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THE FDC COMMAND SET
The increased space between the two heads requires a
larger gap 2 between the address field and data field of a
sector at 1 or 2 Mbps. See Perpendicular Format in FIGURE 5-19 "IBM, Perpendicular, and ISO Formats Supported by the FORMAT TRACK Command" on page 118. A gap
2 length of 41 bytes (at 1 or 2 Mbps) ensures that the preamble in the data field is completely pre-erased by the preerase head.
Execution Phase
THE FDC COMMAND SET
Execution Phase
Result Phase
Internal registers are written.
None.
TABLE 5-15. Effect of Drive Mode and Data Rate on FORMAT TRACK and WRITE DATA Commands
Data Rates
Drive Mode
Length of Gap 2 in FORMAT
TRACK Command
Portion of Gap 2 Rewritten in
WRITE DATA Command
250, 300 or 500 Kbps
Conventional
Perpendicular
22 bytes
22 bytes
0 bytes
19 bytes
1 or 2 Mbps
Conventional
Perpendicular
22 bytes
41 bytes
0 bytes
38 bytes
TABLE 5-16. Effect of GDC Bits on FORMAT TRACK and WRITE DATA Commands
GDC Bits
Drive Mode
Length of Gap 2 in
FORMAT TRACK Command
Portion of Gap 2 Rewritten in
WRITE DATA Command
1
0
0
0
Conventional
22 bytes
0 bytes
0
1
Perpendicular (≤500 Kbps)
22 bytes
19 bytes
1
0
Conventional
22 bytes
0 bytes
1
1
Perpendicular (1 or 2 Mbps)
41 bytes
38 bytes
5.7.10 The READ DATA Command
●
The READ DATA command reads logical sectors that contain a normal data address mark from the selected drive and
makes the data available to the host microprocessor.
End of Track (EOT) sector number. This allows the controller to read multiple sectors.
●
The value of the data length byte is ignored and must be
set to FFh.
After the last command phase byte is written, the controller
waits the Delay Before Processing time (see TABLE 5-25
"Constant Multipliers for Delay Before Processing Factor
and Delay Ranges" on page 132) for the selected drive.
During this time, the drive motor must be turned on by enabling the appropriate drive and motor select disk interface
output signals via the bits of the Digital Output Register
(DOR). See Section 5.3.3 "Digital Output Register (DOR)"
on page 97.
Command Phase
7
6
5
4
3
2
1
0
MT
MFM
SK
0
0
1
1
0
IPS
X
X
X
X
HD
DS1
DS0
Track Number
Head Number
First Command Phase Byte
Sector Number
Bit 5 - Skip Control (SK)
This controls whether or not sectors containing a deleted address mark will be skipped during execution of the
READ DATA command. See TABLE 5-17 "Skip Control
Effect on READ DATA Command" on page 124.
0: Do not skip sector with deleted address mark.
1: Skip sector with deleted address mark.
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Data Length (Obsolete)
Bit 6 - Modified Frequency Modulation (MFM)
This bit indicates the type of the disk drive and the data
transfer rate, and determines the format of the address
marks and the encoding scheme.
0: FM mode, i.e., single density.
1: MFM mode, i.e., double density.
The READ DATA command phase bytes must specify the
following ID information for the desired sector:
●
Track number
●
Head number
●
Sector number
●
Bytes-per-sector code (See TABLE 5-11 "Bytes per
Sector Codes" on page 116.)
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Bit 7 - Multi-Track (MT)
This bit controls whether or not the controller continues
to side 1 of the disk after reaching the last sector of side
0.
122
Execution Phase
In this phase, data read from the disk drive is transferred to
the system via DMA or non-DMA modes. See Section 5.4.2
"Execution Phase" on page 104.
Second Command Phase Byte
Bits 1,0 - Logical Drive Select (DS1,0)
These bits indicate which logical drive is active. See
“Bits 1,0 - Logical Drive Select (DS1,0)” on page 116.
00: Drive 0 is selected. (Default)
01: Drive 1 is selected.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11: If four drives are supported, drive 3 is selected.
The controller looks for the track number specified in the
third command phase byte. If implied seeks are enabled,
the controller also performs all operations of a SENSE INTERRUPT command and of a SEEK command (without issuing these commands). Then, the controller waits the head
settle time. See bits 3-0 of the fourth command phase byte
of the MODE command in “Bits 3-0 - Head Settle Factor” on
page 120.
The controller then starts the data separator and waits for
the data separator to find the address field of the next sector. The controller compares the ID information (track number, head number, sector number, bytes-per-sector code) in
that address field with the corresponding information in the
command phase bytes of the READ DATA command.
Bit 2 - Head (HD)
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected by the head. Its value is the inverse of
the HDSEL disk interface output signal.See “Bit 2 Head Select (HD)” on page 116.
0: HDSEL is not active, i.e., the head of the FDD selects side 0. (Default)
1: HDSEL is active, i.e., the FDD head selects side 1.
If the contents of the bytes do not match, then the controller
waits for the data separator to find the address field of the
next sector. The process is repeated until a match or an
error occurs.
Possible errors, the conditions that may have caused them
and the actions that result are:
Bit 7 - Implied Seek (IPS)
This bit indicates whether or not an implied seek should
be performed. See also, “Bit 5 - Implied Seek (IPS)” on
page 119.
A software reset clears this bit to its default value of 0.
0: No implied seek operations. (Default)
1: The controller performs seek and sense interrupt
operations before executing the command.
●
The microprocessor aborted the command by writing to
the FIFO.
If there is no disk in the drive, the controller gets stuck.
The microprocessor must then write a byte to the FIFO
to advance the controller to the result phase.
●
Two pulses of the INDEX signal were detected since the
search began, and no valid ID was found.
If the track address differs, either the Wrong Track bit
(bit 4) or the Bad Track bit (bit 1) (if the track address is
FFh) is set in result phase Status register 2 (ST2). See
Section 5.5.3 "Result Phase Status Register 2 (ST2)" on
page 108.
If the head number, sector number or bytes-per-sector
code did not match, the Missing Data bit (bit 2) is set in
result phase Status register 1 (ST1).
If the Address Mark (AM) was not found, the Missing Address Mark bit (bit 0) is set in ST1.
Section 5.5.2 "Result Phase Status Register 1 (ST1)" on
page 107 describes the bits of ST1.
●
A CRC error was detected in the address field. In this
case the CRC Error bit (bit 5) is set in ST1.
Third Command Phase Byte - Track Number
The value in this byte specifies the number of the track
to read.
Fourth Command Phase Byte - Head Number
The value in this byte specifies head to use.
Fifth Command Phase Byte - Sector Number
The value in this byte specifies the sector to read.
Sixth Command Phase Byte - Bytes-Per-Sector Code
This byte contains a code in hexadecimal format that indicates the number of bytes in a data field. TABLE 5-11
"Bytes per Sector Codes" on page 116 indicates the
number of bytes that corresponds to each code.
Once the address field of the desired sector is found, the
controller waits for the data separator to find the data field
for that sector.
Seventh Command Phase Byte - End of Track (EOT)
Sector Number
This byte specifies the number of the sector at the End
Of the Track (EOT).
If the data field (normal or deleted) is not found within the
expected time, the controller terminates the operation, enters the result phase and sets bit 0 (Missing Address Mark)
in ST1.
Eighth Command Phase Byte - Bytes Between Sectors
- Gap 3
The value in this byte specifies how many bytes there
are between sectors. See “Fifth Command Phase Byte
- Bytes in Gap 3” on page 117.
If a deleted data mark is found, and Skip (SK) control is set
to 1 in the opcode command phase byte, the controller skips
this sector and searches for the next sector address field as
described above. The effect of Skip Control (SK) on the
READ DATA command is summarized in TABLE 5-17
"Skip Control Effect on READ DATA Command".
123
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THE FDC COMMAND SET
Ninth Command Phase Byte - Data Length (Obsolete)
The value in this byte is ignored and must be set to FFh.
0: Single track. The controller stops at the last sector
of side 0.
1: Multiple tracks. the controller continues to side 1 after reaching the last sector of side 0.
THE FDC COMMAND SET
TABLE 5-17. Skip Control Effect on READ DATA
Command
Skip
Control
(SK)
Data
Type
Control
Sector
Mark Bit 6
Read?
of ST2
7
Result
0
Normal
Y
0
0
Deleted
Y
1
No More
Sectors Read
1
Normal
Y
0
Normal
Termination
1
Deleted
N
1
Sector Skipped
1
5
4
3
2
1
0
MT
MFM
SK
0
1
1
0
0
IPS
X
X
X
X
HD
DS1
DS0
Sector Number
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Data Length (Obsolete)
Execution Phase
Data read from disk drive is transferred to the system in
DMA or non-DMA modes. See Section 5.4.2 "Execution
Phase" on page 104.
See TABLE 5-18 "Result Phase Termination Values with
No Error" for the state of the result bytes when the command terminates normally. The effect of Skip Control (SK)
on the READ DELETED DATA command is summarized in
TABLE 5-19 "SK Effect on READ DELETED DATA Command".
0
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
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6
Head Number
Result Phase
2
7
Track Number
If the Multi-Track (MT) bit was set in the opcode command
byte, and the last sector of side 0 has been transferred, the
controller continues with side 1.
3
Upon terminating the execution phase of the READ DATA
command, the controller asserts IRQ6, indicating the beginning of the result phase. The microprocessor must then
read the result bytes from the FIFO.
Command Phase
CRC error. CRC Error bit (bit 5) in ST1 and CRC Error in
Data Field bit (bit 5) in ST2, are set. The Interrupt Code (IC)
bits (bits 7,6) in ST0 are set to abnormal termination (01).
4
Bytes-Per-Sector Code
This command is like the READ DATA command, except for the
setting of the Control Mark bit (bit 6) in ST2 and the skipping of
sectors. See description of execution phase. See READ DATA
command for a description of the command bytes.
Overrun error. The Overrun bit (bit 4) in ST1 is set. The
Interrupt Code (IC) bits (bits 7,6) in ST0 are set to abnormal termination (01). If the microprocessor cannot service a transfer request in time, the last correctly read
byte is transferred.
5
0
The READ DELETED DATA command reads logical sectors containing a Address Mark (AM) for deleted data from
the selected drive and makes the data available to the host
microprocessor.
The last sector address (of side 1, if the Multi-Track enable bit (MT) was set to 1) was equal to the End of Track
sector number. The End of Track bit (bit 7) in ST1 is set.
The IC bits in ST0 are set to abnormal termination (01).
This is the expected condition during non-DMA transfers.
6
1
5.7.11 The READ DELETED DATA Command
The DMA controller asserted the Terminal Count (TC)
signal to indicate that the operation terminated. The Interrupt Code (IC) bits (bits 7,6) in ST0 are set to normal
termination (00). See “Bits 7,6 - Interrupt Code (IC)” on
page 107.
7
2
The values that are read back in the result bytes are shown
in TABLE 5-18 "Result Phase Termination Values with No
Error" on page 125. If an error occurs, the result bytes indicate the sector read when the error occurred.
After reading the sector, the controller reads the next logical
sector unless one or more of the following termination conditions occurs:
●
3
Sector Number
Normal
Termination
The controller then generates a Cyclic Redundancy Check
(CRC) value for the sector and compares the result with the
CRC value at the end of the data field.
●
4
Head Number
See also Section 5.4 "THE PHASES OF FDC COMMANDS" on page 104.
●
5
Track Number
After finding the data field, the controller transfers data
bytes from the disk drive to the host until the bytes-per-sector count has been reached, or until the host terminates the
operation by issuing the Terminal Count (TC) signal, reaching the end of the track or reporting an overrun.
●
6
124
ID Information in Result Phase
Multi-Track
(MT)
Head #
(HD)
End of Track (EOT)
Sector Number
0
0
< EOT1 Sector #
No Change
No Change
Sector2 # + 1
No Change
Track Number Head Number Sector Number
Bytes-per-Sector
Code
0
0
= EOT1 Sector #
Track3
#+1
No Change
1
No Change
0
1
< EOT1 Sector #
No Change
No Change
Sector2 # + 1
No Change
0
1
= EOT1 Sector #
Track3 # + 1
No Change
1
No Change
1
0
< EOT1 Sector #
No Change
No Change
Sector2 # + 1
No Change
1
0
= EOT1 Sector #
No Change
1
1
No Change
1
1
< EOT1 Sector #
No Change
No Change
Sector2 # + 1
No Change
1
1
= EOT1 Sector #
Track3 # + 1
0
1
No Change
1. End of Track sector number from the command phase.
2. The number of the sector last operated on by controller.
3. Track number programmed in the command phase
TABLE 5-19. SK Effect on READ DELETED DATA
Command
Skip
Control
(SK)
Data
Type
Control
Sector
Mark Bit 6
Read?
of ST2
0
Normal
Y
1
No More
Sectors Read
0
Deleted
Y
0
Normal
Termination
1
Normal
N
1
Sector Skipped
1
Deleted
Y
0
Normal
Termination
5.7.12 The READ ID Command
The READ ID command finds the next available address
field and returns the ID bytes (track number, head number,
sector number, bytes-per-sector code) to the microprocessor in the result phase.
Result
The controller reads the first ID Field header bytes it can
find and reports these bytes to the system in the result
bytes.
Command Phase
6
5
4
3
2
1
6
5
4
3
2
1
0
0
MFM
0
0
1
0
1
0
X
X
X
X
X
HD
DS1
DS0
After the last command phase byte is written, the controller
waits the Delay Before Processing time (see TABLE 5-25
"Constant Multipliers for Delay Before Processing Factor
and Delay Ranges" on page 132) for the selected drive.
During this time, the drive motor must be turned on by enabling the appropriate drive and motor select disk interface
output signals via the bits of the Digital Output Register
(DOR). See Section 5.3.3 "Digital Output Register (DOR)"
on page 97.
Result Phase
7
7
0
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
First Command Phase Byte, Opcode
See “Bit 6 - Modified Frequency Modulation (MFM)” on
page 116.
Head Number
Sector Number
Second Command Phase Byte
See “Second Command Phase Byte” on page 116 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
Bytes-Per-Sector Code
125
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THE FDC COMMAND SET
TABLE 5-18. Result Phase Termination Values with No Error
THE FDC COMMAND SET
The command phase bytes of the READ A TRACK command are like those of the READ DATA command, except
for the MT and SK bits. Multi-track and skip operations are
not allowed in the READ A TRACK command. Therefore,
bits 7 and 5 of the opcode command phase byte (MT and
SK, respectively) must be 0.
Execution Phase
There is no data transfer during the execution phase of this
command. An interrupt is generated when the execution
phase is completed.
The READ ID command does not perform an implied seek.
After waiting the Delay Before Processing time, the controller starts the data separator and waits for the data separator
to find the address field of the next sector. If an error condition occurs, the Interrupt Code (IC) bits in ST0 are set to abnormal termination (01), and the controller enters the result
phase.
First Command Phase Byte, Opcode
See “Bit 6 - Modified Frequency Modulation (MFM)” on
page 116.
Second Command Phase Byte
See “Second Command Phase Byte” on page 116 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
See “Bit 5 - Implied Seek (IPS)” on page 119 for a description of the Implied Seek (IPS) bit.
Possible errors are:
●
●
The microprocessor aborted the command by writing to
the FIFO.
If there is no disk in the drive, the controller gets stuck.
The microprocessor must then write a byte to the FIFO
to advance the controller to the result phase.
Third through Ninth Command Phase Bytes
See Section 5.7.10 "The READ DATA Command" on
page 122.
Two pulses of the INDEX signal were detected since the
search began, and no Address Mark (AM) was found.
When the Address Mark (AM) is not found, the Missing
Address Mark bit (bit 0) is set in ST1. Section 5.5.2 "Result Phase Status Register 1 (ST1)" on page 107 describes the bits of ST1.
Execution Phase
Data read from the disk drive is transferred to the system in
DMA or non-DMA modes. See Section 5.4.2 "Execution
Phase" on page 104.
Result Phase
7
6
5
4
3
2
1
Execution of this command is like execution of the READ
DATA command except for the following differences:
0
●
The controller waits for a pulse from the INDEX signal
before it searches for the address field of a sector.
If the microprocessor writes to the FIFO before the INDEX pulse is detected, the command enters the result
phase with the Interrupt Code (IC) bits (bits 7,6) in ST0
set to abnormal termination (01).
●
All the ID bytes of the sector address are compared, except the sector number. Instead, the sector number is
set to 1, and then incremented for each successive sector read.
●
If no match occurs when the ID bytes of the sector address are compared, the controller sets the Missing
Data bit (bit 2) in ST1, but continues to read the sector.
If there is a CRC error in the address field being read,
the controller sets CRC Error (bit 5) in ST1, but continues to read the sector.
●
If there is a CRC error in the data field, the controller
sets the CRC Error bit (bit 5) in ST1 and CRC Error in
Data Field bit (bit 5) in ST2, but continues reading sectors.
●
The controller reads a maximum of End of Track (EOT)
physical sectors. There is no support for multi-track
reads.
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
Head Number
Sector Number
Bytes-Per-Sector Code
5.7.13 The READ A TRACK Command
The READ A TRACK command reads sectors from the selected drive, in physical order, and makes the data available
to the host.
Command Phase
7
6
5
4
3
2
1
0
0
MFM
0
0
0
0
1
0
IPS
X
X
X
X
HD
DS1
DS0
Track Number
Head Number
Result Phase
Sector Number
Bytes-Per-Sector Code
7
End of Track (EOT) Sector Number
6
5
4
3
2
1
Result Phase Status Register 0 (ST0)
Bytes Between Sectors - Gap 3
Result Phase Status Register 1 (ST1)
Data Length (Obsolete)
Result Phase Status Register 2 (ST2)
Track Number
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126
0
6
5
4
3
2
1
The pulses actually occur while the controller is in the drive
polling phase. See Section 5.4.5 "Drive Polling Phase" on
page 106.
0
Head Number
An interrupt is generated after the TRK0 signal is asserted,
or after the maximum number of RECALIBRATE step pulses is issued.
Sector Number
Bytes-Per-Sector Code
Software should ensure that the RECALIBRATE command
is issued for only one drive at a time. This is because the
drives are actually selected via the Digital Output Register
(DOR), which can only select one drive at a time.
5.7.14 The RECALIBRATE Command
The RECALIBRATE command issues pulses that make the
head of the selected drive step out until it reaches track 0.
No command, except a SENSE INTERRUPT command,
should be issued while a RECALIBRATE command is in
progress.
Command Phase
7
6
5
4
3
2
1
0
Result Phase
0
0
0
0
0
1
1
1
None.
X
X
X
X
X
HD
DS1
DS0
5.7.15 The RELATIVE SEEK Command
The RELATIVE SEEK command issues STEP pulses that
make the head of the selected drive step in or out a programmable number of tracks.
Second Command Phase Byte
See “Second Command Phase Byte” on page 116 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
Command Phase
Execution Phase
After the last command byte is issued, the Drive Busy bit for
the selected drive is set in the Main Status Register (MSR).
See bits 3-0 in Section 5.3.5 "Main Status Register (MSR)"
on page 100.
TABLE 5-20 "Maximum RECALIBRATE Step Pulses for
Values of R255 and ETR" shows the maximum number of
RECALliBRATE step pulses that may be issued, depending
on the RECALIBRATE Step Pulses (R255) bit, bit 0 in the
second command phase byte of the MODE command
(page 119), and the Extended Track Range (ETR) bit, bit 4
of the third command byte of the MODE command (see
Section 5.7.7 "The MODE Command" on page 119).
0
85 (default)
1
0
255
0
1
3925
1
1
4095
3
2
1
0
1
DIR
0
0
1
1
1
1
X
X
X
X
X
HD
DS1
DS0
Third Command Phase Byte - Relative Track Number
(RTN)
This value specifies how many tracks the head should
step in or out from the current track.
Execution Phase
TABLE 5-20. Maximum RECALIBRATE Step Pulses for
Values of R255 and ETR
0
4
Second Command Phase Byte
See “Second Command Phase Byte” on page 116 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
If the number of tracks on the disk drive exceeds the maximum number of RECALIBRATE step pulses, it may be necessary to issue another RECALIBRATE command.
Maximum Number of
RECALIBRATE Step Pulses
5
First Command Phase Byte, Opcode,
Bit - 6 Step Direction DIR
This bit defines the step direction.
0: Step head out.
1: Step head in.
Then, the controller issues pulses until the TRK0 disk interface input signal becomes active or until the maximum number of RECALIBRATE step pulses have been issued.
ETR
6
Relative Track Number (RTN)
The controller waits the Delay Before Processing time (see
TABLE 5-25 "Constant Multipliers for Delay Before Processing Factor and Delay Ranges" on page 132) for the selected drive., and then becomes idle. See Section 5.4.4
"Idle Phase" on page 106.
R255
7
After the last command byte is issued, the Drive Busy bit for
the selected drive is set in the Main Status Register (MSR).
See bits 3-0 in Section 5.3.5 "Main Status Register (MSR)"
on page 100.
The controller waits the Delay Before Processing time (see
TABLE 5-25 "Constant Multipliers for Delay Before Processing Factor and Delay Ranges" on page 132) for the selected drive., and then becomes idle. See Section 5.4.4
"Idle Phase" on page 106.
Then, the controller enters the idle phase and issues RTN
STEP pulses until the TRK0 disk interface input signal becomes active or until the specified number (RTN) of STEP
pulses have been issued. After the RELATIVE SEEK operation is complete, the controller generates an interrupt.
127
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THE FDC COMMAND SET
7
THE FDC COMMAND SET
SCAN HIGH OR EQUAL
Software should ensure that the RELATIVE SEEK command is issued for only one drive at a time. This is because
the drives are actually selected via the Digital Output Register (DOR), which can only select one drive at a time.
No command, except the SENSE INTERRUPT command,
should be issued while a RELATIVE SEEK command is in
progress.
7
6
5
4
3
2
1
0
MT
MFM
SK
1
1
1
0
1
IPS
X
X
X
X
HD
DS1
DS0
Track Number
Result Phase
Head Number
None.
Sector Number
5.7.16 The SCAN EQUAL, the SCAN LOW OR EQUAL
and the SCAN HIGH OR EQUAL Commands
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
The scan commands compare data read from the disk with
data sent from the microprocessor. This comparison produces a match for each scan command, as follows, and as
shown in TABLE 5-21 "The Effect of Scan Commands on
the ST2 Register" on page 129:
●
SCAN EQUAL - Disk data equals microprocessor data.
●
SCAN LOW OR EQUAL - Disk data is less than or
equal to microprocessor data.
●
SCAN HIGH OR EQUAL - Disk data is greater than or
equal to microprocessor data.
Bytes Between Sectors - Gap 3
Sector Step Size
First through Eighth Command Phase Bytes All Scan Commands
See READ DATA command for a description of the first
eight command phase bytes.
Ninth Command Phase Byte, Sector Step Size
During execution, the value of this byte is added to the current sector number to determine the next sector to read.
Command Phase
Execution Phase
SCAN EQUAL
7
6
5
4
3
2
1
0
MT
MFM
SK
1
0
0
0
1
IPS
X
X
X
X
HD
DS1
DS0
The most significant bytes of each sector are compared
first. If wildcard mode is enabled in bit 4 of the fourth command phase byte in the MODE command ( "Bit 4 - Scan
Wild Card (WLD)" on page 120), a value of FFh from either
the disk or the microprocessor always causes a match.
After each sector is read, if there is no match, the next sector
is read. The next sector is the current sector number plus the
Sector Step Size specified in the ninth command phase byte.
Track Number
Head Number
The scan operation continues until the condition is met, the
End of Track (EOT) is reached or the Terminal Count (TC)
signal becomes active.
Sector Number
Bytes-Per-Sector Code
Read error conditions during scan commands are the same
as read error conditions during the execution phase of the
READ DATA command. See Section 5.7.10 "The READ
DATA Command" on page 122.
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
If the Skip Control (SK) bit is set to 1, sectors with deleted
data marks are ignored. If all sectors read are skipped, the
command terminates with bit 3 of ST2 set to 1, i.e., disk data
equals microprocessor data.
Sector Step Size
SCAN LOW OR EQUAL
7
6
5
4
3
2
1
0
MT
MFM
SK
1
1
0
0
1
IPS
X
X
X
X
HD
DS1
DS0
Result Phase
7
5
4
3
2
1
Result Phase Status Register 0 (ST0)
Track Number
Result Phase Status Register 1 (ST1)
Head Number
Result Phase Status Register 2 (ST2)
Sector Number
Track Number
Bytes-Per-Sector Code
Head Number
End of Track (EOT) Sector Number
Sector Number
Bytes Between Sectors - Gap 3
Bytes-Per-Sector Code
Sector Step Size
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6
128
0
lected drive, before issuing the first STEP pulse. After
waiting the Delay Before Processing time, the controller becomes idle. See Section 5.4.4 "Idle Phase" on page 106.
Second Command Phase Byte
See READ DATA command for a description of these bits.
TABLE 5-21. The Effect of Scan Commands on the ST2
Register
Third Command Phase Byte, Number of Track to Seek
The value in this byte is the number of the track to seek.
Result Phase Status
Register 2 (ST2)
Command
Condition
Fourth Command Phase Byte,
Bits 7-4 - MSN of Track Number
If the track number is stored as a 12-bit value, these bits
contain the Most Significant Nibble (MSN), i.e., the four
most significant bits, of the number of the track to seek.
Otherwise (the ETR bit in the MODE command is 0), this
command phase byte is not required.
Bit 3 - Scan Bit 2 - Scan
Satisfied
Not Satisfied
SCAN
EQUAL
1
0
0
1
Disk = µP
Disk ≠ µP
SCAN LOW
OR EQUAL
1
0
0
0
0
1
Disk = µP
Disk < µP
Disk > µP
SCAN HIGH
OR EQUAL
1
0
0
0
0
1
Disk = µP
Disk > µP
Disk < µP
Execution Phase
During the execution phase of the SEEK command, the
track number to seek to is compared with the present track
number. The controller determines how many STEP pulses
to issue and the DIR disk interface output signal indicates
which direction the head should move.
5.7.17 The SEEK Command
The SEEK command issues step pulses while the controller
is in the drive polling phase. The step pulse rate is determined by the value programmed in the second command
phase byte of the SPECIFY command.
The SEEK command issues pulses of the STEP signal to
the selected drive, to move it in or out until the desired track
number is reached.
Software should ensure that the SEEK command is issued
for only one drive at a time. This is because the drives are
actually selected via the Digital Output Register (DOR),
which can only select one drive at a time. See Section 5.3.3
"Digital Output Register (DOR)" on page 97.
An interrupt is generated one step pulse period after the last
step pulse is issued. A SENSE INTERRUPT command
should be issued to determine the cause of the interrupt.
Result Phase
No command, except a SENSE INTERRUPT command,
should be issued while a SEEK command is in progress.
None.
5.7.18 The SENSE DRIVE STATUS Command
Command Phase
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
X
X
X
X
X
HD
DS1
DS0
The SENSE DRIVE STATUS command indicates which
drive and which head are selected, whether or not the head
is at track 0 and whether or not the track is write protected
in result phase Status register 3 (ST3). See Section 5.5.4
"Result Phase Status Register 3 (ST3)" on page 109. This
command does not generate an interrupt.
Number of Track to Seek
Command Phase
MSN of Track # to Seek
When bit 2 of the second command phase byte (ETR) in the
MODE command is set to 1, the track number is stored as
a 12-bit value. See “Bit 0 - Extended Track Range (ETR)”
on page 119.
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
X
X
X
X
X
HD
DS1
DS0
See READ DATA command for a description of these bits.
In this case, a fourth command byte should be written in the
command phase to hold the Most Significant Nibble (MSN),
i.e., the four most significant bits, of the number of the track
to seek. Otherwise (ETR bit in MODE is 0), this command
phase byte is not required. and, only three command bytes
should be written.
Execution Phase
Disk drive status information is detected and reported.
Result Phase
After the last command byte is issued, the Drive Busy bit for
the selected drive is set in the Main Status Register (MSR).
See bits 3-0 in Section 5.3.5 "Main Status Register (MSR)"
on page 100.
7
6
5
4
3
2
1
0
Result Phase Status Register 3 (ST3)
The controller waits the Delay Before Processing time (see
TABLE 5-25 "Constant Multipliers for Delay Before Processing Factor and Delay Ranges" on page 132) for the se-
See Section 5.5.4 "Result Phase Status Register 3 (ST3)"
on page 109.
129
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THE FDC COMMAND SET
TABLE 5-21 "The Effect of Scan Commands on the ST2
Register" shows how all the scan commands affect bits 3,2
of the Status 2 (ST2) result phase register. See Section
5.5.3 "Result Phase Status Register 2 (ST2)" on page 108.
THE FDC COMMAND SET
●
5.7.19 The SENSE INTERRUPT Command
The SENSE INTERRUPT command returns the cause of
an interrupt that is caused by the change in status of any
disk drive.
Data is being transferred in non-DMA mode, during the
execution phase of some command.
Interrupts caused by these conditions are cleared automatically, or by reading or writing information from or to the
Data Register (FIFO).
If a SENSE INTERRUPT command is issued when no interrupt is pending it is treated as an invalid command.
Command Phase
When to Issue SENSE INTERRUPT
The SENSE INTERRUPT command is issued to detect either of the following causes of an interrupt:
●
The FDC became ready during the drive polling phase
for an internally selected drive. See Section 5.4.5 "Drive
Polling Phase" on page 106. This can occur only after a
hardware or software reset.
●
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
3
2
1
0
Execution Phase
Status of interrupt is reported.
Result Phase.
A SEEK, RELATIVE SEEK or RECALIBRATE command terminated.
7
Interrupts caused by these conditions are cleared after the
first result byte has been read. Use the Interrupt Code (IC)
(bits 7,6) and SEEK End bits (bit 5) of result phase Status
register 0 (ST0) to identify the cause of these interrupts. See
“Bit 5 - SEEK End” on page 107 and TABLE 5-22 "Interrupt
Causes Reported by SENSE INTERRUPT" on page 130.
6
5
4
Result Phase Status Register 0 (ST0)
Byte of Present Track Number (PTR)
MSN of PTR
TABLE 5-22. Interrupt Causes Reported by SENSE
INTERRUPT
When bit 2 of the second command phase byte (ETR) in the
MODE command is set to 1, the track number is stored as
a 12-bit value. See “Bit 0 - Extended Track Range (ETR)”
on page 119.
Bits of
ST0
In this case, a third result byte should be read to hold the
Most Significant Nibble (MSN), i.e., the four most significant
bits, of the number of the current track.
Interrupt Cause
7
6
5
1
1
0 FDC became ready during drive polling mode.
SEEK, RELATIVE SEEK or RECALIBRATE
not completed.
0
0
1 SEEK, RELATIVE SEEK or RECALIBRATE
terminated normally.
0
1
Otherwise (ETR bit in MODE is 0), this command phase
byte is not required. and, only two result phase bytes should
be
readFirst
Command
Phase
Byte,
Result Phase Status Register 0
See Section 5.5.1 "Result Phase Status Register 0
(ST0)" on page 107.
Second Command Phase Byte,
Present Track Number (PTR)
The value in this byte is the number of the current track.
1 SEEK, RELATIVE SEEK or RELCALIBRATE
terminated abnormally.
Fourth Command Phase Byte,
Bits 7-4 - MSN of Track Number
If the track number is stored as a 12-bit value, these bits
contain the Most Significant Nibble (MSN), i.e., the four
most significant bits, of the number of the track to seek.
Otherwise (the ETR bit in the MODE command is 0), this
result phase byte is not required.
When SENSE INTERRUPT is not Necessary
Interrupts that occur during most command operations do
not need to be identified by the SENSE INTERRUPT. The
microprocessor can identify them by checking the Request
for Master (RQM) bit (bit 7) of the Main Status Register
(MSR). See page “Bit 7 - Request for Master (RQM)” on
page 101.
It is not necessary to issue a SENSE INTERRUPT command to detect the following causes of Interrupts:
●
7
The result phase of any of the following commands
started:
— READ DATA, READ DELETED DATA, READ A
TRACK, READ ID
— WRITE DATA, WRITE DELETED
— FORMAT TRACK
— SCAN EQUAL, SCAN EQUAL OR LOW, SCAN
EQUAL OR HIGH
— VERIFY
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130
This command is used to verify (read) or change (write) the
number of the present track.
This command could be useful for recovery from disk tracking errors, where the true track number could be read from
the disk using the READ ID command, and used as input to
the SET TRACK command to correct the Present Track
number (PTR) stored internally.
MSB
DS1
DS0
2
1
0
0
0
0
Drive 0 (LSB)
1
0
0
Drive 0 (MSB)
0
0
1
Drive 1 (LSB)
1
0
1
Drive 1 (MSB)
Byte to Read or Write
Terminating this command does not generate an interrupt
Command Phase
7
6
5
4
3
2
1
0
0
1
0
Drive 2 (LSB)
0
WNR
1
0
0
0
0
1
1
1
0
Drive 2 (MSB)
0
0
1
1
0
MSB
DS1
DS0
0
1
1
Drive 3 (LSB)
1
1
1
Drive 3 (MSB)
Byte of Present Track Number (PTR)
When bit 2 of the second command phase byte (ETR) in the
MODE command is set to 1, the track number is stored as
a 12-bit value. See “Bit 0 - Extended Track Range (ETR)”
on page 119.
Execution Phase
Internal register is read or written.
In this case, issue SET TRACK twice - once for the Most
Significant Byte (MSB) of the number of the current track
and once for the Least Significant Byte (LSB).
Result Phase
7
Otherwise (ETR bit in MODE is 0), issue SET TRACK only
once, with bit 2 (MSB) of the second command phase byte
set to 0.
6
5
4
3
2
1
0
Byte of Present Track Number(PTR)
First Command Phase Byte, Bit 6 - Write Track Number
(WNR)
0: Read the existing track number.
The result phase byte already contains the track
number, and the third byte in the command phase
is a dummy byte.
1: Change the track number by writing a new value to
the result phase byte.
This byte is one byte of the track number that was read or
written, depending on the value of WNR in the first command byte.
5.7.21 The SPECIFY Command
The SPECIFY command sets initial values for the following
time periods:
Second Command Phase Byte
Bits 1,0 - Logical Drive Select (DS1,0)
These bits indicate which logical drive is active. See
“Bits 1,0 - Logical Drive Select (DS1,0)” on page 116.
00: Drive 0 is selected.
01: Drive 1 is selected.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11: If four drives are supported, drive 3 is selected.
●
The delay before command processing starts, formerly
called Motor On Time (MNT)
●
The delay after command processing terminates, formerly called Motor Off Time (MFT)
●
The interval step rate time.
The FDC uses the Digital Output Register (DOR) to enable
the drive and motor select signals. See Section 5.3.3 "Digital Output Register (DOR)" on page 97.
The delays may be used to support the µPD765, i.e., to insert delays from selection of a drive motor until a read or
write operation starts, and from termination of a command
until the drive motor is no longer selected, respectively.
Bit 2 - Most Significant Byte (MSB)
This bit, together with bits 1,0, determines the byte to
read or write. See TABLE 5-23 "Defining Bytes to Read
or Write Using SET TRACK".
0: Least significant byte of the track number.
1: Most significant byte of the track number.
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THE FDC COMMAND SET
TABLE 5-23. Defining Bytes to Read or Write Using
SET TRACK
5.7.20 The SET TRACK Command
THE FDC COMMAND SET
The value of the Motor Timer Values (TMR) bit (bit 7) of
the second command phase byte in the MODE command determines which group of constants and delay
ranges to use. See “Bit 7 - Motor Timer Values (TMR)”
on page 119.
The specific constant that will be multiplied by this factor
to determine the actual delay after processing for each
data transfer rate is shown in TABLE 5-24 "Constant
Multipliers for Delay After Processing Factor and Delay
Ranges" on page 132.
Use the smallest possible value for this factor, except 0,
i.e., 1. If this factor is 0, the value16 is used.
The parameters used by this command are undefined after
power up, and are unaffected by any reset. Therefore, software should always issue a SPECIFY command as part of
an initialization routine to initialize these parameters.
Terminating this command does not generate an interrupt.
Command Phase.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
Step Rate Time (SRT)
Delay After Processing
Delay Before Processing
Bits 7-4 - STEP Time Interval Value (SRT)
These bits specify a value that is used to calculate the
time interval between successive STEP signal pulses
during a SEEK, IMPLIED SEEK, RECALIBRATE, or
RELATIVE SEEK command.
TABLE 5-26 "STEP Time Interval Calculation" on page
132 shows how this value is used to calculate the actual
time interval.
DMA
Second Command Phase Byte
Bits 3-0 - Delay After Processing Factor
These bits specify a factor that is multiplied by a constant to determine the delay after command processing
ends, i.e., from termination of a command until the drive
motor is no longer selected.
TABLE 5-24. Constant Multipliers for Delay After Processing Factor and Delay Ranges
Data Transfer
Rate (bps)
Bit 7 of MODE (TMR) = 0
Bit 7 of MODE (TMR) = 1
Constant Multiplier
Permitted Range (msec)
Constant Multiplier
Permitted Range (msec)
1M
8
8 -128
512
512 - 8192
500 K
16
16 - 256
512
512 - 8192
300 K
80 / 3
26.7 - 427
2560 / 3
853 - 13653
250 K
32
32 - 512
1024
1024 -16384
TABLE 5-25. Constant Multipliers for Delay Before Processing Factor and Delay Ranges
Data Transfer
Rate (bps)
Bit 7 of MODE (TMR) = 0
Bit 7 of MODE (TMR) = 1
Constant Multiplier
Permitted Range (msec)
Constant Multiplier
Permitted Range (msec)
1M
1
1 -128
32
32 - 4096
500 K
1
1 -128
32
32 - 4096
300 K
10 / 3
3.3 - 427
160 / 3
53 - 6827
250 K
4
4 - 512
64
64 - 8192
TABLE 5-26. STEP Time Interval Calculation
Data Transfer Calculation of Time
Rate (bps)
Interval
Bit 0 - DMA
This bit selects the data transfer mode in the execution
phase of a read, write, or scan operation.
Data can be transferred between the microprocessor
and the controller during execution in DMA mode or in
non-DMA mode, i.e., interrupt transfer mode or software
polling mode.
See Section 5.4.2 "Execution Phase" on page 104 for a
description of these modes.
0: DMA mode is selected.
1: Non-DMA mode is selected.
Permitted
Range (msec)
1M
(16 − SRT) / 2
0.5 - 8
500 K
(16 − SRT)
1 0 16
300 K
(16 − SRT) x 1.67
1.67 - 26.7
250 K
(16 − SRT) x 2
2 - 32
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Third Command Phase Byte
132
7
6
5
4
3
2
1
0
MT
MFM
SK
1
0
1
1
0
EC
X
X
X
X
HD
DS1
DS0
Track Number
Head Number
Sector Number
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Sectors to read Count (SC)
Execution Phase
First Command Phase Byte
See Section 5.7.10 "The READ DATA Command" on
page 122 for a description of these bits.
Internal registers are written.
Result Phase
None.
Second Command Phase Byte
5.7.22 The VERIFY Command
Bits 2-0 - Drive Select (DS1,0) and Head (HD) Select
See the description of the Drive Select bits (DS1,0) and
the Head (HD) in Section 5.7.10 "The READ DATA
Command" on page 122.
The VERIFY command verifies the contents of data and/or
address fields after they have been formatted or written.
VERIFY reads logical sectors containing a normal data Address Mark (AM) from the selected drive, without transferring the data to the host.
Bit 7 - Enable Count Control (EC)
This bit controls whether the End of Track sector number or the Sectors to read Count (SC) triggers termination of the VERIFY command.
See also TABLE 5-27 "VERIFY Command Termination
Conditions".
0: Terminate VERIFY when the number of last sector
read equals the End of Track (EOT) sector number.
The ninth command phase byte (Sectors to read
Count, SC), is not needed and should be set to FFh.
1: Terminate VERIFY when number of sectors read
equals the number of sectors to read, i.e., Sectors
to read Count (SC).
The TC signal cannot terminate this command since no
data is transferred. Instead, VERIFY simulates a TC signal
by setting the Enable Count (EC) bit to1. In this case, VERIFY terminates when the number of sectors read equals the
number of sectors to read, i.e., Sectors to read Count (SC).
If SC = 0 then 256 sectors will be verified.
When EC is 0, VERIFY ends when the End of the Track
(EOT) sector number equals the number of the sector
checked. In this case, the ninth command phase byte is not
needed and should be set to FFh.
TABLE 5-27 "VERIFY Command Termination Conditions"
on page 134 shows how different values for the VERIFY parameters affect termination.
Third through Eighth Command Phase Bytes
See Section 5.7.10 "The READ DATA Command" on
page 122.
Always set the End of Track (EOT) sector number to the
number of the last sector to be checked on each side of
the disk. If EOT is greater than the number of sectors
per side, the command terminates with an error and no
useful Address Mark (AM) or CRC data is returned.
Ninth Command Phase Byte, Sectors to Read Count (SC)
This byte specifies the number of sectors to read. If the
Enable Count (EC) control bit (bit 7) of the second command byte is 0, this byte is not needed and should be
set to the value FFh.
133
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THE FDC COMMAND SET
Command Phase
Bits 3-0 - Delay Before Processing Factor
These bits specify a factor that is multiplied by a constant to determine the delay before command processing starts, i.e., from selection of a drive motor until a
read or write operation starts.
The value of the Motor Timer Values (TMR) bit (bit 7) of
the second command phase byte in the MODE command determines which group of constants and delay
ranges to use. See “Bit 7 - Motor Timer Values (TMR)”
on page 119.
The specific constant that will be multiplied by this factor
to determine the actual delay before processing for
each data transfer rate shown in TABLE 5-25 "Constant
Multipliers for Delay Before Processing Factor and Delay Ranges".
Use the smallest possible value for this factor, except 0,
i.e., 1. If this factor is 0, the value128 is used.
THE FDC COMMAND SET
Execution Phase
5.7.23 The VERSION Command
Data is read from the disk, as the controller checks for valid
address marks in the address and data fields.
The VERSION command returns the version number of the
current Floppy Disk Controller (FDC).
This command is identical to the READ DATA command,
except that it does not transfer data during the execution
phase. See Section 5.7.10 "The READ DATA Command"
on page 122.
Command Phase
Execution Phase
If the Multi-Track (MT) parameter is 1 and SC is greater
than the number of remaining formatted sectors on side 0,
verification continues on side 1 of the disk.
None.
Result Phase
The result phase byte returns a value of 90h for an FDC that
is compatible with the 82077.
7
6
5
4
3
2
1
Result Phase
0
Other controllers, i.e., the DP8473 and other NEC765 compatible controllers, return a value of 80h (invalid command).
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
5.7.24 The WRITE DATA Command
Result Phase Status Register 2 (ST2)
The WRITE DATA command receives data from the host
and writes logical sectors containing a normal data Address
Mark (AM) to the selected drive.
Track Number
Head Number
This command is like the READ DATA command, except
that the data is transferred from the microprocessor to the
controller instead of the other way around.
Sector Number
Bytes-Per-Sector Code
Command Phase
TABLE 5-27 "VERIFY Command Termination Conditions"
shows how different conditions affect the termination status.
TABLE 5-27. VERIFY Command Termination
Conditions
MT EC
0
0
1
1
7
6
5
4
3
2
1
0
MT
MFM
0
0
0
1
0
1
IPS
X
X
X
X
HD
DS1
DS0
Sector Count (SC) or
End of Track (EOT) Value
Termination
Status
SC should be FFh
EOT ≤ Sectors per Side1
No Errors
SC should be FFh
EOT > Sectors per Side
Abnormal
Termination
SC ≤ Sectors per Side
and
SC ≤ EOT
No Errors
SC > Sectors Remaining2
or
SC > EOT
Abnormal
Termination
SC should be FFh
EOT ≤ Sectors per Side
No Errors
The controller waits the Delay Before Processing time before starting execution.
SC should be FFh
EOT > Sectors per Side
Abnormal
Termination
SC ≤ Sectors per Side
and
SC ≤ EOT
No Errors
If implied seeks are enabled, i.e., IPS in the second command phase byte is 1, the operations performed by SEEK
and SENSE INTERRUPT commands are performed (without these commands being issued).
SC ≤ (EOT x 2)
and
EOT ≤ Sectors per Side
No Errors
SC > (EOT x 2)
Abnormal
Termination
0
1
0
1
Track Number
Head Number
Sector Number
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Data Length (Obsolete)
See Section 5.7.10 "The READ DATA Command" on page
122 for a description of these bytes.
Execution Phase
Data is transferred from the system to the controller via
DMA or non-DMA modes and written to the disk.See Section 5.4.2 "Execution Phase" on page 104 for a description
of these data transfer modes.
The controller starts the data separator and waits for it to
find the address field of the next sector. The controller compares the address ID (track number, head number, sector
number, bytes-per-sector code) with the ID specified in the
command phase.
1. Number of formatted sectors per side of the disk.
2. Number of formatted sectors left which can be read,
including side 1 of the disk, if MT is 1.
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134
Result Phase
7
●
●
●
5
●
2
1
0
Result Phase Status Register 2 (ST2)
The microprocessor aborted the command by writing to
the FIFO.
If there is no disk in the drive, the controller gets stuck.
The microprocessor must then write a byte to the FIFO
to advance the controller to the result phase.
Track Number
Head Number
Sector Number
Two pulses of the INDEX signal were detected since the
search began, and no valid ID was found.
If the track address differs, either the Wrong Track bit
(bit 4) or the Bad Track bit (bit 1) (if the track address is
FFh is set in result phase Status register 2 (ST2). See
Section 5.5.3 "Result Phase Status Register 2 (ST2)" on
page 108.
If the head number, sector number or bytes-per-sector
code did not match, the Missing Data bit (bit 2) is set in
result phase Status register 1 (ST1).
If the Address Mark (AM) is not found, the Missing Address Mark bit (bit 0) is set in ST1.
Section 5.5.2 "Result Phase Status Register 1 (ST1)" on
page 107 describes the bits of ST1.
Bytes-Per-Sector Code
Upon terminating the execution phase of the WRITE DATA
command, the controller asserts IRQ6, indicating the beginning of the result phase. The microprocessor must then
read the result bytes from the FIFO.
The values that are read back in the result bytes are shown
in TABLE 5-18 "Result Phase Termination Values with No
Error" on page 125. If an error occurs, the result bytes indicate the sector read when the error occurred.
5.7.25 The WRITE DELETED DATA Command
The WRITE DELETED DATA command receives data from
the host and writes logical sectors containing a deleted data
Address Mark (AM) to the selected drive.
A CRC error was detected in the address field. In this
case the CRC Error bit (bit 5) is set in ST1.
This command is identical to the WRITE DATA command,
except that a deleted data AM, instead of a normal data AM,
is written to the data field.
The controller detected an active the Write Protect (WP)
disk interface input signal, and set bit 1 of ST1 to 1.
Command Phase
7
6
5
4
3
2
1
0
MT
MFM
0
0
1
0
0
1
IPS
X
X
X
X
HD
DS1
DS0
Track Number
After writing the sector, the controller reads the next logical
sector, unless one or more of the following termination conditions occurs:
●
3
Result Phase Status Register 1 (ST1)
If the correct address field is found, the controller waits for
all (conventional drive mode) or part (perpendicular drive
mode) of gap 2 to pass. See FIGURE 5-19 "IBM, Perpendicular, and ISO Formats Supported by the FORMAT
TRACK Command" on page 118. The controller then writes
the preamble field, Address Marks (AM) and data bytes to
the data field. The microprocessor transfers the data bytes
to the controller.
●
4
Result Phase Status Register 0 (ST0)
Possible errors are:
●
6
Head Number
Sector Number
The DMA controller asserted the Terminal Count (TC)
signal to indicate that the operation terminated. The Interrupt Code (IC) bits (bits 7,6) in ST0 are set to normal
termination (00). See “Bits 7,6 - Interrupt Code (IC)” on
page 107.
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Data Length (Obsolete)
The last sector address (of side 1, if the Multi-Track enable bit (MT) was set to 1) was equal to the End of Track
sector number. The End of Track bit (bit 7) in ST1 is set.
The IC bits in ST0 are set to abnormal termination (01).
This is the expected condition during non-DMA transfers.
See Section 5.7.10 "The READ DATA Command" on page
122 and Section 5.7.24 "The WRITE DATA Command" on
page 134 for a description of these bytes.
Execution Phase
Overrun error. The Overrun bit (bit 4) in ST1 is set. The
Interrupt Code (IC) bits (bits 7,6) in ST0 are set to abnormal termination (01). If the microprocessor cannot service a transfer request in time, the last correctly written
byte is written to the disk.
Data is transferred from the system to the controller in DMA
or non-DMA modes, and written to the disk. See Section
5.4.2 "Execution Phase" on page 104 for a description of
these data transfer modes.
If the Multi-Track (MT) bit was set in the opcode command
byte, and the last sector of side 0 has been transferred, the
controller continues with side 1.
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THE FDC COMMAND SET
If there is no match, the controller waits to find the next sector address field. This process continues until the desired
sector is found. If an error condition occurs, the Interrupt
Control (IC) bits (bits 7,6) in ST0 are set to abnormal termination, and the controller enters the result phase. See “Bits
7,6 - Interrupt Code (IC)” on page 107.
EXAMPLE OF A FOUR-DRIVE CIRCUIT
Result Phase.
7
6
5
4
3
2
1
Upon terminating the execution phase of the WRITE DATA
command, the controller asserts IRQ6, indicating the beginning of the result phase. The microprocessor must then
read the result bytes from the FIFO.
0
Result Phase Status Register 0 (ST0)
The values that are read back in the result bytes are shown
in TABLE 5-18 "Result Phase Termination Values with No
Error" on page 125. If an error occurs, the result bytes indicate the sector read when the error occurred.
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
5.8
Head Number
Figure 5-20 shows one implementation of a four-drive circuit. Refer to TABLE 5-2 "Drive and Motor Pin Encoding for
Four Drive Configurations and Drive Exchange Support" on
page 98 to see how to encode the drive and motor bits for
this configuration.
Sector Number
Bytes-Per-Sector Code
74LS139
EXAMPLE OF A FOUR-DRIVE CIRCUIT
7407 (2)
G1
1Y0
Decoded Signal for Drive 0
DR0
A1
1Y1
Decoded Signal for Drive 1
DR1
B1
1Y2
Decoded Signal for Drive 2
1Y3
Decoded Signal for Drive 3
2Y0
Decoded Signal for Motor 0
G2
2Y1
Decoded Signal for Motor 1
A2
2Y2
Decoded Signal for Motor 2
B2
2Y3
Decoded Signal for Motor 3
PC87317
MTR0
Hex Buffers
ICC = 40 mA
Open Collector
FIGURE 5-20. Four Floppy Disk Drive Circuit
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136
6.0
Parallel Port (Logical Device 4)
The PC87317VUL enters the ECP mode by default after
reset.
The ECP configuration supports several modes that are
determined by bits 7-5 of the ECP Extended Control
Register (ECR) at offset 402h. Section 6.6 "DETAILED
ECP MODE DESCRIPTIONS" on page 154 describes
these modes in detail. The ECR register is described in
Section 6.5.12 "Extended Control Register (ECR)" on
page 150.
The parallel port is a communications device that transfers
parallel data between the system and an external device.
Originally designed to output data to an external printer, the
use of this port has grown to include bidirectional communications, increased data rates and additional applications
(such as network adaptors).
6.1
PARALLEL PORT CONFIGURATION
6.1.2
The PC87317VUL parallel port device offers a wide range
of operational configurations. It utilizes the most advanced
protocols in current use, while maintaining full backward
compatability to support existing hardware and software. It
supports two Standard Parallel Port (SPP) modes of operation for parallel printer ports (as found in the IBM PC-AT,
PS/2 and Centronics systems), two Enhanced Parallel Port
(EPP) modes of operation, and one Extended Capabilities
Port (ECP) mode. This versatility is achieved by user software control of the mode in which the device functions.
The operation mode of the parallel port is determined by
configuration bits that are controlled by software. If ECP
mode is set upon initial system configuration, the operation
mode may also be changed during run-time.
The IEEE 1284 standard establishes a widely accepted
handshake and transfer protocol that ensures transfer data
integrity. This parallel interface fully supports the IEEE 1284
standard of parallel communications, in both Legacy and
Plug and Play configurations, in all modes except the EPP
revision 1.7 mode described in the next section.
6.1.1
●
Configuration at System Initialization (Static) - The
parallel port operation mode is determined at initial system configuration by bits 7-4 of the SuperI/O Parallel
Port Configuration register at index F0h of logical device
4. See Section 2.7.1 on page 41
●
Configuration at System Initialization with RunTime Reconfiguration (Dynamic) - The parallel port
operation mode is initially ECP, but may be changed by
additional mode selection bits if bit 4 of the SuperI/O
Parallel Port Configuration register at index F0h of logical device 4 is 1, and bits 7-5 of the same register are
110 or 111.
In this case, the operation mode is determined by bits 75 of the parallel port Extended Control register (ECR) at
parallel port base address + 402h and by bits 7 and 4 of
the Control2 register at second level offset 2. These registers are accessed via the internal ECP Mode Index
and Data registers at parallel port base address + 403
and parallel port base address + 404h, respectively.
Parallel Port Operation Modes
The PC87317VUL parallel port supports Standard Parallel
Port (SPP), Enhanced Parallel Port (EPP) and Extended
Capabilities Port (ECP) configurations.
●
●
●
Configuring Operation Modes
In Standard Parallel Port (SPP) configuration, data rates
of several hundred bytes per second are achieved. This
configuration supports the following operation modes:
— In SPP Compatible mode the port is write-only (for
data). Data transfers are software-controlled and are
accompanied by status and control handshake signals.
— PP FIFO mode enhances SPP Compatible mode by
the addition of an output data FIFO, and operation
as a state-machine operation instead of softwarecontrolled operation.
— In SPP Extended mode, the parallel port becomes a
read/write port, that can transfer a full data byte in either direction.
TABLE 6-1 "Parallel Port Mode Selection" on page 138
shows how to configure the parallel port for the different operation modes.
TABLE 2-4 "Parallel Port Address Range Allocation" on
page 29 shows how to allocate a range for the base address
of the parallel port for each mode. Parallel port address decoding is described in Section 2.2.2 "Address Decoding" on
page 28.
The parallel port supports Plug and Play operation. Its interrupt can be routed on one of the following ISA interrupts:
IRQ1 to IRQ15 except for IRQ 2 and 13. Its DMA signals
can be routed to one of three 8-bit ISA DMA channels. See
Section 6.5.19 "PP Confg0 Register" on page 153.
The Enhanced Parallel Port (EPP) configuration supports two modes that offer higher bi-directional throughput and more efficient hardware-based handling.
— EPP revision 1.7 mode lacks a comprehensive
handshaking scheme to ensure data transfer integrity between communicating devices with dissimilar
data rates. This is the only mode that does not meet
the requirements of the IEEE 1284 standard handshake and transfer protocol.
— EPP revision 1.9 mode offers data transfer enhancement, while meeting the IEEE 1284 standard.
The parallel port device is activated by setting bit 4 of the
system Function Enable Register 1 (FER1) to 1. See Section 10.2.3 "Function Enable Register 1 (FER1)" on page
219.
6.1.3
Output Pin Protection
The parallel port output pins are protected against potential
damage from connecting an unpowered port to a poweredup printer.
6.2
The Extended Capabilities Port (ECP) configuration extends the port capabilities beyond EPP modes by adding a bi-directional 16-level FIFO with threshold
interrupts, for PIO and DMA data transfer, including demand DMA operation. In this mode, the device becomes
a hardware state-machine with highly efficient data
transfer control by hardware in real-time.
STANDARD PARALLEL PORT (SPP) MODES
Compatible SPP mode is a data write-only mode that outputs data to a parallel printer, using handshake bits, under
software control.
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6.0 Parallel Port (Logical Device 4)
Parallel Port (Logical Device 4)
In SPP Extended mode, parallel data transfer is bi-directional. TABLE 6-12 "Parallel Port Pinout" on page 160 lists
the output signals for the standard 25-pin, D-type connector.
TABLE 6-2 "Parallel Port Reset States" on page 138 lists
the reset states for handshake output pins in this mode.
TABLE 6-1. Parallel Port Mode Selection
Configuration
Time
Configuration at
System Initialization
(Static)
Operation Mode
SuperI/O Parallel Port Extended Control Register Control2 Register
Configuration Register (ECR) of the Parallel Port of the Parallel Port
(Offset 402h) 2
(Offset 02h) 3
(Index F0h)1
7 6 5
7 6 5
4
SPP Compatible
0 0 0
-
-
-
SPP Extended
0 0 1
-
-
-
EPP Revision 1.7
0 1 0
-
-
-
EPP Revision 1.9
01 1
-
-
-
SPP Compatible
1 0 0
or
1 1 1
0 0 0
-
4
0 1 0
-
4
0 0 1
-
4
0
4
1
4
-
-
PP FIFO
Configuration at
System Initialization with
Run-Time Reconfiguration
(Dynamic)
Notes
STANDARD PARALLEL PORT (SPP) MODES
Parallel Port (Logical Device 4)
SPP Extended
EPP Revision 1.7
1 1 1
1 0 0
EPP Revision 1.9
1 0 0
or
1 1 1
ECP (Default)
0 1 1
1. Section 2.7.1 "SuperI/O Parallel Port Configuration Register" on page 41 describes the bits of the SuperI/O Parallel Port configuration register.
2. See Section 6.5.12 "Extended Control Register (ECR)" on page 150
3. Before modifying this bit, set bit 4 of the SuperI/O Parallel Port configuration register at index F0h to 1.
4. Use bit 7 of the Control2 register at second level offset 2 of the parallel port to further specify compatibility. See
Section 6.5.17 "Control2 Register" on page 152.
TABLE 6-2. Parallel Port Reset States
TABLE 6-3. Standard Parallel Port (SPP) Registers
Signal
Reset Control
State After Reset
Offset
Name
Description
R/W
SLIN
MR
TRI-STATE
00h
DTR
Data
R/W
INIT
MR
Zero
01h
STR
Status
R
AFD
MR
TRI-STATE
02h
CTR
Control
R/W
STB
MR
TRI-STATE
03h
-
TRI-STATE
IRQ5,7
MR
TRI-STATE
6.2.2
6.2.1
SPP Modes Register Set
In all Standard Parallel Port (SPP) modes, port operation is
controlled by the registers listed in TABLE 6-3 "Standard
Parallel Port (SPP) Registers".
The read or write operation is activated by the system RD
and WR strobes.
All register bit assignments are compatible with the assignments in existing SPP devices.
TABLE 6-4 "SPP DTR Register Read and Write Modes"
tabulates DTR register operation.
A single Data Register DTR is used for data input and output (see Section 6.2.2 "SPP Data Register (DTR)"). The direction of data flow is determined by the system setting in
bit 5 of the Control Register CTR.
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SPP Data Register (DTR)
This bidirectional data port transfers 8-bit data in the direction determined by bit 5 of SPP register CTR at offset 02h
and mode.
138
Parallel Port (Logical Device 4)
Bit 5 of
RD WR
CTR
Mode
SPP Compatible
SPP Extended
6.2.3
Result
x
1
0
Data written to PD7-0.
x
0
1
Data read from the output latch
0
1
0
Data written to PD7-0.
1
1
0
Data written is latched
0
0
1
Data read from output
latch.
1
0
1
Data read from PD7-0.
If bit 5 of CTR is set to 1, data is read from the output signals
PD7-0 when a read cycle occurs. A write cycle in this setting
only writes to the output latch, not to the output signals PD70.
3
2
1
0
0
0
0
0
0
0
3
2
1
1
1
1
0
SPP Status Register
(STR)
1 Reset
Offset 01h
Required
Bit 2 - IRQ Status
In all modes except SPP Extended, this bit is always 1.
In SPP Extended mode this bit is the IRQ status bit. It remains high unless the interrupt request is enabled (bit 4 of
CTR set high). This bit is high except when latched low
when the ACK signal makes a low to high transition, indicating a character is now being transferred to the printer.
Reading this bit resets it to 1.
0: Interrupt requested in SPP Extended mode.
1: No interrupt requested. (Default)
0
SPP Data Register
(DTR)
0 Reset
Offset 00h
Required
D0
D1
D2
D3
D4
D5
4
1
Bit 1 - Reserved
This bit is reserved and is always 1.
The reset value of this register is 0.
4
5
1
Bit 0 - Time-Out Status
In EPP modes only, this is the time-out status bit. In all
other modes this bit has no function and has the constant value 1.
This bit is cleared when an EPP mode is enabled.
Thereafter, this bit is set to 1 when a time-out occurs in
an EPP cycle and is cleared when STR is read.
In EPP modes:
0: An EPP mode is set. No time-out occurred since
STR was last read.
1: Time-out occurred on EPP cycle (minimum of 10
µsec). (Default)
If bit 5 of CTR is cleared to 0, data is written to the output
signals PD7-0 when a write cycle occurs. (if a read cycle occurs in this setting, the system reads the output latch, not
data from PD7-0).
5
6
1
FIGURE 6-2. STR Register Bitmap (SPP Mode)
In SPP Extended mode, the parallel port can read and write
external data via PD7-0. In this mode, bit 5 sets the direction
for data in or data out, while read or write cycles are possible in both settings of bit 5.
6
7
1
Time-Out Status
Reserved
IRQ Status
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
In SPP Compatible mode, the parallel port does not write
data to the output signals. Bit 5 of the CTR register has no
effect in this state. If data is written (WR goes low), the data
is sent to the output signals PD7-0. If a read cycle is initiated
(RD goes low), the system reads the contents of the output
latch, and not data from the PD7-0 output signals.
7
Status Register (STR)
This read-only register holds status information. A system
write operation to STR is an invalid operation that has no effect on the parallel port.
Data Bits
D6
Bit 3 - ERR Status
This bit reflects the current state of the printer error signal, ERR. The printer sets this bit low when there is a
printer error.
0: Printer error.
1: No printer error.
D7
FIGURE 6-1. DTR Register Bitmap (SPP Mode)
Bit 4 - SLCT Status
This bit reflects the current state of the printer select signal, SLCT. The printer sets this bit high when it is on-line
and selected.
0: No printer selected.
1: Printer selected and online.
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STANDARD PARALLEL PORT (SPP) MODES
TABLE 6-4. SPP DTR Register Read and Write Modes
STANDARD PARALLEL PORT (SPP) MODES
Parallel Port (Logical Device 4)
Bit 5 - PE Status
This bit reflects the current state of the printer paper end
signal (PE). The printer sets this bit high when it detects
the end of the paper.
0: Printer has paper.
1: End of paper in printer.
Bit 1 - Automatic Line Feed Control
This bit directly controls the automatic line feed signal to
the printer via the AFD pin. Setting this bit high causes
the printer to automatically feed after each line is printed.
This bit is the inverse of the AFD signal.
0: No automatic line feed. (Default)
1: Automatic line feed
Bit 6 - ACK Status
This bit reflects the current state of the printer acknowledge signal, ACK. The printer pulses this signal low after it has received a character and is ready to receive
another one. This bit follows the state of the ACK pin.
0: Character reception complete.
1: No character received.
Bit 2 - Printer Initialization Control
Bit 2 directly controls the signal to initialize the printer via
the INIT pin. Setting this bit to low initializes the printer.
The value of the INIT signal reflects the value of this bit.
The default setting of 1 on this bit prevents printer initialization in SPP mode, and enables ECP mode after reset.
0: Initialize Printer.
1: No action (Default).
Bit 7 - Printer Status
This bit reflects the current state of the printer BUSY signal. The printer sets this bit low when it is busy and cannot accept another character.
This bit is the inverse of the (BUSY/WAIT) pin.
0: Printer busy.
1: Printer not busy.
6.2.4
Bit 3 - Select Input Signal Control
This bit directly controls the select in signal to the printer
via the SLIN signal. Setting this bit high selects the printer.
It is the inverse of the SLIN signal.
This bit must be set to 0 before enabling the EPP or
ECP mode.
0: Printer not selected. (Default)
1: Printer selected and online.
SPP Control Register (CTR)
The control register provides all the output signals that control the printer. Except for bit 5, it is a read and write register.
Normally when the Control Register (CTR) is read, the bit
values are provided by the internal output data latch. These
bit values can be superseded by the logic level of the STB,
AFD, INIT, and SLIN signals, if these signals are forced high
or low by external voltage. To force these signals high or
low the corresponding bits should be set to their inactive
states (e.g., AFD, STB and SLIN should all be 0; INIT
should be 1).
Bit 4 - Interrupt Enable
Bit 4 controls the interrupt generated by the ACK signal.
Its function changes slightly depending on the parallel
port mode selected.
In ECP mode, this bit should be set to 0.
In the following description, IRQx indicates an interrupt
allocated for the parallel port.
0: In SPP Compatible, SPP Extended and EPP
modes, IRQx is floated. (Default)
1: In SPP Compatible mode, IRQx follows ACK transitions.
In SPP Extended mode, IRQx is set active on the trailing edge of ACK.
In EPP modes, IRQx follows ACK transitions, or is
set when an EPP time-out occurs.
Section 6.3.10 "EPP Mode Transfer Operations" on page
143 describes the transfer operations that are possible in
EPP modes.
7
6
5
4
3
2
1
1
1
0
0
0
1
0
0
SPP Control Register
(CTR)
0 Reset
Offset 02h
Required
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
Bit 5 - Direction Control
This bit determines the direction of the parallel port in
SPP Extended mode only. In the (default) SPP Compatible mode, this bit has no effect, since the port functions
for output only.
This is a read/write bit in EPP modes. In SPP modes it
is a write only bit. A read from it returns 1.
In SPP Compatible mode and in EPP modes it does not
control the direction. See TABLE 6-4 "SPP DTR Register Read and Write Modes" on page 139.
0: Data output to PD7-0 in SPP Extended mode during write cycles. (Default)
1: Data input from PD7-0 in SPP Extended mode during read cycles.
FIGURE 6-3. CTR Register Bitmap (SPP Mode)
Bit 0 - Data Strobe Control
Bit 0 directly controls the data strobe signal to the printer
via the STB signal.
This bit is the inverse of the STB signal.
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140
Parallel Port (Logical Device 4)
6.3
TABLE 6-5. Enhanced Parallel Port (EPP) Registers
Offset
Name
Description
EPP modes allow greater throughput than SPP modes by
supporting faster transfer times (8, 16 or 32-bit data transfers in a single read or write operation) and a mechanism
that allows the system to address peripheral device registers directly. Faster transfers are achieved by automatically
generating the address and data strobes.
The connector pin assignments for these modes are listed
in TABLE 6-12 "Parallel Port Pinout" on page 160.
EPP modes support revision 1.7 and revision 1.9 of the
IEEE 1284 standard, as shown in TABLE 6-1 "Parallel Port
Mode Selection" on page 138.
00h
DTR
SPP Data
01h
STR
SPP Status
SPP or EPP
02h
CTR
SPP Control
SPP or EPP R/W
03h
ADDR
EPP Address
EPP
R/W
04h
DATA0
EPP Data Port 0
EPP
R/W
05h
DATA1
EPP Data Port 1
EPP
R/W
06h
DATA2
EPP Data Port 2
EPP
R/W
07h
DATA3
EPP Data Port 3
EPP
R/W
In Legacy mode, EPP modes are supported for a parallel
port whose base address is 278h or 378h, but not for a parallel port whose base address is 3BCh. (There are no EPP
registers at 3BFh.) In both Legacy and Plug and Play
modes, bits 2, 1 and 0 of the parallel port base address
must be 000 in EPP modes.
6.3.2
SPP-type data transactions may be conducted in EPP
modes. The appropriate registers are available for this type
of transaction. (See TABLE 6-5 "Enhanced Parallel Port
(EPP) Registers".) As in the SPP modes, software must
generate the control signals required to send or receive data.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
6.3.1
Mode
R/W
ENHANCED PARALLEL PORT (EPP) MODES
SPP or EPP R/W
R
SPP or EPP Data Register (DTR)
The DTR register is the SPP Compatible or SPP Extended
data register. A write to DTR sets the state of the eight data
pins on the 25-pin D-shell connector.
EPP Register Set
SPP or EPP Data
Register (DTR)
Offset 00h
Required
D0
TABLE 6-5 lists the EPP registers. All are single-byte registers.
D1
D2
D3
Bits 0, 1 and 3 of the CTR register must be 0 and bit 2 must
be 1, before the EPP registers can be accessed, since the
signals controlled by these bits are controlled by hardware
during EPP accesses. Once these bits are set to 0 by the
software driver, multiple EPP access cycles may be invoked.
D4
D5
Data Bits
D6
D7
FIGURE 6-4. SPP or EPP DTR Register Bitmap
When EPP modes are enabled, the software can perform
SPP Extended mode cycles. In other words, if there is no
access to one of the EPP registers, EPP Address (ADDR)
or EPP Data Registers 0-3 (DATA0-3), EPP modes behave
like SPP Extended mode, except for the interrupt, which is
pulse triggered instead of level triggered.
6.3.3
SPP or EPP Status Register (STR)
This status port is read only. A read presents the current
status of the five pins on the 25-pin D-shell connector, and
the IRQ.
Bit 7 of STR (BUSY status) must be set to 1 before writing
to DTR in EPP modes to ensure data output to PD7-0.
The enhanced parallel port monitors the IOCHRDY signal
during EPP cycles. If IOCHRDY is driven low for more then
10 µsec, an EPP time-out event occurs, which aborts the
cycle by asserting IOCHRDY, thus releasing the system
from a stuck EPP peripheral device. (This time-out event is
only functional when the clock is applied to this logical device).
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1 Reset
SPP or EPP Status
Register (STR)
Offset 01h
Required
Time-Out Status
Reserved
IRQ Status
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
When the cycle is aborted, ASTRB or DSTRB becomes inactive, and the time-out event is signaled by asserting bit 0
of STR. If bit 4 of CTR is 1, the time-out event also pulses
the IRQ5 or IRQ7 signals when enabled. (IRQ5 and IRQ7
can be routed to any other IRQ lines via the Plug and Play
block).
FIGURE 6-5. SPP or EPP STR Register Bitmap
EPP cycles to the external device are activated by invoking
read or write cycles to the EPP.
The bits of this register have the identical function in EPP
mode as in SPP mode. See Section 6.2.3 "Status Register
(STR)" on page 139 for a detailed description of each bit.
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ENHANCED PARALLEL PORT (EPP) MODES
Bits 7,6: Reserved
These bits are reserved and are always 1.
ENHANCED PARALLEL PORT (EPP) MODES
Parallel Port (Logical Device 4)
6.3.4
SPP or EPP Control Register (CTR)
This control port is read or write. A write operation to it sets
the state of four pins on the 25-pin D-shell connector, and
controls both the parallel port interrupt enable and direction.
7
6
5
4
3
2
1
1
1
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
SPP or EPP Control
Register (CTR)
0 Reset
Offset 02h
Required
0
EPP Data Register 0
(DATA0)
0 Reset
Offset 04h
Required
D0
D1
D2
D3
D4
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
EPP Device
Read or Write Data
D5
D6
D7
FIGURE 6-8. EPP DATA0 Register Bitmap
6.3.7
EPP Data Register 1 (DATA1)
DATA2 is only accessed to transfer bits 15 through 8 of a
16-bit read or write to EPP Data Register 0 (DATA0).
FIGURE 6-6. SPP or EPP CTR Register Bitmap
The bits of this register have the identical function in EPP
modes as in SPP modes. See Section 6.2.4 "SPP Control
Register (CTR)" on page 140 for a detailed description of
each bit.
6.3.5
7
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
EPP Data Register 1
(DATA1)
0 Reset
Offset 05h
Required
EPP Address Register (ADDR)
D8
This port is added in EPP modes to enhance system
throughput by enabling registers in the remote device to be
directly addressed by hardware.
D9
D10
D11
D12
EPP Device
D13
Read or Write Data
D14
D15
This port can be read or written. Writing to it initiates an EPP
device or register selection operation.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
EPP Address
Register (ADDR)
Offset 03h
Required
FIGURE 6-9. EPP DATA1 Register Bitmap
6.3.8
A0
EPP Data Register 2 (DATA2)
This is the third EPP data register. It is only accessed to
transfer bits 16 through 23 of a 32-bit read or write to EPP
Data Register 0 (DATA0).
A1
A2
A3
A4
A5
A6
A7
EPP Device or
Register Selection
Address Bits
FIGURE 6-7. EPP ADDR Register Bitmap
6.3.6
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
EPP Data Register 2
(DATA2)
0 Reset
Offset 06h
Required
D16
D17
D18
D19
D20
EPP Device
D21
Read or Write Data
D22
D23
EPP Data Register 0 (DATA0)
DATA0 is a read/write register. Accessing it initiates device
read or write operations of bits 7 through 0.
FIGURE 6-10. EPP DATA2 Register Bitmap
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142
Parallel Port (Logical Device 4)
ENHANCED PARALLEL PORT (EPP) MODES
6.3.9
EPP Data Register 3 (DATA3)
D7-0
This is the fourth EPP data register. It is only accessed to
transfer bits 24 through 31 of a 32-bit read or write to EPP
Data Register 0 (DATA0).
7
6
5
4
3
2
1
0
0
0
0
0
0
0
WR
WAIT
0
EPP Data Register 3
(DATA3)
0 Reset
Offset 07h
Required
ASTRB
WRITE
D24
D25
D26
D27
D28 EPP Device
D29
Read or Write Data
D30
D31
PD7-0
IOCHRDY
ZWS
FIGURE 6-12. EPP 1.7 Address Write
FIGURE 6-11. EPP DATA3 Register Bitmap
EPP 1.7 Address Read
The following procedure reads from the EPP Address register as shown in FIGURE 6-13 "EPP 1.7 Address Read".
6.3.10 EPP Mode Transfer Operations
The EPP transfer operations are address read or write, and
data read or write. An EPP transfer is composed of a system read or write cycle from or to an EPP register, and an
EPP read or write cycle from a peripheral device to an EPP
register or from an EPP register to a peripheral device.
1. The system reads a byte from the EPP Address register.
RD goes low to gate PD7-0 into D7-0.
2. The EPP pulls ASTRB low to signal the peripheral to
start sending data.
3. If WAIT is low during the system read cycle. Then the
EPP pulls IOCHRDY low. When WAIT becomes high,
the EPP stops pulling IOCHRDY to low.
EPP 1.7 Address Write
The following procedure selects a peripheral device or register as illustrated in FIGURE 6-12 "EPP 1.7 Address Write".
4. When IOCHRDY becomes high, it causes RD to become high. If WAIT is high during the system read cycle
then the EPP does not pull IOCHRDY to low.
1. The system writes a byte to the EPP Address register.
WR becomes low to latch D7-0 into the EPP Address
register. The latch drives the EPP Address register onto
PD7-0 and the EPP pulls WRITE low.
5. When RD becomes high, it causes the EPP to pull
ASTRB high. The EPP can change PD7-0 only when
ASTRB is high. After ASTRB becomes high, the EPP
puts D7-0 in TRI-STATE.
2. The EPP pulls ASTRB low to indicate that data was sent.
3. If WAIT was low during the system write cycle,
IOCHRDY becomes low. When WAIT becomes high,
the EPP pulls IOCHRDY high.
D7-0
4. When IOCHRDY becomes high, it causes WR to become high. If WAIT is high during the system write cycle,
then the EPP does not pull IOCHRDY to low.
RD
5. When WR becomes high, it causes the EPP to pull first
ASTRB and then WRITE to high. The EPP can change
PD7-0 only when WRITE and ASTRB are both high.
WAIT
ASTRB
WRITE
PD7-0
IOCHRDY
ZWS
FIGURE 6-13. EPP 1.7 Address Read
EPP 1.7 Data Write and Read
This procedure writes to the selected peripheral device or
register.
EPP 1.7 data read or write operations are similar to EPP 1.7
Address register read or write operations, except that the
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ENHANCED PARALLEL PORT (EPP) MODES
Parallel Port (Logical Device 4)
data strobe (DSTRB signal), and the EPP Data register, replace the address strobe (ASTRB signal) and the EPP Address register, respectively.
and drives the latched byte onto PD7-0. If WAIT was already low, steps 2 and 3 occur concurrently.
4. The EPP pulls ASTRB low and waits for WAIT to become high.
EPP Revision 1.7 and 1.9 Zero Wait State (ZWS) Address Write and Read Operations
5. When WAIT becomes high, the EPP stops pulling
IOCHRDY low, and waits for WR to become high.
The following procedure performs a short write to the selected peripheral device or register. See also FIGURE 6-14
"EPP Write with Zero Wait States" on page 144.
6. When WR becomes high, the EPP pulls ASTRB high,
and waits for WAIT to become low.
7. If no EPP write is pending when WAIT becomes low, the
EPP pulls WRITE to high. Otherwise, WRITE remains
low, and the EPP may change PD7-0.
1. The system writes a byte to the EPP Address register.
WR becomes low to latch D7-0 into the EPP Data register. The latch drives the EPP Data register to PD7-0.
2. The EPP first pulls WRITE low, and then pulls ASTRB
low to indicate that data has been sent.
D7-0
3. If WAIT was high during the system write cycle, ZWS
goes low and IOCHRDY stays high.
WR
4. When the system pulls WR high, the EPP pulls ASTRB,
ZWS and then WRITE to high. The EPP can change
PD7-0 only when WRITE and ASTRB are high.
WAIT
ASTRB
5. If the peripheral is fast enough to pull WAIT low before
the system terminates the write cycle, the EPP pulls
IOCHRDY to low, but does not pull ZWS to low, thus carrying out a normal (non-ZWS EPP 1.7) write operation.
WRITE
PD7-0
D7-0
IOCHRDY
WR
ZWS
WAIT
FIGURE 6-15. EPP 1.9 Address Write
WRITE
EPP 1.9 Address Read
The following procedure reads from the address register.
PD7-0
1. The system reads a byte from the EPP address register.
When RD becomes low, the EPP pulls IOCHRDY low,
and waits for WAIT to become low.
DSTRB or
ASTRB
2. When WAIT becomes low, the EPP pulls ASTRB low
and waits for WAIT to become high. If WAIT was already
low, steps 2 and 3 occur concurrently.
IOCHRDY
ZWS
3. When WAIT becomes high, the EPP stops pulling IOCHRDY low, and waits for RD to become high.
FIGURE 6-14. EPP Write with Zero Wait States
4. When RD becomes high, the EPP latches PD7-0 (to
provide sufficient hold time), pulls ASTRB high, and puts
D7-0 in TRI-STATE.
A read operation is similar, except for the data direction, activation of RD instead of WR, and WRITE stays high.
6.3.11 EPP 1.7 and 1.9 Zero Wait State Data Write and
Read Operations
EPP 1.7 zero wait state data write and read operations are
similar to EPP zero wait state address write and read operations, with the exception that the data strobe (DSTRB signal), and a data register, replace the address strobe
(ASTRB signal) and the address register, respectively.
EPP 1.9 Address Write
The following procedure selects a peripheral or register as
shown in FIGURE 6-15 "EPP 1.9 Address Write".
1. The system writes a byte to the EPP Address register.
2. The EPP pulls IOCHRDY low, and waits for WAIT to become low.
3. When WAIT becomes low, the EPP pulls WRITE to low
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Parallel Port (Logical Device 4)
When ECP is enabled, software should switch modes
only through modes 000 or 001.
●
When ECP is enabled, the software should change direction only in mode 001.
●
Software should not switch from mode 010 or 011, to
mode 000 or 001, unless the FIFO is empty.
●
Software should switch to mode 011 when bits 0 and 1
of DCR are 0.
WRITE
●
Software should switch to mode 010 when bit 0 of DCR
is 0.
PD7-0
●
Software should disable ECP only in mode 000 or 001.
D7-0
RD
WAIT
ASTRB
5. Software should switch to mode 100 when bits 0, 1 and
3 of the DCR are 0.
IOCHRDY
FIGURE 6-16. EPP 1.9 Address Read
6. Software should switch from mode 100 to mode 000 or
001 only when bit 7 of the DSR (BUSY) is 1. Otherwise,
an on-going EPP cycle can be aborted.
EPP 1.9 Data Write and (Backward) Data Read
7. When the ECP is in mode 100, software should write 0
to bit 5 of the DCR before performing EPP cycles.
ZWS
Software may switch from mode 011 backward to modes
000 or 001, when there is an on-going ECP read cycle. In
this case, the read cycle is aborted by deasserting AFD.
The FIFO is reset (empty) and a potential byte expansion
(RLE) is automatically terminated since the new mode is
000 or 001.
This procedure writes to the selected peripheral drive or
register.
EPP 1.9 data read and write operations are similar to EPP
1.9 address read and write operations, except that the data
strobe (DSTRB signal) and EPP Data register replace the
address strobe (ASTRB signal) and the EPP Address register, respectively.
6.4
6.4.3
EXTENDED CAPABILITIES PARALLEL PORT
(ECP)
In the Extended Capabilities Parallel Port (ECP) modes, the
device is a state machine that supports a 16-byte FIFO that
can be configured for either direction, command and data
FIFO tags (one per byte), a FIFO threshold interrupt for both
directions, FIFO empty and full status bits, automatic generation of strobes (by hardware) to fill or empty the FIFO,
transfer of commands and data, and Run Length Encoding
(RLE) expanding (decompression) as explained below. The
FIFO can be accessed by PIO or system DMA cycles.
6.4.1
The ECP uses an internal clock, which can be frozen to reduce power consumption during power down. In this powerdown state the DMA is disabled, all interrupts (except ACK)
are masked, and the FIFO registers are not accessible (access is ignored). The other ECP registers are unaffected by
power-down and are always accessible when the ECP is
enabled. During power-down the FIFO status and contents
become inaccessible, and the system reads bit 2 of ECR as
0, bit 1 of ECR as 1 and bit 0 of ECR as 1, regardless of the
actual values of these bits. The FIFO status and contents
are not lost, however, and when the clock activity resumes,
the values of these bits resume their designated functions.
ECP Modes
ECP modes are enabled as described in TABLE 6-1 "Parallel Port Mode Selection" on page 138. The ECP mode is
selected at reset by setting bits 7-5 of the SuperI/O Parallel
Port Configuration register at index F0h (see Section 2.7.1
"SuperI/O Parallel Port Configuration Register" on page 41)
to 100 or 111. Thereafter, the mode is controlled via the bits
7-5 of the ECP Extended Control Register (ECR) at offset
402h of the parallel port. See Section 6.5.12 "Extended
Control Register (ECR)" on page 150.
When the clock is frozen, an on-going ECP cycle may be
corrupted, but the next ECP cycle will not start even if the
FIFO is not empty in the forward direction, or not full in the
backward direction. If the ECP clock starts or stops toggling
during a system cycle that accesses the FIFO, the cycle
may yield wrong data.
ECP output signals are inactive when the ECP is disabled.
TABLE 6-9 "ECP Modes Encoding" on page 151 lists the
ECP modes. See TABLE 6-11 "ECP Modes" on page 155
and Section 6.6 "DETAILED ECP MODE DESCRIPTIONS"
on page 154 for more detailed descriptions of these modes.
6.4.2
Only the FIFO, DMA and RLE do not function when the
clock is frozen. All other registers are accessible and functional. The FIFO, DMA and RLE are affected by ECR modifications, i.e., they are reset when exits from modes 010 or
011 are carried out even while the clock is frozen.
Software Operation
Software should operate as described in “Extended Capabilities Port Protocol and ISA Interface Standard”.
6.5
ECP MODE REGISTERS
The ECP registers are each a byte wide, and are listed in
TABLE 6-6 "Extended Capabilities Parallel Port (ECP)
Registers" in order of their offsets from the base address of
the parallel port. In addition, the ECP has control registers
Some of these operations are:
●
Hardware Operation
The ZWS signal is asserted by the ECP when ECP modes
are enabled, and an ECP register is accessed by system
PIO instructions, thus using a system zero wait states cycle
(except during read cycles from ECR).
Software should enable ECP after bits 3-0 of the parallel
port Control Register (CTR) are set to 0100.
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EXTENDED CAPABILITIES PARALLEL PORT (ECP)
●
ECP MODE REGISTERS
Parallel Port (Logical Device 4)
at second level offsets, that are accessed via the EIR and
EDR registers. See Section 6.5.2 "Second Level Offsets" on
page 146.
DMA requests for more than 32 consecutive DMA cycles.
The ECP stops requesting the DMA when TC is detected
during an ECP DMA cycle.
TABLE 6-6. Extended Capabilities Parallel Port (ECP)
Registers
A “Demand DMA” feature reduces system overhead
caused by DMA data transfers. When this feature is enabled by bit 6 of the PP Config0 register at second level offset 05h, it prevents servicing of DMA requests until after
four have accumulated and are held pending. See “Bit 6 Demand DMA Enable” on page 154.
Offset
Symbol
Description
000h
DATAR
Parallel Port Data
Register
000h
AFIFO ECP Address FIFO
Modes
(ECR Bits) R/W
765
000
001
R/W
011
W
R
Writing into a full FIFO, and reading from an empty FIFO,
are ignored. The written data is lost, and the read data is undefined. The FIFO empty and full status bits are not affected
by such accesses.
W
Some registers are not accessible in all modes of operation,
or may be accessed in one direction only. Accessing a non
accessible register has no effect. Data read is undefined;
data written is ignored; and the FIFO does not update. The
SPP registers (DTR, STR and CTR) are not accessible
when the ECP is enabled.
001h
DSR
Status Register
All Modes
002h
DCR
Control Register
All Modes R/W
400h
CFIFO
Parallel Port Data
FIFO
010
400h
DFIFO
ECP Data FIFO
011
R/W
To improve noise immunity in ECP cycles, the state machine does not examine the control handshake response
lines until the data has had time to switch.
400h
TFIFO
Test FIFO
110
R/W
In ECP modes:
CNFGA Configuration Register A
111
R
CNFGB Configuration Register B
111
400h
401h
402h
ECR
R
Extended Control
Register
All Modes R/W
403h
EIR
Extended Index
Register
All Modes R/W
404h
EDR
Extended Data
Register
All Modes R/W
405h
EAR
Extended Auxiliary
Status Register
All Modes R/W
Control0
All Modes R/W
02h
Control2
All Modes R/W
04h
Control4
All Modes R/W
05h
PP Confg0
All Modes R/W
6.5.1
DSR replaces STR of SPP/EPP
●
DCR replaces CTR of SPP/EPP
Second Level Offsets
The EIR, EDR, and EAR registers support enhanced control and status features. When bit 4 of the Parallel Port Configuration register is 1 (as described in Section 2.7.1
"SuperI/O Parallel Port Configuration Register" on page
41), EIR and EDR serve as index and data registers, respectively.
EIR and EDR at offsets 403 and 404, respectively, access
the control registers (Control0, Control2, Control4 and PP
Config0) at second level offsets 00h, 02h, 04h and 05h, respectively. These control registers are functional only. Accessing these registers is possible when bit 4 of the
SuperI/O Parallel Port Configuration register at index F0h of
logical device 4 is1 and when bit 2 or 10 of the base address
is 1.
Accessing the ECP Registers
The AFIFO, CFIFO, DFIFO and TFIFO registers access the
same ECP FIFO. The FIFO is accessed at Base + 000h, or
Base + 400h, depending on the mode field of ECR and the
register.
The FIFO can be accessed by system DMA cycles, as well
as system PIO cycles.
When the DMA is configured and enabled (bit 3 of ECR is 1
and bit 2 of ECR is 0) the ECP automatically (by hardware)
issues DMA requests to fill the FIFO (in the forward direction when bit 5 of DCR is 0) or to empty the FIFO (in the
backward direction when bit 5 of DCR is 1). All DMA transfers are to or from these registers. The ECP does not assert
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DATAR replaces DTR of SPP/EPP
●
6.5.2
Control Registers at Second Level Offsets
00h
●
146
Parallel Port (Logical Device 4)
ECP Data Register (DATAR)
7
The ECP Data Register (DATAR) register is the same as
the DTR register (see Section 6.2.2 "SPP Data Register
(DTR)" on page 138), except that a read always returns the
values of the PD7-0 signals instead of the register latched
data.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0 Reset
5
4
3
2
1
1
1
1
1
0
ECP Status Register
(DSR)
1 Reset
Offset 001h
Required
EPP Time-Out Status
Reserved
Reserved
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
Bits 7-5 of ECR = 000 or 001
0
6
ECP Data Register
(DATAR)
Offset 000h
Required
D0
D1
FIGURE 6-19. ECP DSR Register Bitmap
D2
D3
The ECP Address FIFO Register (AFIFO) is write only. In
the forward direction (when bit 5 of DCR is 0) a byte written
into this register is pushed into the FIFO and tagged as a
command.
Bits 0 - EPP Time-Out Status
In EPP modes only, this is the time-out status bit. In all
other modes this bit has no function and has the constant value 1.
This bit is cleared when an EPP mode is enabled.
Thereafter, this bit is set to 1 when a time-out occurs in
an EPP cycle and is cleared when STR is read.
In EPP modes:
0: An EPP mode is set. No time-out occurred since
STR was last read.
1: Time-out occurred on EPP cycle (minimum of 10
µsec). (Default)
Reading this register returns undefined contents. Writing to
this register in a backward direction (when bit 5 of DCR is 1)
has no effect and the data is ignored.
Bits 2,1: Reserved
These bits are reserved and are always 1.
D4
Data Bits
D5
D6
D7
FIGURE 6-17. EPP DATAR Register Bitmap
6.5.4
ECP Address FIFO (AFIFO) Register
Bit 3 - ERR Status
This bit reflects the status of the ERR signal.
0: Printer error.
1: No printer error.
Bits 7-5 of ECR = 011
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
ECP Address Register
(AFIFO)
0 Reset
Offset 000h
Required
Bit 4 - SLCT Status
This bit reflects the status of the Select signal. The printer sets this signal high when it is online and selected
0: Printer not selected. (Default)
1: Printer selected and on-line.
A0
A1
A2
A3
A4
A5
Address Bits
Bit 5 - PE Status
This bit reflects the status of the Paper End (PE) signal.
0: Paper not ended.
1: No paper in printer.
A6
A7
FIGURE 6-18. AFIFO Register Bitmap
6.5.5
Bit 6 - ACK Status
This bit reflects the status of the ACK signal. This signal
is pulsed low after a character is received.
0: Character received.
1: No character received. (Default)
ECP Status Register (DSR)
This read-only register displays device status. Writes to this
DSR have no effect and the data is ignored.
This register should not be confused with the DSR register
of the Floppy Disk Controller (FDC).
Bit 7 - Printer Status
This bit reflects the inverse of the state of the BUSY signal.
0: Printer is busy (cannot accept another character
now).
1: Printer not busy (ready for another character).
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ECP MODE REGISTERS
6.5.3
ECP MODE REGISTERS
Parallel Port (Logical Device 4)
6.5.6
Bit 5 - Direction Control
This bit determines the direction of the parallel port.
This is a read/write bit in EPP mode. In SPP mode it is
a write only bit. A read from it returns 1. In SPP Compatible mode and in EPP mode it does not control the direction. See TABLE 6-4 "SPP DTR Register Read and
Write Modes" on page 139.
The ECP drives the PD7-0 pins in the forward direction,
but does not drive them in the backward direction.
This bit is readable and writable. In modes 000 and 010
the direction bit is forced to 0, internally, regardless of
the data written into this bit.
0: ECP drives forward in output mode. (Default)
1: ECP direction is backward.
Bits 7,6 - Reserved
These bits are reserved and are always 1.
ECP Control Register (DCR)
Reading this register returns the register content (not the
signal values, as in SPP mode).
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0 Reset
ECP Control
Register (DCR)
Offset 002h
Required
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
6.5.7
FIGURE 6-20. DCR Register Bitmap
Bit 0 - Data Strobe Control
Bit 0 directly controls the data strobe signal to the printer
via the STB signal. It is the inverse of the STB signal.
0: The STB signal is inactive in all modes except 010
and 011. In these modes, it may be active or inactive as set by the software.
1: In all modes, STB is active.
Reading this register has no effect and the data read is undefined.
Bit 1 - Automatic Line Feed Control
This bit directly controls the automatic feed XT signal to
the printer via the AFD signal. Setting this bit high causes the printer to automatically feed after each line is
printed. This bit is the inverse of the AFD signal.
In mode 011, AFD is activated by both ECP hardware
and by software using this bit.
0: No automatic line feed. (Default)
1: Automatic line feed.
7
6
5
4
0
0
0
0
Bits 7-5 of ECR = 010
3 2 1 0
Parallel Port FIFO
0 0 0 0 Reset Register (CFIFO)
Offset 400h
Required
D0
D1
D2
D3
D4
D5
Data Bits
D6
D7
Bit 2 - Printer Initialization Control
Bit 2 directly controls the signal to initialize the printer via
the INIT signal. Setting this bit to low initializes the printer. The INIT signal follows this bit.
0: Initialize printer. (Default)
1: Printer initialized.
FIGURE 6-21. CFIFO Register Bitmap
6.5.8
ECP Data FIFO (DFIFO) Register
This bi-directional FIFO functions as either a write-only device when bit 5 of DCR is 0, or a read-only device when it is
1.
Bit 3 - Parallel Port Input Control
This bit directly controls the select input device signal to
the printer via the SLIN signal. It is the inverse of the
SLIN signal.
This bit must be set to 1 before enabling the EPP or
ECP modes.
0: The printer is not selected.
1: The printer is selected.
In the forward direction (bit 5 of DCR is 0), a byte written to
the ECP Data FIFO (DFIFO) register by PIO or DMA is
pushed into the FIFO and tagged as data. Reading this register when set for write-only has no effect and the data read
is undefined.
In the backward direction (bit 5 of DCR is 1), the ECP automatically issues ECP read cycles to fill the FIFO.
Reading from this register pops a byte from the FIFO. Writing to this register when it is set for read-only has no effect,
and the data written is ignored.
Bit 4 - Interrupt Enable
Bit 4 enables the interrupt generated by the ACK signal.
In ECP mode, this bit should be set to 0. This bit does
not float the IRQ pin.
0: Masked. (Default)
1: Enabled.
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Parallel Port Data FIFO (CFIFO) Register
The Parallel Port FIFO (CFIFO) register is write only. A byte
written to this register by PIO or DMA is pushed into the
FIFO and tagged as data.
148
Parallel Port (Logical Device 4)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
This register is read only. Reading CNFGA always returns
100 on bits 2 through 0 and 0001 on bits 7 through 4.
ECP Data FIFO
Register (DFIFO)
Offset 400h
Required
Writing this register has no effect and the data is ignored.
D0
D1
D2
D3
D4
7
6
5
4
0
0
0
1
0
0
0
1
Data Bits
D5
Always 0
Always 0
Always 1
Bit 7 of PP Confg0
Always 1
Always 0
Always 0
Always 0
D6
D7
FIGURE 6-22. DFIFO Register Bitmap
6.5.9
Bits 7-5 of ECR = 111
3 2 1 0 Configuration Register A
(CNFGA)
0 1 0 0 Reset
Offset 400h
1 0 0 Required
Test FIFO (TFIFO) Register
A byte written into the Test FIFO (TFIFO) register is pushed
into the FIFO. A byte read from this register is popped from
the FIFO. The ECP does not issue an ECP cycle to transfer
the data to or from the peripheral device.
FIGURE 6-24. CNFGA Register Bitmap
Bits 2-0 - Reserved
These bits are reserved and are always 100.
The TFIFO is readable and writable in both directions. In the
forward direction (bit 5 of DCR is 0) PD7-0 are driven, but
the data is undefined.
Bit 3 - Bit 7 of PP Confg0
This bit reflects the value of bit 7 of the ECP PP Confg0
register (second level offset 05h), which has no specific
function. Whatever value is put in bit 7 of PP Confg0 will
appear in this bit.
This bit reflects a specific system configuration parameter, as opposed to other devices, e.g., 8-bit data word
length.
The FIFO does not stall when overwritten or underrun (access is ignored). Bytes are always read from the top of the
FIFO, regardless of the direction bit setting (bit 5 of DCR).
For example if 44h, 33h, 22h, 11h is written into the FIFO,
reading the FIFO returns 44h, 33h, 22h, 11h (in the same
order it was written).
Bits 7-5 of ECR = 110
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Bit 7-4 - Reserved
These bits are reserved and are always 0001.
0
Test FIFO
0 Reset Register (TFIFO)
Offset 400h
Required
6.5.11 Configuration Register B (CNFGB)
Configuration register B (CNFGB) is read only. Reading this
register returns the configured parallel port interrupt line
and DMA channel, and the state of the interrupt line.
D0
D1
D2
Writing to this register has no effect and the data is ignored.
D3
D4
D5
Data Bits
D6
D7
FIGURE 6-23. TFIFO Register Bitmap
7
6
0
0
Bits 7-5 of ECR = 111
5 4 3 2 1 0 Configuration Register B
(CNFGB)
x x x 0 0 0 Reset
Offset 401h
Required
DMA Channel Select
Reserved
Interrupt Select
IRQ Signal Value
Reserved
FIGURE 6-25. CNFGB Register Bitmap
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ECP MODE REGISTERS
6.5.10 Configuration Register A (CNFGA)
Bits 7-5 of ECR = 011
ECP MODE REGISTERS
Parallel Port (Logical Device 4)
Bits 1,0 - DMA Channel Select
These bits reflect the value of bits 1,0 of the PP Config0
register (second level offset 05h). Microsoft’s ECP Protocol and ISA Interface Standard defines these bits as
shown in TABLE 6-7 "ECP Mode DMA Selection".
Bits 1,0 of PP Config0 are read/write bits, but CNFGB
bits are read only.
Upon reset, these bits are initialized to 00.
5
4
3
0
0
0
1
0
2
1
0
Extended Control
Register (ECR)
Offset 402h
Required
1 Reset
DMA Configuration
0
0
8-bit DMA selected by jumpers. (Default)
0
1
DMA channel 1 selected.
1
0
DMA channel 2 selected.
1
1
DMA channel 3 selected.
ECP Mode Control
FIGURE 6-26. ECR Register Bitmap
Bit 0 - FIFO Empty
This bit continuously reflects the FIFO state, and therefore can only be read. Data written to this bit is ignored.
When the ECP clock is frozen this bit is read as 1, regardless of the actual FIFO state.
0: The FIFO has at least one byte of data.
1: The FIFO is empty or ECP clock is frozen.
Bit 2 - Reserved
This bit is reserved and is always 0.
Bits 5-3 - Interrupt Select Bits
These bits reflect the value of bits 5-3 of the PP Config0
register at second level index 05h. Microsoft’s ECP Protocol and ISA Interface Standard defines these bits as
shown in TABLE 6-8 "ECP Mode Interrupt Selection".
Bits 5-3 of PP Config0 are read/write bits, but CNFGB
bits are read only.
Upon reset, these bits have undefined values.
Bit 1 - FIFO Full
This bit continuously reflects the FIFO state, and therefore can only be read. Data written to this bit is ignored.
When the ECP clock is frozen this bit is read as 1, regardless of the actual FIFO state.
0: The FIFO has at least one free byte.
1: The FIFO is full or ECP clock frozen.
TABLE 6-8. ECP Mode Interrupt Selection
Bit 5
Bit 4
Bit 3
Interrupt Selection
0
0
0
Selected by jumpers.
0
0
1
IRQ7 selected.
0
1
0
IRQ9 selected.
0
1
1
IRQ10 selected.
1
0
0
IRQ11 selected.
1
0
1
IRQ14 selected.
1
1
0
IRQ15 selected.
1
1
1
IRQ5 selected.
Bit 2 - ECP Interrupt Service
This bit enables servicing of interrupt requests. It is set
to 1 upon reset, and by the occurrence of interrupt
events. It is set to 0 by software.
While this bit is 1, neither the DMA nor the interrupt
events listed below will generate an interrupt.
While this bit is 0, the interrupt setup is “armed” and an
interrupt is generated on occurrence of an interrupt
event.
While the ECP clock is frozen, this bit always returns a
0 value, although it retains its proper value and may be
modified.
When one of the following interrupt events occurs while
this bit is 0, an interrupt is generated and this bit is set
to 1 by hardware.
— DMA is enabled (bit 3 of ECR is 1) and terminal
count is reached.
— FIFO write threshold reached (no DMA - bit 3 of ECR
is 0; forward direction (bit 5 of DCR is 0), and there
are eight or more bytes free in the FIFO).
— FIFO read threshold reached (no DMA - bit 3 of ECR
is 0; read direction set - bit 5 of DCR is 1, and there
are eight or more bytes to read from the FIFO).
Bit 6 - IRQ Signal Value
This bit holds the value of the IRQ signal configured by
the Interrupt Select register (index 70h of this logical device).
Bit 7 - Reserved
This bit is reserved and is always 0.
6.5.12 Extended Control Register (ECR)
This register controls the ECP and parallel port functions. On
reset this register is initialized to 00010xx1 (bits 1 and 2 depend on the clock status). IOCHRDY is driven low on an ECR
read when the ECR status bits do not hold updated data.
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6
FIFO Empty
FIFO Full
ECP Interrupt Service
ECP DMA Enable
ECP Interrupt Mask
TABLE 6-7. ECP Mode DMA Selection
Bit 1 Bit 0
7
150
Parallel Port (Logical Device 4)
The configuration bits within the parallel port address space
are initialized to their default values on reset, and not when
the parallel port is activated.
Bit 3 - ECP DMA Enable
0: The DMA request signal (DRQ3-0) is set to TRISTATE and the appropriate acknowledge signal
(DACK3-0) is assumed inactive.
1: The DMA is enabled and the DMA starts when bit 2
of ECR is 0.
Bit 4 - ECP Interrupt Mask
0: An interrupt is generated on ERR assertion (the
high-to-low edge of ERR). An interrupt is also generated while ERR is asserted when this bit is
changed from 1 to 0; this prevents the loss of an interrupt between ECR read and ECR write.
1: No interrupt is generated.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
ECP Extended Index
Register (EIR)
0 Reset
Offset 403h
Required
Second Level Offset
Reserved
Reserved
Reserved
Reserved
Reserved
Bits 7-5 - ECP Mode Control
These bits set the mode for the ECP device. See Section 6.6 "DETAILED ECP MODE DESCRIPTIONS" on
page 154 for a more detailed description of operation in
each of these ECP modes. The ECP modes are listed in
TABLE 6-9 "ECP Modes Encoding" and described in
detail in TABLE 6-11 "ECP Modes" on page 155.
FIGURE 6-27. EIR Register Bitmap
Bits 2-0 - Second Level Offset
Data written to these bits is used as a second level offset for accesses to a specific control register. Second
level offsets of 00h, 02h, 04h and 05h are supported. Attempts to access registers at any other offset have no
effect.
TABLE 6-9. ECP Modes Encoding
TABLE 6-10. Second Level Offsets
ECR Bit Encoding
Mode Name
Bit 7
Bit 6
Bit 5
0
0
0
Standard
0
0
1
PS/2
00h
Control0
6.5.16 on page 152
0
1
0
Parallel Port FIFO
02h
Control2
6.5.17 on page 152
0
1
1
ECP FIFO
04h
Control4
6.5.18 on page 153
1
0
0
EPP Mode
05h
PP Confg0
6.5.19 on page 153
1
1
0
FIFO Test
1
1
1
Configuration
Second Level
Control
Offset
Register Name
Described in
Section
000:Access the Control0 register.
010:Access the Control2 register.
100:Access the Control4 register.
101:Access the PP Confg0 register.
6.5.13 ECP Extended Index Register (EIR)
The parallel port is partially configured by bits within the logical device address space. These configuration bits are accessed via this read/write register and the Extended Data
Register (EDR) (see Section 6.5.14 "ECP Extended Data
Register (EDR)" on page 152), when bit 4 of the SuperI/O
Bits 7-3 - Reserved
These bits are treated as 0 for offset calculations. Writing any other value to them has no effect.
These bits are read only. They return 00000 on reads
and must be written as 00000.
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ECP MODE REGISTERS
Parallel Port Configuration register at index F0h of logical
device 4 is set to 1. See Section 2.7.1 "SuperI/O Parallel
Port Configuration Register" on page 41.
0: The DMA and the above interrupts are not disabled.
1: The DMA and the above three interrupts are disabled.
ECP MODE REGISTERS
Parallel Port (Logical Device 4)
6.5.14 ECP Extended Data Register (EDR)
6.5.16 Control0 Register
This read/write register is the data port of the control register indicated by the index stored in the EIR. Reading or writing this register reads or writes the data in the control
register whose second level offset is specified by the EIR.
Upon reset, this register is initialized to 00h.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
ECP Extended Data
Register (EDR)
Offset 404h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
EPP Time-Out
Interrupt Mask
Reserved
Reserved
Reserved
Freeze Bit
DCR Register Live
Reserved
Reserved
D0
D1
D2
D3
D4
Data Bits
D5
Control0 Register
Second Level
Offset 00h
Required
FIGURE 6-30. Control0 Register Bitmap
D6
D7
Bit 0 - EPP Time-Out Interrupt Mask
0: The EPP time-out is masked.
1: The EPP time-out is generated.
FIGURE 6-28. EDR Register Bitmap
Bits 7-0 - Data Bits
These read/write data bits transfer data to and from the
Control Register pointed at by the EIR register.
Bit 3-1 - Reserved
Bit 4 - Freeze Bit
In mode 011, setting this bit to 1 freezes part of the interface with the peripheral device, and clearing this bit to
0 releases and initializes it.
In all other modes the value of this bit is ignored.
6.5.15 ECP Extended Auxiliary Status Register (EAR)
Upon reset, this register is initialized to 00h.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
ECP Extended Auxiliary
Status Register (EAR)
0 Reset
Offset 405h
0
Bit 5 - DCR Register Live
When this bit is 1, reading DCR (see Section 6.5.6 "ECP
Control Register (DCR)" on page 148) reads the interface control lines pin values regardless of the mode selected.
Otherwise, reading the DCR reads the content of the
register.
Required
Reserved
Bits 7, 6 - Reserved
6.5.17 Control2 Register
FIFO Tag
Upon reset, this register is initialized to 00h.
FIGURE 6-29. EAR Register Bitmap
Bits 6-0 - Reserved
Bit 7 - FIFO Tag
Read only. In mode 011, when bit 5 of the DCR is 1
(backward direction), this bit reflects the value of the tag
bit (BUSY status) of the word currently in the bottom of
the FIFO.
In other modes this bit is indeterminate.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
Control2 Register
Second Level
Offset 02h
Required
Reserved
Reserved
Reserved
EPP 1.7 ZWS Control
Revision 1.7 or 1.9 Select
Reserved
Channel Address Enable
SPP Compatability
FIGURE 6-31. Control2 Register Bitmap
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152
Parallel Port (Logical Device 4)
Bit 3 - EPP 1.7 ZWS Control
Upon reset this bit is initialized to 0. This bit controls assertion of ZWS on EPP 1.7 access.
There is no ZWS assertion on SPP and on EPP 1.9 access. ZWS is always asserted on ECP access.
Control of ZWS assertion on parallel port access, except
in EPP mode, is done via the SuperI/O Configuration 1
register. See Section 2.4.3 "SuperI/O Configuration 1
Register (SIOC1)" on page 37.
0: ZWS not asserted on EPP 1.7 access.
1: ZWS asserted on EPP 1.7 access.
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1 Reset
Control4 Register
Second Level
Offset 04h
Required
PP DMA Request
Active Time
Reserved
PP DMA Request Inactive Time
Reserved
Bit 4 - EPP 1.7/1.9 Select
Selects EPP version 1.7 or 1.9.
0: EPP version 1.7.
1: EPP version 1.9.
FIGURE 6-32. Control4 Register Bitmap
Bits 2- 0 - Parallel Port DMA Request Active Time
This field specifies the maximum number of consecutive
bus cycles that the parallel port DMA signals can remain
active.
The default value is 111, which specifies 32 cycles.
When these bits are 0, the number is 1 cycle.
Otherwise, the number is 4(n+1) where n is the value of
these bits.
Bit 5 - Reserved
Bit 6 - Channel Address Enable
When this bit is 1, mode is 011, direction is backward,
there is an input command (BUSY is 0), and bit 7 of the
data is 1, the command is written into the FIFO.
Bit 3 - Reserved
Bit 7 - SPP Compatibility
See “Bits 7-5 - ECP Mode Control” on page 151 for a description of each mode.
0: Modes 000, 001 and 100 are identical to ECP.
1: Modes 000 and 001 of the ECP are identical with
Compatible and Extended modes of the SPP (see
Section 6.1 "PARALLEL PORT CONFIGURATION"
on page 137), and mode 100 of the ECP is compatible with EPP mode.
Modes 000, 001 and 100 differ as follows:
000, 001 and 100 – Reading DCR returns pin values of
bits 3-0.
000 and 001 – Reading DCR returns 1 for bit 5.
000, or 001 or 100 when bit 5 of DCR is 0 (forward direction) – Reading DATAR returns register latched
value instead of pin values.
000, 001, and 100, when bit 4 of DCR is 0 – IRQx is
floated.
001 – IRQx is a level interrupt generated on the trailing
edge of ACK. Bit 2 of the DSR is the IRQ status bit
(same behavior as bit 2 of the STR).
Bits 6-4 - Parallel Port DMA Request Inactive Time
This field specifies the minimum number of clock cycles
that the parallel port DMA signals remain inactive after
being deactivated by the fairness mechanism.
The default value is 000, which specifies 8 clock cycles.
Otherwise, the number of clock cycles is 8 + 32n, where
n is the value of these bits.
Bit 7 - Reserved
6.5.19 PP Confg0 Register
Upon reset this register is initialized to 00h.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
PP Confg0 Register
Second Level
0 Reset
Offset 05h
Required
ECP DMA Channel Number
PE Internal Pull-up or Pull-down
6.5.18 Control4 Register
Upon reset this register is initialized to 00000111.
ECP IRQ Number
This register enables control of the fairness mechanism of
the DMA by programming the maximum number of bus cycles that the parallel port DMA request signals can remain
active, and the minimum number of clock cycles that they
will remain inactive after they were deactivated.
Demand DMA Enable
Bit 3 of CNFGA
FIGURE 6-33. PP Confg0 Register Bitmap
Bits 1, 0 - ECP DMA Channel Number
These bits identify the ECP DMA channel number, as
reflected on bits 1 and 0 of the ECP CNFGB register.
See Section 6.5.11 "Configuration Register B (CNFGB)"
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ECP MODE REGISTERS
Bits 2-0 - Reserved
DETAILED ECP MODE DESCRIPTIONS
Parallel Port (Logical Device 4)
6.6
on page 149. Actual ECP DMA routing is controlled by
the DMA channel select register (index 74h) of this logical device.
Microsoft’s ECP protocol and ISA interface standard define bits 1 and 0 of CNFGB as shown in TABLE 6-7
"ECP Mode DMA Selection" on page 150.
DETAILED ECP MODE DESCRIPTIONS
TABLE 6-11 "ECP Modes" on page 155 summarizes the
functionality of the ECP in each mode. The following Sections describe how the ECP functions in each mode, in detail.
6.6.1
Bit 2 - Paper End (PE) Internal Pull-up or Pull-down
Resistor Select
0: PE has a nominal 25 KΩ internal pull-down resistor.
1: PE has a nominal 25 KΩ internal pull-up resistor.
Software Controlled Data Transfer
(Modes 000 and 001)
Software controlled data transfer is supported in modes 000
and 001. The software generates peripheral-device cycles
by modifying the DATAR and DCR registers and reading
the DSR, DCR and DATAR registers. The negotiation
phase and nibble mode transfer, as defined in the IEEE
1284 standard, are performed in these modes.
Bits 5- 3 - ECP IRQ Number
These bits identify the ECP IRQ number, as reflected on
bits 5 through 3 of the ECP CNFGB register. See Section 6.5.11 "Configuration Register B (CNFGB)" on
page 149. Actual ECP IRQ routing is controlled by interrupt select register (index 70h) of this logical device.
Microsoft’s ECP protocol and ISA interface standard defines bits 5 through 3 of CNFGB, as shown in TABLE
6-8 "ECP Mode Interrupt Selection" on page 150.
In these modes the FIFO is reset (empty) and is not functional, the DMA and RLE are idle.
Mode 000 is for the forward direction only; the direction bit
(bit 5 of DCR) is forced to 0 and PD7-0 are driven. Mode 001
is for both the forward and backward directions. The direction bit controls whether or not pins PD7-0 are driven.
6.6.2
Bit 6 - Demand DMA Enable
If enabled, DRQ is asserted when a FIFO threshold of 4
is reached or when flush-time-out expires, except when
DMA fairness prevents DRQ assertion. The threshold of
4 is for four empty entries forward and for four valid entries backward.
Once DRQ is asserted, it is held asserted for four DMA
transfers, as long as the FIFO is able to process these
four transfers, i.e., FIFO not empty backward.
When these four transfers are done, the DRQ behaves
as follows:
— If DMA fairness prevents DRQ assertion (as in the
case of 32 consecutive DMA transfers) then DRQ
becomes low.
— If the FIFO is not able to process another four transfers (below threshold), then DRQ is becomes low.
— If the FIFO is able to process another four transfers
(still above the threshold and no fairness to prevent
DRQ assertion), then DRQ is held asserted as detailed above.
The flush time-out is an 8-bit counter that counts 256
clocks of 24 MHz and triggers DRQ assertion when the
terminal-count is reached, i.e., when flush time-out expires). The counter is enabled for counting backward
when the peripheral state machine writes a byte and
DRQ is not asserted. Once enabled, it counts the 24
MHz clocks. The counter is reset and disabled when
DRQ is asserted. The counter is also reset and disabled
for counting forward and when demand the DMA is disabled.
This mechanism is reset whenever ECP mode is
changed, the same way the FIFO is flushed in this case.
0: Disabled.
1: Enabled.
Automatic Data Transfer
(Modes 010 and 011)
Automatic data transfer (ECP cycles generated by hardware) is supported only in modes 010 and 011 (Parallel Port
and ECP FIFO modes). Automatic DMA access to fill or
empty the FIFO is supported in modes 010, 011 and 110.
Mode 010 is for the forward direction only; the direction bit
is forced to 0 and PD7-0 are driven. Mode 011 is for both
the forward and backward directions. The direction bit controls whether PD7-0 are driven.
Automatic Run Length Expanding (RLE) is supported in the
backward direction.
Forward Direction (Bit 5 of DCR = 0)
When the ECP is in forward direction and the FIFO is not full
(bit 1 of ECR is 0) the FIFO can be filled by software writes
to the FIFO registers (AFIFO and DFIFO in mode 011, and
CFIFO in mode 010).
When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is
0) the ECP automatically issues DMA requests to fill the
FIFO with data bytes (not including command bytes).
When the ECP is in forward direction and the FIFO is not
empty (bit 0 of ECR is 0) the ECP pops a byte from the FIFO
and issues a write signal to the peripheral device. The ECP
drives AFD according to the operation mode (bits 7-5 of
ECR) and according to the tag of the popped byte as follows:
●
In Parallel Port FIFO mode (mode 010) AFD is controlled by bit 1 of DCR.
●
In ECP mode (mode 011) AFD is controlled by the
popped tag. AFD is driven high for normal data bytes
and driven low for command bytes.
ECP (Forward) Write Cycle
An ECP write cycle starts when the ECP drives the popped
tag onto AFD and the popped byte onto PD7-0. When
BUSY is low the ECP asserts STB. In 010 mode the ECP
deactivates STB to terminate the write cycle. In 011 mode
the ECP waits for BUSY to be high.
Bit 7 - Bit 3 of CNFGA
This bit may be utilized by the user. The value of this bit
is reflected on bit 3 of the ECP CNFGA register.
When BUSY is high, the ECP deactivates STB, and changes AFD and PD7-0 only after BUSY is low.
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154
Parallel Port (Logical Device 4)
DETAILED ECP MODE DESCRIPTIONS
TABLE 6-11. ECP Modes
ECP Mode
(ECR Bits)
ECP Mode
Name
7
6
5
0
0
0
Standard
0
0
1
PS/2
0
1
0
0
1
1
ECP FIFO
1
0
0
EPP
1
0
1
Reserved
1
1
0
FIFO Test
1
1
1
Operation Description
Write cycles are under software control.
STB, AFD, INIT and SLIN are open-drain output signals.
Bit 5 of DCR is forced to 0 (forward direction) and PD7-0 are driven.
The FIFO is reset (empty).
Reading DATAR returns the last value written to DATAR.
Read and write cycles are under software control.
The FIFO is reset (empty).
STB, AFD, INIT and SLIN are push-pull output signals.
Parallel Port Write cycles are automatic, i.e., under hardware control (STB is controlled by hardware).
FIFO
Bit 5 of DCR is forced to 0 internally (forward direction) and PD7-0 are driven.
STB, AFD, INIT and SLIN are push-pull output signals.
The FIFO direction is automatic, i.e., controlled by bit 5 of DCR.
Read and write cycles to the device are controlled by hardware (STB and AFD are
controlled by hardware).
STB, AFD, INIT and SLIN are push-pull output signals.
EPP mode is enabled by bits 7 through 5 of the SuperI/O Parallel Port Configuration
register, as described in Section 2.7.1.
In this mode, registers DATAR, DSR, and DCR are used as registers at offsets 00h, 01h and
02h of the EPP instead of registers DTR, STR, and CTR.
STB, AFD, INIT, and SLIN are push-pull output buffers.
When there is no access to one of the EPP registers (ADDR, DATA0, DATA1, DATA2 or
DATA3), mode 100 behaves like mode 001, i.e., software can perform read and write cycles.
The software should check that bit 7 of the DSR is 1 before reading or writing the DATAR
register, to avoid corrupting an ongoing EPP cycle.
The FIFO is accessible via the TFIFO register.
The ECP does not issue ECP cycles to fill or empty the FIFO.
Configuration CNFGA and CNFGB registers are accessible.
to expand the next byte read). Following an RLC read the
ECP issues a read cycle from the peripheral device to read
the data byte to be expanded. This byte is considered a
data byte, regardless of its BUSY state (even if it is low).
This byte is pushed into the FIFO (RLC+1) times (e.g. for
RLC=0, push the byte once. For RLC=127 push the byte
128 times).
AFD
PD7-0
STB
When the ECP is in the backward direction, and the FIFO is
not empty (bit 0 of ECR is 0), the FIFO can be emptied by
software reads from the FIFO register (true only for the
TFIFO in mode 011, not for AFIFO or CFIFO reads).
BUSY
FIGURE 6-34. ECP Forward Write Cycle
When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is
0) the ECP automatically issues DMA requests to empty the
FIFO (only in mode 011).
Backward Direction (Bit 5 of DCR is 1)
When the ECP is in the backward direction, and the FIFO is
not full (bit 1 of ECR is 0), the ECP issues a read cycle to
the peripheral device and monitors the BUSY signal. If
BUSY is high the byte is a data byte and it is pushed into the
FIFO. If BUSY is low the byte is a command byte.
ECP (Backward) Read Cycle
An ECP read cycle starts when the ECP drives AFD low.
The peripheral device drives BUSY high for a normal data
read cycle, or drives BUSY low for a command read cycle,
and drives the byte to be read onto PD7-0.
The ECP checks bit 7 of the command byte. If it is high the
byte is ignored, if it is low the byte is tagged as an RLC byte
(not pushed into the FIFO but used as a Run Length Count
155
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DETAILED ECP MODE DESCRIPTIONS
Parallel Port (Logical Device 4)
6.6.4
When ACK is asserted the ECP drives AFD high. When
AFD is high the peripheral device deasserts ACK. The ECP
reads the PD7-0 byte, then drives AFD low. When AFD is
low the peripheral device may change BUSY and PD7-0
states in preparation for the next cycle
FIFO Test Access (Mode 110)
Mode 110 is for testing the FIFO in PIO and DMA cycles.
Both read and write operations (pop and push) are supported, regardless of the direction bit.
In the forward direction PD7-0 are driven, but the data is undefined. This mode can be used to measure the systemECP cycle throughput, usually with DMA cycles. This mode
can also be used to check the FIFO depth and its interrupt
threshold, usually with PIO cycles.
.
PD7-0
BUSY
AFD
6.6.5
ACK
Configuration Registers Access
(Mode 111)
The two configuration registers, CNFGA and CNFGB, are
accessible only in this mode.
FIGURE 6-35. ECP (Backward) Read Cycle
Notes:
6.6.6
1. FIFO-full condition is checked before every expanded
byte push.
An interrupt is generated when any of the events described
in this section occurs. Interrupt events 2, 3 and 4 are level
events. They are shaped as interrupt pulses, and are
masked (inactive) when the ECP clock is frozen.
2. Switching from modes 010 or 011 to other modes removes pending DMA requests and aborts pending RLE
expansion.
Event 1
Bit 2 of ECR is 0, bit 3 of ECR is 1 and TC is asserted
during ECP DMA cycle. Interrupt event 1 is a pulse
event.
3. FIFO pushes and pops are neither synchronized nor
linked at the hardware level. The FIFO will not delay
these operations, even if performed concurrently. Care
must be taken by the programmer to utilize the empty
and full FIFO status bits to avoid corrupting PD7-0 or
D7-0 while a previous FIFO port access not complete.
Event 2
Bit 2 of ECR is 0, bit 3 of ECR is 0, bit 5 of DCR is 0 and
there are eight or more bytes free in the FIFO.
This event includes the case when bit 2 of ECR is
cleared to 0 and there are already eight or more bytes
free in the FIFO (modes 010, 011 and 110 only).
4. In the forward direction, the empty bit is updated when
the ECP cycle is completed, not when the last byte is
popped from the FIFO (valid cleared on cycle end).
5. ZWS is not asserted for DMA cycles.
Event 3
Bit 2 of ECR is 0, bit 3 of ECR is 0, bit 5 of DCR is 1 and
there are eight or more bytes to be read from the FIFO.
This event includes the case when bit 2 of ECR is
cleared to 0 and there are already eight or more bytes
to be read from the FIFO (modes 011 and 110 only).
6. The one-bit command/data tag is used only in the forward direction.
6.6.3
Automatic Address and Data Transfers
(Mode 100)
Automatic address and data transfer (EPP cycles generated by hardware) is supported in mode 100. Fast transfers
are achieved by automatically generating the address and
data strobes.
Event 4
Bit 4 of ECR is 0 and ERR is asserted (high to low edge)
or ERR is asserted when bit 4 of ECR is modified from
1 to 0.
This event may be lost when the ECP clock is frozen.
In this mode, the FIFO is reset (empty) and is not functional,
the DMA and RLE are idle.
Event 5
When bit 4 of DCR is 1 and ACK is deasserted (low-tohigh edge).
This event behaves as in the normal SPP mode, i.e., the
IRQ signal follows the ACK signal transition.
The direction of the automatic data transfers is determined
by the RD and WR signals. The direction of software data
transfer can be forward or backward, depending on bit 5 of
the DCR. Bit 5 of the DCR determines the default direction
of the data transfers only when there is no on-going EPP cycles.
In EPP mode 100, registers DATAR, DSR and DCR are
used instead of DTR, STR and CTR respectively.
Some differences are caused by the registers. Reading DATAR returns pins values instead of register value returned
when reading DTR. Reading DSR returns register value instead of pins values returned when reading STR. Writing to
the DATAR during an on-going EPP 1.9 forward cycle (i.e.
- when bit 7 of DSR is 1) causes the new data to appear immediately on PD7-0, instead of waiting for BUSY to become
low to switch PD7-0 to the new data when writing to the
DTR.
In addition, the bit 4 of the DCR functions differently relative
to bit 4 of the CTR (IRQ float).
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Interrupt Generation
156
Parallel Port (Logical Device 4)
PARALLEL PORT REGISTER BITMAPS
6.7.1
EPP Modes
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
SPP or EPP Data
Register (DTR)
Offset 00h
Required
EPP Data
Register 0
Offset 04h
Required
D0
D1
D2
D0
D3
D1
D4
D2
D5
D3
D6
D4
D5
EPP Device
Read or Write Data
D7
Data Bits
D6
D7
7
6
5
4
3
2
1
1
1
1
1
1
1
1
0
SPP or EPP Status
Register(STR)
1 Reset
Offset 01h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Required
D8
Time-Out Status
Reserved
IRQ Status
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
7
6
5
4
3
2
1
1
1
0
0
0
0
0
D9
D10
D11
D12
EPP Device
D13
Read or Write Data
D14
D15
0
SPP or EPP Control
Register (CTR)
0 Reset
Offset 02h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
EPP Data
Register 2
Offset 06h
Required
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
7
Reset
EPP Data
Register 1
Offset 05h
D16
D17
D18
D19
D20
EPP Device
D21
Read or Write Data
D22
D23
EPP Address
Register
Offset 03h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
EPP Data
Register 3
Offset 07h
Required
A0
D24
D25
D26
D27
D28
EPP Device
D29
Read or Write Data
D30
D31
A1
A2
A3
A4 EPP Device or
A5
Register Selection
Address Bits
A6
A7
157
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PARALLEL PORT REGISTER BITMAPS
6.7
PARALLEL PORT REGISTER BITMAPS
Parallel Port (Logical Device 4)
6.7.2
ECP Modes
Bits 7-5 of ECR = 010
7
6
0
0
Bits 7-5 of ECR = 000 or 001
5 4 3 2 1 0
ECP Data Register
(DATAR)
0 0 0 0 0 0 Reset
Offset 000h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
Parallel Port FIFO
Register (CFIFO)
Offset 400h
Required
D0
D1
D0
D2
D1
D3
D2
D4
D3
Data Bits
D5
D4
Data Bits
D5
D6
D7
D6
D7
Bits 7-5 of ECR = 011
7
6
5
4
Bits 7-5 of ECR = 011
3 2 1 0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
ECP Address Register
(AFIFO)
0 Reset
Offset 000h
Required
0
0
ECP Data FIFO
Register (DFIFO)
Offset 400h
Required
0 Reset
D0
D1
A0
D2
A1
D3
A2
D4
A3
Data Bits
D5
A4
Address Bits
A5
D6
D7
A6
A7
7
6
5
4
3
2
1
1
1
0
ECP Status Register
(DSR)
1 Reset
Offset 001h
Required
7
6
5
4
0
0
0
0
D0
EPP Time-Out Status
Reserved
Reserved
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0 Reset
D1
D2
D3
D4
D5
Data Bits
D6
D7
ECP Control
Register (DCR)
Offset 002h
Required
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
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Bits 7-5 of ECR = 110
3 2 1 0
Test FIFO
0 0 0 0 Reset Register (TFIFO)
Offset 400h
Required
7
6
5
4
0
0
0
1
0
0
0
1
Bits 7-5 of ECR = 111
3 2 1 0 Configuration Register A
(CNFGA)
0 1 0 0 Reset
Offset 400h
1 0 0 Required
Always 0
Always 0
Always 1
Bit 7 of PP Confg0
Always 1
Always 0
Always 0
Always 0
158
Parallel Port (Logical Device 4)
6
5
4
0
0
0
0
Bits 7-5 of ECR = 111
3 2 1 0 Configuration Register B
(CNFGB)
0 0 0 0 Reset
Offset 401h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
ECP Extended Auxiliary
Status Register (EAR)
0 Reset
Offset 405h
0
Required
DMA Channel Select
Reserved
Reserved
Interrupt Select
IRQ Signal Value
Reserved
7
0
6
0
5
0
4
1
3
2
1
0
FIFO Tag
0
Extended Control
Register(ECR)
1 Reset
Offset 402h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
EPP Time-Out
Interrupt Mask
Reserved
Reserved
Reserved
Freeze Bit
DCR Register Live
FIFO Empty
FIFO Full
ECP Interrupt Service
ECP DMA Enable
ECP Interrupt Mask
ECP Mode Control
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Control0 Register
Second Level
Offset 00h
Required
Reserved
0
ECP Extended Index
Register (EIR)
0 Reset
Offset 403h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
Control2 Register
Second Level
Offset 02h
Required
Reserved
Reserved
Reserved
Second Level Offset
Reserved
Reserved
Reserved
Reserved
Reserved
EPP 1.7 ZWS Control
Revision 1.7 or 1.9 Select
Reserved
Channel Address Enable
SPP Compatability
ECP Extended Data
Register (EDR)
Offset 404h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 Reset
D0
D1
D2
D3
D4
D5
Data Bits
D6
D7
159
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PARALLEL PORT REGISTER BITMAPS
7
PARALLEL PORT PIN/SIGNAL LIST
Parallel Port (Logical Device 4)
6.8
PARALLEL PORT PIN/SIGNAL LIST
TABLE 6-12 "Parallel Port Pinout" shows the standard 25-pin, D-type connector definition for parallel port operations.
TABLE 6-12. Parallel Port Pinout
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Connector Pin
Pin No.
SPP, ECP
Mode
I/O
EPP Mode
I/O
1
112
STB
I/O
WRITE
I/O
2
122
PD0
I/O
PD0
I/O
3
123
PD1
I/O
PD1
I/O
4
124
PD2
I/O
PD2
I/O
5
125
PD3
I/O
PD3
I/O
6
126
PD4
I/O
PD4
I/O
7
127
PD5
I/O
PD5
I/O
8
128
PD6
I/O
PD6
I/O
9
129
PD7
I/O
PD7
I/O
10
113
ACK
I
ACK
I
11
111
BUSY
I
WAIT
I
12
115
PE
I
PE
I
13
114
SLCT
I
SLCT
I
14
119
AFD
I/O
DSTRB
I/O
15
116
ERR
I
ERR
I
16
117
INIT
I/O
INIT
I/O
17
118
SLIN
I/O
ASTRB
I/O
18 - 23
GND
GND
25
GND
GND
160
7.0
Enhanced Serial Port with IR UART2 (Logical Device 5)
The following UART modes are supported:
UART2 supports standard 16450/16550, Enhanced UART
and InfraRed (IR) modes.
16450 or 16550 mode (Non-Extended modes)
●
Extended mode
The 16450 or 16550 mode is functionally and softwarecompatible with the standard 16450 or 16550 UARTs. This
is the default mode of operation after power up, after reset
or when initialized by software written for the 16450 or
16550 UART (Special mechanisms switch the module automatically to 16550 UART mode when standard 16550 software is run).
This module provides advanced, versatile serial communications features with infrared capabilities. It supports four
modes of operation: UART, Sharp-IR, IrDA 1.0 SIR (hereafter called SIR) and Consumer-IR (also called TV-Remote or
Consumer remote-control). In UART mode, the module can
function as a standard 16450 or 16550, or as an Extended
UART.
The 16550 UART mode has all the features of the 16450
mode, with the addition of 16-byte data FIFOs for more efficient data I/O.
Existing 16550-based legacy software is completely and
transparently supported. Module organization and specific
fallback mechanisms switch the module to 16550 compatibility mode upon reset or when initialized by 16550 software.
In Extended mode, additional features become available
that enhance the UART performance, such as additional interrupts and DMA ability (see “Extended UART Mode” on
page 163).
The module includes two DMA channels that can support all
operational modes. The device can use either 1 or 2 DMA
channels. One channel is required for infrared based applications since infrared communications work in half duplex
fashion. Two channels would normally be needed to handle
high-speed full duplex UART based applications.
7.1
●
The UART supports baud rates of up to 115.2 Kbps in 16450
or 16550 mode, and up to 1.5 Mbps in Extended mode.
7.2.2
Sharp-IR, IrDA SIR Infrared Modes
The Sharp-IR mode provides bidirectional communication
by transmitting and receiving infrared radiation. In this
mode, infrared I/O circuits was added to the UART, which
operates at 38.4 Kbps in half-duplex, using normal UART
serial data formats with Digital Amplitude Shift Keying
(DASK) modulation. The modulation/demodulation can be
operated internally or externally.
FEATURES
●
Fully compatible with 16550 and 16450 devices
●
Automatic fallback to 16550 compatibility mode
●
Extended UART mode
●
UART baud rates up to 1.5 Mbps
In SIR mode, the system functions similarly to the Sharp-IR
mode, but at 115.2 Kbps.
●
Sharp-IR with selectable internal or external modulation/demodulation
7.2.3
●
IrDA 1.0 SIR with data rates up to 115.2 Kbps
●
Consumer-IR (TV-Remote) mode
●
Full duplex infrared capability for diagnostics
●
Transmission deferral (in Consumer-IR mode)
●
Selectable 16-level transmission and reception FIFOs
(RX_FIFO & TX_FIFO respectively)
●
Multiple optical transceiver support
●
Automatic or manual transceiver configuration
●
Support for Plug-n-Play infrared adapters
7.2
Consumer-IR mode supports all the protocols presently
used in remote-controlled home entertainment equipment:
RC-5, RC-6, RECS 80, NEC and RCA. The serial format is
not compatible with UART operation, and specific circuitry
performs all the hardware tasks required for signal conditioning and formatting. The software is responsible for the
generation of the infrared code to be transmitted, and for the
interpretation of the received code.
7.3
REGISTER BANK OVERVIEW
Eight register banks, each containing eight registers, control UART operation. All registers use the same 8-byte address space to indicate offsets 00h through 07h, and the
active bank must be selected by the software.
FUNCTIONAL MODES OVERVIEW
The register bank organization enables access to the banks
as required for activation of all module modes, while maintaining transparent compatibility with 16450 or 16550 software, which activates only the registers and specific bits
used in those devices. For details, See Section 7.4.
This multi-mode module can be configured to act as any
one of several different functions. Although each mode is
unique, certain system resources and features are common
to some or to all modes.
7.2.1
Consumer IR Mode
The Bank Selection Register (BSR) selects the active bank
and is common to all banks. See Figure 7-1. Therefore,
each bank defines seven new registers.
UART Modes: 16450 or 16550, and Extended
UART modes support serial data communications with a remote peripheral device or modem using a wired interface.
The device transmits and receives data concurrently in fullduplex operation, performing parallel-to-serial and serial-toparallel conversion and other functions required to exchange parallel data with the system. It also interfaces with
external devices using a programmable serial communications format.
161
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7.0 Enhanced Serial Port with IR - UART2 (Logical Device 5)
Enhanced Serial Port with IR - UART2 (Logical Device 5)
UART MODES – DETAILED DESCRIPTION
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Banks 0 and 1 are the 16550 register banks. The registers
in these banks are equivalent to the registers contained
in the 16550 UARTs and are accessed by 16550 software drivers as if the module was a 16550. Bank 1 contains the legacy Baud Generator Divisor Ports. Bank 0
registers control all other aspects of the UART function,
including data transfers, format setup parameters, interrupt setup and status monitoring.
BANK 7
BANK 6
BANK 5
BANK 4
BANK 3
BANK 2
BANK 1
Bank 2 contains the non-legacy Baud Generator Divisor
Ports, and controls the extended features special to this
UART, that are not included in the 16550 repertoire.
These include DMA usage. See ”Extended UART
Mode” on page 163.
BANK 0
Offset 07h
Bank 3 contains the Module Revision ID and shadow registers. The Module Revision ID (MRID) register contains
a code that identifies the revision of the module when
read by software. The shadow registers contain the
identical content as reset-when-read registers within
bank 0. Reading their contents from the shadow registers lets the system read the register content without resetting them.
Offset 06h
Offset 05h
Offset 04h
LCR/BSR
Common
Register
Throughout
All Banks
Offset 02h
Offset 01h
Bank 4 contains setup parameters for the Infra-red modes.
Bank 5 registers control infrared parameters related to the
logical system I/O parameters.
Bank 6 registers control physical characteristics involved
in infrared communications (e.g. pulse width selection).
Offset 00h
16550 Banks
Bank 7 registers are dedicated to Consumer-IR configuration and control.
FIGURE 7-1. Register Bank Architecture
The default bank selection after system reset is 0, which
places the module in the UART 16550 mode. Additionally,
setting the baud in bank 1 (as required to initialize the 16550
UART) switches the module to a Non-Extended UART
mode. This ensures that running existing 16550 software
will switch the system to the 16550 configuration without
software modification.
7.4
The UART modes support serial data communications with
a remote peripheral device or modem using a wired interface.
The module provides receive and transmit channels that
can operate concurrently in full-duplex mode. This module
performs all functions required to conduct parallel data interchange with the system and composite serial data exchange with the external data channel, including:
Table 7-1 shows the main functions of the registers in each
bank. Banks 0-3 control both UART and infrared modes of
operation; banks 4-7 control and configure the infrared
modes only.
●
Format conversion between the internal parallel data
format and the external programmable composite serial format. See Figure 7-2.
●
Serial data timing generation and recognition
●
Parallel data interchange with the system using a
choice of bi-directional data transfer mechanisms
●
Status monitoring for all phases of the communications activity
TABLE 7-1. Register Bank Summary
Bank
UART
IR
Mode
UART MODES – DETAILED DESCRIPTION
Main Functions
0
✓
✓
Global Control and Status
1
✓
✓
Legacy Bank
2
✓
✓
Baud Generator Divisor,
Extended Control and Status
The module supplies modem control registers, and a prioritized interrupt system for efficient interrupt handling.
3
✓
✓
Module Revision ID and
Shadow Registers
7.4.1
4
✓
IR mode setup
5
✓
Infrared Control
6
✓
Infrared Physical Layer
Configuration
7
✓
Consumer-IR and Optical
Transceiver Configuration
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16450 or 16550 UART Mode
The module defaults to 16450 mode after power up or reset.
UART 16550 mode is equivalent to 16450 mode, with the
addition of a 16-byte data FIFO for more efficient data I/O.
Transparent compatibility is maintained with this UART
mode in this module.
Despite the many additions to the basic UART hardware
and organization, the UART responds correctly to existing
software drivers with no software modification required.
When 16450 software initializes and addresses this module, it will in always perform as a 16450 device.
162
Enhanced Serial Port with IR - UART2 (Logical Device 5)
The software can read the status of the module at any time
during operation. The status information includes full or
empty state for both transmission and reception channels,
and any other condition detected on the received data
stream, like parity error, framing error, data overrun, or
break event.
The composite serial data stream interfaces with the data
channel through signal conditioning circuitry such as
TTL/RS232 converters, modem tone generators, etc.
Data transfer is accompanied by software-generated control signals, which may be utilized to activate the communications channel and “handshake” with the remote device.
These may be supplied directly by the UART, or generated
by control interface circuits such as telephone dialing and
answering circuits, etc.
START -LSB- DATA 5-8 -MSB- PARITY
7.4.2
Extended UART Mode
In Extended UART mode of operation, the module configuration changes and additional features become available
which enhance UART capabilities.
STOP
●
The interrupt sources are no longer prioritized; they
are presented bit-by-bit in the EIR (see page 168).
●
An auxiliary status and control register replaces the
scratchpad register. It contains additional status and
control flag bits (“Auxiliary Status and Control Register
(ASCR)” on page 176).
●
The TX_FIFO can generate interrupts when the number of outgoing bytes in the TX_FIFO drops below a
programmable threshold. In the Non-Extended UART
modes, only reception FIFOs have the thresholding
feature.
●
DMA capability is available.
●
Interrupts occur when the transmitter becomes empty
or a DMA event occurs.
FIGURE 7-2. Composite Serial Data
The composite serial data stream produced by the UART is
illustrated in Figure 7-2. A data word containing five to eight
bits is preceded by start bits and followed by an optional
parity bit and a stop bit. The data is clocked out, LSB first,
at a predetermined rate (the baud).
The data word length, parity bit option, number of start bits
and baud are programmable parameters.
The UART includes a programmable Baud Generator that
produces the baud clocks and associated timing signals for
serial communication.
7.5
The system can monitor this module status at any time. Status information includes the type and condition of the transfer operation in process, as well as any error conditions
(e.g., parity, overrun, framing, or break interrupt).
SHARP-IR MODE – DETAILED DESCRIPTION
This mode supports bidirectional data communication with
a remote device using infrared radiation as the transmission
medium. Sharp-IR uses Digital Amplitude Shift Keying
(DASK) and allows serial communication at baud rates up
to 38.4 Kbaud. The format of the serial data is similar to the
UART data format. Each data word is sent serially beginning with a zero value start bit, followed by up to eight data
bits (LSB first), an optional parity bit, and ending with at
least one stop bit with a binary value of one. A logical zero
is signalled by sending a 500 KHz continuous pulse train of
infrared radiation. A logical 1 is signalled by the absence of
any infrared signal. This module can perform the modulation and demodulation operations internally, or can rely on
the external optical module to perform them.
The module resources include modem control capability
and a prioritized interrupt system. Interrupts can be programmed to match system requirements, minimizing the
CPU overhead required to handle the communications link.
Programmable Baud Generator
This module contains a programmable Baud Generator that
generates the clock rates for serial data communication
(both transmit and receive channels). It divides its input
clock by any divisor value from 1 to 216 - 1. The output clock
frequency of the Baud Generator must be programmed to
be sixteen times the baud value. A 24 MHz input frequency
is divided by a prescale value (PRESL field of EXCR2 - see
page 180. Its default value is 13) and by a 16-bit programmable divisor value contained in the Baud Generator Divisor High and Low registers (BGD(H) and BGD(L) - see page
178). Each divisor value yields a clock signal (BOUT) and a
further division by 16 produces the baud clock for the serial
data stream. It may also be output as a test signal when enabled (see bit 7 of EXCR1 on page 178.)
Sharp-IR device operation is similar to the operation in
UART mode, the main difference being that data transfer
operations are normally performed in half duplex fashion,
and the modem control and status signals are not used. Selection of the Sharp-IR mode is controlled by the Mode Select (MDSL) bits in the MCR register when the module is in
Extended mode, or by the IR_SL bits in the IRCR1 register
when the module is not in extended mode. This prevents
legacy software, running in non-extended mode, from spuriously switching the module to UART mode, when the software writes to the MCR register.
These user-selectable parameters enable the user to generate a large choice of serial data rates, including all standard baud rates. A list of baud rates and their settings
appears in Table 7-14 on page 178.
7.6
SIR MODE – DETAILED DESCRIPTION
Module Operation
This operational mode supports bidirectional data communication with a remote device using infrared radiation as the
transmission medium.
Before module operation can begin, both the communications format and baud must be programmed by the software. The communications format is programmed by
SIR allows serial communication at baud rates up to
115.2 Kbuad. The serial data format is similar to the UART
data format. Each data word is sent serially beginning with
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SHARP-IR MODE – DETAILED DESCRIPTION
loading a control byte into the LCR register, while the baud
is selected by loading an appropriate value into the Baud
Generator Divisor Registers and the divisor preselect values (PRESL) into EXCR2 (see page 180).
Data transfer takes place by use of data buffers that interface internally in parallel and with the external data channel
in a serial format. 16-byte data FIFOs may reduce host
overhead by enabling multiple-byte data transfers within a
single interrupt. With FIFOs disabled, this module is equivalent to the standard 16450 UART. With FIFOs enabled, the
hardware functions as a standard 16550 UART.
CONSUMER-IR MODE – DETAILED DESCRIPTION
Enhanced Serial Port with IR - UART2 (Logical Device 5)
a 0 value start bit, followed by eight data bits (LSB first), an
optional parity bit, and ending with at least one stop bit with
a binary value of 1.
IRTXMC register as well as the TXHSC bit in the RCCFG
register. Sections 7.18.2 and 7.18.3 describe these registers in detail.
A zero value is signalled by sending a single infrared pulse.
A one value is signalled by not sending any pulse. The width
of each pulse can be either 1.6 µsec or 3/16 of the time required to transmit a single bit. (1.6 µsec equals 3/16 of the
time required to transmit a single bit at 115.2 Kbps). This
way, each word begins with a pulse for the start bit.
The RC_MMD field selects the transmitter modulation
mode. If C_PLS mode is selected, modulating pulses are
generated continuously for the entire logic 0 bit time. If
6_PLS or 8_PLS mode is selected, six or eight pulses are
generated each time a logic 0 bit is transmitted following a
logic 1 bit. The total transmission time for the logic 0 bits
must be equal-to or greater-than 6 or 8 times the period of
the modulation subcarrier, otherwise, fewer pulses will be
transmitted.
The module operation in SIR is similar to the operation in
UART mode, the main difference being that data transfer
operations are normally performed in half duplex fashion.
Selection of the IrDA 1.0 SIR mode is controlled by the
MDSL bits in the MCR register when the UART is in Extended mode, or by the IR_SL bits in the IRCR1 register when
the UART is not in Extended mode. This prevents legacy
software, running in Non-Extended mode, from spuriously
switching the module to UART mode, when the software
writes to the MCR register.
7.7
C_PLS modulation mode is used for RC-5, RC-6, NEC and
RCA protocols. 8_PLS or 6_PLS modulation mode is used
for the RECS 80 protocol. The 8_PLS or 6_PLS mode allows minimization of the number of bits needed to represent
the RECS 80 infrared code sequence. The current transmitter implementation supports only the modulated modes of
the RECS 80 protocol. It does not support Flash mode.
7.7.2
CONSUMER-IR MODE – DETAILED DESCRIPTION
The Consumer-IR receiver is significantly different from a
UART receiver in two ways. Firstly, the incoming infrared
signals are DASK modulated. Therefore, demodulation may
be necessary. Secondly, there are no start bits in the incoming data stream.
The Consumer-IR circuitry in this module is designed to optimally support all the major protocols presently used in remote-controlled home entertainment equipment: RC-5, RC6, RECS 80, NEC and RCA.
This module, in conjunction with an external optical device,
provides the physical layer functions necessary to support
these protocols. These functions include: modulation, demodulation, serialization, deserialization, data buffering,
status reporting, interrupt generation, etc.
Whenever an infrared signal is detected, receiver operations depend on whether or not receiver demodulation is enabled. If demodulation is disabled, the receiver immediately
becomes active. If demodulation is enabled, the receiver
checks the carrier frequency of the incoming signal, and becomes active only if the frequency is within the programmed
range. Otherwise, the signal is ignored and no other action
is taken.
The software is responsible for the generation of the infrared code to be transmitted, and for the interpretation of the
received code.
7.7.1
Consumer-IR Transmission
When the receiver enters the active state, the RXACT bit in
the ASCR register is set to 1. Once in the active state, the
receiver keeps sampling the infrared input signal and generates a bit string where a logic 1 indicates an idle condition
and a logic 0 indicates the presence of infrared energy. The
infrared input is sampled regardless of the presence of infrared pulses at a rate determined by the value loaded into
the Baud Generator Divisor Registers. The received bit
string is either de-serialized and assembled into 8-bit characters, or it is converted to run-length encoded values. The
resulting data bytes are then transferred into the RX_FIFO.
The code to be transmitted consists of a sequence of bytes
that represent either a bit string or a set of run-length codes.
The number of bits or run-length codes usually needed to
represent each infrared code bit depends on the infrared
protocol to be used. The RC-5 protocol, for example, needs
two bits or between one and two run-length codes to represent each infrared code bit.
Transmission is initiated when the CPU or DMA module
writes code bytes into the empty TX_FIFO. Transmission is
normally completed when the CPU sets the S_EOT bit in
the ASCR register (See Section 7.11.10 on page 175), before writing the last byte, or when the DMA controller activates the TC (terminal count) signal. Transmission will also
terminate if the CPU simply stops transferring data and the
transmitter becomes empty. In this case, however, a transmitter-underrun condition will be generated, which must be
cleared in order to begin the next transmission.
The receiver also sets the RXWDG bit in the ASCR register
each time an infrared pulse signal is detected. This bit is automatically cleared when the ASCR register is read, and it
is intended to assist the software in determining when the
infrared link has been idle for a certain time. The software
can then stop the data reception by writing a 1 into the RXACT bit to clear it and return the receiver to the inactive
state.
The transmission bytes are either de-serialized or runlength encoded, and the resulting bit string modulates a carrier signal and is sent to the transmitter LED. The transfer
rate of this bit string, like in the UART mode, is determined
by the value programmed in the Baud Generator Divisor
Registers. Unlike a UART transmission, start, stop and parity bits are not included in the transmitted data stream. A
logic 1 in the bit string keeps the LED off, so no infrared signal is transmitted. A logic 0, generates a sequence of modulating pulses which will turn on the transmitter LED.
Frequency and pulse width of the modulating pulses are
programmed by the MCFR and MCPW fields in the
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Consumer-IR Reception
The frequency bandwidth for the incoming modulated infrared signal is selected by the DFR and DBW fields in the IRRXDC register.
There are two Consumer-IR reception data modes: “Oversampled” and “Programmed T Period” mode. For either
mode the sampling rate is determined by the setting of the
Baud Generator Divisor Registers.
The “Over-sampled” mode can be used with the receiver
demodulator either enabled or disabled. It should be used
with the demodulator disabled when a detailed snapshot of
the incoming signal is needed, for example to determine the
period of the carrier signal. If the demodulator is enabled,
164
Enhanced Serial Port with IR - UART2 (Logical Device 5)
The “Programmed-T-Period” mode should be used with the
receiver demodulator enabled. The T Period represents
one half bit time for protocols using biphase encoding, or
the basic unit of pulse distance for protocols using pulse distance encoding. The baud is usually programmed to match
the T Period. For long periods of logic low or high, the receiver samples the demodulated signal at the programmed
sampling rate.
More than 64 µsec or four character times, whichever is
smaller, have elapsed since the last byte was read from
the RX_FIFO by the CPU or DMA controller.
7.8.2
Consumer-IR Mode Time-Out Conditions
The RX_FIFO time-out, in Consumer-IR mode, is disabled
while the receiver is active. It occurs when all of the following are true:
Whenever a new infrared energy pulse is detected, the receiver synchronizes the sampling process to the incoming
signal timing. This reduces timing related errors and eliminates the possibility of missing short infrared pulse sequences, especially with the RECS 80 protocol.
●
At least one byte has been in the RX_FIFO for 64 µsec
or more, and
●
The receiver has been inactive (RXACT = 0) for 64 µsec
or more, and
●
More than 64 µsec have elapsed since the last byte was
read from the RX_FIFO by the CPU or DMA controller.
In addition, the “Programmed-T-Period” sampling minimizes the amount of data used to represent the incoming infrared signal, therefore reducing the processing overhead in
the host CPU.
7.8.3
7.8
Transmission deferral is available only in Extended mode
and when the TX_FIFO is enabled. When transmission deferral is enabled (TX_DFR bit in the MCR register set to 1)
and the transmitter becomes empty, an internal flag is set
and locks the transmitter. If the CPU now writes data into
the TX_FIFO, the transmitter does not start sending the
data until the TX_FIFO level reaches 14 at which time the
internal flag is cleared. The internal flag is also cleared and
the transmitter starts transmitting when a time-out condition
is reached. This prevents some bytes from being in the
TX_FIFO indefinitely if the threshold is not reached.
Transmission Deferral
This feature allows software to send high-speed data in Programmed Input/Output (PIO) mode without the risk of generating a transmitter underrun.
FIFO TIME-OUTS
Time-out mechanisms prevent received data from remaining in the RX_FIFO indefinitely, if the programmed interrupt
or DMA thresholds are not reached.
An RX_FIFO time-out generates a Receiver Data Ready interrupt and/or a receiver DMA request if bit 0 of IER and/or
bit 2 of MCR (in Extended mode) are set to 1 respectively.
An RX_FIFO time-out also sets bit 0 of ASCR to 1 if the
RX_FIFO is below the threshold. When a Receiver Data
Ready interrupt occurs, this bit is tested by the software to
determine whether a number of bytes indicated by the
RX_FIFO threshold can be read without checking bit 0 of
the LSR register.
When a time-out has occurred, it can only be reset when the
FIFO is read by the CPU or DMA controller.
The time-out mechanism is implemented by a timer that is
enabled when the internal flag is set and there is at least
one byte in the TX_FIFO. Whenever a byte is loaded into
the TX_FIFO the timer gets reloaded with the initial value. If
no bytes are loaded for a 64-µsec time, the timer times out
and the internal flag is cleared, thus enabling the transmitter.
7.8.1
7.9
The conditions that must exist for a time-out to occur in the
various modes of operation are described below.
UART, SIR or Sharp-IR Mode Time-Out Conditions
Two timers (timer1 and timer 2) are used to generate two
different time-out events (A and B, respectively). Timer 1
times out after 64 µsec. Timer 2 times out after four character times.
The automatic fallback feature supports existing legacy
software packages that use the 16550 UART by automatically turning off any Extended mode features and switches
the UART to Non-Extended mode when either of the LBGD(L) or LBGD(H) ports in bank 1 is read from or written to
by the CPU.
Time-out event A generates an interrupt and sets the
RXF_TOUT bit (bit 0 of ASCR) when all of the following are
true:
●
At least one byte is in the RX_FIFO, and
●
More than 64 µsec or four character times, whichever is
greater, have elapsed since the last byte was loaded
into the RX_FIFO from the receiver logic, and
●
More than 64 µsec or four character times, whichever is
greater, have elapsed since the last byte was read from
the RX_FIFO by the CPU or DMA controller.
AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE
This eliminates the need for user intervention prior to running a legacy program.
In order to avoid spurious fallbacks, alternate baud registers
are provided in bank 2. Any program designed to take advantage of the UART’s extended features, should not use
LBGD(L) and LBGD(H) to change the baud. It should use
the BGD(L) and BGD(H) registers instead. Access to these
ports will not cause fallback.
Time-out event B activates the receiver DMA request and is
invisible to the software. It occurs when all of the following
are true:
●
At least one byte is in the RX_FIFO, and
●
More than 64 µsec or four character times, whichever is
smaller, have elapsed since the last byte was loaded
into the RX_FIFO from the receiver logic, and
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FIFO TIME-OUTS
●
the stream of samples can be used to reconstruct the incoming bit string. To obtain good resolution, a fairly high
sampling rate should be selected.
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Fallback can occur in any mode. In Extended UART mode,
fallback is always enabled. In this case, when a fallback occurs, the following happens:
●
Transmission and Reception FIFOs switch to 16 levels.
●
A value of 13 is selected for the Baud Generator Prescaler
●
The BTEST and ETDLBK bits in the EXCR1 register
are cleared.
●
UART mode is selected.
●
7.11 BANK 0 – GLOBAL CONTROL AND STATUS
REGISTERS
In the Non-Extended modes of operation, bank 0 is compatible with both the 16450 and the 16550. Upon reset, this
module defaults to the 16450 mode. In the Extended mode,
all the Registers (except RXD/ TXD) offer additional features.
TABLE 7-2. Bank 0 Serial Controller Base Registers
Offset
A switch to a Non-Extended UART mode occurs.
Register
Name
Description
When a fallback occurs in a Non-Extended UART mode, the
last two of the above actions do not take place.
00h
RXD/
TXD
Receiver Data Port/ Transmitter Data
Port
No switch to UART mode occurs if either SIR or Sharp-IR
mode was selected. This prevents spurious switching to
UART mode when a legacy program running in infrared
mode accesses the Baud Generator Divisor Registers from
bank 1.
01h
IER
Interrupt Enable Register
02h
EIR/
FCR
Event Identification Register/
FIFO Control Register
03h
LCR/
BSR
Link Control Register/
Bank Select Register
04h
MCR
Modem Control Register
05h
LSR
Link Status Register
06h
MSR
Modem Status Register
07h
SCR/
ASCR
Scratch Register/
Auxiliary Status and Control Register
Fallback from a Non-Extended mode can be disabled by
setting the LOCK bit in register EXCR2. When LOCK is set
to 1 and the UART is in a Non-Extended mode, two scratch
registers overlaid with LBGD(L) and LBGD(H) are enabled.
Any attempted CPU access of LBGD(L) and LBGD(H) accesses the scratch registers, and the baud setting is not affected. This feature allows existing legacy programs to run
faster than 115.2 Kbps.
7.10 OPTICAL TRANSCEIVER INTERFACE
This module implements a flexible interface for the external
infrared transceiver. Several signals are provided for this
purpose. A transceiver module with one or two reception
signals, or two transceiver modules can interface directly
with this module without any additional logic.
7.11.1 Receiver Data Port (RXD) or the Transmitter
Data Port (TXD)
Since various operational modes are supported by this
module, the transmitter power as well as the receiver filter
in the transceiver module must be configured according to
the selected mode.
RXD is accessed during CPU read cycles. It is used to read
data from the Receiver Holding Register when the FIFOs
are disabled, or from the bottom of the RX_FIFO when the
FIFOs are enabled. See Figure 7-3.
This module provides four interface pins to control the infrared transceiver. ID/IRSL(2-0) are three I/O pins and ID3 is
an Input pin. All of these pins are powered up as inputs.
Receiver Data Port (RXD)
These ports share the same address.
7
When in input mode, they can be used to read the identification data of Plug-n-Play infrared adapters.
6
5
4
3
2
1
0
Reset
When in output mode, the logic levels of IRSL(2-0) can be
either controlled directly by the software by setting bits 2-0
of the IRCFG1 register, or they can be automatically selected by this module whenever the operation mode changes.
Required
Receiver Data
Port (RXD)
Bank 0,
Offset 00h
The automatic transceiver configuration is enabled by setting the AMCFG bit (bit 7) in the IRCFG4 register to 1. It allows the low-level functional details of the transceiver
module being used to be hidden from the software drivers.
Received Data
The operation mode settings for the automatic configuration
are determined by various bit fields in the Infrared Interface
Configuration registers (IRCFG[4-1]) that must be programmed when the UART is initialized.
FIGURE 7-3. RXD Register Bitmap
The ID0/IRSL0/IRRX2 pin can also be used as an input to
support an additional infrared reception signal. In this case,
however, only two configuration pins are available.
Bits 7-0 - Received Data
Used to access the Receiver Holding Register when the
FIFOs are disabled, or the bottom of the RX_FIFO when
the FIFOs are enabled.
The IRSL0_DS and IRSL21_DS bits in the IRCFG4 register
determines the direction of IRSL(2-0).
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166
Enhanced Serial Port with IR - UART2 (Logical Device 5)
If an interrupt source must be disabled, the CPU can do so
by clearing the corresponding bit in the IER register. However, if an interrupt event occurs just before the corresponding enable bit in the IER register is cleared, a spurious
interrupt may be generated. To avoid this problem, the
clearing of any IER bit should be done during execution of
the interrupt service routine. If the interrupt controller is programmed for level-sensitive interrupts, the clearing of IER
bits can also be performed outside the interrupt service routine, but with the CPU interrupt disabled.
DMA cycles always access the TXD and RXD ports, regardless of the selected bank.
Transmitter Data Port (TXD)
7
6
5
4
3
2
1
0
Interrupt Enable Register (IER), in the Non-Extended
Modes (UART, SIR and Sharp-IR)
Transmitter Data
Port (TXD)
Reset
Bank 0,
Offset 00h
Required
Upon reset, the IER supports UART, SIR and Sharp-IR in
the Non-Extended modes. Figure 7-5 shows the bitmap of
the Interrupt Enable Register in these modes.
IER in Non-Extended Modes
7
0
Transmitted Data
Bits 7-0 - Transmitted Data
Used to access the Transmitter Holding Register when
the FIFOs are disabled or the top of TX_FIFO when the
FIFOs are enabled.
7.11.2 Interrupt Enable Register (IER)
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
Setting this bit enables interrupts on Receiver HighData-Level, or RX_FIFO Time-Out events (EIR Bits 3-0
are 0100 or 1100. See Table 7-3 on page 169).
0: Disable Receiver High-Data-Level and RX_FIFO
Time-Out interrupts (Default).
1: Enable Receiver High-Data-Level and RX_FIFO
Time-Out interrupts.
The different modes can be divided into the following four
groups:
●
UART and Sharp-IR in Extended mode.
●
SIR in Extended mode.
●
Consumer-IR.
Interrupt Enable
Register (IER)
Bank 0,
Required
Offset 01h
FIGURE 7-5. IER Register Bitmap, Non-Extended Mode
This register controls the enabling of various interrupts.
Some interrupts are common to all operating modes of the
module, while others are mode specific. Bits 4 to 7 can be
set in Extended mode only. They are cleared in Non-Extended mode. The bits of the Interrupt Enable Register
(IER) are defined differently, depending on the operating
mode of the module.
Non-Extended (which includes UART, Sharp-IR and
SIR).
5 4 3 2 1 0
0 0 0 0 0 0 Reset
RXHDL_IE
TXLDL_IE
LS_IE
MS_IE
Reserved
Reserved
Reserved
Reserved
FIGURE 7-4. TXD Register Bitmap
●
6
0
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
Setting this bit enables interrupts on Transmitter Low
Data-Level-events (EIR Bits 3-0 are 0010. See Table
7-3 on page 169).
0: Disable Transmitter Low-Data-Level Interrupts (Default).
1: Enable Transmitter Low-Data-Level Interrupts.
The following sections describe the bits in this register for
each of these modes.
The reset mode for the IER is the Non-Extended UART
mode.
When edge-sensitive interrupt triggers are employed, user is
advised to clear all IER bits immediately upon entering the interrupt service routine and to re-enable them prior to exiting
(or alternatively, to disable CPU interrupts and re-enable prior to exiting). This will guarantee proper interrupt triggering in
the interrupt controller in case one or more interrupt events
occur during execution of the interrupt routine.
Bit 2 - Link Status Interrupt Enable (LS_IE)
Setting this bit enables interrupts on Link Status events.
(EIR Bits 3-0 are 0110. See Table 7-3 on page 169).
0: Disable Link Status Interrupts (LS_EV) (Default).
1: Enable Link Status Interrupts (LS_EV).
If the LSR, MSR or EIR registers are to be polled, interrupt
sources which are identified by self-clearing bits should
have their corresponding IER bits set to 0, to prevent spurious pulses on the interrupt output pin.
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Setting this bit enables the interrupts on Modem Status
events. (EIR Bits 3-0 are 0000. See Table 7-3 on page
169).
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BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
TXD is accessed during CPU write cycles. It is used to write
data to the Transmitter Holding Register when the FIFOs
are disabled, or to the TX_FIFO when the FIFOs are enabled. See Figure 7-4.
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Bit 4 - DMA Interrupt Enable (DMA_IE)
Setting this bit enables the interrupt on terminal count
when the DMA is enabled.
0: Disable DMA terminal count interrupt (Default)
1: Enable DMA terminal count interrupt.
0 - Disable Modem Status Interrupts (MS_EV) (Default).
1: Enable Modem Status Interrupts (MS_EV).
Bits 7-4- Reserved
These bits are reserved.
Bit 5 - Transmitter Empty Interrupt Enable (TXEMP_IE)
Setting this bit enables interrupt generation if the transmitter and TX_FIFO become empty.
0: Disable Transmitter Empty interrupts (Default)
1: Enable Transmitter Empty interrupts.
Interrupt Enable Register (IER), in the Extended Modes
of UART, Sharp-IR and SIR
Figure 7-6 shows the bitmap of the Interrupt Enable Register in these modes.
Extended Mode of UART, Sharp-IR and SIR
7
0
6
0
Bits 7,6 - Reserved
Reserved.
5 4 3 2 1 0
0 0 0 0 0 0 Reset
Interrupt Enable
Register (IER)
Bank 0,
Required
Offset 01h
Interrupt Enable Register (IER), Consumer-IR Mode
Figure 7-7 shows the bitmap of the Interrupt Enable Register (IER) in this mode.
RXHDL_IE
TXLDL_IE
LS_IE
MS_IE
DMA_IE
TXEMP_IE
Reserved
Reserved
Consumer-IR Mode
7
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
Interrupt Enable
Register (IER)
Bank 0,
Required
Offset 01h
RXHDL_IE
TXLDL_IE
LS_IE or TXUR_IE
MS_IE
DMA_IE
TXEMP_IE
Reserved
Reserved
FIGURE 7-6. IER Register Bitmap, Extended Modes of
UART and Sharp-IR
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
Setting this bit enables interrupts when the RX_FIFO is
equal to or above the RX_FIFO threshold level, or an
RX_FIFO time out occurs.
0: Disable Receiver Data Ready interrupt. (Default)
1: Enable Receiver Data Ready interrupt.
FIGURE 7-7. IER Register Bitmap, Consumer-IR Mode
Bit 1-0 Same as in the Extended Modes of UART and Sharp-IR
(See previous sections).
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
Setting this bit enables interrupts when the TX_FIFO is
below the threshold level or the Transmitter Holding
Register is empty.
0: Disable Transmitter Low-Data-Level Interrupts (Default).
1: Enable Transmitter Low-Data-Level Interrupts.
Bit 2 - Link Status Interrupt Enable (LS_IE) or TX_FIFO
Underrun Interrupt Enable (TXUR_IE)
On reception, Setting this bit enables Link Status Interrupts.
On transmission, Setting this bit enables TX_FIFO underrun interrupts.
0: Disable Link Status and TX_FIFO underrun interrupts (Default)
1: Enable Link Status and TX_FIFO underrun interrupts.
Bit 2 - Link Status Interrupt Enable (LS_IE)
Setting this bit enables interrupts on Link Status events.
0: Disable Link Status Interrupts (LS_EV) (Default)
1: Enable Link Status Interrupts (LS_EV).
Bit 7-3 Same as in the Extended Modes of UART and Sharp-IR
(See the section “Interrupt Enable Register (IER), in the
Extended Modes of UART, Sharp-IR and SIR” on page
168).
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Setting this bit enables the interrupts on Modem Status
events.
0: Disable Modem Status Interrupts (MS_EV) (Default)
1: Enable Modem Status Interrupts (MS_EV).
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6
0
7.11.3 Event Identification Register (EIR)
The Event Identification Register (EIR) and the FIFO
Control Register (FCR) (see next register description)
share the same address. The EIR is accessed during CPU
read cycles while the FCR is accessed during CPU write cy-
168
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Event Identification Register (EIR), Non-Extended Mode
Bits 2,1 - Interrupt Priority 1,0 (IPR1,0)
When bit 0 (IPF) is 0, these bits indicate the pending interrupt with the highest priority. See Table 7-3 on page
169.
Default value is 00.
When Extended mode is not selected (EXT_SL bit in
EXCR1 register is set to 0), this register is the same as in
the 16550.
In a Non-Extended UART mode, this module prioritizes interrupts into four levels. The EIR indicates the highest level
of interrupt that is pending. The encoding of these interrupts
is shown in Table 7-3 on page 169.
7
0
6
0
Bit 3 - RX_FIFO Time-Out (RXFT)
In the 16450 mode, this bit is always 0. In the 16550
mode (FIFOs enabled), this bit is set to 1 when an
RX_FIFO read time-out occurred and the associated interrupt is currently the highest priority pending interrupt.
Non-Extended Modes, Read Cycles
Event Identification
5 4 3 2 1 0
Register (EIR)
0 0 0 0 0 1 Reset
Bank 0,
Offset 02h
0 0
Required
Bits 5,4 - Reserved
Read/Write 0.
IPF - Interrupt Pending
IPR0 - Interrupt Priority 0
IPR1 - Interrupt Priority 1
RXFT - RX_FIFO Time-Out
Reserved
Reserved
FEN0 - FIFOs Enabled
FEN1 - FIFOs Enabled
Bit 7,6 - FIFOs Enabled (FEN1,0)
0: No FIFO enabled. (Default)
1: FIFOs are enabled (bit 0 of FCR is set to 1).
FIGURE 7-8. EIR Register Bitmap, Non-Extended Modes
TABLE 7-3. Non-Extended Mode Interrupt Priorities
Interrupt Set and Reset Functions
EIR Bits
3210
Priority
Level
Interrupt Type
Interrupt Source
Interrupt Reset Control
0001
−
None
None
−
0110
Highest
Link Status
0100
Second
Receiver High
Data Level
Event
1100
Second
0010
Third
0000
Fourth
Parity error, framing error, data overrun Read Link Status Register (LSR).
or break event
Receiver Holding Register (RXD) full, or Reading the RXD or, RX_FIFO level
RX_FIFO level equal to or above
drops below threshold.
threshold.
RX_FIFO Time- At least one character is in the
Reading the RXD port.
Out
RX_FIFO, and no character has been
input to or read from the RX_FIFO for 4
character times.
Transmitter Low Transmitter Holding Register or
Data Level
TX_FIFO empty.
Event
Reading the EIR Register if this
interrupt is currently the highest
priority pending interrupt, or writing
into the TXD port.
Modem Status Any transition on CTS, DSR or DCD or a Reading the Modem Status Register
low to high transition on RI.
(MSR).
Event Identification Register (EIR), Extended Mode
When this register is read the DMA event bit (bit 4) is
cleared if an 8237 type DMA is used. All other bits are
cleared when the corresponding interrupts are acknowledged by reading the relevant register (e.g. reading MSR
clears MS_EV bit).
In Extended mode, each of the previously prioritized and
encoded interrupt sources is broken down into individual
bits. Each bit in this register acts as an interrupt pending
flag, and is set to 1 when the corresponding event occurred
or is pending, regardless of the IER register bit setting.
169
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BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Bit 0 - Interrupt Pending Flag (IPF)
0: There is an interrupt pending.
1: No interrupt pending. (Default)
cles.The Event Identification Register (EIR) indicates the interrupt source. The function of this register changes
according to the selected mode of operation.
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7
0
6
0
Bit 4 - DMA Event Occurred (DMA_EV)
When an 8237 type DMA controller is used, this bit is set
to 1 when a DMA terminal count (TC) is signalled. It is
cleared upon read.
Extended Mode, Read Cycles
Event Identification
5 4 3 2 1 0
Register (EIR)
0 0 0 0 0 1 Reset
Bank 0,
Offset 02h
Required
Bit 5 - Transmitter Empty (TXEMP_EV)
In UART, Sharp-IR and Consumer-IR modes, this bit is
the same as bit 6 of the LSR register. It is set to 1 when
the transmitter is empty.
RXHDL_EV
TXLDL_EV
LS_EV or TXHLT_EV
MS_EV
DMA_EV
TXEMP-EV
Reserved
Reserved
Bits 7,6 - Reserved
Read/Write 0.
7.11.4 FIFO Control Register (FCR)
The FIFO Control Register (FCR) is write only. It is used to
enable the FIFOs, clear the FIFOs and set the interrupt
thresholds levels for the reception and transmission FIFOs.
FIGURE 7-9. EIR Register Bitmap, Extended Mode
Bit 0 - Receiver High-Data-Level Event (RXHDL_EV)
When FIFOs are disabled, this bit is set to 1 when a
character is in the Receiver Holding Register.
When FIFOs are enabled, this bit is set to 1 when the
RX_FIFO is above threshold or an RX_FIFO time-out
has occurred.
7
0
FIGURE 7-10. FCR Register Bitmap
Bit 0 - FIFO Enable (FIFO_EN)
When set to 1 enables both the Transmision and Reception FIFOs. Resetting this bit clears both FIFOs.
In Consumer-IR modes the FIFOs are always enabled
and the setting of this bit is ignored.
Bit 1 - Receiver Soft Reset (RXSR)
Writing a 1 to this bit generates a receiver soft reset,
which clears the RX_FIFO and the receiver logic. This
bit is automatically cleared by the hardware.
Bit 2 - Transmitter Soft Reset (TXSR)
Writing a 1 to this bit generates a transmitter soft reset,
which clears the TX_FIFO and the transmitter logic. This
bit is automatically cleared by the hardware.
Bit 3 - Modem Status Event (MS_EV)
In UART mode this bit is set to 1 when any of the 0 to 3
bits in the MSR register is set to 1.
In any IR mode, the function of this bit depends on the
setting of the IRMSSL bit in the IRCR2 register (see Table 7-4 and also “Bit 1 - MSR Register Function Select
in Infrared Mode (IRMSSL)” on page 183).
Bit 3 - Reserved
Read/Write 0.
Writing to this bit has no effect on the UART operation.
TABLE 7-4. Modem Status Event Detection Enable
1
Forced to 0.
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Bits 5,4 - TX_FIFO Threshold Level (TXFTH1,0)
In Non-Extended modes, these bits have no effect.
In Extended modes, these bits select the TX_FIFO interrupt threshold level. An interrupt is generated when
the level of the data in the TX_FIFO drops below the encoded threshold.
Bit Function
Modem Status Event (MS_EV)
FIFO Control
Register (FCR)
Bank 0,
Offset 02h
Required
FIFO_EN
RXSR
TXSR
Reserved
TXFTH0
TXFTH1
RXFTH0
RXFTH1
Bit 2 - Link Status Event (LS_EV) or Transmitter Halted
Event (TXHLT_EV)
In the UART, Sharp-IR and SIR modes, this bit is set to
1 when a receiver error or break condition is reported.
When FIFOs are enabled, the Parity Error(PE), Frame
Error(FE) and Break(BRK) conditions are only reported
when the associated character reaches the bottom of
the RX_FIFO. An Overrun Error (OE) is reported as
soon as it occurs.
In the Consumer-IR mode, this bit indicates that a Link
Status Event (LS_EV) or a Transmitter Halted Event
(TXHLT_EV) occurred. It is set to 1 when any of the following conditions occurs:
— A receiver overrun.
— A transmitter underrun.
0
Write Cycles
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
Bit 1 - Transmitter Low-Data-Level Event (TXLDL_EV)
When FIFOs are disabled, this bit is set to 1 when the
Transmitter Holding Register is empty.
When FIFOs are enabled, this bit is set to 1 when the
TX_FIFO is below the threshold level.
IRMSSL Value
6
0
170
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Link Control Register (LCR)
TXFTH (Bits 5,4) TX_FIF0 Threshold
Bits 6-0 are only effective in UART, Sharp-IR and SIR
modes. They are ignored in Consumer-IR mode.
00(Default)
1
01
3
10
9
11
13
7
0
Link Control
Register (LCR)
All Banks,
Offset 03h
Required
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
Bits 7,6 - RX_FIFO Threshold Level (RXFTH1,0)
These bits select the RX_FIFO interrupt threshold level.
An interrupt is generated when the level of the data in
the RX_FIFO is equal to or above the encoded threshold.
TABLE 7-6. RX_FIFO Level Selection
FIGURE 7-11. LCR Register Bitmap
RXFTH (Bits 5,4) RX_FIF0 Threshold
00(Default)
1
01
4
Bits 1,0 - Character Length Select (WLS1,0)
These bits specify the number of data bits in each transmitted or received serial character. Table 7-7 shows
how to encode these bits.
10
8
TABLE 7-7. Word Length Select Encoding
11
14
7.11.5 Link Control Register (LCR) and Bank
Selection Register (BSR)
The Link Control Register (LCR) and the Bank Select
Register (BSR) (see the next register) share the same address.
The Link Control Register (LCR) selects the communications format for data transfers in UART, SIR and Sharp-IR
modes.
Reading the register at this address location returns the
content of the BSR. The content of LCR may be read from
the Shadow of Link Control Register (SH_LCR) register in
bank 3 (See Section 7.14.2 on page 181). During a write operation to this register at this address location, the setting of
bit 7 (Bank Select Enable, BKSE) determines whether LCR
or BSR is to be accessed, as follows:
●
WLS0
Character Length
0
0
5 (Default)
0
1
6
1
0
7
1
1
8
Bits 2 - Number of Stop Bits (STB)
This bit specifies the number of stop bits transmitted
with each serial character.
0: One stop bit is generated. (Default)
1: If the data length is set to 5-bits via bits 1,0
(WLS1,0), 1.5 stop bits are generated. For 6, 7 or 8
bit word lengths, two stop bits are transmitted. The
receiver checks for one stop bit only, regardless of
the number of stop bits selected.
Upon reset, all bits are set to 0.
●
WLS1
If bit 7 is 0, the write affects both LCR and BSR.
Bit 3 - Parity Enable (PEN)
This bit enable the parity bit See Table 7-8 on page 172.
The parity enable bit is used to produce an even or odd
number of 1s when the data bits and parity bit are
summed, as an error detection device.
0: No parity bit is used. (Default)
1: A parity bit is generated by the transmitter and
checked by the receiver.
If bit 7 is 1, the write affects only BSR, and LCR remains
unchanged. This prevents the communications format
from being spuriously affected when a bank other than
0 or 1 is accessed.
Upon reset, all bits are set to 0.
Bit 4 - Even Parity Select (EPS)
When Parity is enabled (PEN is 1), this bit, together with
bit 5 (STKP), controls the parity bit as shown in Table
7-8.
0: If parity is enabled, an odd number of logic 1s are
transmitted or checked in the data word bits and
parity bit. (Default)
171
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BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
TABLE 7-5. TX_FIFO Level Selection
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7.11.6 Bank Selection Register (BSR)
1: If parity is enabled, an even number of logic 1s are
transmitted or checked.
Bit 5 - Stick Parity (STKP)
When Parity is enabled (PEN is 1), this bit, together with
bit 4 (EPS), controls the parity bit as show in Table 7-8.
7
0
6
0
Required
TABLE 7-8. Bit Settings for Parity Control
PEN
EPS
STKP
Selected Parity Bit
0
x
x
None
1
0
0
Odd
1
1
0
Even
1
0
1
Logic 1
1
1
1
Logic 0
Bank Selection
Register (BSR)
All Banks,
Offset 03h
5 4 3 2 1 0
0 0 0 0 0 0 Reset
Bank Selection
BKSE-Bank Selection Enable
FIGURE 7-12. BSR Register Bitmap
The Bank Selection Register (BSR) selects which register
bank is to be accessed next.
Bit 6 - Set Break (SBRK)
This bit enables or disables a break. During the break,
the transmitter can be used as a character timer to accurately establish the break duration.
This bit acts only on the transmitter front-end and has no
effect on the rest of the transmitter logic.
When set to 1 the following occurs:
— If a UART mode is selected, the SOUT pin is forced
to a logic 0 state.
— If SIR mode is selected, pulses are issued continuously on the IRTX pin.
— If Sharp-IR mode is selected and internal modulation is enabled, pulses are issued continuously on
the IRTX pin.
— If Sharp-IR mode is selected and internal modulation is disabled, the IRTX pin is forced to a logic 1
state.
To avoid transmission of erroneous characters as a result of the break, use the following procedure to set
SBRK:
About accessing this register see the description of bit
7 of the LCR Register.
Bits 6-0 - Bank Selection
When bit 7 is set to 1, bits 6-0 of BSR select the bank,
as shown in Table 7-9.
Bit 7 - Bank Selection Enable (BKSE)
0: Bank 0 is selected.
1: Bits 6-0 specify the selected bank.
TABLE 7-9. Bank Selection Encoding
BSR Bits
Bank
Selected
7
6
5
4
3
2
1
0
0
x
x
x
x
x
x
x
0
1. Wait for the transmitter to be empty. (TXEMP = 1).
1
0
x
x
x
x
x
x
1
2. Set SBRK to 1.
1
1
x
x
x
x
1
x
1
3. Wait for the transmitter to be empty, and clear SBRK
when normal transmission must be restored.
1
1
x
x
x
x
x
1
1
1
1
1
0
0
0
0
0
2
1
1
1
0
0
1
0
0
3
1
1
1
0
1
0
0
0
4
1
1
1
0
1
1
0
0
5
1
1
1
1
0
0
0
0
6
1
1
1
1
0
1
0
0
7
1
1
1
1
1
x
0
0
Reserved
1
1
0
x
x
x
0
0
Reserved
Bit 7 - Bank Select Enable (BKSE)
0: This register functions as the Link Control Register
(LCR).
1: This register functions as the Bank Select Register
(BSR).
LCR
LCR is
written
LCR is not
written
7.11.7 Modem/Mode Control Register (MCR)
This register controls the interface with the modem or data
communications set, and the device operational mode
when the device is in the Extended mode. The register
function differs for Extended and Non-Extended modes.
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172
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
Extended Mode
7
0
Modem Control
Register (MCR)
Bank 0,
Offset 04h
Required
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
Modem Control
Register (MCR)
Bank 0,
Offset 04h
Required
DTR
RTS
DMA_EN
TX_DFR
Reserved
MDSL0
MDSL1
MDSL2
DTR
RTS
RILP
ISEN or DCDLP
LOOP
Reserved
Reserved
Reserved
FIGURE 7-14. MCR Register Bitmap, Extended Modes
FIGURE 7-13. MCR Register Bitmap, Non-Extended
Mode
Bit 0 - Data Terminal Ready (DTR)
This bit controls the DTR signal output. When set to1,
DTR is driven low. When loopback is enabled (LOOP is
set), this bit internally drives both DSR and RI.
Bit 0 - Data Terminal Ready (DTR)
This bit controls the DTR signal output. When set to 1,
DTR is driven low. When loopback is enabled (LOOP is
set to 1), this bit internally drives DSR.
Bit 1 - Request To Send (RTS)
This bit controls the RTS signal output. When set to1,
RTS is driven low. When loopback is enabled (LOOP is
set), this bit internally drives both CTS and DCD.
Bit 1 - Request To Send (RTS)
This bit controls the RTS signal output. When set to 1,
drives RTS low. When loopback is enabled (LOOP is
set), this bit drives CTS, internally.
Bit 2 - DMA Enable (DMA_EN)
When set to1, DMA mode of operation is enabled. When
DMA is selected, transmit and/or receive interrupts
should be disabled to avoid spurious interrupts.
DMA cycles always address the Data Holding Registers
or FIFOs, regardless of the selected bank.
Bit 2 - Loopback Interrupt Request (RILP)
When loopback is enabled, this bit internally drives RI.
Otherwise it is unused.
Bit 3 - Interrupt Signal Enable (ISEN) or Loopback DCD
(DCDLP)
In normal operation (standard 16450 or 16550) mode,
this bit controls the interrupt signal and must be set to 1
in order to enable the interrupt request signal.
When loopback is enabled, the interrupt output signal is
always enabled, and this bit internally drives DCD.
New programs should always keep this bit set to 1 during normal operation. The interrupt signal should be
controlled through the Plug-n-Play logic.
Bit 3 - Transmission Deferral (TX_DFR)
For a detailed description of the Transmission Deferral
see “Transmission Deferral” on page 165.
0: No transmission deferral enabled. (Default)
1: Transmission deferral enabled.
This bit is effective only if the Transmission FIFOs is enabled.
Bit 4 - Reserved
Read/Write 0.
Bit 4 - Loopback Enable (LOOP)
When this bit is set to 1, it enables loopback. This bit accesses the same internal register as bit 4 of the EXCR1
register. (see “Bit 4 - Loopback Enable (LOOP)” on page
179 for more information on the Loopback mode).
0: Loopback disabled. (Default)
1: Loopback enabled.
Bits 7-5 - Mode Select (MDSL2-0)
These bits select the operational mode of the module
when in Extended mode, as shown in Table 7-10.
When the mode is changed, the transmission and reception FIFOs are flushed, Link Status and Modem Status Interrupts are cleared, and all of the bits in the
auxiliary status and control register are cleared.
Bits 7-5 - Reserved
Read/Write 0.
Modem/Mode Control Register (MCR), Extended Mode
In Extended mode, this register is used to select the operation mode (IrDA, Sharp, etc.) of the device and to enable the
DMA interface. In these modes, the interrupt output signal
is always enabled, and loopback can be enabled by setting
bit 4 of the EXCR1 register.
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BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Modem/Mode Control Register (MCR), Non-Extended
Mode
Non-Extended UART mode
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Bit 1 - Overrun Error (OE)
This bit is set to 1 as soon as an overrun condition is detected by the receiver.
Cleared upon read.
With FIFOs Disabled:
An overrun occurs when a new character is completely
received into the receiver front-end section and the CPU
has not yet read the previous character in the receiver
holding register. The new character is discarded, and
the receiver holding register is not affected.
With FIFOs Enabled:
An overrun occurs when a new character is completely
received into the receiver front-end section and the
RX_FIFO is full. The new character is discarded, and
the RX_FIFO is not affected.
TABLE 7-10. The Module Operation Modes
MDSL2
MDSL1
MDSL0
(Bit 7)
(Bit 6)
(Bit 5)
0
0
0
UART mode (Default)
0
0
1
Reserved
0
1
0
Sharp-IR
0
1
1
SIR
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Consumer-IR
1
1
1
Reserved
Operational Mode
Bit 2 - Parity Error (PE)
In UART, Sharp-IR and SIR modes, this bit is set to 1 if
the received data character does not have the correct
parity, even or odd as selected by the parity control bits
of the LCR register.
If the FIFOs are enabled, this error is associated with
the particular character in the FIFO that it applies to.
This error is revealed to the CPU when its associated
character is at the bottom of the RX_FIFO.
This bit is cleared upon read.
7.11.8 Link Status Register (LSR)
This register provides status information concerning the
data transfer. Bits 1 through 4 indicate link status events.
These bits are sticky (accumulate the occurrence of error
conditions since the last time they were read). They are
cleared when one of the following events occurs:
●
Hardware reset.
●
The receiver is soft-reset.
●
The LSR register is read.
Bit 3 - Framing Error (FE)
In UART, Sharp-IR and SIR modes, this bit is set to 1
when the received data character does not have a valid
stop bit (i.e., the stop bit following the last data bit or parity bit is a 0).
If the FIFOs are enabled, this Framing Error is associated with the particular character in the FIFO that it applies to. This error is revealed to the CPU when its
associated character is at the bottom of the RX_FIFO.
After a framing error is detected, the receiver will try to
resynchronize.
If the bit following the erroneous stop bit is 0, the receiver assumes it to be a valid start bit and shifts in the new
character. If that bit is a 1, the receiver enters the idle
state and awaits the next start bit.
This bit is cleared upon read.
Upon reset this register assumes the value of 0x60h.
The bit definitions change depending upon the operation
mode of the module.
Bits 4 through 1 of the LSR are the error conditions that generate a Receiver Link Status interrupt whenever any of the
corresponding conditions are detected and that interrupt is
enabled.
The LSR is intended for read operations only. Writing to the
LSR is not permitted
7
0
6
1
5 4 3 2 1 0
1 0 0 0 0 0 Reset
Link Status
Register (LSR)
Bank 0,
Offset 05h
Required
Bit 4 - Break Event Detected (BRK)
In UART, Sharp-IR and SIR modes this bit is set to 1
when a break event is detected (i.e. when a sequence
of logic 0 bits, equal or longer than a full character transmission, is received). If the FIFOs are enabled, the
break condition is associated with the particular character in the RX_FIFO to which it applies. In this case, the
BRK bit is set when the character reaches the bottom of
the RX_FIFO.
When a break event occurs, only one zero character is
transferred to the Receiver Holding Register or to the
RX_FIFO.
The next character transfer takes place after at least
one logic 1 bit is received followed by a valid start bit.
RXDA
OE
PE
FE
BRK
TXRDY
TXEMP
ER_INF
FIGURE 7-15. LSR Register Bitmap
Bit 0 - Receiver Data Available (RXDA)
Set to 1 when the Receiver Holding Register is full.
If the FIFOs are enabled, this bit is set when at least one
character is in the RX_FIFO.
Cleared when the CPU reads all the data in the Holding
Register or in the RX_FIFO.
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This bit is cleared upon read.
Bit 5 - Transmitter Ready (TXRDY)
This bit is set to 1 when the Transmitter Holding Register or the TX_FIFO is empty.
174
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7
X
Bit 6 - Transmitter Empty (TXEMP)
This bit is set to 1 when the Transmitter Holding Register or the TX_FIFO is empty, and the transmitter frontend is idle.
6
X
5 4 3 2 1 0
X X 0 0 0 0 Reset
Modem Status
Register (MSR)
Bank 0,
Offset 06h
Required
DCTS
DDSR
TERI
DDCD
CTS
DSR
Bit 7 - Error in RX_FIFO (ER_INF)
In UART, Sharp-IR and SIR modes, this bit is set to a 1
if there is at least 1 framing error, parity error or break
indication in the RX_FIFO.
This bit is always 0 in the 16450 mode.
This bit is cleared upon read.
RI
DCD
7.11.9 Modem Status Register (MSR)
FIGURE 7-16. MSR Register Bitmap
The function of this register depends on the selected operational mode. When a UART mode is selected, this register
provides the current-state as well as state-change information of the status lines from the modem or data transmission
module.
Bit 0 - Delta Clear to Send (DCTS)
Set to 1, when the CTS input signal changes state.
This bit is cleared upon read.
When any of the infrared modes is selected, the register
function is controlled by the setting of the IRMSSL bit in the
IRCR2 (see page 183). If IRMSSL is 0, the MSR register
works as in UART mode. If IRMSSL is 1, the MSR register
returns the value 30 hex, regardless of the state of the modem input lines.
Bit 1 - Delta Data Set Ready (DDSR)
Set to 1, when the DSR input signal changes state.
This bit is cleared upon read
Bit 2 - Trailing Edge Ring Indicate (TERI)
Set to 1, when the RI input signal changes state from
low to high.
This bit is cleared upon read
When loopback is enabled, the MSR register works similarly except that its status input signals are internally driven by
appropriate bits in the MCR register since the modem input
lines are internally disconnected. Refer to bits 3-0 at the
MCR (see page 172) and to the LOOP & ETDLBK bits at the
EXCR1 (see page 178) for more information.
Bit 3 - Delta Data Carrier Detect (DDCD)
Set to 1, when the DCD input signal changes state.
1: DCD signal state changed.
A description of the various bits of the MSR register, with
Loopback disabled and UART Mode selected, is provided
below.
Bit 4 - Clear To Send (CTS)
This bit returns the inverse of the CTS input signal.
When bits 0, 1, 2 or 3 is set to 1, a Modem Status Event
(MS_EV) is generated if the MS_IE bit is enabled in the IER
Bits 0 to 3 are set to 0 as a result of any of the following
events:
Bit 5 - Data Set Ready (DSR)
This bit returns the inverse of the DSR input signal.
●
A hardware reset occurs.
●
The operational mode is changed and the IRMSSL bit
is 0.
Bit 6 - Ring Indicate (RI)
This bit returns the inverse of the RI input signal.
●
The MSR register is read.
Bit 7 - Data Carrier Detect (DCD)
This bit returns the inverse of the DCD input signal.
In the reset state, bits 4 through 7 are indeterminate as they
reflect their corresponding input signals.
Note: The modem status lines can be used as general
purpose inputs. They have no effect on the transmitter or receiver operation.
7.11.10 Scratchpad Register (SPR)
This register shares a common address with the ASCR
Register.
In Non-Extended mode, this is a scratch register (as in the
16550) for temporary data storage.
175
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BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
It is cleared when a data character is written to the TXD
register.
BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7
6
5
4
3
case this is not an error, but the software must clear the
underrun before the next transmission can occur. This
bit is automatically cleared by hardware when a character is written to the TX_FIFO.
Non-Extended Modes
2 1 0
Scratchpad Register
(SCR)
Reset
Bank 0,
Offset 07h
Required
Bit 3 - Reserved
Read/Write 0.
Bit 4 - Reception Watchdog (RXWDG)
In Consumer-IR mode, this is the Reception Watchdog
(RXWDG) bit. It is set to 1 each time a pulse or pulsetrain (modulated pulse) is detected by the receiver. It
can be used by the software to detect a receiver idle
condition. It is cleared upon read.
Scratch Data
Bit 5 - Receiver Active (RXACT)
In Consumer-IR Mode this is the Receiver Active (RXACT) bit. It is set to 1 when an infrared pulse or pulsetrain is received. If a 1 is written into this bit position, the
bit is cleared and the receiver is deactivated. When this
bit is set, the receiver samples the infrared input continuously at the programmed baud and transfers the data
to the RX_FIFO. See “Consumer-IR Reception” on
page 164.
FIGURE 7-17. SPR Register Bitmap
7.11.11 Auxiliary Status and Control Register (ASCR)
This register shares a common address with the previous
one (SCR).
This register is accessed when the Extended mode of operation is selected. The definition of the bits in this case is
dependent upon the mode selected in the MCR register,
bits 7 through 5. This register is cleared upon hardware reset Bits 2 and 6 are cleared when the transmitter is “soft reset”. Bits 0,1,4 and 5 are cleared when the receiver is “soft
reset”.
Bit 6 - Infrared Transmitter Underrun (TXUR)
In the Consumer-IR mode, this is the Transmitter Underrun flag. This bit is set to 1 when a transmitter underrun occurs. It is always cleared when a mode other than
Consumer-IR is selected. This bit must be cleared, by
writing 1 into it, to re-enable transmission.
Extended Modes
7
0
6
0
Bit 7 - Reserved
Read/Write 0.
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
Auxiliary Status
Register (ASCR)
Bank 0,
Offset 07h
Required
7.12 BANK 1 – THE LEGACY BAUD GENERATOR
DIVISOR PORTS
RXF_TOUT
Reserved
S_EOT
Reserved
RXWDG
RXACT
TXUR
Reserved
This register bank contains two Baud Generator Divisor
Ports, and a bank select register.
The Legacy Baud Generator Divisor (LBGD) port provides
an alternate path to the Baud Divisor Generator register.
This bank is implemented to maintain compatibility with
16550 standard and to support existing legacy software
packages. In case of using legacy software, the addresses
0 and 1 are shared with the data ports RXD/TXD (see page
166). The selection between them is controlled by the value
of the BKSE bit (LCR bit 7 page 171).
FIGURE 7-18. ASCR Register Bitmap
TABLE 7-11. Bank 1 Register Set
Bit 0 - RX_FIFO Time-Out (RXF_TOUT)
This bit is read only and set to 1 when an RX_FIFO timeout occurs. It is cleared when a character is read from
the RX_FIFO.
Bit 1 -Reserved
Read/Write 0.
Bit 2 - Set End of Transmission (S_EOT)
In Consumer-IR mode this is the Set End of Transmission bit. When a 1 is written into this bit position before
writing the last character into the TX_FIFO, data transmission is gracefully completed.
In this mode, if the CPU simply stops writing data into
the TX_FIFO at the end of the data stream, a transmitter
underrun is generated and the transmitter stops. In this
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Offset
Register
Name
00h
LBGD(L)
Legacy Baud Generator Divisor
Port (Low Byte)
01h
LBGD(H)
Legacy Baud Generator Divisor
Port (High Byte)
02h
03h
04h - 07h
176
Description
Reserved
LCR/
BSR
Link Control /
Bank Select Register
Reserved
Enhanced Serial Port with IR - UART2 (Logical Device 5)
.
7
6
5
4
3
2
Legacy Baud Generator Divisor
1 0
Low Byte port
(LBGD(L))
Reset
Bank 1,
Required
Offset 00h
To enable other modes to program their desired baud rates
without activating this fallback mechanism, the Baud Generator Divisor Port pair in bank 2 should be used.
7.12.1 Legacy Baud Generator Divisor Ports (LBGD(L)
and LBGD(H)),
Least Significant Byte
of Baud Generator
The programmable baud rates in the Non-Extended mode
are achieved by dividing a 24 MHz clock by a prescale value
of 13, 1.625 or 1. This prescale value is selected by the
PRESL field of EXCR2 (see page 180). This clock is subdivided by the two Baud Generator Divisor buffers, which output a clock at 16 times the desired baud (this clock is the
BOUT clock). This clock is used by I/O circuitry, and after a
last division by 16 produces the output baud.
FIGURE 7-19. LBGD(L) Register Bitmap
.
7
6
5
4
3
Divisor values between 1 and 216-1 can be used. (Zero is
forbidden). The Baud Generator Divisor must be loaded
during initialization to ensure proper operation of the Baud
Generator. Upon loading either part of it, the Baud Generator counter is immediately loaded. Table 7-15 on page 179
shows typical baud divisors. After reset the divisor register
contents are indeterminate.
Any access to the LBGD(L) or LBGD(H) ports causes a reset to the default Non-Extended mode, i.e., 16550 mode
(See “AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE” on page 165).To access a Baud Generator
Divisor when in the Extended mode, use the port pair in
bank 2 (BGD on page 178).
FIGURE 7-20. LBGD(H) Register Bitmap
7.12.2 Link Control Register (LCR) and Bank Select
Register (BSR)
If the UART is in Non-Extended mode and the LOCK bit is
1, the content of the divisor (BGD) ports will not be affected
and no other action is taken.
These registers are the same as the registers at offset 03h
in bank 0.
When programming the baud, the new divisor is loaded
upon writing into LBGD(L) and LBGD(H). After reset, the
contents of these registers are indeterminate.
7.13 BANK 2 – EXTENDED CONTROL AND STATUS
REGISTERS
Divisor values between 1 and 216-1 can be used. (Zero is
forbidden.) Table 7-14 shows typical baud divisors.
Bank 2 contains two alternate Baud Generator Divisor ports
and the Extended Control Registers (EXCR1 and EXCR2).
TABLE 7-12. Bits Cleared On Fallback
TABLE 7-13. Bank 2 Register Set
UART Mode & LOCK bit before Fallback
Non-Extended
Mode
Non-Extended
Mode
LOCK = x
LOCK = 0
LOCK = 1
MCR
2 to 7
none
none
EXCR1
0, 5 and 7
5 and 7
none
EXCR2
0 to 5
0 to 5
none
IRCR1
2 and 3
none
none
Legacy Baud Generator Divisor
1 0
High Byte port
(LBGD(H))
Reset
Bank 1,
Offset 01h
Required
Most Significant Byte
of Baud Generator
Table 7-12 shows the bits which are cleared when Fallback
occurs during Extended or Non-Extended modes.
Register Extended
Mode
2
Offset
Register
Name
00h
BGD(L)
Baud Generator Divisor Port (Low
byte)
01h
BGD(H)
Baud Generator Divisor Port (High
byte)
02h
EXCR1
Extended Control Register 1
03h
LCR/BSR
Link Control/ Bank Select Register
04h
EXCR2
Extended Control Register 2
05h
177
Description
Reserved
06h
TXFLV
TX_FIFO Level
07h
RXFLV
RX_FIFO Level
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BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS
In addition, a fallback mechanism maintains this compatibility by forcing the UART to revert to 16550 mode if 16550
software addresses the module after a different mode was
set. Since setting the Baud Divisor values is a necessary initialization of the 16550, setting the divisor values in bank 1
forces the UART to enter 16550 mode. (This is called fallback.)
BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7.13.1 Baud Generator Divisor Ports, LSB (BGD(L))
and MSB (BGD(H))
7
x
These ports perform the same function as the Legacy Baud
Divisor Ports in Bank 1 and are accessed identically, but do
not change the operation mode of the module when accessed. Refer to Section 7.12.1 on page 177 for more details.
6
x
Baud Generator Divisor
5 4 3 2 1 0
High Byte Port
(BGD(H))
x x x x x x Reset
Bank 2,
Required
Offset 01h
Use these ports to set the baud when operating in Extended
mode to avoid fallback to a Non-Extended operation mode,
i.e., 16550 compatible.When programming the baud, writing to BGDH causes the baud to change immediately.
7
x
6
x
Most Significant Byte
of Baud Generator
Baud Generator Divisor
5 4 3 2 1 0
Low Byte Port
(BGD(L))
x x x x x x Reset
Bank 2,
Required
Offset 00h
FIGURE 7-22. BGD(H) Register Bitmap
Least Significant Byte
of Baud Generator
FIGURE 7-21. BGD(L) Register Bitmap
TABLE 7-14. Baud Generator Divisor Settings
Prescaler Value
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13
1.625
1
Baud
Divisor
% Error
Divisor
% Error
Divisor
% Error
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
14400
19200
28800
38400
57600
115200
230400
460800
750000
921600
1500000
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
8
6
4
3
2
1
-----------
0.16%
0.16%
0.19%
0.10%
0.16%
0.16%
0.16%
0.16%
0.16%
0.53%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
-----------
18461
12307
8391
6863
6153
3076
1538
769
512
461
384
256
192
128
96
64
48
32
24
16
8
4
2
--1
---
0.00%
0.01%
0.01%
0.00%
0.01%
0.03%
0.03%
0.03%
0.16%
0.12%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
--0.16%
---
30000
20000
13636
11150
10000
5000
2500
1250
833
750
625
416
312
208
156
104
78
52
39
26
13
----2
--1
0.00%
0.00%
0.00%
0.02%
0.00%
0.00%
0.00%
0.00%
0.04%
0.00%
0.00%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
----0.00%
--0.00%
178
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Use this register to control module operation in the Extended mode. Upon reset all bits are set to 0.
7
0
6
0
1
Extended Control and
5 4 3 2 1 0
Status Register 1
0 0 0 0 0 0 Reset
(EXCR1)
Bank 2,
Required
Offset 02h
.
DMA Swap Configuration
Logic
Module
EXT_SL
DMANF
DMATH
DMASWP
LOOP
ETDLBK
Reserved
BTEST
TX Channel RX_DMA
DMA
Logic
Bit 0 - Extended Mode Select (EXT_SL)
When set to 1, the Extended mode is selected.
FIGURE 7-24. DMA Control Signals Routing
Bit 4 - Loopback Enable (LOOP)
During loopback, the transmitter output is connected internally to the receiver input, to enable system self-test
of serial communications. In addition to the data signal,
all additional signals within the UART are interconnected to enable real transmission and reception using the
UART mechanisms.
When this bit is set to 1, loopback is selected. This bit
accesses the same internal register as bit 4 in the MCR
register, when the UART is in a Non-Extended mode.
Loopback behaves similarly in both Non-Extended and
Extended modes.
When Extended mode is selected, the DTR bit in the
MCR register internally drives both DSR and RI, and the
RTS bit drives CTS and DCD.
During loopback, the following actions occur:
Bit 2 - DMA FIFO Threshold (DMATH)
This bit selects the TX_FIFO and RX_FIFO threshold
levels used by the DMA request logic to support demand transfer mode.
A transmission DMA request is generated when the
TX_FIFO level is below the threshold.
A reception DMA request is generated when the
RX_FIFO level reaches the threshold or when a DMA
timeout occurs.
Table 7-15 lists the threshold levels for each FIFO.
1. The transmitter and receiver interrupts are fully operational. The Modem Status Interrupts are also fully
operational, but the interrupt sources are now the
lower bits of the MCR register. Modem interrupts in
infrared modes are disabled unless the IRMSSL bit
in the IRCR2 register is 0. Individual interrupts are
still controlled by the IER register bits.
TABLE 7-15. DMA Threshold Levels
DMA Threshold for FIFO Type
Tx_FIFO
0
4
13
1
10
7
DMA
Handshake
Signals
DMASWP
Bit 1 - DMA Fairness Control (DMANF)
This bit controls the maximum duration of DMA burst
transfers.
0: DMA requests are forced inactive after approximately 10.5 µsec of continuous transmitter and/or
receiver DMA operation. (Default)
1: A transmission DMA request is deactivated when
the TX_FIFO is full. A reception DMA request is deactivated when the RX_FIFO is empty.
RX_FIFO
Logic
TX Channel TX_DMA
DMA
Logic
FIGURE 7-23. EXCR1 Register Bitmap
Bit
Value
Routing
2. The DMA control signals are fully operational.
3. UART and infrared receiver serial input signals are
disconnected. The internal receiver input signals are
connected to the corresponding internal transmitter
output signals.
4. The UART transmitter serial output is forced high
and the infrared transmitter serial output is forced
low, unless the ETDLBK bit is set to 1. In which case
they function normally.
Bit 3 - DMA Swap (DMASWP)
This bit selects the routing of the DMA control signals
between the internal DMA logic and the configuration
module of the chip. When this bit is 0, the transmitter
and receiver DMA control signals are not swapped.
When it is 1, they are swapped. A block diagram illustrating the control signals routing is given in Fig. 7-24.
5. The modem status input pins (DSR, CTS, RI and
DCD) are disconnected. The internal modem status
signals, are driven by the lower bits of the MCR register.
179
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BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS
The swap feature is particularly useful when only one
8237 DMA channel is used to serve both transmitter and
receiver. In this case only one external DRQ/DACK signal pair will be interconnected to the swap logic by the
configuration module. Routing the external DMA channel to either the transmitter or the receiver DMA logic is
then simply controlled by the DMASWP bit. This way,
the infrared device drivers do not need to know the details of the configuration module.
7.13.2 Extended Control Register 1 (EXCR1)
BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Bit 7 - Baud Divisor Register Lock (LOCK)
When set to 1, accesses to the Baud Generator Divisor
Register through LBGD(L) and LBGD(H) as well as fallback are disabled from non-extended mode.
In this case two scratchpad registers overlaid with LBGD(L) and LBGD(H) are enabled, and any attempted
CPU access of the Baud Generator Divisor Register
through LBGD(L) and LBGD(H) will access the ScratchPad Registers instead. This bit must be set to 0 when
extended mode is selected.
Bit 5 - Enable Transmitter During Loopback (ETDLBK)
When this bit is set to 1, the transmitter serial output is
enabled and functions normally when loopback is enabled.
Bit 6 - Reserved
Write 1.
Bit 7 - Baud Generator Test (BTEST)
When set, this bit routes the Baud Generator output to
the DTR pin for testing purposes.
7.13.5 Reserved Register
7.13.3 Link Control Register (LCR) and Bank Select
Register (BSR)
Upon reset, all bits in Bank 2 register with offset 05h are set
to 0.
These registers are the same as the registers at offset 03h
in bank 0.
Bits 7-0 - Reserved
7.13.4 Extended Control and Status Register 2
(EXCR2)
7.13.6 TX_FIFO Current Level Register (TXFLV)
Read/write 0’s.
This read-only register returns the number of bytes in the
TX_FIFO. It can be used to facilitate programmed I/O
modes during recovery from transmitter underrun in one of
the fast infrared modes.
This register configures the Prescaler and controls the
Baud Divisor Register Lock.
Upon reset all bits are set to 0.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
Extended Control and
and Status Register 2
0 Reset
(EXCR2)
Bank 2,
0 Required
Offset 04h
0
Extended Modes
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
TFL0
TFL1
TFL2
TFL3
TFL4
Reserved
PRESL0
PRESL1
Reserved
LOCK
Reserved
FIGURE 7-25. EXCR2 Register Bitmap
FIGURE 7-26. TXFLV Register Bitmap
Bits 3 - 0 - Reserved
Bits 4-0 - Number of Bytes in TX_FIFO (TFL(4-0))
These bits specify the number of bytes in the TX_FIFO.
Read/Write 0.
Bits 7,6 - Reserved
Read/Write 0’s.
Bits 5,4 - Prescaler Select
The prescaler divides the 24 MHz input clock frequency
to provide the clock for the Baud Generator. (See Table
7-16).
TABLE 7-16. Prescaler Select
Bit 5
Bit 4
Prescaler Value
0
0
13
0
1
1.625
1
0
Reserved
1
1
1.0
Bit 6 - Reserved
Read/write 0.
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TX_
Current Level
Register (TXFLV)
Bank 2,
Required
Offset 06h
7
0
180
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7.14.1 Module Revision ID Register (MRID)
This read-only register returns the number of bytes in the
RX_FIFO. It can be used for software debugging.
This read-only register identifies the revision of the module.
When read, it returns the module ID and revision level. This
module returns the code 2xh, where x indicates the revision
number.
Extended Modes
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
7
0
Current Level
Register (RXFLV)
Bank 2,
Required
Offset 07h
6
0
RFL0
RFL1
RFL2
RFL3
RFL4
5 4 3 2 1 0
Module Revision ID
Register
1 0 x x x x Reset
(MRID)
Required
Bank 3,
Offset 00h
Revision ID(RID 3-0)
Reserved
Module ID(MID 7-4)
FIGURE 7-27. RXFLV Register Bitmap
FIGURE 7-28. MRID Register Bitmap
Bits 4-0 - Number of Bytes in RX_FIFO (RFL(4-0))
These bits specify the number of bytes in the RX_FIFO.
Bits 3-0 - Revision ID (MID3-0)
The value in these bits identifies the revision level.
Bits 7-5 - Reserved
Read/Write 0’s.
Note: The contents of TXFLV and RXFLV are not frozen
during CPU reads. Therefore, invalid data could be returned if the CPU reads these registers during normal
transmitter and receiver operation. To obtain correct data, the software should perform three consecutive reads
and then take the data from the second read, if first and
second read yield the same result, or from the third
read, if first and second read yield different results.
Bits 7-4 - Module ID (MID7-4)
The value in these bits identifies the module type.
7.14.2 Shadow of Link Control Register (SH_LCR)
This register returns the value of the LCR register. The LCR
register is written into when a byte value according to Table
7-9 on page 172, is written to the LCR/BSR registers location (at offset 03h) from any bank.
7.14 BANK 3 – MODULE REVISION ID AND SHADOW
REGISTERS
7
0
Bank 3 contains the Module Revision ID register which
identifies the revision of the module, shadow registers for
monitoring various registers whose contents are modified
by being read, and status and control registers for handling
the flow control.
Register
Name
Description
00h
MRID
Module Revision ID Register
01h
SH_LCR
Shadow of LCR Register
(Read Only)
02h
SH_FCR Shadow of FIFO Control Register
(Read Only)
03h
04h-07h
LCR/
BSR
Shadow of
5 4 3 2 1 0
Link Control Register
(SH_LCR)
0 0 0 0 0 0 Reset
Bank 3,
Offset 01h
Required
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
TABLE 7-17. Bank 3 Register Set
Offset
6
0
FIGURE 7-29. SH_LCR Register Bitmap
See “Link Control Register (LCR)” on page 171 for bit descriptions.
Link Control Register/
Bank Select Register
Reserved
181
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BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS
7.13.7 RX_FIFO Current Level Register (RXFLV)
BANK 4 – IR MODE SETUP REGISTER
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7.14.3 Shadow of FIFO Control Register (SH_FCR)
7.15.2 Infrared Control Register 1 (IRCR1)
This read-only register returns the contents of the FCR register in bank 0.
Enables the Sharp-IR or SIR infrared mode in the Non-Extended mode of operation.
Upon reset, all bits are set to 0.
7
0
Shadow of
5 4 3 2 1 0
FIFO Control Register
(SH_FCR)
0 0 0 0 0 0 Reset
Bank 3,
Required
Offset 02h
6
0
FIFO_EN
RXSR
TXSR
Reserved
TXFTH0
TXFHT1
RXFTH0
RXFTH1
7
0
6
0
0
0
Infrared Control Register1
5 4 3 2 1 0
(IRCR1)
Bank 4,
0 0 0 0 0 0 Reset
Offset 02h
0 0
0 0 Required
Reserved
Reserved
IR_SL0
IR_SL1
Reserved
FIGURE 7-30. SH_LCR Register Bitmap
See “FIFO Control Register (FCR)” on page 170 for bit descriptions.
FIGURE 7-31. IRCR1 Register Bitmap
Bits 1,0 - Reserved
7.14.4 Link Control Register (LCR) and Bank Select
Register (BSR)
Read/Write 0.
These registers are the same as the registers at offset 03h
in bank 0.
Bits 3,2 - Sharp-IR or SIR Mode Select (IR_SL1,0), NonExtended Mode Only
These bits enable Sharp-IR and SIR modes in Non-Extended mode. They allow selection of the appropriate infrared interface when Extended mode is not selected.
These bits are ignored when Extended mode is selected.
7.15 BANK 4 – IR MODE SETUP REGISTER
TABLE 7-18. Bank 4 Register Set
Offset
Register
Name
TABLE 7-19. Sharp-IR or SIR Mode Selection
Description
00-01h
Reserved
IR_SL1
IR_SL0
Selected Mode
02h
IRCR1
Infrared Control Register 1
0
0
UART (Default)
03h
LCR/
BSR
Link Control/
Bank Select Registers
0
1
Reserved
1
0
Sharp-IR
1
1
SIR
04-07h
Reserved
7.15.1 Reserved Registers
Bits 7-4 - Reserved
Bank 4 registers with offsets 00h and 01h are reserved.
Read/Write 0.
7.15.3 Link Control Register (LCR) and Bank Select
Register (BSR)
These registers are the same as the registers at offset 03h
in bank 0.
7.15.4 Reserved Registers
Bank 4 registers with offsets 04h-07h are reserved.
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182
Enhanced Serial Port with IR - UART2 (Logical Device 5)
TABLE 7-20. Bank 5 Registers
Register
Name
Offset
Bit 4 - Auxiliary Infrared Input Select (AUX_IRRX)
When set to 1, the infrared signal is received from the
auxiliary input. (Separate input signals may be desired
for different front-end circuits). See Table 7-29 on page
190.
Description
00-02h
Reserved
03h
LCR/
BSR
04h
IRCR2
Link Control Register/
Bank Select Register
Bit 5-7 - Reserved
Read/Write 0.
Infrared Control Register 2
05h - 07h
7.16.4 Reserved Registers
Reserved
Bank 5 registers with offsets 05h-07h are reserved.
7.16.1 Reserved Registers
Bank 5 registers with offsets 00h-02h are reserved.
7.17 BANK 6 – INFRARED PHYSICAL LAYER
CONFIGURATION REGISTERS
7.16.2 (LCR/BSR) Register
This Bank of registers controls aspects of the framing and
timing of the infrared modes.
These registers are the same as the registers at offset 03h
in bank 0.
TABLE 7-21. Bank 6 Register Set
7.16.3 Infrared Control Register 2 (IRCR2)
Offset
Register
Name
Description
00h
IRCR3
Infrared Control Register 3
This register controls the basic settings of the infrared
modes.
Upon reset, the content of this register is 02h.
7
0
6
0
01h
Infrared Control
Register 2
(IRCR2)
Bank 5,
Required
Offset 04h
5 4 3 2 1 0
0 0 0 0 1 0 Reset
0
Reserved
02h
SIR_PW
SIR Pulse Width Control
(≤ 115 Kbps)
03h
LCR/ BSR
Link Control Register/
Bank Select Register
04h - 07h
IR_FDPLX
IRMSSL
Reserved
Reserved
7.17.1 Infrared Control Register 3 (IRCR3)
AUX_IRRX
This Register enables/disables modulation in Sharp-IR
mode.
Upon reset, the content of this register is 20h.
Reserved
7
0
FIGURE 7-32. IRCR2 Register Bitmap
Bit 0 - Enable Infrared Full Duplex Mode (IR_FDPLX)
When set to 1, the infrared receiver is not masked during transmission.
6
0
5 4 3 2 1 0
1 0 0 0 0 0 Reset
0
Bit 1 - MSR Register Function Select in Infrared Mode
(IRMSSL)
This bit selects the behavior of the Modem Status Register (MSR) and the Modem Status Interrupt (MS_EV)
when any infrared mode is selected. When a UART
mode is selected, the Modem Status Register and the
Modem Status Interrupt function normally, and this bit is
ignored.
0: MSR register and modem status interrupt work in
the IR modes as in the UART mode (Enables external circuitry to perform carrier detection and provide wake-up events).
1: The MSR returns 30h, and the Modem Status Interrupt is disabled. (Default)
0
0
0
0
Infrared Control
Register 3
(IRCR3)
0 Required
Bank 6,
Offset 00h
Reserved
SHMD_DS
SHDM_DS
FIGURE 7-33. IRCR3 Register Bitmap
Bit 0-5 - Reserved
Read/Write 0.
183
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BANK 5 – INFRARED CONTROL REGISTERS
Bits 3,2 -Reserved
Read/Write 0.
7.16 BANK 5 – INFRARED CONTROL REGISTERS
BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
TABLE 7-22. Bank 7 Register Set
Bit 6 - Sharp-IR Modulation Disable (SHMD_DS)
0: Enables internal 500 KHz transmitter modulation.
(Default)
1: Disables internal modulation.
Bit 7 - Sharp-IR Demodulation Disable (SHDM_DS)
0: Enables internal 500 KHz receiver demodulation.
(Default)
1: Disables internal demodulation.
7.17.2 Reserved Register
Bank 6 register with offset 01h is reserved.
Offset
Register
Name
00h
IRRXDC
Infrared Receiver Demodulator
Control Register
01h
IRTXMC
Infrared Transmitter Modulator
Control Register
02h
RCCFG Consumer-IR Configuration Register
03h
LCR/BSR
Link Control Register/
Bank Select Register
04h
IRCFG1
Infrared Interface Configuration
Register 1
7.17.3 SIR Pulse Width Register (SIR_PW)
This register sets the pulse width for transmitted pulses in
SIR operation mode. These setting do not affect the receiver. Upon reset, the content of this register is 00h, which defaults to a pulse width of 3/16 of the baud.
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
05h
SIR Pulse Width
Register
(SIR_PW)
Bank 6,
Required
Offset 02h
0
Description
Reserved
06h
IRCFG3
Infrared Interface Configuration
Register 3
07h
IRCFG4
Infrared Interface Configuration
Register 4
The Consumer-IR utilizes two carrier frequency ranges (see
also Table 7-26).
— Low range which spans from 30 KHz to 56 KHz, in
1 KHz increments, and
— High range which includes three frequencies:
400 KHz, 450 KHz or 480 KHz.
SPW(3-0)
Reserved
High and low frequencies are specified independently to allow separate transmission and reception modulation settings. The transmitter uses the carrier frequency settings in
Table 7-26.
FIGURE 7-34. SIR_PW Register Bitmap
Bits 3-0 - SIR Pulse Width Register (SPW)
Two codes for setting the pulse width are available. All
other values for this field are reserved.
0000:Pulse width is 3/16 of the bit period. (Default)
1101:Pulse width is 1.6 µsec.
The four registers at offsets 04h through 07h (the infrared
transceiver configuration registers) are provided to configure the Infrared Interface (the transceiver). The transceiver
mode is selected by up to three special output signals
(IRSL2-0). When programmed as outputs these signals are
forced to low when automatic configuration is enabled (AMCFG bit set to 1) and a UART mode is selected.
Bits 7-4 - Reserved
Read/Write 0’s.
7.18.1 Infrared Receiver Demodulator Control
Register (IRRXDC)
7.17.4 Link Control Register (LCR) and Bank Select
Register (BSR)
This register controls settings for Sharp-IR and Consumer
IR reception. After reset, the content of this register is 29h.
This setting selects a subcarrier frequency in a range between 34.61 KHz and 38.26 KHz for the Consumer-IR
mode, and from 480.0 to 533.3 KHz for the Sharp-IR mode.
The value of this register is ignored in both modes if the receiver demodulator is disabled. The available frequency
ranges for Consumer-IR and Sharp-IR modes are given in
Tables 7-23 through 7-25.
These registers are the same as the registers at offset 03h
in Bank 0.
7.17.5 Reserved Registers
Bank 6 registers with offsets 04h-07h are reserved.
7.18 BANK 7 – CONSUMER-IR AND OPTICAL
TRANSCEIVER CONFIGURATION REGISTERS
Bank 7 contains the registers that configure Consumer-IR
functions and infrared transceiver controls. See Table 7-22.
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184
Enhanced Serial Port with IR - UART2 (Logical Device 5)
6
0
This register controls modulation subcarrier parameters for
Consumer-IR and Sharp-IR mode transmission. For SharpIR, only the carrier pulse width is controlled by this register
- the carrier frequency is fixed at 500 KHz.
After reset, the value of this register is 69h, selecting a carrier frequency of 36 KHz and an IR pulse width of 7 µsec for
Consumer-IR, or a pulse width of 0.8 µsec for Sharp-IR.
DFR0
DFR1
DFR2
DFR3
DFR4
DBW0
DBW1
DBW2
7
0
6
1
FIGURE 7-35. IRRXDC Register Bitmap
Bits 4-0 - Demodulator Frequency (DFR(4-0))
These bits select the subcarrier’s center frequency for
the Consumer-IR receiver demodulator. Table 7-25
shows the selection for low speed demodulation (bit 5 of
RCCFG=0, see page 187), and Table 7-24 shows the
selection for high speed demodulation (bit 5 of RCCFG=1).
Infrared Transmitter
5 4 3 2 1 0
Modulation Control
1 0 1 0 0 1 Reset
Register
(IRTXMC)
Required
Bank 7,
Offset 01h
MCFR(4-0)
MCPW(2-0)
FIGURE 7-36. IRTXMC Register Bitmap
Bits 7-5 - Demodulator Bandwidth (DBW(2-0))
These bits set the demodulator bandwidth for the selected frequency range. The subcarrier signal frequency
must fall within the specified frequency range in order to
be accepted. Used for both Sharp-IR and Consumer-IR
modes.
See Tables 7-23, 7-25 and bit 5 (RXHSC) of the Consumer-IR Configuration (RCCFG) Register on page
187.
Bits 4-0 - Modulation Subcarrier Frequency (MCFR)
These bits set the frequency for the Consumer-IR modulation subcarrier. The encoding are defined in Table 7-26. Bits
7-5 - Modulation Subcarrier Pulse Width (MCPW)
Specify the pulse width of the subcarrier clock as shown
in Table 7-27.
TABLE 7-23. Consumer IR, High Speed Demodulator (RXHSC = 1) (Frequency Ranges in KHz)
DFR Bits
43210
DBW2-0 (Bits 7, 6 and 5 of IRRXDC)
min/max
001
010
011
100
101
110
min
380.95
363.63
347.82
333.33
320.00
307.69
max
421.05
444.44
470.58
500.00
533.33
571.42
min
436.36
417.39
400.00
384.00
369.23
355.55
max
480.00
505.26
533.33
564.70
600.00
640.00
min
457.71
436.36
417.39
400.00
384.00
369.92
max
502.26
533.33
564.70
600.00
640.00
685.57
00011
01000
01011
TABLE 7-24. Sharp-IR Demodulator (Frequency Ranges in KHz)
DBW2-0 (Bits 7, 6 and 5 of IRRXDC)
DFR Bits
43210
min/max
001
010
011
100
101
110
min
480.0
457.1
436.4
417.4
400.0
384.0
max
533.3
564.7
600.0
640.0
685.6
738.5
xxxxxx
185
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BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS
7
0
7.18.2 Infrared Transmitter Modulator Control
Register (IRTXMC)
Infrared Receiver
Demodulation Control
5 4 3 2 1 0
1 0 1 0 0 1 Reset Register (IRRXDC)
Bank 7,
Offset 00h
Required
BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
TABLE 7-25. Consumer-IR, Low Speed Demodulator (RXHSC = 0) (Frequency Ranges in KHz)
DBW2-0 (Bits 7, 6 and 5 of IRRXDC)
DFR Bits
43210
min/max
001
010
011
100
101
110
min
26.66
25.45
24.34
23.33
22.40
21.53
max
29.47
31.11
32.94
35.00
37.33
40.00
min
28.57
27.27
26.08
25.00
24.00
23.07
max
31.57
33.33
35.29
37.50
40.00
42.85
min
29.28
27.95
26.73
25.62
24.60
23.65
max
32.37
34.16
36.17
38.43
41.00
43.92
min
30.07
28.68
27.43
26.29
25.24
24.27
max
33.24
35.05
37.11
39.43
42.06
45.07
min
31.74
30.30
28.98
27.77
26.66
25.63
max
35.08
37.03
39.21
41.66
44.44
47.61
min
32.60
31.13
29.78
28.54
27.40
26.34
max
36.00
38.05
40.29
42.81
45.66
48.92
min
33.57
32.04
30.65
29.37
28.20
27.11
max
37.10
39.16
41.47
44.06
47.00
50.35
min
34.61
33.04
31.60
30.29
29.08
27.96
max
38.26
40.38
42.76
45.43
48.46
51.92
min
35.71
34.09
32.60
31.25
30.00
28.84
max
39.47
41.66
44.11
46.87
50.00
53.57
min
36.85
35.18
33.65
32.25
30.96
29.76
max
40.73
43.00
45.52
48.37
51.60
55.28
min
38.10
36.36
34.78
33.33
32.00
30.77
max
42.10
44.44
47.05
50.00
53.33
57.14
min
39.40
37.59
36.00
34.45
33.08
31.80
max
43.55
45.94
48.64
51.68
55.13
59.07
min
40.81
38.95
37.26
35.70
34.28
32.96
max
45.11
47.61
50.41
53.56
57.13
61.21
min
42.32
40.40
38.64
37.03
35.55
34.18
max
46.78
49.37
52.28
55.55
59.25
63.48
min
43.95
41.95
40.13
38.45
36.92
35.50
max
48.58
51.27
54.29
57.68
61.53
65.92
min
45.71
43.63
41.74
40.00
38.40
36.92
max
50.52
53.33
56.47
60.00
64.00
68.57
min
47.62
45.45
43.47
41.66
40.00
38.46
max
52.63
55.55
58.82
62.50
66.66
71.42
min
49.66
47.40
45.34
43.45
41.72
40.11
max
54.90
57.94
61.35
65.18
69.53
74.50
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
10010
10011
10101
10111
11010
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186
Enhanced Serial Port with IR - UART2 (Logical Device 5)
43210
min/max
001
010
011
100
101
110
min
51.90
49.54
47.39
45.41
43.60
41.92
max
57.36
60.55
64.11
68.12
72.66
77.85
min
54.38
51.90
49.65
47.58
45.68
43.92
max
60.10
63.44
67.17
71.37
76.13
81.57
11011
11101
TABLE 7-26. Consumer-IR Carrier Frequency Encoding
TABLE 7-27. Carrier Clock Pulse Width Options
Encoding
Low Frequency
(TXHSC = 0)
High Frequency
(TXHSC = 1)
00000
reserved
reserved
00001
reserved
reserved
00010
reserved
reserved
00011
30 KHz
400 KHz
00100
31 KHz
reserved
00101
32 KHz
reserved
00110
33 KHz
reserved
00111
34 KHz
reserved
01000
35 KHz
450 KHz
01001
36 KHz
reserved
01010
37 KHz
reserved
01011
38 KHz
480 KHz
01100
39 KHz
reserved
01101
40 KHz
reserved
01110
41 KHz
reserved
...
...
...
11010
53 KHz
reserved
11011
54 KHz
reserved
11100
55 KHz
reserved
11101
56 KHz
reserved
11110
56.9 KHz
reserved
11111
reserved
reserved
MCFR Bits
43210
Encoding
MCPW Bits
765
Low Frequency
(TXHSC = 0)
High Frequency
(TXHSC = 1)
000
Reserved
Reserved
001
Reserved
Reserved
010
6 µsec
0.7 µsec
011
7 µsec
0.8 µsec
100
9 µsec
0.9 µsec
101
10.6 µsec
Reserved
110
Reserved
Reserved
111
Reserved
Reserved
7.18.3 Consumer-IR Configuration Register (RCCFG),
This register control the basic operation of the ConsumerIR mode. After reset, the content of this register is 00h.
7
0
6
0
Consumer-IR
5 4 3 2 1 0 Configuration Register
(RCCFG)
0 0 0 0 0 0 Reset
Bank 7,
0
Offset 02h
Required
RC_MMD0
RC_MMD1
TXHSC
Reserved
RCDM_DS
RXHSC
T_OV
R_LEN
FIGURE 7-37. RCCFG Register Bitmap
Bits 1,0 - Transmitter Modulator Mode (RC_MMD(1,0))
Determines how infrared pulses are generated from the
transmitted bit string. (see Table 7-28).
187
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BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS
DBW2-0 (Bits 7, 6 and 5 of IRRXDC)
DFR Bits
BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7.18.4 Link Control/Bank Select Registers (LCR/BSR)
TABLE 7-28. Transmitter Modulation Mode Selection
These registers are the same as the registers at offset
03h in bank 0.
RCCFG
Bits
Modulation Mode
7.18.5 Infrared Interface Configuration Register 1
(IRCFG1)
10
00
C_PLS Modulation mode. Pulses are
generated continuously for the entire logic
0 bit time.
01
8_PLS Modulation Mode. 8 pulses are
generated each time one or more logic 0
bits are transmitted following a logic 1 bit.
10
6_PLS Modulation Mode. 6 pulses are
generated each time one or more logic 0
bits are transmitted following a logic 1 bit.
11
Reserved. Result is indeterminate.
This register holds the transceiver configuration data for
Sharp-IR and SIR modes. It is also used to directly control
the transceiver operation mode when automatic configuration is not enabled. The four least significant bits are also
used to read the identification data of a Plug and Play infrared interface adaptor.
7
0
Bit 2 - Transmitter Subcarrier Frequency Select
(TXHSC)
This bit selects the modulation carrier frequency range.
0: Low frequency: 30-56.9 KHz
1: High frequency: 400-480 KHz
Infrared Configuration
5 4 3 2 1 0
Register 1
0 0 0 0 0 x Reset
(IRCFG1)
Bank 7,
Required
Offset 04h
IRIC(2-0)
IRID3
SIRC(2-0)
STRV_MS
Bit 3 - Reserved
Read/Write 0.
FIGURE 7-38. IRCFG1 Register Bitmap
Bit 4 - Receiver Demodulation Disable (RCDM_DS)
When this bit is 1, the internal demodulator is disabled.
The internal demodulator, when enabled, performs carrier frequency checking and envelope detection.
This bit must be set to 1 (disabled), when the demodulation is performed externally, or when oversampling
mode is selected to determine the carrier frequency.
0: Internal demodulation enabled.
1: Internal demodulation disabled.
Bit 0 - Transceiver Identification/Control Bit 0 (IRIC0)
The function of this bit depends on whether the
ID0/IRSL0/IRRX2 pin is programmed as an input or an
output.
If ID0/IRSL0/IRRX2 is programmed as an input
(IRSL0_DS = 0) then:
— Upon read, this bit returns the logic level of the pin
(allowing external devices to identify themselves).
— Data written to this bit position is ignored.
If ID0/IRSL0/IRXX2 is programmed as an output
(IRSL0_DS = 1), then:
— If AMCFG (bit 7 of IRCFG4) is set to 1, this bit drives
the ID0/IRSL0/IRRX2 pin when Sharp-IR mode is
selected.
— If AMCFG is 0, this bit will drive the
ID0/IRSL0/IRRX2 pin, regardless of the selected
mode.
Upon read, this bit returns the value previously written.
Bit 5 - Receiver Carrier Frequency Select (RXHSC)
This bit selects the receiver demodulator frequency
range.
0: Low frequency: 30-56.9 KHz
1: High frequency: 400-480 KHz
Bit 6 - Receiver Sampling Mode Select(T_OV)
0: Programmed-T-period sampling.
1: Oversampling mode.
Bits 2-1 - Transceiver Identification/Control Bits 2-1
(IRIC2-1)
The function of these bits depends on whether the
ID/IRSL(2-1) pins are programmed as inputs or outputs.
If ID/IRSL(2-1) are programmed as input (IRSL21_DS =
0) then:
— Upon read, these bits return the logic level of the
pins (allowing external devices to identify themselves).
— Data written to these bit positions will be ignored.
If ID/IRSL(2-1) are programmed as output (IRSL21_DS
= 1) then:
Bit 7 - Run Length Control (R_LEN)
Enables or disables run length encoding/decoding. The
format of a run length code is:
YXXXXXXX
where, Y is the bit value and XXXXXXX is the number
of bits minus 1 (Selects from 1 to 128 bits).
0: Run Length Encoding/decoding is disabled.
1: Run Length Encoding/decoding is enabled.
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6
0
188
Enhanced Serial Port with IR - UART2 (Logical Device 5)
Bit 3 - Reserved
Read/Write 0.
Bits 6-4 - Consumer-IR Mode Transceiver
Configuration, High-Speed (RCHC)
These bits drive the IRSL(2-0) pins when AMCFG (bit 7
of IRCFG4) is 1 and Consumer-IR mode with 400-480
KHz receiver carrier frequency is selected. They are unused when AMCFG is 0 or when the ID/IRSL(2-0) pins
are programmed as inputs.
Upon read, these bits return the values previously written.
Bit 3 - Transceiver identification (IRID3)
Upon read, this bit returns the logic level of the ID3 pin.
Data written to this bit position is ignored.
Bits 6-4 - SIR Mode Transceiver Configuration (SIRC(20))
These bits will drive the ID/IRSL(2-0) pins when AMCFG
(bit 7 of IRCFG4) is 1 and SIR mode is selected. They
are unused when AMCFG is 0 or when the ID/IRSL (20) pins are programmed as inputs. SIRC0 is also unused when the IRSL0_DS bit in IRCFG4 is 0.
Upon read, these bits return the values previously written.
Bit 7 - Reserved
Read/Write 0.
7.18.8 Infrared Interface Configuration Register 4
(IRCFG4)
Bit 7 - Special Transceiver Mode Selection (STRV_MS)
When this bit is set to 1, the IRTX output signal is forced
to active high and a timer is started.
The timer times out after 64 µsec, at which time the bit
is reset and the IRTX output signal becomes low again.
The timer is restarted every time a 1 is written to this bit.
Although it is possible to extend the period during which
IRTX remains high beyond 64 µsec, this should be
avoided to prevent damage to the transmitter LED.
Writing a zero to this bit has no effect.
This register configures the receiver data path and enables
the automatic selection of the configuration pins.
After reset, this register contains 00h.
7
0
7.18.6 Reserved Register
Bank 7 register with offset 05h is reserved.
7.18.7 Infrared Interface Configuration 3 Register
(IRCFG3)
This register sets the external transceiver configuration for
the low speed and high speed Consumer IR modes of operation. Upon reset, the content of this register is 00h.
7
0
0
6
0
6
0
5 4 3 2 1 0
Infrared Configuration
Register 4
0 0 0 0 0 0 Reset
(IRCFG4)
0
0 0 0 Required
Bank 7,
Offset 07h
Reserved
Reserved
Reserved
IRSL21_DS
RXINV
IRSL0_DS
Reserved
AMCFG
FIGURE 7-40. IRCFG4 Register Bitmap
5 4 3 2 1 0
Infrared Configuration
Register 3
0 0 0 0 0 0 Reset
(IRCFG3)
0
Required
Bank 7,
Offset 06h
Bits 2-0 - Reserved
Read/write 0.
Bit 3- ID/IRSL(2-1) Pins’ Direction Select (IRSL21_DS)
This bit determines the direction of the ID/IRSL2 and
ID/IRSL1 pins.
0: Pins’ direction is input.
1: Pins’ direction is output.
RCLC(2-0)
Reserved
Bit 4 - IRRX Signal Invert (RXINV)
This bit supports optical transceivers with receive signals of opposite polarity (active high instead of active
low).
When set to 1 an inverter is put on the path of the input
signal of the receiver.
RCHC(2-0)
Reserved
FIGURE 7-39. IRCFG3 Register Bitmap
Bits 2-0 - Consumer-IR Mode Transceiver
Configuration, Low-Speed (RCLC)
These bits drive the ID/IRSL(2-0) pins when AMCFG is
1 and Consumer-IR mode with 30-56 KHz receiver carrier frequency is selected. They are unused when AM-
Bit 5 - ID0/IRSL0/IRRX2 Pin Direction Select (IRSL0_DS)
This bit determines the direction of the ID0/
IRSL0/IRRX2 pin. See Table 7-29 on page 190.
189
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BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS
CFG is 0 or when the ID/IRSL(2-0) pins are
programmed as inputs. Upon read, these bits return the
values previously written.
— If AMCFG (bit 7 of IRCFG4) is set to 1, these bits
drive the ID/IRSL(2-1) pins when Sharp-IR mode is
selected.
— If AMCFG is 0, these bits will drive the ID/IRSL(21)pins, regardless of the selected mode.
Upon read, these bits return the values previously written.
UART2 WITH IR REGISTER BITMAPS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
0: Pin’s direction is input.
1: Pin’s direction is output.
Bit 6 - Reserved
Read/write 0.
7
0
6
0
0
0
Bit 7 - Automatic Module Configuration (AMCFG)
When set to 1, this bit enables automatic infrared configuration.
RXHDL_IE
TXLDL_IE
LS_IE or TXUR_IE
MS_IE
DMA_IE
TXEMP_IE
Reserved
Reserved
TABLE 7-29. Infrared Receiver Input Selection
Bit 4 of IRCR2
(AUX_IRRX)2
Selected IRRX
0
0
IRRX1
0
1
IRRX2
1
0
IRRX1
1
1
1
Bit 5 of IRCFG41
(IRSL0_DS)
7
0
1. IRCFG4 is in bank 7, offset 07h. It is
described on page 189.
2. AUX_IRRX (bit 4 of IRCR2) is described on
page 183.
6
5
4
3
Read Cycles
2 1 0
Receiver Data
Register (RXD)
Reset
Bank 0,
Offset 00h
Required
7
0
6
0
0
0
6
5
4
3
Non-Extended Modes, Read Cycles
Event Identification
5 4 3 2 1 0
Register (EIR)
0 0 0 0 0 1 Reset
Bank 0,
Offset 02h
0 0
Required
Extended Mode, Read Cycles
Event Identification
5 4 3 2 1 0
Register (EIR)
0 0 0 0 0 1 Reset
Bank 0,
Offset 02h
Required
RXHDL_EV
TXLDL_EV
LS_EV or TXHLT_EV
MS_EV
DMA_EV
TXEMP-EV
Reserved
Reserved
Received Data
7
6
0
IPF - Interrupt Pending
IPR0 - Interrupt Priority 0
IPR1 - Interrupt Priority 1
RXFT - RX_FIFO Time-Out
Reserved
Reserved
FEN0 - FIFO Enabled
FEN1 - FIFO Enabled
7.19 UART2 WITH IR REGISTER BITMAPS
7
Extended Mode
5 4 3 2 1 0
Interrupt Enable
Register (IER)
0 0 0 0 0 0 Reset
Bank 0,
Offset 01h
Required
Write Cycles
2 1 0
Transmitter Data
Register (TXD)
Reset
Bank 0,
Offset 00h
Required
7
0
6
0
Write Cycles
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
FIFO_EN
RXSR
TXSR
Reserved
TXFTH0
TXFTH1
RXFTH0
RXFTH1
Transmitted Data
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FIFO Control
Register (FCR)
Bank 0,
Offset 02h
Required
190
Enhanced Serial Port with IR - UART2 (Logical Device 5)
6
0
Link Control
Register (LCR)
All Banks,
Offset 03h
Required
5 4 3 2 1 0
0 0 0 0 0 0 Reset
7
0
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
7
0
6
0
6
1
5 4 3 2 1 0
1 0 0 0 0 0 Reset
Link Status
Register (LSR)
Bank 0,
Offset 05h
Required
RXDA
OE
PE
FE
BRK
TXRDY
TXEMP
ER_INF
7
X
Bank Selection
Register (BSR)
All Banks,
Offset 03h
Required
5 4 3 2 1 0
0 0 0 0 0 0 Reset
6
X
5 4 3 2 1 0
X X 0 0 0 0 Reset
Modem Status
Register (MSR)
Bank 0,
Offset 06h
Required
DCTS
DDSR
TERI
DDCD
CTS
DSR
Bank Selected
RI
DCD
BKSE-Bank Selection Enable
Non-Extended Mode
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
Non-Extended Mode
7
Modem Control
Register (MCR)
Bank 0,
Required
Offset 04h
6
5
4
3
DTR
RTS
RILP
ISEN or DCDLP
LOOP
Reserved
Reserved
Reserved
6
0
1
0
Scratch Register
(SCR)
Reset
Bank 0,
Offset 07h
Required
Scratch Data
Extended Mode
7
0
2
Extended Mode
5 4 3 2 1 0
0 0 0 0 0 0 Reset
Modem Control
Register (MCR)
Bank 0,
Offset 04h
Required
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
DTR
RTS
DMA_EN
TX_DFR
IR_PLS
MDSL0
MDSL1
MDSL2
Auxiliary Status
Register (ASCR)
Bank 0,
Offset 07h
Required
RXF_TOUT
EOF_INF
S_EOT
Reserved
RXWDG
RXACT
TXUR
Reserved
191
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UART2 WITH IR REGISTER BITMAPS
Non-Extended Mode
7
0
UART2 WITH IR REGISTER BITMAPS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7
6
5
4
3
2
Legacy Baud Generator Divisor
1 0
Low Byte Register
(LBGD(L)
Reset
Bank 1,
Offset 00h
Required
7
0
1
6
5
4
3
2
Extended Control and
5 4 3 2 1 0
Status Register 1
0 0 0 0 0 0 Reset
(EXCR1)
Bank 2,
Required
Offset 02h
EXT_SL
DMANF
DMATH
DMASWP
LOOP
ETDLBK
Reserved
BTEST
Least Significant Byte
of Baud Generator
7
6
0
Legacy Baud Generator Divisor
1 0
High Byte Register
(LBGD(H))
Reset
Bank 1,
Offset 01h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
Extended Control and
Status Register 2
0 Reset
(EXCR2)
Bank 2,
0 Required
Offset 04h
0
Reserved
Most Significant Byte
of Baud Generator
7
x
6
x
PRESL0
PRESL1
Reserved
LOCK
Baud Generator Divisor
Low Byte Register
5 4 3 2 1 0
(BGD(L))
x x x x x x Reset
Bank 2,
Offset 00h
Required
TX_FIFO
Current Level
Register (TXFLV)
Bank 2,
Required
Offset 06h
TFL0
TFL1
TFL2
TFL3
TFL4
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
Least Significant Byte
of Baud Generator
Reserved
7
x
6
x
Baud Generator Divisor
High Byte Register
5 4 3 2 1 0
(BGD(H))
x x x x x x Reset
Bank 2,
Offset 01h
Required
I
RX_FIFO
Current Level
Register (RXFLV)
Bank 2,
Required
Offset 07h
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
RFL0
RFL1
RFL2
RFL3
RFL4
Most Significant Byte
of Baud Generator
Reserved
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192
Enhanced Serial Port with IR - UART2 (Logical Device 5)
6
0
5 4 3 2 1 0
Module Revision ID
Register
1 0 x x x x Reset
(MRID)
Required
Bank 3
Offset 00h
Infrared Control
Register 2
(IRCR2)
Bank 5,
Required
Offset 04h
7
0
6
0
5 4 3 2 1 0
0 0 0 0 1 0 Reset
0
0
0
IR_FDPLX
IRMSSL
Reserved
Reserved
AUX_IRRX
Revision ID(RID 3-0)
Module ID(MID 7-4)
7
0
6
0
Reserved
Shadow of
5 4 3 2 1 0
Link Control Register
0 0 0 0 0 0 Reset
(SH_LCR)
Bank 3,
Required
Offset 01h
7
0
6
0
6
0
0
0
Infrared Control
Register 3
(IRCR3)
0 Required
Bank 6,
Offset 00h
Reserved
SHMD_DS
SHDM_DS
Shadow of
5 4 3 2 1 0
FIFO Control Register
(SH_FCR)
0 0 0 0 0 0 Reset
Bank 3,
0
Required
Offset 02h
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
FIFO_EN
RXFR
TXFR
Reserved
TXFTH0
TXFHT1
RXFTH0
RXFTH1
7
0
5 4 3 2 1 0
1 0 0 0 0 0 Reset
0
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
7
0
6
0
0
SIR Pulse Width
Register
(SIR_PW)
Bank 6,
Required
Offset 02h
SPW(3-0)
Reserved
Infrared Control Register1
5 4 3 2 1 0
(IRCR1)
Bank 4,
0 0 0 0 0 0 Reset
Offset 02h
0 0
Required
7
0
Reserved
Reserved
IR_SL0
IR_SL1
6
0
Infrared Receiver
Demodulation Control
5 4 3 2 1 0
1 0 1 0 0 1 Reset Register (IRRXDC)
Bank 7,
Offset 00h
Required
DFR0
DFR1
DFR2
DFR3
DFR4
DBW0
DBW1
DBW2
Reserved
193
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UART2 WITH IR REGISTER BITMAPS
7
0
UART2 WITH IR REGISTER BITMAPS
Enhanced Serial Port with IR - UART2 (Logical Device 5)
7
0
6
1
Infrared Transmitter
5 4 3 2 1 0
Modulation Control
1 0 1 0 0 1 Reset
Register
(IRTXMC)
Required
Bank 7,
Offset 01h
7
0
6
0
0
5 4 3 2 1 0
Infrared Configuration
Register 4
0 0 0 0 0 0 Reset
(IRCFG4)
0 0 0 Required
Bank 7,
Offset 07h
Reserved
IRSL21_DS
RXINV
IRSL0_DS
Reserved
AMCFG
MCFR(4-0)
MCPW(2-0)
7
0
6
0
Consumer-IR Mode
5 4 3 2 1 0 Configuration Register
(RCCFG)
0 0 0 0 0 0 Reset
Bank 7,
0
Offset 02h
Required
RC_MMD0
RC_MMD1
TXHSC
Reserved
RCDM_DS
RXHSC
T_OV
R_LEN
7
0
6
0
Infrared Configuration
5 4 3 2 1 0
Register 1
0 0 0 0 0 x Reset
(IRCFG1)
Bank 7,
Required
Offset 04h
IRIC(2-0)
IRID3
SIRC(2-0)
STRV_MS
7
0
0
6
0
5 4 3 2 1 0
Infrared Configuration
Register 3
0 0 0 0 0 0 Reset
(IRCFG3)
0
Required
Bank 7,
Offset 06h
RCLC(2-0)
Reserved
RCHC(2-0)
Reserved
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194
8.0
Enhanced Serial Port - UART1
(Logical Device 6)
The default bank selection after system reset is 0, which
places the module in the UART 16550 mode. Additionally,
setting the baud in bank 1 (as required to initialize the 16550
UART) switches the module to a Non-Extended UART
mode. This ensures that running existing 16550 software
will switch the system to the 16550 configuration without
software modification.
UART1 supports serial data communications with a remote
peripheral device or modem using a wired interface. The
module can function as a standard 16450 or 16550, or as
an Extended UART.
Table 8-1 shows the main functions of the registers in each
bank.
This module provides receive and transmit channels that
can operate concurrently in full-duplex mode. This module
performs all functions required to conduct parallel data interchange with the system and composite serial data exchange with the external data channel, including:
●
TABLE 8-1. Register Bank Summary
Bank
Format conversion between the internal parallel data
format and the external programmable composite serial format. See Figure 8-2.
●
Serial data timing generation and recognition.
●
Parallel data interchange with the system using a
choice of bi-directional data transfer mechanisms.
●
Status monitoring for all phases of communications
activity.
Existing 16550-based legacy software is completely and
transparently supported. Module organization and specific
fallback mechanisms switch the module to 16550 compatibility mode upon reset or when initialized by 16550 software.
8.1
Main Functions
0
Global Control and Status
1
Legacy Bank
2
Baud Generator Divisor,
Extended Control and Status
3
Module Revision ID and
Shadow Registers
Banks 0 and 1 are the 16550 register banks. The registers
in these banks are equivalent to the registers contained
in the 16550 UARTs and are accessed by 16550 software drivers as if the module was a 16550. Bank 1 contains the legacy Baud Generator Divisor Ports. Bank 0
registers control all other aspects of the UART function,
including data transfers, format setup parameters, interrupt setup and status monitoring.
REGISTER BANK OVERVIEW
Four register banks, each containing eight registers, control
UART operation. All registers use the same 8-byte address
space to indicate offsets 00h through 07h, and the active
bank must be selected by the software.
Bank 2 contains the non-legacy Baud Generator Divisor
Ports, and controls the extended features special to this
UART, that are not included in the 16550 repertoire. See
”Extended UART Mode” on page 196.
The register bank organization enables access to the banks
as required for activation of all module modes, while maintaining transparent compatibility with 16450 or 16550 software, which activates only the registers and specific bits
used in those devices. For details, See Section 8.2.
Bank 3 contains the Module Revision ID and shadow registers. The Module Revision ID (MRID) register contains
a code that identifies the revision of the module when
read by software. The shadow registers contain the
identical content as reset-when-read registers within
bank 0. Reading their contents from the shadow registers lets the system read the register content without resetting them.
The Bank Selection Register (BSR) selects the active bank
and is common to all banks. See Figure 8-1. Therefore,
each bank defines seven new registers.
BANK 3
BANK 2
BANK 1
8.2
DETAILED DESCRIPTION
The module provides receive and transmit channels that
can operate concurrently in full-duplex mode. This module
performs all functions required to conduct parallel data interchange with the system and composite serial data exchange with the external data channel, including:
BANK 0
Offset 07h
Offset 06h
●
Format conversion between the internal parallel data
format and the external programmable composite serial format. See Figure 8-2.
●
Serial data timing generation and recognition
●
Parallel data interchange with the system using a
choice of bi-directional data transfer mechanisms
●
Offset 01h
Status monitoring for all phases of the communications activity
Offset 00h
The module supplies modem control registers, and a prioritized interrupt system for efficient interrupt handling.
Offset 05h
Offset 04h
LCR/BSR
Offset 02h
Common
Register
Throughout
All Banks
16550 Banks
FIGURE 8-1. Register Bank Architecture
195
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8.0 Enhanced Serial Port - UART1 (Logical Device 6)
Enhanced Serial Port - UART1 (Logical Device 6)
FIFO TIME-OUTS
Enhanced Serial Port - UART1 (Logical Device 6)
8.2.1
- see page 207). Each divisor value yields a clock signal
(BOUT) and a further division by 16 produces the baud rate
clock for the serial data stream. It may also be output as a
test signal when enabled (see bit 7 of EXCR1 on page 207.)
16450 or 16550 UART Mode
The module defaults to 16450 mode after power up or reset.
UART 16550 mode is equivalent to 16450 mode, with the
addition of a 16-byte data FIFO for more efficient data I/O.
Transparent compatibility is maintained with this UART
mode in this module.
These user-selectable parameters enable the user to generate a large choice of serial data rates, including all standard baud rates. A list of baud rates and their settings
appears in Table 8-12 on page 208.
Despite the many additions to the basic UART hardware
and organization, the UART responds correctly to existing
software drivers with no software modification required.
When 16450 software initializes and addresses this module, it will in always perform as a 16450 device.
Module Operation
Before module operation can begin, both the communications format and baud rate must be programmed by the software. The communications format is programmed by
loading a control byte into the LCR register, while the baud
rate is selected by loading an appropriate value into the
baud rate generator divisor registers and the divisor preselect values (PRESL) into EXCR2 (see page 209).
Data transfer takes place by use of data buffers that interface internally in parallel and with the external data channel
in a serial format. 16-byte data FIFOs may reduce host
overhead by enabling multiple-byte data transfers within a
single interrupt. With FIFOs disabled, this module is equivalent to the standard 16450 UART. With FIFOs enabled, the
hardware functions as a standard 16550 UART.
The software can read the status of the module at any time
during operation. The status information includes full or
empty state for both transmission and reception channels,
and any other condition detected on the received data
stream, like parity error, framing error, data overrun, or
break event.
The composite serial data stream interfaces with the data
channel through signal conditioning circuitry such as
TTL/RS232 converters, modem tone generators, etc.
Data transfer is accompanied by software-generated control signals, which may be utilized to activate the communications channel and “handshake” with the remote device.
These may be supplied directly by the UART, or generated
by control interface circuits such as telephone dialing and
answering circuits, etc.
START -LSB- DATA 5-8 -MSB- PARITY
8.2.2
In Extended UART mode of operation, the module configuration changes and additional features become available
which enhance UART capabilities.
●
The interrupt sources are no longer prioritized; they
are presented bit-by-bit in the EIR (see page 199).
●
An auxiliary status and control register replaces the
scratchpad register. It contains additional status and
control flag bits (“Auxiliary Status and Control Register
(ASCR)” on page 205).
●
The TX_FIFO can generate interrupts when the number of outgoing bytes in the TX_FIFO drops below a
programmable threshold. In the Non-Extended UART
modes, only reception FIFOs have the thresholding
feature.
STOP
FIGURE 8-2. Composite Serial Data
The composite serial data stream produced by the UART is
illustrated in Figure 8-2. A data word containing five to eight
bits is preceded by start bits and followed by an optional
parity bit and a stop bit. The data is clocked out, LSB first,
at a predetermined rate (the baud).
The data word length, parity bit option, number of start bits
and baud rate are programmable parameters.
The UART includes a programmable baud rate generator
that produces the baud rate clocks and associated timing
signals for serial communication.
8.3
FIFO TIME-OUTS
Time-out mechanisms prevent received data from remaining in the RX_FIFO indefinitely, if the programmed interrupt
threshold is not reached.
The system can monitor this module status at any time. Status information includes the type and condition of the transfer operation in process, as well as any error conditions
(e.g., parity, overrun, framing, or break interrupt).
An RX_FIFO time-out generates a Receiver Data Ready interrupt if bit 0 of IER is set to 1. An RX_FIFO time-out also
sets bit 0 of ASCR to 1 if the RX_FIFO is below the threshold. When a Receiver Data Ready interrupt occurs, this bit
is tested by the software to determine whether a number of
bytes indicated by the RX_FIFO threshold can be read without checking bit 0 of the LSR register.
The module resources include modem control capability
and a prioritized interrupt system. Interrupts can be programmed to match system requirements, minimizing the
CPU overhead required to handle the communications
Line.
The conditions that must exist for a time-out to occur in the
various modes of operation are described below.
Programmable Baud Generator
When a time-out has occurred, it can only be reset when the
FIFO is read by the CPU.
This module contains a programmable baud rate generator
that generates the clock rates for serial data communication
(both transmit and receive channels). It divides its input
clock by any divisor value from 1 to 216 - 1. The output clock
frequency of the baud rate generator must be programmed
to be sixteen times the baud rate value. A 24 MHz input frequency is divided by a prescale value (PRESL field of
EXCR2 - see page 209. Its default value is 13) and by a 16bit programmable divisor value contained in the Baud Generator Divisor High and Low registers (BGD(H) and BGD(L)
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Extended UART Mode
Time-out event A generates an interrupt and sets the
RXF_TOUT bit (bit 0 of ASCR) when all of the following are
true:
196
●
At least one byte is in the RX_FIFO, and
●
More than 64 µsec or four character times, whichever is
greater, have elapsed since the last byte was loaded
into the RX_FIFO from the receiver logic, and
Enhanced Serial Port - UART1 (Logical Device 6)
More than 64 µsec or four character times, whichever is
greater, have elapsed since the last byte was read from
the RX_FIFO by the CPU.
8.4
AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE
no bytes are loaded for a 64-µsec time, the timer times out
and the internal flag is cleared, thus enabling the transmitter.
8.5
BANK 0 – GLOBAL CONTROL AND STATUS
REGISTERS
In the Non-Extended modes of operation, bank 0 is compatible with both the 16450 and the 16550. Upon reset, this
module defaults to the 16450 mode. In the Extended mode,
all the Registers (except RXD/ TXD) offer additional features.
The automatic fallback feature supports existing legacy
software packages that use the 16550 UART by automatically turning off any Extended mode features and switches
the UART to Non-Extended mode when either of the LBGD(L) or LBGD(H) ports in bank 1 is read from or written to
by the CPU.
TABLE 8-2. Bank 0 Serial Controller Base Registers
This eliminates the need for user intervention prior to running a legacy program.
Register
Name
Description
00h
RXD/
TXD
Receiver Data Port/ Transmitter Data
Port
01h
IER
Interrupt Enable Register
02h
EIR/
FCR
Event Identification Register/
FIFO Control Register
03h
LCR/
BSR
Line Control Register/
Bank Select Register
04h
MCR
Modem Control Register
05h
LSR
Line Status Register
06h
MSR
Modem Status Register
07h
SCR/
ASCR
Scratch Register/
Auxiliary Status and Control Register
In order to avoid spurious fallbacks, alternate baud rate registers are provided in bank 2. Any program designed to take
advantage of the UART’s extended features, should not use
LBGD(L) and LBGD(H) to change the baud rate. It should
use the BGD(L) and BGD(H) registers instead. Access to
these ports will not cause fallback.
Offset
Fallback can occur in any mode. In Extended UART mode,
fallback is always enabled. In this case, when a fallback occurs, the following happens:
●
Transmission and Reception FIFOs switch to 16 levels.
●
A value of 13 is selected for the baud rate generator
prescaler
●
The BTEST and ETDLBK bits in the EXCR1 register
are cleared.
●
UART mode is selected.
●
A switch to a Non-Extended UART mode occurs.
When a fallback occurs in a Non-Extended UART mode, the
last two of the above actions do not take place.
8.5.1
Fallback from a Non-Extended mode can be disabled by
setting the LOCK bit in register EXCR2. When LOCK is set
to 1 and the UART is in a Non-Extended mode, two scratch
registers overlaid with LBGD(L) and LBGD(H) are enabled.
Any attempted CPU access of LBGD(L) and LBGD(H) accesses the scratch registers, and the baud rate setting is not
affected. This feature allows existing legacy programs to
run faster than 115.2 Kbps.
Receiver Data Port (RXD) or the Transmitter
Data Port (TXD)
These ports share the same address.
RXD is accessed during CPU read cycles. It is used to read
data from the Receiver Holding Register when the FIFOs
are disabled, or from the bottom of the RX_FIFO when the
FIFOs are enabled. See Figure 8-3.
Receiver Data Port (RXD)
8.4.1
Transmission Deferral
This feature allows software to send high-speed data in Programmed Input/Output (PIO) mode without the risk of generating a transmitter underrun.
7
6
5
4
3
2
1
0
Reset
Required
Transmission deferral is available only in Extended mode
and when the TX_FIFO is enabled. When transmission deferral is enabled (TX_DFR bit in the MCR register set to 1)
and the transmitter becomes empty, an internal flag is set
and locks the transmitter. If the CPU now writes data into
the TX_FIFO, the transmitter does not start sending the
data until the TX_FIFO level reaches 14 at which time the
internal flag is cleared. The internal flag is also cleared and
the transmitter starts transmitting when a time-out condition
is reached. This prevents some bytes from being in the
TX_FIFO indefinitely if the threshold is not reached.
Receiver Data
Port (RXD)
Bank 0,
Offset 00h
Received Data
The time-out mechanism is implemented by a timer that is
enabled when the internal flag is set and there is at least
one byte in the TX_FIFO. Whenever a byte is loaded into
the TX_FIFO the timer gets reloaded with the initial value. If
FIGURE 8-3. RXD Register Bitmap
Bits 7-0 - Received Data
Used to access the Receiver Holding Register when the
FIFOs are disabled, or the bottom of the RX_FIFO when
the FIFOs are enabled.
197
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AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE
●
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Enhanced Serial Port - UART1 (Logical Device 6)
Interrupt Enable Register (IER), in the Non-Extended
Mode
TXD is accessed during CPU write cycles. It is used to write
data to the Transmitter Holding Register when the FIFOs
are disabled, or to the TX_FIFO when the FIFOs are enabled. See Figure 8-4.
7
6
5
4
3
2
1
0
Upon reset, the IER supports the Non-Extended mode. Figure 8-5 shows the bitmap of the Interrupt Enable Register in
these modes.
Transmitter Data
Port (TXD)
Bank 0,
Offset 00h
Required
IER in Non-Extended Modes
Reset
7
0
FIGURE 8-4. TXD Register Bitmap
Bits 7-0 - Transmitted Data
Used to access the Transmitter Holding Register when
the FIFOs are disabled or the top of TX_FIFO when the
FIFOs are enabled.
Interrupt Enable
Register (IER)
Bank 0,
Required
Offset 01h
FIGURE 8-5. IER Register Bitmap, Non-Extended Mode
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
Setting this bit enables interrupts on Receiver HighData-Level, or RX_FIFO Time-Out events (EIR Bits 3-0
are 0100 or 1100. See Table 8-3 on page 200).
0: Disable Receiver High-Data-Level and RX_FIFO
Time-Out interrupts (Default).
1: Enable Receiver High-Data-Level and RX_FIFO
Time-Out interrupts.
Interrupt Enable Register (IER)
This register controls the enabling of various interrupts.
Some interrupts are common to all operating modes of the
module, while others are mode specific. Bits 4 to 7 can be
set in Extended mode only. They are cleared in Non-Extended mode. The bits of the Interrupt Enable Register
(IER) are defined differently, depending on operating the
module in Extended or Non-Extended mode.
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
Setting this bit enables interrupts on Transmitter Low
Data-Level-events (EIR Bits 3-0 are 0010. See Table
8-3 on page 200).
0: Disable Transmitter Low-Data-Level Interrupts (Default).
1: Enable Transmitter Low-Data-Level Interrupts.
The following sections describe the bits in this register for
each of these modes.
The reset mode for the IER is the Non-Extended UART
mode.
When edge-sensitive interrupt triggers are employed, user is
advised to clear all IER bits immediately upon entering the interrupt service routine and to re-enable them prior to exiting
(or alternatively, to disable CPU interrupts and re-enable prior to exiting). This will guarantee proper interrupt triggering in
the interrupt controller in case one or more interrupt events
occur during execution of the interrupt routine.
Bit 2 - Line Status Interrupt Enable (LS_IE)
Setting this bit enables interrupts on Line Status events.
(EIR Bits 3-0 are 0110. See Table 8-3 on page 200).
0: Disable Line Status Interrupts (LS_EV) (Default).
1: Enable Line Status Interrupts (LS_EV).
If the LSR, MSR or EIR registers are to be polled, interrupt
sources which are identified by self-clearing bits should
have their corresponding IER bits set to 0, to prevent spurious pulses on the interrupt output pin.
If an interrupt source must be disabled, the CPU can do so
by clearing the corresponding bit in the IER register. However, if an interrupt event occurs just before the corresponding enable bit in the IER register is cleared, a spurious
interrupt may be generated. To avoid this problem, the
clearing of any IER bit should be done during execution of
the interrupt service routine. If the interrupt controller is programmed for level-sensitive interrupts, the clearing of IER
bits can also be performed outside the interrupt service routine, but with the CPU interrupt disabled.
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5 4 3 2 1 0
0 0 0 0 0 0 Reset
RXHDL_IE
TXLDL_IE
LS_IE
MS_IE
Reserved
Reserved
Reserved
Reserved
Transmitted Data
8.5.2
6
0
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Setting this bit enables the interrupts on Modem Status
events. (EIR Bits 3-0 are 0000. See Table 8-3 on page
200).
0 - Disable Modem Status Interrupts (MS_EV) (Default).
1: Enable Modem Status Interrupts (MS_EV).
Bits 7-4- Reserved
These bits are reserved.
198
Enhanced Serial Port - UART1 (Logical Device 6)
8.5.3
Figure 8-6 shows the bitmap of the Interrupt Enable Register in these mode.
The Event Identification Register (EIR) and the FIFO
Control Register (FCR) (see next register description)
share the same address. The EIR is accessed during CPU
read cycles while the FCR is accessed during CPU write cycles.The Event Identification Register (EIR) indicates the interrupt source. The function of this register changes
according to the selected mode of operation.
IER in Extended Mode
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
Interrupt Enable
Register (IER)
Bank 0,
Required
Offset 01h
Event Identification Register (EIR)
Event Identification Register (EIR), Non-Extended Mode
When Extended mode is not selected (EXT_SL bit in
EXCR1 register is set to 0), this register is the same as in
the 16550.
RXHDL_IE
TXLDL_IE
LS_IE
MS_IE
Reserved
TXEMP_IE
Reserved
Reserved
In a Non-Extended UART mode, this module prioritizes interrupts into four levels. The EIR indicates the highest level
of interrupt that is pending. The encoding of these interrupts
is shown in Table 8-3 on page 200.
7
0
FIGURE 8-6. IER Register Bitmap, Extended Mode
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
Setting this bit enables interrupts when the RX_FIFO is
equal to or above the RX_FIFO threshold level, or an
RX_FIFO time out occurs.
0: Disable Receiver Data Ready interrupt. (Default)
1: Enable Receiver Data Ready interrupt.
6
0
Non-Extended Modes, Read Cycles
Event Identification
5 4 3 2 1 0
Register (EIR)
0 0 0 0 0 1 Reset
Bank 0,
Offset 02h
0 0
Required
IPF - Interrupt Pending
IPR0 - Interrupt Priority 0
IPR1 - Interrupt Priority 1
RXFT - RX_FIFO Time-Out
Reserved
Reserved
FEN0 - FIFOs Enabled
FEN1 - FIFOs Enabled
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
Setting this bit enables interrupts when the TX_FIFO is
below the threshold level or the Transmitter Holding
Register is empty.
0: Disable Transmitter Low-Data-Level Interrupts (Default).
1: Enable Transmitter Low-Data-Level Interrupts.
FIGURE 8-7. EIR Register Bitmap, Non-Extended Modes
Bit 0 - Interrupt Pending Flag (IPF)
0: There is an interrupt pending.
1: No interrupt pending. (Default)
Bit 2 - Line Status Interrupt Enable (LS_IE)
Setting this bit enables interrupts on Line Status events.
0: Disable Line Status Interrupts (LS_EV) (Default)
1: Enable Line Status Interrupts (LS_EV).
Bits 2,1 - Interrupt Priority 1,0 (IPR1,0)
When bit 0 (IPF) is 0, these bits indicate the pending interrupt with the highest priority. See Table 8-3 on page
200.
Default value is 00.
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Setting this bit enables the interrupts on Modem Status
events.
0: Disable Modem Status Interrupts (MS_EV) (Default)
1: Enable Modem Status Interrupts (MS_EV).
Bit 3 - RX_FIFO Time-Out (RXFT)
In the 16450 mode, this bit is always 0. In the 16550
mode (FIFOs enabled), this bit is set to 1 when an
RX_FIFO read time-out occurred and the associated interrupt is currently the highest priority pending interrupt.
Bits 5,4 - Reserved
Read/Write 0.
Bit 4 - Reserved
Reserved.
Bit 7,6 - FIFOs Enabled (FEN1,0)
0: No FIFO enabled. (Default)
Bit 5 - Transmitter Empty Interrupt Enable (TXEMP_IE)
Setting this bit enables interrupt generation if the transmitter and TX_FIFO become empty.
0: Disable Transmitter Empty interrupts (Default)
1: Enable Transmitter Empty interrupts.
1: FIFOs are enabled (bit 0 of FCR is set to 1).
Bits 7,6 - Reserved
Reserved.
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BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Interrupt Enable Register (IER), in the Extended Mode
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Enhanced Serial Port - UART1 (Logical Device 6)
TABLE 8-3. Non-Extended Mode Interrupt Priorities
Interrupt Set and Reset Functions
EIR Bits
3210
Priority
Level
Interrupt Type
Interrupt Source
Interrupt Reset Control
0001
−
None
None
−
0110
Highest
Line Status
0100
Second
Receiver High
Data Level
Event
1100
Second
0010
Third
0000
Fourth
Parity error, framing error, data overrun Read Line Status Register (LSR).
or break event
Receiver Holding Register (RXD) full, or Reading the RXD or, RX_FIFO level
RX_FIFO level equal to or above
drops below threshold.
threshold.
RX_FIFO Time- At least one character is in the
Reading the RXD port.
Out
RX_FIFO, and no character has been
input to or read from the RX_FIFO for 4
character times.
Transmitter Low Transmitter Holding Register or
Data Level
TX_FIFO empty.
Event
Modem Status Any transition on CTS, DSR or DCD or a Reading the Modem Status Register
low to high transition on RI.
(MSR).
Bit 2 - Line Status Event (LS_EV) or Transmitter Halted
Event (TXHLT_EV)
This bit is set to 1 when a receiver error or break condition is reported.
When FIFOs are enabled, the Parity Error(PE), Frame
Error(FE) and Break(BRK) conditions are only reported
when the associated character reaches the bottom of
the RX_FIFO. An Overrun Error (OE) is reported as
soon as it occurs.
Event Identification Register (EIR), Extended Mode
In Extended mode, each of the previously prioritized and
encoded interrupt sources is broken down into individual
bits. Each bit in this register acts as an interrupt pending
flag, and is set to 1 when the corresponding event occurred
or is pending, regardless of the IER register bit setting.
7
0
6
0
Extended Mode, Read Cycles
Event Identification
5 4 3 2 1 0
Register (EIR)
0 0 0 0 0 1 Reset
Bank 0,
Offset 02h
Required
Bit 3 - Modem Status Event (MS_EV)
In UART mode this bit is set to 1 when any of the 0 to 3
bits in the MSR register is set to 1.
RXHDL_EV
TXLDL_EV
LS_EV or TXHLT_EV
MS_EV
Reserved
TXEMP-EV
Reserved
Reserved
Bit 4 - Reserved
Read/Write 0.
Bit 5 - Transmitter Empty (TXEMP_EV)
This bit is the same as bit 6 of the LSR register. It is set
to 1 when the transmitter is empty.
Bits 7,6 - Reserved
Read/Write 0.
FIGURE 8-8. EIR Register Bitmap, Extended Mode
8.5.4
Bit 0 - Receiver High-Data-Level Event (RXHDL_EV)
When FIFOs are disabled, this bit is set to 1 when a
character is in the Receiver Holding Register.
When FIFOs are enabled, this bit is set to 1 when the
RX_FIFO is above threshold or an RX_FIFO time-out
has occurred.
FIFO Control Register (FCR)
The FIFO Control Register (FCR) is write only. It is used to
enable the FIFOs, clear the FIFOs and set the interrupt
thresholds levels for the reception and transmission FIFOs.
Bit 1 - Transmitter Low-Data-Level Event (TXLDL_EV)
When FIFOs are disabled, this bit is set to 1 when the
Transmitter Holding Register is empty.
When FIFOs are enabled, this bit is set to 1 when the
TX_FIFO is below the threshold level.
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Reading the EIR Register if this
interrupt is currently the highest
priority pending interrupt, or writing
into the TXD port.
200
Enhanced Serial Port - UART1 (Logical Device 6)
7
0
6
0
0
RXFTH (Bits 5,4) RX_FIF0 Threshold
FIFO Control
Register (FCR)
Bank 0,
Offset 02h
Required
FIFO_EN
RXSR
TXSR
Reserved
TXFTH0
TXFTH1
RXFTH0
RXFTH1
8.5.5
00(Default)
1
01
4
10
8
11
14
Line Control Register (LCR) and Bank
Selection Register (BSR)
The Line Control Register (LCR) and the Bank Select
Register (BSR) (see the next register) share the same address.
FIGURE 8-9. FCR Register Bitmap
The Line Control Register (LCR) selects the communications format for data transfers.
Bit 0 - FIFO Enable (FIFO_EN)
When set to 1 enables both the Transmision and Reception FIFOs. Resetting this bit clears both FIFOs.
Upon reset, all bits are set to 0.
Reading the register at this address location returns the
content of the BSR. The content of LCR may be read from
the Shadow of Line Control Register (SH_LCR) register in
bank 3 (See Section 8.8.2 on page 210). During a write operation to this register at this address location, the setting of
bit 7 (Bank Select Enable, BKSE) determines whether LCR
or BSR is to be accessed, as follows:
Bit 1 - Receiver Soft Reset (RXSR)
Writing a 1 to this bit generates a receiver soft reset,
which clears the RX_FIFO and the receiver logic. This
bit is automatically cleared by the hardware.
Bit 2 - Transmitter Soft Reset (TXSR)
Writing a 1 to this bit generates a transmitter soft reset,
which clears the TX_FIFO and the transmitter logic. This
bit is automatically cleared by the hardware.
Bit 3 - Reserved
Read/Write 0.
●
If bit 7 is 0, the write affects both LCR and BSR.
●
If bit 7 is 1, the write affects only BSR, and LCR remains
unchanged. This prevents the communications format
from being spuriously affected when a bank other than
0 or 1 is accessed.
Upon reset, all bits are set to 0.
Bits 5,4 - TX_FIFO Threshold Level (TXFTH1,0)
In Non-Extended modes, these bits have no effect.
In Extended modes, these bits select the TX_FIFO interrupt threshold level. An interrupt is generated when
the level of the data in the TX_FIFO drops below the encoded threshold.
Line Control Register (LCR)
7
0
6
0
Line Control
Register (LCR)
All Banks,
Offset 03h
Required
5 4 3 2 1 0
0 0 0 0 0 0 Reset
TABLE 8-4. TX_FIFO Level Selection
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
TXFTH (Bits 5,4) TX_FIF0 Threshold
00(Default)
1
01
3
10
9
11
13
FIGURE 8-10. LCR Register Bitmap
Bits 7,6 - RX_FIFO Threshold Level (RXFTH1,0)
These bits select the RX_FIFO interrupt threshold level.
An interrupt is generated when the level of the data in
the RX_FIFO is equal to or above the encoded threshold.
Bits 1,0 - Character Length Select (WLS1,0)
These bits specify the number of data bits in each transmitted or received serial character. Table 8-6 shows
how to encode these bits.
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BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
TABLE 8-5. RX_FIFO Level Selection
Write Cycles
5 4 3 2 1 0
0 0 0 0 0 0 Reset
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Enhanced Serial Port - UART1 (Logical Device 6)
This bit acts only on the transmitter front-end and has no
effect on the rest of the transmitter logic.
When set to 1 the SOUT pin is forced to a logic 0 state.
To avoid transmission of erroneous characters as a result of the break, use the following procedure to set
SBRK:
TABLE 8-6. Word Length Select Encoding
WLS1
WLS0
Character Length
0
0
5 (Default)
0
1
6
1
0
7
1
1
8
1. Wait for the transmitter to be empty. (TXEMP = 1).
2. Set SBRK to 1.
3. Wait for the transmitter to be empty, and clear SBRK
when normal transmission must be restored.
Bits 2 - Number of Stop Bits (STB)
This bit specifies the number of stop bits transmitted
with each serial character.
0: One stop bit is generated. (Default)
1: If the data length is set to 5-bits via bits 1,0
(WLS1,0), 1.5 stop bits are generated. For 6, 7 or 8
bit word lengths, two stop bits are transmitted. The
receiver checks for one stop bit only, regardless of
the number of stop bits selected.
Bit 7 - Bank Select Enable (BKSE)
0: This register functions as the Line Control Register
(LCR).
1: This register functions as the Bank Select Register
(BSR).
8.5.6
7
0
Bit 3 - Parity Enable (PEN)
This bit enable the parity bit See Table 8-7 on page 202.
The parity enable bit is used to produce an even or odd
number of 1s when the data bits and parity bit are
summed, as an error detection device.
0: No parity bit is used. (Default)
1: A parity bit is generated by the transmitter and
checked by the receiver.
Bank Selection Register (BSR)
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
Bank Selection
Register (BSR)
All Banks,
Offset 03h
Required
Bank Selection
Bit 4 - Even Parity Select (EPS)
When Parity is enabled (PEN is 1), this bit, together with
bit 5 (STKP), controls the parity bit as shown in Table
8-7.
0: If parity is enabled, an odd number of logic 1s are
transmitted or checked in the data word bits and
parity bit. (Default)
1: If parity is enabled, an even number of logic 1s are
transmitted or checked.
BKSE-Bank Selection Enable
FIGURE 8-11. BSR Register Bitmap
The Bank Selection Register (BSR) selects which register
bank is to be accessed next.
About accessing this register see the description of bit
7 of the LCR Register.
Bit 5 - Stick Parity (STKP)
When Parity is enabled (PEN is 1), this bit, together with
bit 4 (EPS), controls the parity bit as show in Table 8-7.
Bits 6-0 - Bank Selection
When bit 7 is set to 1, bits 6-0 of BSR select the bank,
as shown in Table 8-8.
TABLE 8-7. Bit Settings for Parity Control
PEN
EPS
STKP
Selected Parity Bit
0
x
x
None
1
0
0
Odd
1
1
0
Even
1
0
1
Logic 1
1
1
1
Logic 0
Bit 7 - Bank Selection Enable (BKSE)
0: Bank 0 is selected.
1: Bits 6-0 specify the selected bank.
Bit 6 - Set Break (SBRK)
This bit enables or disables a break. During the break,
the transmitter can be used as a character timer to accurately establish the break duration.
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202
Enhanced Serial Port - UART1 (Logical Device 6)
BSR Bits
Bank
Selected
7
6
5
4
3
2
1
0
0
x
x
x
x
x
x
x
0
1
0
x
x
x
x
x
x
1
1
1
x
x
x
x
1
x
1
1
1
x
x
x
x
x
1
1
1
1
1
0
0
0
0
0
2
1
1
1
0
0
1
0
0
3
8.5.7
LCR
LCR is written
Bit 4 - Loopback Enable (LOOP)
When this bit is set to 1, it enables loopback. This bit accesses the same internal register as bit 4 of the EXCR1
register. (see “Bit 4 - Loopback Enable (LOOP)” on page
208 for more information on the Loopback mode).
0: Loopback disabled. (Default)
1: Loopback enabled.
LCR is not
written
Bits 7-5 - Reserved
Read/Write 0.
Modem/Mode Control Register (MCR)
Modem/Mode Control Register (MCR), Extended Mode
This register controls the interface with the modem or data
communications set, and the device operational mode
when the device is in the Extended mode. The register
function differs for Extended and Non-Extended modes.
In Extended mode the interrupt output signal is always enabled, and loopback can be enabled by setting bit 4 of the
EXCR1 register.
Modem/Mode Control Register (MCR), Non-Extended
Mode
Non-Extended UART mode
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
Extended Mode
Modem Control
Register (MCR)
Bank 0,
Offset 04h
Required
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
Modem Control
Register (MCR)
Bank 0,
Offset 04h
Required
0
DTR
RTS
Reserved
TX_DFR
DTR
RTS
RILP
ISEN or DCDLP
LOOP
Reserved
Reserved
FIGURE 8-13. MCR Register Bitmap, Extended Modes
Bit 0 - Data Terminal Ready (DTR)
This bit controls the DTR signal output. When set to1,
DTR is driven low. When loopback is enabled (LOOP is
set), this bit internally drives both DSR and RI.
FIGURE 8-12. MCR Register Bitmap, Non-Extended
Mode
Bit 0 - Data Terminal Ready (DTR)
This bit controls the DTR signal output. When set to 1,
DTR is driven low. When loopback is enabled (LOOP is
set to 1), this bit internally drives DSR.
Bit 1 - Request To Send (RTS)
This bit controls the RTS signal output. When set to1,
RTS is driven low. When loopback is enabled (LOOP is
set), this bit internally drives both CTS and DCD.
Bit 1 - Request To Send (RTS)
This bit controls the RTS signal output. When set to 1,
drives RTS low. When loopback is enabled (LOOP is
set), this bit drives CTS, internally.
Bit 2 - Reserved
Read/Write 0.
Bit 3 - Transmission Deferral (TX_DFR)
For a detailed description of the Transmission Deferral
see “Fallback from a Non-Extended mode can be disabled by setting the LOCK bit in register EXCR2. When
LOCK is set to 1 and the UART is in a Non-Extended
mode, two scratch registers overlaid with LBGD(L) and
LBGD(H) are enabled. Any attempted CPU access of
LBGD(L) and LBGD(H) accesses the scratch registers,
and the baud rate setting is not affected. This feature allows existing legacy programs to run faster than 115.2
Kbps.” on page 197.
Bit 2 - Loopback Interrupt Request (RILP)
When loopback is enabled, this bit internally drives RI.
Otherwise it is unused.
Bit 3 - Interrupt Signal Enable (ISEN) or Loopback DCD
(DCDLP)
In normal operation (standard 16450 or 16550) mode,
this bit controls the interrupt signal and must be set to 1
in order to enable the interrupt request signal.
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BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
When loopback is enabled, the interrupt output signal is
always enabled, and this bit internally drives DCD.
New programs should always keep this bit set to 1 during normal operation. The interrupt signal should be
controlled through the Plug-n-Play logic.
TABLE 8-8. Bank Selection Encoding
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
Enhanced Serial Port - UART1 (Logical Device 6)
With FIFOs Enabled:
An overrun occurs when a new character is completely
received into the receiver front-end section and the
RX_FIFO is full. The new character is discarded, and
the RX_FIFO is not affected.
0: No transmission deferral enabled. (Default)
1: Transmission deferral enabled.
This bit is effective only if the Transmission FIFOs is enabled.
Bits 7- 4 - Reserved
Read/Write 0.
8.5.8
Bit 2 - Parity Error (PE)
This bit is set to 1 if the received data character does not
have the correct parity, even or odd as selected by the
parity control bits of the LCR register.
If the FIFOs are enabled, this error is associated with
the particular character in the FIFO that it applies to.
This error is revealed to the CPU when its associated
character is at the bottom of the RX_FIFO.
This bit is cleared upon read.
Line Status Register (LSR)
This register provides status information concerning the
data transfer. Bits 1 through 4 indicate Line status events.
These bits are sticky (accumulate the occurrence of error
conditions since the last time they were read). They are
cleared when one of the following events occurs:
●
Hardware reset.
●
The receiver is soft-reset.
●
The LSR register is read.
Bit 3 - Framing Error (FE)
This bit is set to 1 when the received data character
does not have a valid stop bit (i.e., the stop bit following
the last data bit or parity bit is a 0).
If the FIFOs are enabled, this Framing Error is associated with the particular character in the FIFO that it applies to. This error is revealed to the CPU when its
associated character is at the bottom of the RX_FIFO.
After a framing error is detected, the receiver will try to
resynchronize.
If the bit following the erroneous stop bit is 0, the receiver assumes it to be a valid start bit and shifts in the new
character. If that bit is a 1, the receiver enters the idle
state and awaits the next start bit.
This bit is cleared upon read.
Upon reset this register assumes the value of 0x60h.
The bit definitions change depending upon the operation
mode of the module.
Bits 4 through 1 of the LSR are the error conditions that generate a Receiver Line Status interrupt whenever any of the
corresponding conditions are detected and that interrupt is
enabled.
The LSR is intended for read operations only. Writing to the
LSR is not permitted
7
0
6
1
5 4 3 2 1 0
1 0 0 0 0 0 Reset
Line Status
Register (LSR)
Bank 0,
Offset 05h
Required
Bit 4 - Break Event Detected (BRK)
This bit is set to 1 when a break event is detected (i.e.
when a sequence of logic 0 bits, equal or longer than a
full character transmission, is received). If the FIFOs are
enabled, the break condition is associated with the particular character in the RX_FIFO to which it applies. In
this case, the BRK bit is set when the character reaches
the bottom of the RX_FIFO.
When a break event occurs, only one zero character is
transferred to the Receiver Holding Register or to the
RX_FIFO.
The next character transfer takes place after at least
one logic 1 bit is received followed by a valid start bit.
RXDA
OE
PE
FE
BRK
TXRDY
TXEMP
ER_INF
FIGURE 8-14. LSR Register Bitmap
This bit is cleared upon read.
Bit 0 - Receiver Data Available (RXDA)
Set to 1 when the Receiver Holding Register is full.
If the FIFOs are enabled, this bit is set when at least one
character is in the RX_FIFO.
Cleared when the CPU reads all the data in the Holding
Register or in the RX_FIFO.
Bit 5 - Transmitter Ready (TXRDY)
This bit is set to 1 when the Transmitter Holding Register or the TX_FIFO is empty.
It is cleared when a data character is written to the TXD
register.
Bit 1 - Overrun Error (OE)
This bit is set to 1 as soon as an overrun condition is detected by the receiver.
Cleared upon read.
With FIFOs Disabled:
An overrun occurs when a new character is completely
received into the receiver front-end section and the CPU
has not yet read the previous character in the receiver
holding register. The new character is discarded, and
the receiver holding register is not affected.
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Bit 6 - Transmitter Empty (TXEMP)
This bit is set to 1 when the Transmitter Holding Register or the TX_FIFO is empty, and the transmitter frontend is idle.
Bit 7 - Error in RX_FIFO (ER_INF)
This bit is set to a 1 if there is at least 1 framing error,
parity error or break indication in the RX_FIFO.
This bit is always 0 in the 16450 mode.
This bit is cleared upon read.
204
Enhanced Serial Port - UART1 (Logical Device 6)
Modem Status Register (MSR)
Bit 4 - Clear To Send (CTS)
This bit returns the inverse of the CTS input signal.
The function of this register depends on the selected operational mode. When a UART mode is selected, this register
provides the current-state as well as state-change information of the status lines from the modem or data transmission
module.
Bit 5 - Data Set Ready (DSR)
This bit returns the inverse of the DSR input signal.
When loopback is enabled, the MSR register works similarly except that its status input signals are internally driven by
appropriate bits in the MCR register since the modem input
lines are internally disconnected. Refer to bits 3-0 at the
MCR (see page 203) and to the LOOP & ETDLBK bits at the
EXCR1 (see page 207) for more information.
Bit 6 - Ring Indicate (RI)
This bit returns the inverse of the RI input signal.
A description of the various bits of the MSR register, with
Loopback disabled and UART Mode selected, is provided
below.
8.5.10 Scratchpad Register (SPR)
Bit 7 - Data Carrier Detect (DCD)
This bit returns the inverse of the DCD input signal.
This register shares a common address with the ASCR
Register.
When bits 0, 1, 2 or 3 is set to 1, a Modem Status Event
(MS_EV) is generated if the MS_IE bit is enabled in the IER
In Non-Extended mode, this is a scratch register (as in the
16550) for temporary data storage.
Bits 0 to 3 are set to 0 as a result of any of the following
events:
●
Hardware reset occurs.
●
The MSR register is read.
7
6
5
4
3
In the reset state, bits 4 through 7 are indeterminate as they
reflect their corresponding input signals.
Note: The modem status lines can be used as general
purpose inputs. They have no effect on the transmitter or receiver operation.
7
X
6
X
Non-Extended Modes
2 1 0
Scratchpad Register
(SCR)
Reset
Bank 0,
Offset 07h
Required
5 4 3 2 1 0
X X 0 0 0 0 Reset
Modem Status
Register (MSR)
Bank 0,
Offset 06h
Required
Scratch Data
FIGURE 8-16. SPR Register Bitmap
DCTS
DDSR
TERI
DDCD
CTS
DSR
8.5.11 Auxiliary Status and Control Register (ASCR)
This register shares a common address with the previous
one (SCR).
This register is accessed when the Extended mode of operation is selected. The definition of the bits in this case is
dependent upon the mode selected in the MCR register,
bits 7 through 5. This register is cleared upon hardware reset Bits 2 and 6 are cleared when the transmitter is “soft reset”. Bits 0,1,4 and 5 are cleared when the receiver is “soft
reset”.
RI
DCD
FIGURE 8-15. MSR Register Bitmap
Bit 0 - Delta Clear to Send (DCTS)
Set to 1, when the CTS input signal changes state.
This bit is cleared upon read.
Extended Modes
Bit 1 - Delta Data Set Ready (DDSR)
Set to 1, when the DSR input signal changes state.
This bit is cleared upon read
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
0
0
0
0
Auxiliary Status
Register (ASCR)
Bank 0,
Offset 07h
Required
RXF_TOUT
Bit 2 - Trailing Edge Ring Indicate (TERI)
Set to 1, when the RI input signal changes state from
low to high.
This bit is cleared upon read
Reserved
Bit 3 - Delta Data Carrier Detect (DDCD)
Set to 1, when the DCD input signal changes state.
1: DCD signal state changed.
FIGURE 8-17. ASCR Register Bitmap
205
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BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS
8.5.9
BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS
Enhanced Serial Port - UART1 (Logical Device 6)
Any access to the LBGD(L) or LBGD(H) ports causes a reset to the default Non-Extended mode, i.e., 16550 mode
(See “AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE” on page 197).To access a Baud Generator
Divisor when in the Extended mode, use the port pair in
bank 2 (BGD on page 207).
Bit 0 - RX_FIFO Time-Out (RXF_TOUT)
This bit is read only and set to 1 when an RX_FIFO timeout occurs. It is cleared when a character is read from
the RX_FIFO.
Bits 7 - 1 -Reserved
Read/Write 0.
8.6
Table 8-10 shows the bits which are cleared when Fallback
occurs during Extended or Non-Extended modes.
BANK 1 – THE LEGACY BAUD GENERATOR
DIVISOR PORTS
If the UART is in Non-Extended mode and the LOCK bit is
1, the content of the divisor (BGD) ports will not be affected
and no other action is taken.
This register bank contains two registers as the Baud Generator Divisor Port, and a bank select register.
When programming the baud rate, the new divisor is loaded
upon writing into LBGD(L) and LBGD(H). After reset, the
contents of these registers are indeterminate.
The Legacy Baud Generator Divisor (LBGD) port provides
an alternate path to the Baud Divisor Generator register.
This bank is implemented to maintain compatibility with
16550 standard and to support existing legacy software
packages. In case of using legacy software, the addresses
0 and 1 are shared with the data ports RXD/TXD (see page
197). The selection between them is controlled by the value
of the BKSE bit (LCR bit 7 page 201).
Divisor values between 1 and 216-1 can be used. (Zero is
forbidden.) Table 8-12 shows typical baud rate divisors.
TABLE 8-10. Bits Cleared On Fallback
UART Mode & LOCK bit before Fallback
TABLE 8-9. Bank 1 Register Set
Offset
Register
Name
00h
LBGD(L)
01h
LBGD(H)
02h
03h
04h - 07h
Register Extended
Mode
Non-Extended
Mode
LOCK = x
LOCK = 0
LOCK = 1
MCR
2 to 7
none
none
EXCR1
0, 5 and 7
5 and 7
none
EXCR2
0 to 5
0 to 5
none
Description
Legacy Baud Generator
Divisor Port (Low Byte)
Legacy Baud Generator
Divisor Port (High Byte)
.
Reserved
LCR/
BSR
Non-Extended
Mode
Line Control /
Bank Select Register
7
6
5
4
3
2
Reserved
In addition, a fallback mechanism maintains this compatibility by forcing the UART to revert to 16550 mode if 16550
software addresses the module after a different mode was
set. Since setting the baud rate divisor values is a necessary initialization of the 16550, setting the divisor values in
bank 1 forces the UART to enter 16550 mode. (This is
called fallback.)
Legacy Baud Generator Divisor
1 0
Low Byte port
(LBGD(L))
Reset
Bank 1,
Required
Offset 00h
Least Significant Byte
of Baud Generator
To enable other modes to program their desired baud rates
without activating this fallback mechanism, the baud rate divisor register in bank 2 should be used.
8.6.1
FIGURE 8-18. LBGD(L) Register Bitmap
Legacy Baud Generator Divisor Ports (LBGD(L)
and LBGD(H)),
.
The programmable baud rates in the Non-Extended mode
are achieved by dividing a 24 MHz clock by a prescale value
of 13, 1.625 or 1. This prescale value is selected by the
PRESL field of EXCR2 (see page 209). This clock is subdivided by the two baud rate generator divisor buffers, which
output a clock at 16 times the desired baud rate (this clock is
the BOUT clock). This clock is used by I/O circuitry, and after
a last division by 16 produces the output baud rate.
7
Divisor values between 1 and 216-1 can be used. (Zero is
forbidden). The baud rate generator divisor must be loaded
during initialization to ensure proper operation of the baud
rate generator. Upon loading either part of it, the baud rate
generator counter is immediately loaded. Table 8-12 on
page 208 shows typical baud divisors. After reset the divisor
register contents are indeterminate.
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6
5
4
3
2
Legacy Baud Generator Divisor
1 0
High Byte port
(LBGD(H))
Reset
Bank 1,
Offset 01h
Required
Most Significant Byte
of Baud Generator
FIGURE 8-19. LBGD(H) Register Bitmap
206
Enhanced Serial Port - UART1 (Logical Device 6)
Line Control Register (LCR) and Bank Select
Register (BSR)
7
x
These registers are the same as the registers at offset 03h
in bank 0.
8.7
6
x
BANK 2 – EXTENDED CONTROL AND STATUS
REGISTERS
Baud Generator Divisor
5 4 3 2 1 0
Low Byte Port
(BGD(L))
x x x x x x Reset
Bank 2,
Required
Offset 00h
Bank 2 contains two alternate Baud rate Generator Divisor
ports and the Extended Control Registers (EXCR1 and
EXCR2).
TABLE 8-11. Bank 2 Register Set
Offset
Register
Name
00h
BGD(L)
Baud Generator Divisor Port (Low
byte)
01h
BGD(H)
Baud Generator Divisor Port (High
byte)
02h
EXCR1
Extended Control Register 1
03h
04h
Description
FIGURE 8-20. BGD(L) Register Bitmap
7
x
LCR/BSR Line Control/ Bank Select Register
EXCR2
05h
6
x
Baud Generator Divisor
5 4 3 2 1 0
High Byte Port
(BGD(H))
x x x x x x Reset
Bank 2,
Required
Offset 01h
Extended Control Register 2
Reserved
06h
TXFLV
TX_FIFO Level
07h
RXFLV
RX_FIFO Level
8.7.1
Least Significant Byte
of Baud Generator
Most Significant Byte
of Baud Generator
Baud Generator Divisor Ports, LSB (BGD(L))
and MSB (BGD(H))
FIGURE 8-21. BGD(H) Register Bitmap
These ports perform the same function as the Legacy Baud
Divisor Ports in Bank 1 and are accessed identically to
them, but do not change the operation mode of the module
when accessed. Refer to Section 8.6.1 on page 206 for
more detail.
Use these ports to set the baud rate when operating in Extended mode to avoid fallback to a Non-Extended operation
mode, i.e., 16550 compatible.When programming the baud
rate, writing to BGDH causes the baud rate to change immediately.
207
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BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS
8.6.2
BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS
Enhanced Serial Port - UART1 (Logical Device 6)
TABLE 8-12. Baud Generator Divisor settings
Prescaler Value
8.7.2
13
1.625
1
Baud
Divisor
% Error
Divisor
% Error
Divisor
% Error
50
2304
0.16%
18461
0.00%
30000
0.00%
75
1536
0.16%
12307
0.01%
20000
0.00%
110
1047
0.19%
8391
0.01%
13636
0.00%
134.5
857
0.10%
6863
0.00%
11150
0.02%
150
768
0.16%
6153
0.01%
10000
0.00%
300
384
0.16%
3076
0.03%
5000
0.00%
600
192
0.16%
1538
0.03%
2500
0.00%
1200
96
0.16%
769
0.03%
1250
0.00%
1800
64
0.16%
512
0.16%
833
0.04%
2000
58
0.53%
461
0.12%
750
0.00%
2400
48
0.16%
384
0.16%
625
0.00%
3600
32
0.16%
256
0.16%
416
0.16%
4800
24
0.16%
192
0.16%
312
0.16%
7200
16
0.16%
128
0.16%
208
0.16%
9600
12
0.16%
96
0.16%
156
0.16%
14400
8
0.16%
64
0.16%
104
0.16%
19200
6
0.16%
48
0.16%
78
0.16%
28800
4
0.16%
32
0.16%
52
0.16%
38400
3
0.16%
24
0.16%
39
0.16%
57600
2
0.16%
16
0.16%
26
0.16%
115200
1
0.16%
8
0.16%
13
0.16%
230400
---
---
4
0.16%
---
---
460800
---
---
2
0.16%
---
---
750000
---
---
---
---
2
0.00%
921600
---
---
1
0.16%
---
---
1500000
---
---
---
---
1
0.00%
Extended Control Register 1 (EXCR1)
Bit 0 - Extended Mode Select (EXT_SL)
When set to 1, the Extended mode is selected.
Use this register to control module operation in the Extended mode. Upon reset all bits are set to 0.
Bits 3 - 1 - Reserved
7
0
6
0
1
Read/Write 0.
Extended Control and
5 4 3 2 1 0
Status Register 1
0 0 0 0 0 0 Reset
(EXCR1)
Bank 2,
0 0 0
Required
Offset 02h
Bit 4 - Loopback Enable (LOOP)
During loopback, the transmitter output is connected internally to the receiver input, to enable system self-test
of serial communications. In addition to the data signal,
all additional signals within the UART are interconnected to enable real transmission and reception using the
UART mechanisms.
When this bit is set to 1, loopback is selected. This bit
accesses the same internal register as bit 4 in the MCR
register, when the UART is in a Non-Extended mode.
Loopback behaves similarly in both Non-Extended and
Extended modes.
When Extended mode is selected, the DTR bit in the
MCR register internally drives both DSR and RI, and the
RTS bit drives CTS and DCD.
EXT_SL
Reserved
LOOP
ETDLBK
Reserved
BTEST
FIGURE 8-22. EXCR1 Register Bitmap
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208
Enhanced Serial Port - UART1 (Logical Device 6)
1. The transmitter and receiver interrupts are fully operational. The Modem Status Interrupts are also fully
operational, but the interrupt sources are now the
lower bits of the MCR register.
TABLE 8-13. Prescaler Select
2. UART and infrared receiver serial input signals are
disconnected. The internal receiver input signals are
connected to the corresponding internal transmitter
output signals.
Bit 5
Bit 4
Prescaler Value
0
0
13
0
1
1.625
1
0
Reserved
1
1
1.0
3. The UART transmitter serial output is forced high
and the infrared transmitter serial output is forced
low, unless the ETDLBK bit is set to 1. In which case
they function normally.
4. The modem status input pins (DSR, CTS, RI and
DCD) are disconnected. The internal modem status
signals, are driven by the lower bits of the MCR register.
Bit 6 - Reserved
Read/write 0.
Bit 5 - Enable Transmitter During Loopback (ETDLBK)
When this bit is set to 1, the transmitter serial output is
enabled and functions normally when loopback is enabled.
Bit 7 - Baud Generator Test (BTEST)
When set, this bit routes the Baud Generator to the DTR
pin for testing purposes.
Bit 7 - Baud Divisor Register Lock (LOCK)
When set to 1, accesses to the Baud Generator Divisor
Register through LBGD(L) and LBGD(H) as well as fallback are disabled from non-extended mode.
In this case two scratchpad registers overlaid with LBGD(L) and LBGD(H) are enabled, and any attempted
CPU access of the Baud Generator Divisor Register
through LBGD(L) and LBGD(H) will access the scratchpad registers instead. This bit must be set to 0 when extended mode is selected.
8.7.3
8.7.5
Bit 6 - Reserved
Read/Write 0.
Line Control Register (LCR) and Bank Select
Register (BSR)
These registers are the same as the registers at offset 03h
in bank 0.
8.7.4
Bits 7-0 - Reserved
Extended Control and Status Register 2
(EXCR2)
Read/write 0’s.
8.7.6
This register configures the Prescaler and controls the
Baud Divisor Register Lock.
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
TX_FIFO Current Level Register (TXFLV)
This read-only register returns the number of bytes in the
TX_FIFO. It can be used to facilitate programmed I/O
modes during recovery from transmitter underrun in one of
the fast infrared modes.
Upon reset all bits are set to 0.
7
Reserved Register
Upon reset, all bits in Bank 2 register with offset 05h are set
to 0.
Extended Control and
Status Register 2
0 Reset
(EXCR2)
Bank 2,
0 Required
Offset 04h
0
Extended Modes
TX_FIFO
Current Level
Register (TXFLV)
Bank 2,
Required
Offset 06h
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
TFL0
TFL1
TFL2
TFL3
TFL4
Reserved
PRESL0
PRESL1
Reserved
LOCK
Reserved
FIGURE 8-23. EXCR2 Register Bitmap
FIGURE 8-24. TXFLV Register Bitmap
Bits 3 - 0 - Reserved
Bits 4-0 - Number of Bytes in TX_FIFO (TFL(4-0))
These bits specify the number of bytes in the TX_FIFO.
Read/Write 0.
209
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BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS
Bits 5,4 - Prescaler Select
The prescaler divides the 24 MHz input clock frequency
to provide the clock for the Baud Generator. (See Table
8-13).
During loopback, the following actions occur:
BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS
Enhanced Serial Port - UART1 (Logical Device 6)
8.8.1
Bits 7,6 - Reserved
Read/Write 0’s.
8.7.7
This read-only register identifies the revision of the module.
When read, it returns the module ID and revision level. This
module returns the code 2xh, where x indicates the revision
number.
RX_FIFO Current Level Register (RXFLV)
This read-only register returns the number of bytes in the
RX_FIFO. It can be used for software debugging.
7
0
Extended Modes
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
Module Revision ID Register (MRID)
6
0
Current Level
Register (RXFLV)
Bank 2,
Required
Offset 07h
RFL0
RFL1
RFL2
RFL3
RFL4
Revision ID(RID 3-0)
Module ID(MID 7-4)
Reserved
FIGURE 8-26. MRID Register Bitmap
FIGURE 8-25. RXFLV Register Bitmap
Bits 3-0 - Revision ID (MID3-0)
The value in these bits identifies the revision level.
Bits 4-0 - Number of Bytes in RX_FIFO (RFL(4-0))
These bits specify the number of bytes in the RX_FIFO.
Bits 7-4 - Module ID (MID7-4)
The value in these bits identifies the module type.
Bits 7,6 - Reserved
Read/Write 0’s.
Note: The contents of TXFLV and RXFLV are not frozen
during CPU reads. Therefore, invalid data could be returned if the CPU reads these registers during normal
transmitter and receiver operation. To obtain correct data, the software should perform three consecutive reads
and then take the data from the second read, if first and
second read yield the same result, or from the third
read, if first and second read yield different results.
8.8
8.8.2
7
0
Bank 3 contains the Module Revision ID register which
identifies the revision of the module, shadow registers for
monitoring various registers whose contents are modified
by being read, and status and control registers for handling
the flow control.
Register
Name
Description
00h
MRID
Module Revision ID Register
01h
SH_LCR
Shadow of LCR Register
(Read Only)
02h
SH_FCR Shadow of FIFO Control Register
(Read Only)
04h-07h
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LCR/
BSR
6
0
Shadow of
5 4 3 2 1 0
Line Control Register
(SH_LCR)
0 0 0 0 0 0 Reset
Bank 3,
Offset 01h
Required
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
TABLE 8-14. Bank 3 Register Set
Offset
Shadow of Line Control Register (SH_LCR)
This register returns the value of the LCR register. The LCR
register is written into when a byte value according to Table
8-8 on page 203, is written to the LCR/BSR registers location (at offset 03h) from any bank.
BANK 3 – MODULE REVISION ID AND SHADOW
REGISTERS
03h
5 4 3 2 1 0
Module Revision ID
Register
1 0 x x x x Reset
(MRID)
Required
Bank 3,
Offset 00h
FIGURE 8-27. SH_LCR Register Bitmap
See “Line Control Register (LCR)” on page 201 for bit descriptions.
Line Control Register/
Bank Select Register
Reserved
210
Enhanced Serial Port - UART1 (Logical Device 6)
Shadow of FIFO Control Register (SH_FCR)
This read-only register returns the contents of the FCR register in bank 0.
7
0
6
0
Shadow of
5 4 3 2 1 0
FIFO Control Register
(SH_FCR)
0 0 0 0 0 0 Reset
Bank 3,
Required
Offset 02h
7
0
6
0
0
0
RXHDL_IE
TXLDL_IE
LS_IE or TXUR_IE
MS_IE
Reserved
TXEMP_IE
Reserved
Reserved
FIFO_EN
RXSR
TXSR
Reserved
TXFTH0
TXFHT1
RXFTH0
RXFTH1
7
0
FIGURE 8-28. SH_LCR Register Bitmap
6
0
See “FIFO Control Register (FCR)” on page 200 for bit descriptions.
8.8.4
7
UART1 REGISTER BITMAPS
6
5
4
3
Read Cycles
2 1 0
Receiver Data
Register (RXD)
Reset
Bank 0,
Offset 00h
Required
7
0
6
0
0
0
6
5
4
3
Extended Mode, Read Cycles
Event Identification
5 4 3 2 1 0
Register (EIR)
0 0 0 0 0 1 Reset
Bank 0,
Offset 02h
Required
RXHDL_EV
TXLDL_EV
LS_EV or TXHLT_EV
MS_EV
Reserved
TXEMP-EV
Reserved
Reserved
Received Data
7
Non-Extended Modes, Read Cycles
Event Identification
5 4 3 2 1 0
Register (EIR)
0 0 0 0 0 1 Reset
Bank 0,
Offset 02h
0 0
Required
IPF - Interrupt Pending
IPR0 - Interrupt Priority 0
IPR1 - Interrupt Priority 1
RXFT - RX_FIFO Time-Out
Reserved
Reserved
FEN0 - FIFO Enabled
FEN1 - FIFO Enabled
Line Control Register (LCR) and Bank Select
Register (BSR)
These registers are the same as the registers at offset 03h
in bank 0.
8.9
Extended Mode
5 4 3 2 1 0
Interrupt Enable
Register (IER)
0 0 0 0 0 0 Reset
Bank 0,
Offset 01h
Required
Write Cycles
2 1 0
Transmitter Data
Register (TXD)
Bank 0,
Offset 00h
Required
Reset
7
0
6
0
Write Cycles
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
FIFO Control
Register (FCR)
Bank 0,
Offset 02h
Required
FIFO_EN
RXSR
TXSR
Reserved
TXFTH0
TXFTH1
RXFTH0
RXFTH1
Transmitted Data
211
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UART1 REGISTER BITMAPS
8.8.3
UART1 REGISTER BITMAPS
Enhanced Serial Port - UART1 (Logical Device 6)
Non-Extended Mode
7
0
6
0
Line Control
Register (LCR)
All Banks,
Offset 03h
Required
5 4 3 2 1 0
0 0 0 0 0 0 Reset
7
0
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
7
0
6
0
6
1
5 4 3 2 1 0
1 0 0 0 0 0 Reset
Line Status
Register (LSR)
Bank 0,
Offset 05h
Required
RXDA
OE
PE
FE
BRK
TXRDY
TXEMP
ER_INF
7
X
Bank Selection
Register (BSR)
All Banks,
Offset 03h
Required
5 4 3 2 1 0
0 0 0 0 0 0 Reset
6
X
5 4 3 2 1 0
X X 0 0 0 0 Reset
Modem Status
Register (MSR)
Bank 0,
Offset 06h
Required
DCTS
DDSR
TERI
DDCD
CTS
DSR
Bank Selected
RI
DCD
BKSE-Bank Selection Enable
Non-Extended Mode
Non-Extended Mode
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
7
6
5
4
3
2
1
0
Scratch Register
(SCR)
Reset
Bank 0,
Offset 07h
Required
Modem Control
Register (MCR)
Bank 0,
Required
Offset 04h
DTR
RTS
RILP
ISEN or DCDLP
LOOP
Scratch Data
Reserved
Extended Mode
Extended Mode
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
7
0
Modem Control
Register (MCR)
Bank 0,
Offset 04h
Required
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
Auxiliary Status
Register (ASCR)
Bank 0,
Offset 07h
Required
RXF_TOUT
DTR
RTS
Reserved
TX_DFR
Reserved
Reserved
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212
Enhanced Serial Port - UART1 (Logical Device 6)
6
5
4
3
2
Legacy Baud Generator Divisor
1 0
Low Byte Register
(LBGD(L)
Reset
Bank 1,
Offset 00h
Required
7
0
6
0
1
Extended Control and
5 4 3 2 1 0
Status Register 1
0 0 0 0 0 0 Reset
(EXCR1)
Bank 2,
0 0 0
Required
Offset 02h
EXT_SL
Reserved
LOOP
ETDLBK
Reserved
BTEST
Least Significant Byte
of Baud Generator
7
6
5
4
3
2
Legacy Baud Generator Divisor
1 0
High Byte Register
(LBGD(H))
Reset
Bank 1,
Offset 01h
Required
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
Extended Control and
Status Register 2
0 Reset
(EXCR2)
Bank 2,
0 Required
Offset 04h
0
Reserved
Most Significant Byte
of Baud Generator
7
x
6
x
PRESL0
PRESL1
Reserved
LOCK
Baud Generator Divisor
Low Byte Register
5 4 3 2 1 0
(BGD(L))
x x x x x x Reset
Bank 2,
Offset 00h
Required
IrDA or Consumer-IR Modes
TX_FIFO
Current Level
Register (TXFLV)
Bank 2,
Required
Offset 06h
TFL0
TFL1
TFL2
TFL3
TFL4
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
Least Significant Byte
of Baud Generator
Reserved
7
x
6
x
Baud Generator Divisor
High Byte Register
(BGD(H))
Bank 2,
Offset 01h
Required
5 4 3 2 1 0
x x x x x x Reset
IrDA or Consumer-IR Modes
RX_FIFO
Current Level
Register (RXFLV)
Bank 2,
Required
Offset 07h
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
0
0
0
RFL0
RFL1
RFL2
RFL3
RFL4
Most Significant Byte
of Baud Generator
Reserved
213
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UART1 REGISTER BITMAPS
7
UART1 REGISTER BITMAPS
Enhanced Serial Port - UART1 (Logical Device 6)
7
0
6
0
5 4 3 2 1 0
Module Revision ID
Register
1 0 x x x x Reset
(MRID)
Required
Bank 3
Offset 00h
Revision ID(RID 3-0)
Module ID(MID 7-4)
7
0
6
0
Shadow of
5 4 3 2 1 0
Line Control Register
0 0 0 0 0 0 Reset
(SH_LCR)
Bank 3,
Required
Offset 01h
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
7
0
6
0
Shadow of
5 4 3 2 1 0
FIFO Control Register
(SH_FCR)
0 0 0 0 0 0 Reset
Bank 3,
0
Required
Offset 02h
FIFO_EN
RXFR
TXFR
Reserved
TXFTH0
TXFHT1
RXFTH0
RXFTH1
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9.0
General Purpose Input and Output
(GPIO) Ports (Logical Device 7) and
Chip Select Output Signals
type and pull-up control). If GPIO10 is inactive, GPIO11 is
‘0’. Undefined results, when GPIO10 pin is configured as
output and/or GPIO11 pin is configured as input.
When configured as an input, GPIO10, GPIO12 and
GPIO13 can be routed to POR and/or SCI. GPIO10 can
also be routed to ONCTL. For more details, see the Advanced Power Control (APC) section.
The PC87317VUL supports three General Purpose I/O
(GPIO) ports.
The signals associated with these ports are as follows:
●
Port 1: GPIO10 to GPIO17
●
Port 2: GPIO20 to GPIO27
●
Port 3: GPIO30 to GPIO37.
9.2.2
Reading an output pin returns the internally latched bit value, not the pin value.
Writing to an input pin has no effect on the pin, except for
internally latching the written value. The latched value is reflected on the pin when the direction changes to output.
Upon reset the write latches are initialized to FFh.
The PC87317VUL has three programmable chip select signals, CS0, CS1 and CS2, which are also described in this
chapter.
9.1
The port pins are back-drive protected when the
PC87317VUL is powered down and also when the port is inactive (disabled).
GPIO PORT ACTIVATION
Activation and deactivation (enable/disable) of GPIO Ports
1 and 2 are controlled by the Activate register (index 30h) of
logical device 7 and by bit 7 of the Function Enable Register
2 (FER2) of the Power Management logical device. See
Section 10.2.4 "Function Enable Register 2 (FER2)" on
page 219.
9.2
Reading and Writing to GPIO Pins
9.2.3
Multiplexed GPIO Signals
See TABLE 9-1 for GPIO signal multiplexing.
TABLE 9-1. GPIO Multplexed Signals
GPIO CONTROL REGISTERS
The base address of the GPIO Ports is software configurable. It is controlled by two Base Address registers at indexes 60 and 61 of logical device 7. See Table 2-19 "GPIO
Ports Configuration Registers - Logical Device 7" on page
36.
GPIO Signal
Multiplexed with
GPIO15
PME2
GPIO16
PME1
PGIO17
WDO
The registers that control the GPIO Ports are located in two
banks. The active bank is selected by the GPIO Bank Select
bit, bit 7 of SuperI/O Configuration 2 register, at index 22h.
GPIO20
IRSL1
GPIO21
IRSL0 and IRSL2
Seven registers control GPIO Port 1, four registers control
GPIO Port 2 and four control GPIO Port 3. The registers that
control Port 1 are at offsets 00h through 03h from the base
address in bank 0 and 00h to 02h in bank 1. The registers
that control Port 2 are at offsets 04h through 07h from the
base address in bank 0. Port 3 is controlled by the registers
in offsets 04h to 07h of bank 1. See TABLES 9-2 "The
GPIO Registers, Bank 0" on page 216 and 9-3 "The GPIO
Registers, Bank 1" on page 217.
GPIO22
POR
GPIO23
RING
GPIO24
IRRX1 or XD2
GPIO25
P16 or XD3
GPIO26,27
XDB signals XD4,5
GPIO30
CTS2
GPIO31
DCD2
GPIO32
DSR2
GPIO33
RI2
GPIO34
RTS2
GPIO35
SIN2
GPIO36
SOUT2 and BOUT2
GPIO37
IRRX, IRSL0 and ID0
For each of the three ports:
●
Port Data registers read or write the data I/O bits.
●
Port Direction registers control the direction of each bit.
●
Port Output Type registers control the buffer type (opendrain or push-pull) of each bit.
●
The GPIO ports have open-drain output signals with internal pull-ups and TTL input signals. Pull-up Control
registers enable or disable the internal pull-up capability
of each bit.
9.2.1
Special GPIO Signal Features
The output type and pull-up settings for the GPIO17-14 signals can be locked by setting bits 7-4 of the Port 1 Lock register in bank 1. See TABLE 9-3 "The GPIO Registers, Bank
1" on page 217.
A GPIO port must not be enabled at the same address as
another accessible PC87317VUL register. Undefined results will occur if a GPIO is configured in this way.
GPIO10 pin is routed to GPIO11 pin, when bit 0 of Port 1
In2out register is ‘1’ and bit 1 of Port 1 Data register is ‘0’.
GPIO10 pin’s polarity is configurable via bit 0 of Port 1 Polarity register. If GPIO10 pin is active, GPIO11 pin is ‘1’ or in
high-impedance (depending on the settings of its output
9.2.4
Multiplexed GPIO Signal Selection
The signal that will actually use the I/O pin at any given time
depends on the selection made by the user.
GPIO15 is selected by bit 1 of the APC Control Register 3
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9.0 General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip Select Output Signals
General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip Select Output Signals
PROGRAMMABLE CHIP SELECT OUTPUT SIGNALS
General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip Select Output Signals
9.3
(Index 49h, Bank 2, APC registers, Logical Device 2).
GPIO16 is selected by bit 0 of the APC Control Register 3
(Index 49h, Bank 2, APC registers, Logical Device 2).
GPIO24 is selected on GPIO24/XD2 by bit 4 of SuperI/O
Configuration 1 register (index 21h in the Card Control Registers). It is selected on GPIO24/IRRX1 by bit 3 of APC Control Register 3 (Index 49h, Bank 2, APC registers, Logical
Device 2). GPIO24 can be selected on both pins at the
same time: when configured as an output, its value will be
driven on both pins; when configured as an input, the value
of GPIO24/IRRX1 will be read and the value on
GPIO24/XD2 will be ignored.
PROGRAMMABLE CHIP SELECT OUTPUT
SIGNALS
The three programmable chip select output signals have
the following characteristics:
●
CS0 is an open drain output signal.
●
CS1 and CS2 have push-pull buffers.
●
CS0 is in TRI-STATE when no VDD is applied.
Activation and deactivation (enabling and disabling) of these
chip select signals are controlled by the Function Enable
Register 2 (FER2) of logical device 8 (See Section 10.2.4
"Function Enable Register 2 (FER2)" on page 219) and the
configuration registers for CS0, CS1 and CS2 at second level indexes 02h, 06h and 0Ah, respectively.These registers
are accessed using two index levels.
GPIO25 is selected on GPIO25/XD3 by bit 4 of SuperI/O
Configuration 1 register (in the Card Control Registers). It is
selected on GPIO25/P16 by bit 0 of SuperI/O Configuration
3 register (in the Card Control Registers). GPIO25 can be
selected on both pins at the same time: when configured as
an output, its value will be driven on both pins; when configured as an input, the value of GPIO25/P16 will be read and
the value on GPIO25/XD3 will be ignored.
The first level index points to the Programmable Chip Select
Index and Data registers, like other PC87317CS0, CS1 and
CS2 VUL configuration registers. See Sections 2.4.5 "Programmable Chip Select Configuration Index Register" and
2.4.6 "Programmable Chip Select Configuration Data Register" on page 39. The Programmable Chip Select Configuration Index and Data registers are at index 23h and 24h
respectively.
GPIO30-32 and GPIO34-36 are selected by bit 3 of the SuperI/O Configuration 1 register (index 21h in the Card Control Registers).
GPIO33 is selected by bit 6 of the APC Control Register 5
(Index 4Bh, Bank 2, APC registers, Logical Device 2).
GPIO37 is selected by bit 4 of the APC Control Register 3
(Index 49h, Bank 2, APC registers, Logical Device 2).
The second level points to one of the three registers for
each CS pin. See Section 2.10 "PROGRAMMABLE CHIP
SELECT CONFIGURATION REGISTERS" on page 42.
Each CS pin is configured by the three registers assigned
to it. One specifies the base address MSB. One specifies
the base address LSB and one configures the CS pin.
All 16 address bits are decoded, with five mask options to
ignore (not decode) address bits A0, A1, A2, A3 and A4-11.
Decoding of only address and AEN pins, without RD or WR
pins, is also supported.
A CS signal is asserted when an address match occurs and
may be qualified by RD or WR signal(s). An address match
occurs when the AEN signal is inactive (low) and the nonmasked address pins match the corresponding base address bits.
TABLE 9-2. The GPIO Registers, Bank 0
Offset
Type
Hard Reset
Value
Port 1 Data
00h
R/W
FFh
Reads return the bit or pin value, according to the direction bit.
Writes are saved in this register and affect the output pins.
Port 1 Direction
01h
R/W
00h
Each bit controls the direction of the corresponding port pin.
0: Input. Reads of Port Data register return pin value.
1: Output. Reads of Port Data register return bit value.
Port 1 Output Type
02h
R/W
00h
Each bit controls the type of the corresponding port pin.
0: Open-drain.
1: Push-pull.
Port 1 Pull-up Control
03h
R/W
FFh
Each bit controls the internal pull-up for the corresponding port pin.
0: No internal pull-up.
1: Internal pull-up.
Port 2 Data
04h
R/W
FFh
Same as Port 1 Data register.
Port 2 Direction
05h
R/W
00h
Same as Port 1 Direction register.
Port 2 Output Type
06h
R/W
00h
Same as Port 1 Output Type register.
Port 2 Pull-up Control
07h
R/W
FFh
Same as Port 1 Pull-up Control register.
GPIO Register
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Description
216
General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip Select Output Signals
Offset
Type
Hard Reset
Value
Port 1 Lock
Register
00h
R/W
00h
Port 1 Polarity
01h
GPIO Register
Description
Bits 3-0 - Reserved.
Bits 7-4:
0: No effect
1: locks the corresponding bit of the Port 1 Direction, Output Type
and Pull-up Control Registers. If the corresponding bit of the Port
1 Direction Register is 1 (output), the contents of the corresponding bit of the Port 1 Data Register is also locked.
Once a bit is set to “1” by software, it can only be cleared to “0” by
a Hard Reset (No Power or Master Reset).
R/W
00h
Bit 0: When GPIO is input, it is
0: Active low
1: Active high
Bits 7-1 - Reserved
Port 1 In2out
02h
R/W
00h
Bit 0:
0: GPIO10 and GPIO11 are not connected.
1: GPIO10 is routed to GPIO11, if bit 1 of Port 1 Data Register is
0
Bits 7-1 - Reserved
Reserved
03h
-
-
Port 3 Data
04h
R/W
FFh
Same as Port1,2 Data registers
Port 3 Direction
05h
R/W
00h
Same as Port1,2 Direction registers
Port 3 Output Type
06h
R/W
00h
Same as Port1,2 Output Type registers
Port 3 Pullup
Control
07h
R/
FFh
Same as Port1,2 Pullup Control registers
-
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PROGRAMMABLE CHIP SELECT OUTPUT SIGNALS
TABLE 9-3. The GPIO Registers, Bank 1
10.0 Power Management (Logical Device 8)
Power Management (Logical Device 8)
10.0 Power Management
(Logical Device 8)
TABLE 10-1. The Power Management Registers
Index Symbol
10.1 POWER MANAGEMENT OPTIONS
The power management logical device provides configuration options and control of the WATCHDOG feature.
Description
Type
Base+0
Power Management Index Register R/W
Base+1
Power Management Data Register R/W
00h
FER1
Function Enable Register 1
R/W
Registers in this logical device enable activation of other
logical devices, and set signal characteristics for certain I/O
pins. (See Section 10.2 "POWER MANAGEMENT REGISTERS")
01h
FER2
Function Enable Register 2
R/W
02h
PMC1
Power Management Control 1
R/W
03h
PMC2
Power Management Control 2
R/W
10.1.2 WATCHDOG Feature
04h
PMC3
Power Management Control 3
R/W
The WATCHDOG feature lets the user implement power
saving strategies that power down the entire system if it is
unused for a user-defined period of time. This feature is especially attractive for battery-powered systems.
05h
WDTO
WATCHDOG Time-Out Register
R/W
06h
WDCF WATCHDOG Configuration Register R/W
07h
WDST
10.1.1 Configuration Options
The WATCHDOG function generates the WDO output signal, which the system may use to implement power-down
activities.
WATCHDOG Status Register
R/W
08
PM1 Event Base Address bit 7-0 R/W
09
PM1 Event Base Address bit 15-8 R/W
0A
PM1 Timer Base Address bit 7-0 R/W
0B
PM1 Timer Base Address bit 15-8 R/W
0C
PM1 Control Base Address bit 7-0 R/W
0D
PM1 Control Base Address bit 15-8 R/W
The WATCHDOG Configuration register (WDCF) specifies
the trigger events that cause reloading of the WATCHDOG
time-out value into the timer and restart the countdown. See
Section 10.2.9 "WATCHDOG Configuration Register (WDCF)" on page 222.
0E
General Purpose Status Base Ad- R/W
dress bit 7-0
0F
General Purpose Status Base Ad- R/W
dress bit 15-8
If the timer reaches zero, it is disabled, the WDO signal becomes active (low) and the host system can use WDO to
trigger power down.The state of the WDO signal can be
monitored at any time by reading bit 1 of the WATCHDOG
Status (WDST) register.
10
The WATCHDOG function is activated by setting the
WATCHDOG Time-Out (WDTO) register to a value from 1
through 255. This value defines a maximum countdown period, in minutes. The WATCHDOG timer starts with this value and counts down to 0 unless a trigger event restarts the
countdown, or unless reset aborts the countdown before
completion.
10.2 POWER MANAGEMENT REGISTERS
Seventeen power Management register control, activate
and monitor all activity of the power Management Logical
device.
Access to these registers is achieved by the use of two registers mapped in the PC87317VUL address space: the
power management registers are accessed via the Power
Management Index and Data registers, which are located at
base address and base address + 01h, respectively. The
base address is indicated by the Base Address registers at
indexes 60h and 61h of logical device 8, respectively. See
TABLE 2-20 "Power Management Configuration Registers
- Logical Device 8" on page 36.
ACPI Support register
W
10.2.1 Power Management Index Register
This read/write register points to one of the power management registers. Bits 7 through 5 are read only and return
000 when read.
It is reset by hardware to 00h. The data in the indicated register is accessed via the Power Management Data register
at the base address + 01h.
7
0
6
0
0
0
5 4 3 2 1 0
Power Management
Index Register,
0 0 0 0 0 0 Reset
Base Address
0
Required
+00h
TABLE 10-1 "The Power Management Registers" lists
these registers.
Index of a Power
Management Register
Read Only
FIGURE 10-1. Power Management Index Register Bitmap
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218
Power Management (Logical Device 8)
This read/write register contains the data in the register
pointed to by the Power Management Index register at the
base address.
7
0
6
0
POWER MANAGEMENT REGISTERS
Bit 4 - Parallel Port Function Enable
0: Disabled.
1: Enabled. (Default).
10.2.2 Power Management Data Register
Bit 5 - UART2 and Infrared Function Enable
0: Disabled.
1: Enabled. (Default).
5 4 3 2 1 0
Power Management
Data Register,
0 0 0 0 0 0 Reset
Base Address
Required
+ 01h
Bit 6 - UART1 Function Enable
0: Disabled.
1: Enabled. (Default).
Bit 7 - Reserved
10.2.4 Function Enable Register 2 (FER2)
Data in the Indicated Power
Management Register
This bits of the register enable or disable activity of Logic
devices within the PC87317 VUL.
Hard reset sets this read/write register to 87h.
FIGURE 10-2. Power Management Data Register Bitmap
7
1
10.2.3 Function Enable Register 1 (FER1)
This bits of the register enable or disable activity of Logic
devices within the PC87317 VUL.
A set bit enables activation of the corresponding logical device via its Active register at index 30h.
Hard reset sets this read/write register to FFh.
6
1
5 4 3 2 1 0
Function Enable
0 0 0 1 1 1 Reset Register 2 (FER2),
Index 01h
Required
Programmable CS0 Enable
Programmable CS1 Enable
Programmable CS2 Enable
PM1 Event Registers Enable
PM1 Control Registers Enable
General Purpose Events Registers Enable
SMI Command Register Enable
GPIO Ports Function Enable
A cleared bit disables the corresponding logical device regardless of the value in its Active register. Bit 0 of the Active
register of a logical device is ignored when the corresponding FER1 bit is cleared.
7
1
6
0
5 4 3 2 1 0
Function Enable
1 1 1 1 1 1 Reset Register 1 (FER1),
Index 00h
Required
FIGURE 10-4. FER2 Register Bitmap
Bit 0 - Programmable CS0 Function Enable
See CS0 Configuration 0 register in Section 2.10.3
"CS0 Configuration Register" on page 43.
0: CS0 is disabled.CS0 is not asserted; CS0 configuration and base address registers are maintained.
1: CS0 is enabled. (Default)
KBC Function Enable
Reserved
RTC Function Enable
FDC Function Enable
Parallel Port Function Enable
UART2 and Infrared Function Enable
UART1 Function Enable
Reserved
Bit 1 - Programmable CS1 Function Enable
See CS1 Configuration 1 register in Section 2.10.7
"CS1 Configuration Register" on page 43.
0: CS1 is disabled.CS1 signal is not asserted, CS1
configuration and base address registers are maintained.
1: CS1 is enabled. (Default)
FIGURE 10-3. FER1 Register Bitmap
Bit 0 - KBC Function Enable
0: Disabled.
1: Enabled. (Default)
Bit 2 - Programmable CS2 Function Enable
See CS2 Configuration 2 register in Section 2.10.11
"CS2 Configuration Register" on page 44.
0: CS2 is disabled.The CS2 signal is not asserted,
CS2 configuration and base address registers are
maintained.
1: CS2 is enabled. (Default)
Bit 1 - Reserved
Bit 2 - RTC Function Enable
0: Disabled.
1: Enabled. (Default)
Bit 3 - FDC Function Enable
0: Disabled.
1: Enabled. (Default)
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POWER MANAGEMENT REGISTERS
Power Management (Logical Device 8)
Bit 3 - PM1 Event Registers Enable
0: The registers pointed by PM1 Event Base Address
Bits 7-0 register (10.2.11 on page 223) and PM1
Event Base Address Bits15-8 register (10.2.12 on
page 223) are not accessible. Reads and writes
are ignored. Registers’ values are maintained. (Default)
1: The registers pointed by PM1 Event Base Address
Bits 7-0 register and PM1 Event Base Address Bits
15-8 register are accessible.
7
0
6
0
5 4 3 2 1 0
Power Management
0 0 0 0 0 0 Reset Control 1 Register
(PMC1)
Required
Index 02h
KBD/Mouse Tri-state contro
Reserved
FDC TRI-STATE Control
Parallel Port TRI-STATE Control
UART2 and Infrared TRI-STATE Control
UART1 TRI-STATE Control
Reserved
Bit 4 - PM1 Control Registers Enable
0: The registers pointed by PM1 Control Base Address Bits 7-0 register (10.2.15 on page 224) and
PM1 Control Base Address Bits 15-8 register
(10.2.16 on page 224) are not accessible. Reads
and writes are ignored. Registers’ values are maintained. (Default)
1: The registers pointed by PM1 Control Base Address Bits 7-0 register and PM1 Control Base Address Bits15-8 register are accessible.
FIGURE 10-5. PMC1 Register Bitmap
Bit 0 - Keyboard and Mouse Tri-state Control
This bit overrides the Tri-state setting at the SuperI/O Configuration register: When set to 1, the Keyboard and Mouse
output signals (KBCLK, KBDAT, MCLK and MDAT) are in
Tri-state. If cleared to 0, their state is set at the SuperI/O
Configuration register.
0: No effect (Default)
1: KBCLK, KBDAT, MCLK and MDAT are in Tri-state.
Bit 5 - General Purpose Event Registers Enable
0: The registers pointed by General Purpose Status
Base Address Bits 7-0 register (10.2.17 on page
224) and General Purpose Status Base Address
Bits 15-8 register (10.2.18 on page 224) are not accessible. Reads and writes are ignored. Registers’
values are maintained. (Default)
1: The registers pointed by General Purpose Status
Base Address Bits 7-0 register and General Purpose Status Base Address Bits15-8 register are accessible.
This bit does not control access to the SMI Command
register.
Bits 2-1 - Reserved
Bit 3 - FDC TRI-STATE Control
0: No effect. TRI-STATE controlled by bit 0 of the SuperI/O FDC Configuration register. (Default)
See Section 2.6.1 "SuperI/O FDC Configuration
Register" on page 40.
1: FDC signals are in TRI-STATE.
Bit 6 - SMI Command Register Enable
0: SMI Command register (4.7.11 on page 83) is not
accessible. Reads and writes are ignored. Register
values are maintained. (Default)
1: SMI Command register is accessible.
Bit 4 - Parallel Port TRI-STATE Control
0: No effect. TRI-STATE controlled by bit 0 of the SuperI/O Parallel Port Configuration register. (Default)
See Section 2.7.1 "SuperI/O Parallel Port Configuration Register" on page 41.
1: Parallel Port signals are in TRI-STATE.
Bit 7 - GPIO Ports Function Enable
0: GPIO Ports 1,2 and 3 are inactive (disabled).
Reads and writes are ignored; registers and pins
are maintained. Bit 0 of the Activate register (index
30h) of the GPIO Ports logical device is ignored.
1: GPIO Ports 1 and 2 are active (enabled) when bit 0
of the Activate register (index 30h) of the GPIO
Ports logical device is set. (Default)
Bit 5 - UART2 and Infrared TRI-STATE Control
0: No effect. TRI-STATE controlled by bit 0 of the SuperI/O UART2 Configuration register. (Default)
See Section 2.8.1 "SuperI/O UART2 Configuration
Register" on page 42.
1: UART2 signals are in TRI-STATE.
10.2.5 Power Management Control Register (PMC1)
Bit 6 - UART1 TRI-STATE Control
0: No effect. TRI-STATE controlled by bit 0 of the SuperI/O UART1 Configuration register. (Default)
See Section 2.9.1 "SuperI/O UART1 Configuration
Register" on page 42.
1: UART1 signals are in TRI-STATE.
The bits of this register place the signals of the corresponding inactive logical device in TRI-STATE (except IRQ and
DMA pins) when set to “1”,regardless of the value of bit 0 of
the corresponding logical device register at index F0h.
A cleared bit has no effect. In this case, the TRI-STATE status of signals is controlled by bit 0 of the corresponding logical device register at index F0h.
Bit 7 - Reserved
Reserved.
This is an OR function between PMC1 and the register at index F0h of the corresponding logical device.
Hard reset clears this read/write register to 00h.
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Power Management (Logical Device 8)
10.2.7 Power Management Control 3 Register (PMC3)
This register selects the SuperI/O Clock source, enables
the Clock Multiplier and monitors Multiplier Clock Status.
This register enables and monitors functions and devices.
7
6
0
Hard reset initializes this register to 0Eh.
7
0
5 4 3 2 1 0
Power Management
0 0 0 0 1 X Reset Control 2 Register
(PMC2)
Required
Index 03h
Reserved
UART2 Busy Indicator
UART1 busy Indicator
Reserved
Valid Multiplier Clock Status
FIGURE 10-7. PMC3 Register Bitmap
FIGURE 10-6. PMC2 Register Bitmap
Bit 0 - Power Management Timer CLock Enable
0: The clock is disabled.
The PM Timer registers (see Fixed ACPI registers)
are not accessible. Reads are ignored.
The TMR_STS and the TMR_EN bits (in PM1
Event registers) are read-only bits. Read returns 0.
1: The clock is enabled.
The PM Timer registers (see Fixed ACPI registers)
are accessible.
The TMR_STS and the TMR_EN bits (in PM1
Event registers) are functional.
Bits 1,0 - SuperI/O Clock Source
These bits determine the SuperI/O clock source.
The reset value of bit 0 is determined by the CFG0 Strapping (See Section 2). When CFG0 is 0, the reset value is 1;
when CFG0 is 1, this bit’s reset value is 0.
TABLE 10-2. SuperI/O Clock Source selection
PMC2
SuperI/O Clock Source
10
00
The 24 MHz clock is fed via the X1 pin
01
Reserved
10
The 48 MHz clock is fed via the X1 pin
11
The clock source is the on-chip clock multiplier
5 4 3 2 1 0
Power Management
0 0 1 1 1 0 Reset Control 3 Register
(PMC3)
Required
Index 04h
PM Timer Clock Enable
Parallel Port Clock Enable
UART2 Clock Enable
UART1 Clock Enable
SuperI/O Clock Source
Clock Multiplier Enable
Bits
6
0
Bit 1 - Parallel Port Clock Enable
This bit is ANDed with bit 1 of the SuperI/O Parallel Port
Configuration register at index F0h of logical device 4. If
either bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
0: The clock is disabled.
1: If bit 1 of the SuperI/O Parallel Port Configuration
register is set to 1, the clock is enabled. (Default)
Bit 2 - Clock Multiplier Enable
0: On-chip clock multiplier is disabled. (Default)
1: On-chip clock multiplier is enabled.
Bit 2 - UART2 Clock Enable
This bit is ANDed with bit 1 of the SuperI/O UART2 Configuration register at index F0h of logical device 5. If either bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
0: The clock is disabled.
1: If bit 1 of the SuperI/O UART2 Configuration register is set to 1, the clock is enabled. (Default)
Bits 6-3 - Reserved
Bit 7 - Valid Multiplier Clock Status
This bit is read only.
0: On-chip clock (clock multiplier output) is frozen.
1: On-chip clock (clock multiplier output) is stable and
toggling.
Bit 3 - UART1 Clock Enable
This bit is ANDed with bit 1 of the SuperI/O UART1 Configuration register at index F0h of logical device 6. If, either bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
0: The clock is disabled.
1: If bit 1 of the SuperI/O UART1 Configuration register is set to 1, the clock is enabled. (Default)
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POWER MANAGEMENT REGISTERS
10.2.6 Power Management Control 2 Register (PMC2)
POWER MANAGEMENT REGISTERS
Power Management (Logical Device 8)
10.2.9 WATCHDOG Configuration Register (WDCF)
Bits 5,4 - Reserved
This register enables or masks the trigger events that restart the WATCHDOG timer.
Bit 6 - UART2 Busy Indicator
When set to 1, this read-only bit indicates the UART2 is
busy. It is also accessed via the SuperI/O UART2 Configuration register at index F0h of logical device 5. See
Section 2.8 "UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5)" on page 42.
When an enabled trigger event occurs, the programmed
time-out value (the value in the WDTO register) is reloaded
into the WATCHDOG timer. The WATCHDOG timer can
reach zero and activate WDO only if no trigger event occurs
for an entire time-out period.
Trigger events are not affected by the polarity or type of the
module interrupt.
Bit 7 - UART1 Busy Indicator
When set to 1, this read-only bit indicates the UART1 is
busy. It is also accessed via the SuperI/O UART2 Configuration register at index F0h of logical device 6. See Section
2.9.1 "SuperI/O UART1 Configuration Register" on page
42.
Upon reset and upon activation of the power management
device, all trigger events are disabled, i.e., bits are cleared
to zero.
See Section 10.1.2 "WATCHDOG Feature" on page 218 for
more information.
10.2.8 WATCHDOG Time-Out Register (WDTO)
This read/write register specifies the WATCHDOG time-out
period programmed by the user. It does not reflect the current count while a countdown is in progress. The time-out
period may be from 1 to 255 minutes.
7
0
KBC IRQ Trigger Enable
Mouse IRQ Trigger Enable
UART1 IRQ Trigger Enable
UART2 IRQ Trigger Enable
See Section 10.1.2 "WATCHDOG Feature" on page 218 for
more information.
6
0
WATCHDOG Configuration
5 4 3 2 1 0
Register (WDCF)
0 0 0 0 0 0 Reset
Index 06h
Required
This register is cleared to 00h after reset. This register is
also reset to zero and disabled when the Power Management device is activated.
7
0
6
0
WATCHDOG Time-Out
5 4 3 2 1 0
0 0 0 0 0 0 Reset Register (WDTO)
Index 05h
Required
Reserved
FIGURE 10-9. WDCF Register Bitmap
Bit 0 - KBC IRQ Trigger Enable
This bit enables the IRQ assigned to the KBC to trigger
reloading of the WATCHDOG timer.
Reset clears this bit to 0.
0: KBC IRQ trigger disabled. (Default)
1: An active KBC IRQ signal triggers reloading of the
WATCHDOG timer.
Programmed Time-Out Period
FIGURE 10-8. WDTO Register Bitmap
Bit 1 - Mouse IRQ Trigger Enable
This bit enables the IRQ assigned to the mouse to trigger reloading of the WATCHDOG timer.
Reset clears this bit to 0.
0: Mouse IRQ trigger disabled. (Default)
1: An active mouse IRQ signal triggers reloading of
the WATCHDOG timer.
Bits 7-0 - Programmed Time-Out Period
These bits contain the programmed time-out period for
the WATCHDOG timer. They do not reflect the current
count while countdown is in progress.
Writing the value 00h resets the timer and deactivates
the WDO signal. Hardware reset clears the register to
00h, and deactivates the WATCHDOG timer function
and WDO. Software reset deactivates power management (logical device 8) and resets the WATCHDOG timer.
Values between 1 and 255 specify the countdown period, with one minute for each decrement.
When the timer reaches 00h, the WDO signal is enabled
(active low).
Writing a non-zero value to these bits resets the WDO
signal to 1 (inactive high).
Bit 2 - UART1 IRQ Trigger Enable
This bit enables the IRQ assigned to UART1 to trigger
reloading of the WATCHDOG timer.
Reset clears this bit to 0.
0: UART1 IRQ trigger disabled. (Default)
1: An active UART1 IRQ signal triggers reloading of
the WATCHDOG timer.
Bit 3 - UART2 IRQ Trigger Enable
This bit enables the IRQ assigned to UART2 to trigger
reloading of the WATCHDOG timer.
Reset clears this bit to 0.
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Power Management (Logical Device 8)
7
0
6
0
Bits 7-4 - Reserved
Reserved
PM1 Event Base Address
5 4 3 2 1 0
Register Bits 7-0,
0 0 0 0 0 0 Reset
Index 08h
Required
10.2.10 WATCHDOG Status Register (WDST)
Bit 1 of this register contains the value of the WDO signal,
for monitoring by software.
On reset or on PM logical device activation this register is
initialized to 01h.
PM1 Event Base Address Bits 7-0
See Section 10.1.2 "WATCHDOG Feature" on page 218 for
more information.
FIGURE 10-11. PM1 Bits 7-0 Register Bitmap
7
0
6
0
5 4 3 2 1 0
WATCHDOG Status
0 0 0 0 0 1 Reset Register (WDST)
Index 07h
Required
10.2.12 PM1 Event Base Address Register (Bits 15-8)
This read/write register holds the base address bits 15-8 of
the PM1 Event Registers of the ACPI fixed registers (See
Logical device 2).
WDO Value
On reset this register is initialized to 00h.
7
0
Reserved
6
0
PM1 Event Base Address
5 4 3 2 1 0
Register Bits 15-8,
0 0 0 0 0 0 Reset
Index 09h
Required
FIGURE 10-10. WDST Register Bitmap
Bit 0 - WDO Value
This read-only bit reflects the value of WDO. It is initialized to 1 by a hardware reset.
This bit reflects the status of the WDO signal, even if
WDO is not configured for output by bit 6 of SuperI/O
Configuration register 2, in which case the pin is used
for GPIO17.
0: WDO is active.
1: WDO is not active. (Default)
PM1 Event Base Address Bits 15-8
FIGURE 10-12. PM1 Bits 15-8 Register Bitmap
10.2.13 PM Timer Base Address (Bits 7-0)
This read/write register holds the base address bits 7-0 of
the PM Timer Registers of the ACPI fixed registers (See
Logical device 2).
Bits 7-1 - Reserved
10.2.11 PM1 Event Base Address Register (Bits 7-0)
Bits 0,1 are read-only. On reset this register is initialized to
00h.
This read/write register holds the base address bits 7-0 of
the PM1 Event Registers of the ACPI fixed registers (See
Logical device 2).
7
0
Bits 0,1 are read-only. On reset this register is initialized to
00h.
6
0
PM Timer Base Address
5 4 3 2 1 0
Register Bits 7-0,
0 0 0 0 0 0 Reset
Index 0Ah
Required
PM TImer Base Address Bits 7-0
FIGURE 10-13. PM Timer Base Address Bits 7-0
Register Bitmap
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POWER MANAGEMENT REGISTERS
0: UART2 IRQ trigger disabled. (Default)
1: An active UART2 IRQ signal triggers reloading of
the WATCHDOG timer.
POWER MANAGEMENT REGISTERS
Power Management (Logical Device 8)
10.2.14 PM Timer Base Address Register (Bits 15-8)
This read/write register holds the base address bits 15-8 of
the PM Timer Registers of the ACPI fixed registers (See
Logical device 2).
7
0
6
0
On reset this register is initialized to 00h.
7
0
6
0
PM1 Control Base Address
5 4 3 2 1 0
Register Bits 15-8,
0 0 0 0 0 0 Reset
Index 0Dh
Required
PM Timer Base Address
5 4 3 2 1 0
Register Bits 15-8,
0 0 0 0 0 0 Reset
Index 0Bh
Required
PM1 Control Base Address Bits 15-8
FIGURE 10-16. PM1 Control Base Address Bits 15-8
Register Bitmap
PM Timer Base Address Bits 15-8
10.2.17 General Purpose Status Base Address Register
(Bits 7-0)
FIGURE 10-14. PM Timer Base Address Bits 15-8 Register Bitmap
This read/write register holds the base address bits 7-0 of
the General Purpose Status Registers of the ACPI fixed
registers (See Logical device 2).
10.2.15 PM1 Control Base Address Register (Bits 7-0)
Bits 3-0 are read-only. On reset this register is initialized to
00h.
This read/write register holds the base address bits 7-0 of
the PM1 Control Registers of the ACPI fixed registers (See
Logical device 2).
Bit 0 is read-only. On reset this register is initialized to 00h.
7
0
6
0
7
0
PM1 Control Base Address
5 4 3 2 1 0
Register Bits 7-0,
0 0 0 0 0 0 Reset
Index 0Ch
Required
6
0
General Purpose Status Base Address
5 4 3 2 1 0
Register Bits 7-0,
0 0 0 0 0 0 Reset
Index 0Eh
Required
General Purpose Status
Base Address Bits 7-0
PM1 Control Base Address Bits 7-0
FIGURE 10-17. General Purpose Base Address Bits 70 Register Bitmap
10.2.18 General Purpose Status Base Address Register
(Bits 15-8)
FIGURE 10-15. PM1 Control Base Address Bits 7-0
Register Bitmap
This read/write register holds the base address bits 7-0 of
the General Purpose Status Registers of the ACPI fixed
registers (See Logical device 7).
10.2.16 PM1 Control Base Address Register (Bits 15-8)
This read/write register holds the base address bits 7-0 of
the PM1 Event Registers of the ACPI fixed registers (See
Logical device 2).
On reset this register is initialized to 00h.
On reset this register is initialized to 00h.
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Power Management (Logical Device 8)
6
0
General Purpose Status Base Address
5 4 3 2 1 0
Register Bits 15-8,
0 0 0 0 0 0 Reset
Index 0Fh
Required
Bit 4 - BIOS Global Lock Release
When “1” is written to this bit, the GLobal Lock Status bit
is set to “1” (fixed ACPI register PM1_STS_LOW, bit 5),
and as SCI interrupt request can be thus asserted.
Writing a “0” to this bit has no effect on the SCI signal.
Bit 5 - SMI Command Status
This is a sticky bit. It is set to '1', when SMI Command
Register is written (see ACPI Fixed registers). It is
cleared to '0' only by software writing a one.
General Purpose Status
Base Address Bits 15-8
Bit 6 - SMI Command Enable
0: SMI Command Status bit is ignored (bit 5 of the
ACPI Support register).
1: Activate the POR pin, when the SMI Command
Status bit is '1'.
FIGURE 10-18. General Purpose Base Address Bits
15-8 Register Bitmap
10.2.19 ACPI Support Register
This register allows the system to enter suspended mode
via software emulation. It also supports the Global Lock
mechanism.
Bit 7 - Mask PM1 Event Register Bits
0: All defined bits of PM1 Event Registers are functional.
1: Only RTC_STS, RTC_EN and WAK_STS bits of
PM1 Event Registers are functional. All other defined bits are forced to ‘0’ (writes to these ‘other defined’ bits are ignored).
This bit does not effect TMR_STS and TMR_EN bits
which behave according to bit 0 of PMC3 register.
Upon reset, this register is initialized to 00h.
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
ACPI Support
Register
Index 10h
Required
Sleep Enable Status
Enable POR on Sleep Enable
ACPI GLobal Lock Status
ACPI GLobal Lock Enable
BIOS Global Lock release
Reserved
FIGURE 10-19. ACPI Support Register Bitmap
Bit 0 - Sleep Enable Status
This sticky bit shows the status of the Sleep Enable bit
It is set to “1” when the Sleep Enable bit (in the
PM1_CNT_HIGH register in the fixed ACPI registers,
Logical device 7) is written with a “1”. It is cleared to “0”
only when software writes a “1” to it.
Bit 1 - Enable POR on Sleep Enable
This bit is enables activation of the POR interrupt request pin, when the Sleep Enable Status bit goes to 1.
0: Sleep Enable Status bit is ignored.
1: Activate POR pin if Sleep Enable Status is “1”.
Bit 2 - ACPI Global Lock Status
This sticky bit is set to “1” when a “1” is written to the
ACPI Global Lock release bit (bit 2 in the ACPI fixed register PM1_CNT_LOW). It is cleared to “0” only when
software writes a “1” to it.
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POWER MANAGEMENT REGISTERS
7
0
Bit 3 - ACPI Global Lock Enable
0: ACPI GLobal Lock Status bit is ignored (bit 2 of this
register).
1: Activate POR pin if Sleep Enable Status is “1.
POWER MANAGEMENT REGISTER BITMAPS
Power Management (Logical Device 8)
10.3 POWER MANAGEMENT REGISTER BITMAPS
7
0
6
0
0
0
7
0
5 4 3 2 1 0
Power Management
Index Register,
0 0 0 0 0 0 Reset
Base Address
0
Required
+00h
6
0
5 4 3 2 1 0
Power Management
0 0 0 0 0 0 Reset Control 1 Register
(PMC1)
Required
Index 02h
KBD/Mouse Tri-state contro
Reserved
FDC TRI-STATE Control
Parallel Port TRI-STATE Control
UART2 and Infrared TRI-STATE Control
UART1 TRI-STATE Control
Reserved
Index of a Power
Management Register
Read Only
7
0
6
0
5 4 3 2 1 0
Power Management
Data Register,
0 0 0 0 0 0 Reset
Base Address
Required
+ 01h
7
6
0
5 4 3 2 1 0
Power Management
0 0 0 0 1 X Reset Control 2 Register
(PMC2)
Required
Index 03h
SuperI/O Clock Source
Clock Multiplier Enable
Data in the Indicated Power
Management Register
Reserved
Valid Multiplier Clock Status
7
1
6
1
5 4 3 2 1 0
Function Enable
1 1 1 1 1 1 Reset Register 1 (FER1),
Index 00h
Required
7
0
KBC Function Enable
Reserved
RTC Function Enable
FDC Function Enable
Parallel Port Function Enable
UART2 and Infrared Function Enable
UART1 Function Enable
Reserved
7
1
6
0
5 4 3 2 1 0
Power Management
0 0 1 1 1 0 Reset Control 3 Register
(PMC3)
Required
Index 04h
PM Timer Clock Enable
Parallel Port Clock Enable
UART2 Clock Enable
UART1 Clock Enable
Reserved
UART2 Busy Indicator
UART1 busy Indicator
5 4 3 2 1 0
Function Enable
0 0 0 1 1 1 Reset Register 2 (FER2),
Index 01h
Required
7
0
Programmable CS0 Enable
Programmable CS1 Enable
Programmable CS2 Enable
PM1 Event Registers Enable
PM1 Control Registers Enable
General Purpose Events Registers Enable
SMI Command Register Enable
GPIO Ports Function Enable
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6
0
6
0
WATCHDOG Time-Out
5 4 3 2 1 0
(WDTO) Register
0 0 0 0 0 0 Reset
Index 05h
Required
Programmed Time-Out Period
226
Power Management (Logical Device 8)
6
0
WATCHDOG Configuration
5 4 3 2 1 0
(WDCF) Register,
Index 06h
0 0 0 0 0 0 Reset
7
0
6
0
Required
PM Timer Base Address
5 4 3 2 1 0
Register Bits 7-0,
0 0 0 0 0 0 Reset
Index 0Ah
Required
KBD IRQ
Mouse IRQ
UART 1 IRQ
UART 2 IRQ
PM TImer Base Address Bits 7-0
Reserved
7
0
6
0
5 4 3 2 1 0
WATCHDOG Status
Register,
0 0 0 0 0 1 Reset
Index 07h
Required
7
0
6
0
PM Timer Base Address
5 4 3 2 1 0
Register Bits 15-8,
0 0 0 0 0 0 Reset
Index 0Bh
Required
WDO Value
Reserved
7
6
5
4
3
2
1
0
0
0
0
0
0
0
PM Timer Base Address Bits 15-8
PM1 Event Base Address
Register Bits 7-0,
0 Reset
Index 08h
Required
0
7
0
6
0
PM1 Control Base Address Bits 7-0
PM1 Event Base Address Bits7-0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
PM1 Control Base Address
5 4 3 2 1 0
Register Bits 7-0,
0 0 0 0 0 0 Reset
Index 0Ch
Required
PM1 Event Base Address
Register Bits 15-8,
0 Reset
Index 09h
Required
0
7
0
6
0
PM1 Control Base Address
5 4 3 2 1 0
Register Bits 15-8,
0 0 0 0 0 0 Reset
Index 0Dh
Required
PM1 Control Base Address Bits 15-8
PM1 Event Base Address Bits 15-8
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POWER MANAGEMENT REGISTER BITMAPS
7
0
POWER MANAGEMENT REGISTER BITMAPS
Power Management (Logical Device 8)
7
0
6
0
General Purpose Status Base Address
5 4 3 2 1 0
Register Bits 7-0,
0 0 0 0 0 0 Reset
Index 0Eh
Required
General Purpose Status
Base Address Bits 7-0
7
0
6
0
General Purpose Status Base Address
5 4 3 2 1 0
Register Bits 15-8,
0 0 0 0 0 0 Reset
Index 0Fh
Required
General Purpose Status
Base Address Bits 15-8
7
0
6
0
5 4 3 2 1 0
0 0 0 0 0 0 Reset
ACPI Support
Register
Index 10h
Required
Sleep Enable Status
Enable POR on Sleep Enable
ACPI GLobal Lock Status
ACPI GLobal Lock Enable
BIOS Global Lock release
Reserved
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11.0 X-Bus Data Buffer
X-Bus Data Buffer
11.0 X-Bus Data Buffer
The X-Bus Data Buffer (XDB) connects the 8-bit X data bus
to the system data bus via the PC87307VUL data bus. The
XDB is selected by bit 4 of Super/O Chip Configuration 1 register (index 21h), as described in Section 2.4.3 "SuperI/O
Configuration 1 Register (SIOC1)" on page 37. This bit is initialized according to the CFG1 strap pin value.
When XDB is not selected, these pins have alternate functions. See the XDB pin multiplexing Table 1-2 on page 25.
When XDCS is inactive, XD7-0 are not driven or gated to D7-0.
When XDCS is active XD7-0 are linked to D7-0 as follows:
●
D7-0 values are driven onto XD7-0 pins when XDRD
is inactive.
●
XD7-0 values are driven onto D7-0 pins when XDRD
is active.
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12.0 The Internal Clock
The Internal Clock
12.0 The Internal Clock
12.4 POWER-ON PROCEDURE WHEN CFG0 = 0
12.1 THE CLOCK SOURCE
The source of the internal clock of the PC87317VUL can be
24 MHz or 48 MHz clock signals via the X1 pin, or an internal on-chip clock multiplier fed by the 32.768 KHz crystal of
the Real-Time Clock (RTC). The clock source is determined
by bits 1,0 of the Power Management Control 2 (PMC2) register of logical device 8. See Section 10.2.6 "Power Management Control 2 Register (PMC2)" on page 221. Bit 0 is
determined by the CFG0 strap pin. Toggling of the 32.768
KHz clock cannot be stopped while VCCH is active. When
the 32.768 KHz oscillator is not running, the internal circuit
is blocked.
12.2 THE INTERNAL ON-CHIP CLOCK MULTIPLIER
Two events can trigger the internal on-chip clock multiplier.
One is power-on while VDD is active. The other is changing
the multiplier enable bit (bit 2 of the PMC2 register of logical
device 8) from 0 to 1. See Section10.2.6 "Power Management Control 2 Register (PMC2)" on page 221. This bit can
also disable the clock multiplier and its output clock.
Once enabled, the output clock of the clock multiplier is frozen until the clock multiplier can provide an output clock that
meets all requirements; then it starts. When the power is
turned on, the PC87317VUL wakes up with the internal onchip clock multiplier disabled.
The 32.768 KHz and output clocks of the internal on-chip
clock multiplier operate regardless of the status of the Master Reset (MR) signal. They can operate while MR is active.
The multiplier must have a 32.768 KHz input clock operating. Otherwise, the multiplier waits until this input clock
starts operating.
Bit 7 of the PMC2 register of logical device 8 is the Valid
Multiplier Clock status bit. When the 32.768 KHz clock toggles before MR becomes active, this bit is usually set to 1
before power-up reset ends (while MR is high, if MR is high
for a few msec).
While it is stabilizing, the output clock is frozen and the status bit is cleared to 0 to indicate a frozen clock. When the
clock multiplier becomes stable, the output clock starts toggling and the status bit is set to 1. A longer time is required
to set the Valid Multiplier Clock status bit if the multiplier
waits for a stable 32.768 KHz clock.
The Valid Multiplier Clock status bit indicates when the
clock is operating. Software should poll this bit and activate
(enable) the KBC, FDC, UART1, the UART2 and infrared interface (IR), and the Parallel Port according to its value.
The multiplier and its output clock do not use power when
they are disabled.
12.3 SPECIFICATIONS
●
Wake-up time (from the time the 32.768 KHz clock is operating and on-chip clock multiplier is enabled) is a maximum of 1.5 msec.
●
Tolerance (long term deviation) of the multiplier output
clock, above the 32.768 KHz tolerance, is ± 110 ppm.
Total tolerance is therefore ± (32.768 KHz clock tolerance + 110 ppm).
●
Cycle by cycle variance is a maximum of 0.1 nsec.
●
Power consumption is a maximum of 5 mA.
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230
For proper operation, follow the procedure below after power-on:
1. If on-chip clock multiplier is used: Go to step 2.
If 24 MHz or 48 Mhz clock on X1 pin is used: Set bits 0
and 1 of PMC2 register of logical device 8 to the desired
clock source. Go to step 4.
2. Set bit 2 of PMC2 register of logical device 8 to 1. The
on-chip clock multiplier is enabled and starts stabilizing.
Steps 1 and 2 can be unified, if both are required.
3. Poll bit 7 of PMC2 register of logical device 8. Wait until
it is set to 1. When set to 1, go to step 4.
4. Enable any module of the PC87317.
13.0 Interrupt and DMA Mapping
Interrupt and DMA Mapping
13.0 Interrupt and DMA Mapping
The standard Plug and Play configuration registers map
IRQs and DMA channels for the PC87317VUL. See TABLES 2-8 "Plug and Play (PnP) Interrupt Configuration
Registers" on page 32 and 2-9 "Plug and Play (PnP) DMA
Configuration Registers" on page 32.
13.1 IRQ MAPPING
The PC87317VUL allows connection of some logical devices to the 13 IRQ signals.
The polarity of an IRQ signal is controlled by bit 1 of the Interrupt Type registers (index 71h) of each logical device.
The same bit also controls selection of push-pull or opendrain IRQ output. High polarity implies push-pull output.
Low polarity implies open-drain output with strong pull-up
for a short time, followed by weak pull-up.
The IRQ input signals of the KBC or mouse, and of the parallel port are not affected by this bit, i.e., bit 1 at index 71h
of each logical device. This bit affects only the output buffer,
not the input buffer.
Only the UART1 and UART2 may map more than one logical device to any IRQ signal. Other devices may not do so.
An IRQ signal is in TRI-STATE when any of the following
conditions is true:
●
No logical device is mapped to the IRQ signal.
●
The logical device mapped to the IRQ signal is inactive.
●
The logical device mapped to the IRQ signal floats its
IRQ signal.
13.2 DMA MAPPING
Although the PC87317VUL allows some logical devices to
be connected to the four 8-bit DMA channels, it is illegal to
map two logical devices to the same pair of DMA signals.
A DRQ signal is in TRI-STATE and the DACK input signal
is blocked to 1 when any of the following conditions is true:
●
No logical device is mapped to the DMA channel.
●
The logical device mapped to the DMA channel is inactive.
●
The logical device mapped to the DMA channel floats its
DRQ signal.
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14.0 Device Specifications
Device Specifications
14.0 Device Specifications
14.1 GENERAL DC ELECTRICAL CHARACTERISTICS
14.1.1 Recommended Operating Conditions
TABLE 14-1. Recommended Operating Conditions
Symbol
Parameter
VDD, VCCH Supply Voltage
VBAT
Battery Backup Supply Voltage
TA
Min
Typ
Max
Unit
4.5
5.0
5.5
V
2.4
3.0
3.7
V
+70
°C
Operating Temperature
0
14.1.2 Absolute Maximum Ratings
Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all voltages are relative to ground.
TABLE 14-2. Absolute Maximum Ratings
Symbol
Min
Max
Unit
Supply Voltage
−0.5
6.5
V
VI
Input Voltage
−0.5
VDD + 0.5
V
VO
Output Voltage
−0.5
VDD + 0.5
V
Storage Temperature
−65
+165
°C
VDD
TSTG
Parameter
Conditions
PD
Power Dissipation
1
W
TL
Lead Temperature
Soldering (10 sec.)
+260
°C
CZAP = 100 pF
ESD Tolerance
RZAP = 1.5 KΩ 1
1500
V
1. Value based on test complying with RAI-5-048-RA human body model ESD testing.
14.1.3 Capacitance
TABLE 14-3. Capacitance: TA = 25°C, f = 1 MHz
Symbol
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Parameter
Min
Typ
Max
Unit
CIN
Input Pin Capacitance
5
7
pF
CIN1
Clock Input Capacitance
8
10
pF
CIO
I/O Pin Capacitance
10
12
pF
CO
Output Pin Capacitance
6
8
pF
232
Device Specifications
TABLE 14-4. Power Consumption
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD Average Main Supply
Current 1
VIL = 0.5 V
VIH = 2.4 V
No Load
32
50
mA
ICCSB
VDD Quiescent Main Supply
Current in Low Power Mode
VIL = VSS
VIH = VDD
No Load
1.3
1.7
mA
ICCH
VCCH RTC/APC (Logical
Device 2) Help Supply
Current
VCCH = 5 V ±10%
2
IBAT
VBAT Battery Supply Current
ICC
mA
VBAT = 3 V
µA
2
1. Do not permit VCCH to ramp down at a rate exceeding 1 V/msec. Exceeding this rate may
reset the Valid RAM and Time (VRT) bit (bit 7) of the RTC Control Register D (CRD) at offset
0Dh of logical device 2.
14.2 DC CHARACTERISTICS OF PINS, BY GROUP
The following tables list the DC characteristics of all device pins described in Section 1.2. The pin list preceeding each table
lists the device pins to which the table applies.
14.2.1 Group 1
Pin List:
A15-0, AEN, CTS2,1, DACK3-0, DCD2,1, DSKCHG, DSR2,1, ID3-0, INDEX, MR, RD, RDATA, SIN2,1, TC, TRK0, WP,
WR, XDRD
TABLE 14-5. DC Characteristics of Group 1 Pins
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD 1
V
VIL
Input Low Voltage
−0.5 1
0.8
V
µA
Input Leakage Current
VIN = VDD
10
IIL
VIN = VSS
−10
µA
VH
Input Hysteresis
250
mV
1. Not tested. Guaranteed by design.
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DC CHARACTERISTICS OF PINS, BY GROUP
14.1.4 Power Consumption Under Recommended Operating Conditions
Device Specifications
DC CHARACTERISTICS OF PINS, BY GROUP
14.2.2 Group 2
Pin List:
BUSY, PE, SLCT, WAIT
Output from SLCT, PE and BUSY is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode
is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. (See TABLE 6-1 "Parallel Port Mode Selection" on
page 138.) Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be used.
PE is in Group 2 only if bit 2 of PP Confg0 Register is “0” (see Section 6.5.19 "PP Confg0 Register" on page 153).
All group 2 pins are back-drive protected.
TABLE 14-6. DC Characteristics of Group 2 Pins
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD 1
V
VIL
Input Low Voltage
−0.5 1
0.8
V
µA
Input Leakage Current
VIN = VDD
120
IIL
VIN = VSS
−10
µA
1. Not tested. Guaranteed by design.
14.2.3 Group 3
Pin List:
ACK, ERR, PE
Output from ACK, ERR and PE is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is
ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. (See TABLE 6-1 "Parallel Port Mode Selection" on page
138.) Otherwise, output from these signals is level 2.
External 4.7 KΩ pull-up resistors should be used.
PE is in Group 3 only if bit 2 of PP Confg0 Register is “1” (see Section 6.5.19 "PP Confg0 Register" on page 153).
All group 3 pins are back-drive protected.
TABLE 14-7. DC Characteristics of Group 3 Pins
Symbol
Parameter
Conditions
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
−0.5 1
IIL
Input Leakage Current
1. Not tested. Guaranteed by design.
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Min
234
Max
VDD
1
Unit
V
0.8
V
VIN = VDD
10
µA
VIN = VSS
−120
µA
Device Specifications
DC CHARACTERISTICS OF PINS, BY GROUP
14.2.4 Group 4
Pin List:
MSEN1,0, SELCS
SELCS is a CMOS input pin.
TABLE 14-8. DC Characteristics of Group 4 Pins
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD 1
V
VIL
Input Low Voltage
−0.5 1
0.8
V
µA
Input Leakage Current
During Reset: VIN = VDD
10
IIL
VIN = VSS
−150
µA
Min
Max
Unit
1. Not tested. Guaranteed by design.
14.2.5 Group 5
Pin List:
BADDR1,0, CFG1-0
These are CMOS input pins.
TABLE 14-9. DC Characteristics of Group 5 Pins
Symbol
Parameter
Conditions
VIH
Input High Voltage
2.5
VDD 1
V
VIL
Input Low Voltage
−0.5 1
0.8
V
µA
Input Leakage Current
During Reset: VIN = VDD
150
IIL
VIN = VSS
−10
µA
Min
Max
Unit
1. Not tested. Guaranteed by design.
14.2.6 Group 6
Pin List:
X1
TABLE 14-10. DC Characteristics of Group 6 Pins
Symbol
Parameter
Conditions
VIH
Input High Voltage
2.0
VDD 1
V
VIL
Input Low Voltage
-0.5 1
0.8
V
VIN = VDD
400
µA
VIN = VSS
−400
µA
IXLKG
X1 Leakage Current
1. Not tested. Guaranteed by design.
235
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Device Specifications
DC CHARACTERISTICS OF PINS, BY GROUP
14.2.7 Group 7
Pin List:
RI1, RI2, RING, SWITCH, XDCS
RING and XDCS are back-drive protected.
TABLE 14-11. DC Characteristics of Group 7 Pins
Symbol
Parameter
Conditions
Min
Max
VIH
Input High Voltage 1
2.0
VIL
Input Low Voltage 1
−0.5 1
VH
Hysteresis
IIL
Input Leakage Current
VBAT = 3 V
Unit
V
0.8
200
V
mV
VIN = VDD
10
µA
VIN = VSS
−102
µA
1. Not tested. Guaranteed by design.
2. SWITCH has an internal pull-up resistor of 1MΩ.
14.2.8 Group 8
Pin List:
D7-0
TABLE 14-12. DC Characteristics of Group 8 Input Pins
Symbol
Parameter
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD 1
V
VIL
Input Low Voltage
−0.5 1
0.8
V
VH
Hysteresis
250
mV
1. Not tested. Guaranteed by design.
TABLE 14-13. DC Characteristics of Group 8 Output Pins
Symbol
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Parameter
Conditions
Min
2.4
VOH
Output High Voltage
IOH = −15 mA
VOL
Output Low Voltage
IOL = 24 mA
236
Max
Unit
V
0.4
V
Device Specifications
DC CHARACTERISTICS OF PINS, BY GROUP
14.2.9 Group 9
Pin List:
CS2,1, CSOUT-NSC-Test,XD7,6, XD1,0
TABLE 14-14. DC Characteristics of Group 9 Input Pins
Symbol
Parameter
Conditions
Min
VIH
Input High Voltage 1
2.0
VIL
Input Low Voltage 1
−0.5 1
VH
Hysteresis
IIL
Input Leakage Current
VBAT = 3 V
Max
Unit
V
0.8
200
V
mV
VIN = VDD
10
µA
VIN = VSS
−102
µA
1. Not tested. Guaranteed by design.
2. For XD7,6 - IIL (Max) = −150 µA.
TABLE 14-15. DC Characteristics of Group 9 Output Pins
Symbol
Parameter
Conditions
Min
VOH
Output High Voltage
IOH = −6 mA
2.4
VOL
Output Low Voltage
IOL = 12 mA
Max
Unit
V
0.4
V
14.2.10 Group 10
Pin List:
GPIO37-30,27-26, 24-20,17-15,13,10, XD5-2, WDO
All GPIO pins are back-drive protected.
TABLE 14-16. DC Characteristics of Group 10 Input Pins
Symbol
Parameter
Conditions
Min
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
−0.5 1
VH
Hysteresis
IIL
Input Leakage Current
Max
VDD
1
0.8
250
Unit
V
V
mV
VIN = VDD
10
µA
VIN = VSS
−102
µA
Max
Unit
1. Not tested. Guaranteed by design.
2. For GPIO pins the IIL (Max) = −550 µA.
TABLE 14-17. DC Characteristics of Group 10 Output Pins
Symbol
Parameter
Conditions
Min
2.4
VOH
Output High Voltage
IOH = −2 mA 1
VOL
Output Low Voltage
IOL = 2 mA
V
0.4
V
1. IOH is valid for a GPIO signal only when it is not configured as open-drain.
237
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Device Specifications
DC CHARACTERISTICS OF PINS, BY GROUP
14.2.11 Group 11
Pin List:
KBCLK, KBDAT, MCLK, MDAT
Output from these signals is open-drain and cannot be forced high.
TABLE 14-18. DC Characteristics of Group 11 Input Pins
Symbol
Parameter
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD 1
V
VIL
Input Low Voltage
−0.5 1
0.8
V
VH
Hysteresis
250
mV
1. Not tested. Guaranteed by design.
TABLE 14-19. DC Characteristics of Group 11 Output Pins
Symbol
VOL
Parameter
Conditions
Output Low Voltage
IOL = 16 mA
Min
Max
Unit
0.4
V
Max
Unit
14.2.12 Group 12
Pin List:
CS0 (on pin 106), P12, P16, P17, P20, P21.
TABLE 14-20. DC Characteristics of Group 12 Input Pins
Symbol
Parameter
Min
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
−0.5 1
VH
Hysteresis
Max
VDD
Unit
1
V
0.8
V
250
mV
1. Not tested. Guaranteed by design.
TABLE 14-21. DC Characteristics of Group 12 Output Pins
Symbol
Parameter
Conditions
Min
2.4
VOH
Output High Voltage
IOH = −2 mA 1
VOL
Output Low Voltage
IOL = 2 mA
V
0.4
V
1. IOH is driven for a period of 3 KBC clock periods (of 8MHz, 12MHz or 16MHz) after the
low-to-high transition, on pins P12, P16 and P17. CS0, P20 and P21 are open-drain
output pins.
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238
Device Specifications
DC CHARACTERISTICS OF PINS, BY GROUP
14.2.13 Group 13
Pin List:
AFD, ASTRB, INIT, SLIN, STB.
Group 13 pins are back-drive protected.
TABLE 14-22. DC Characteristics of Group 13 Input Pins
Symbol
Parameter
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD 1
V
VIL
Input Low Voltage
−0.5 1
0.8
V
VH
Hysteresis
250
mV
1. Not tested. Guaranteed by design.
TABLE 14-23. DC Characteristics of Group 13 Output Pins
Symbol
Parameter
VOH
Output High Voltage 1
VOL
Output Low Voltage
Conditions
Min
IOH = −14 mA
2.4
Max
Unit
V
IOL = 14 mA
0.4
V
1. Output from STB, AFD, INIT, SLIN is open-drain in all SPP modes, except in SPP
Compatible mode when the setup mode is ECP-based (FIFO). (See TABLE 6-1 "Parallel Port Mode Selection" on page 138.) Otherwise, output from these signals is Level
2. External 4.7 KΩ pull-up resistors should be used.
14.2.14 Group 14
Pin List:
PD7-0
Group 14 pins are back-drive protected.
TABLE 14-24. DC Characteristics of Group 14 Input Pins
Symbol
Parameter
Min
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
−0.5 1
VH
Hysteresis
Max
VDD
Unit
1
V
0.8
V
250
mV
1. Not tested. Guaranteed by design.
TABLE 14-25. DC Characteristics of Group 14 Output Pins
Symbol
Parameter
VOH
Output High Voltage 1
VOL
Output Low Voltage
Conditions
Min
IOH = −14 mA
2.4
IOL = 14mA
Max
Unit
V
0.4
V
1. Output from PD7-0 is open-drain in all SPP modes, except in SPP Compatible mode
when the setup mode is ECP-based (FIFO) and bit 4 of the Control2 parallel port register is 1. (See TABLE 6-1 "Parallel Port Mode Selection" on page 138.) Otherwise,
output from these signals is Level 2. External 4.7 KΩ pull-up resistors should be used.
239
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Device Specifications
DC CHARACTERISTICS OF PINS, BY GROUP
14.2.15 Group 15
Pin List:
IRQ1,3,4,5,6,7,8,9,10,11,12,14,15.
TABLE 14-26. DC Characteristics of Group 15 Output Pins
Symbol
Parameter
Conditions
Min
2.4
VOH
Output High Voltage
IOH = −15 mA
VOL
Output Low Voltage
IOL = 24 mA
VH
Hysteresis
Max
Unit
V
0.4
250
V
mV
14.2.16 Group 16
Pin List:
DENSEL, DIR, DR1,0, HDSEL, MTR1,0, STEP, WDATA, WGATE.
TABLE 14-27. DC Characteristics of Group 16 Output Pins
Symbol
Parameter
Conditions
Min
VOH
Output High Voltage
IOH = −4 mA
2.4
VOL
Output Low Voltage1
IOL = 40 mA
Max
Unit
V
0.4
V
Max
Unit
1. Not 100% tested. Guaranteed by characterization.
14.2.17 Group 17
Pin List:
BOUT2,1, DTR2,1, IRSL2-0, RTS2,1, SOUT2,1.
TABLE 14-28. DC Characteristics of Group 17 Output Pins
Symbol
Parameter
Conditions
Min
VOH
Output High Voltage
IOH = −6 mA
2.4
VOL
Output Low Voltage
IOL = 12 mA
VH
Hysteresis
V
0.4
250
V
mV
14.2.18 Group 18
Pin List:
DRQ3-0
TABLE 14-29. DC Characteristics of Group 18 Output Pins
Symbol
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Parameter
Conditions
Min
2.4
VOH
Output High Voltage
IOH = −15 mA
VOL
Output Low Voltage
IOL = 24 mA
240
Max
Unit
V
0.4
V
Device Specifications
DC CHARACTERISTICS OF PINS, BY GROUP
14.2.19 Group 19
Pin List:
IRTX
TABLE 14-30. DC Characteristics of Group 19 Output Pins
Symbol
Parameter
Conditions
Min
VOH
Output High Voltage
IOH = −6mA
2.4
VOL
Output Low Voltage
IOL = 12 mA
Max
Unit
V
0.4
V
Max
Unit
14.2.20 Group 20
Pin List:
DRATE0
TABLE 14-31. DC Characteristics of Group 20 Output Pins
Symbol
Parameter
Conditions
Min
VOH
Output High Voltage
IOH = −6 mA
2.4
VOL
Output Low Voltage
IOL = 6 mA
V
0.4
V
Max
Unit
0.4
V
Max
Unit
14.2.21 Group 21
Pin List:
CS0 (on pin 68), CSOUT, POR
POR is back-drive protected.
TABLE 14-32. DC Characteristics of Group 21 Output Pins
Symbol
Parameter
Conditions
VOH
Output High Voltage
Open-Drain
VOL
Output Low Voltage
IOL = 2 mA
Min
14.2.22 Group 22
Pin List:
IOCHRDY, ZWS
TABLE 14-33. DC Characteristics of Group 22 Output Pins
Symbol
Parameter
Conditions
Min
2.4
VOH
Output High Voltage
IOH = −15 mA
VOL
Output Low Voltage
IOL = 24 mA
V
0.4
V
Max
Unit
0.4
V
14.2.23 Group 23
Pin List:
ONCTL, WRITE
This pin is back-drive protected and open-drain. VOH is not tested for ONCTL.
TABLE 14-34. DC Characteristics of Group 23 Output Pins
Symbol
VOL
Parameter
Conditions
Output Low Voltage
IOL = 14 mA
241
Min
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Device Specifications
DC CHARACTERISTICS OF PINS, BY GROUP
14.2.24 Group 24
Pin List:
GPIO11
This pin is back-drive protected.
TABLE 14-35. DC Characteristics of Group 24 Input Pins
Symbol
Parameter
Conditions
Min
Max
Unit
VIH
Input High Voltage
2.0
VDD 1
V
VIL
Input Low Voltage
−0.5 1
0.8
V
VH
Hysteresis
IIL
Input Leakage Current
250
mV
VIN = VDD
10
µA
VIN = VSS
−550
µA
Max
Unit
1. Not tested. Guaranteed by design.
TABLE 14-36. DC Characteristics of Group 24 Output Pins
Symbol
Parameter
Conditions
Min
2.4
VOH
Output High Voltage
IOH = −2 mA 1
VOL
Output Low Voltage
IOL = 14 mA
V
0.4
V
1. IOH is valid for a GPIO signal only when it is not configured as open-drain.
14.2.25 Group 25
Pin List:
GPIO25,14.
These pins are back-drive protected.
TABLE 14-37. DC Characteristics of Group 25 Input Pins
Symbol
Parameter
Conditions
Min
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
−0.5 1
VH
Hysteresis
IIL
Input Leakage Current
Max
VDD
1
0.8
250
Unit
V
V
mV
VIN = VDD
10
µA
VIN = VSS
−550
µA
Max
Unit
1. Not tested. Guaranteed by design.
TABLE 14-38. DC Characteristics of Group 25 Output Pins
Symbol
Parameter
Conditions
VOH
Output High Voltage
IOH = −2 mA
VOL
Output Low Voltage
IOL = 4 mA
Min
1
2.4
1. IOH is valid for a GPIO signal only when it is not configured as open-drain.
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242
V
0.4
V
Device Specifications
DC CHARACTERISTICS OF PINS, BY GROUP
14.2.26 Group 26
Pin List:
LED
TABLE 14-39. DC Characteristics of Group 26 Output Pins
Symbol
Parameter
Conditions
VOH
Output High Voltage
Open-Drain
VOL
Output Low Voltage
IOL = 16 mA
Min
Max
Unit
0.4
V
Min
Max
Unit
14.2.27 Group 27
Pin List:
IRRX2,1.
All pins are back-drive protected.
TABLE 14-40. DC Characteristics of Group 27 Pins
Symbol
Parameter
Conditions
VIH
Input High Voltage
2.0
VCCH 1
V
VIL
Input Low Voltage
−0.5 1
0.8
V
µA
Input Leakage Current
VIN = VDD
10
IIL
VIN = VSS
−10
µA
VH
Input Hysteresis
250
mV
1. Not tested. Guaranteed by design.
14.2.28 Group 28
Pin List:
PME2,1
All pins are back-drive protected.
TABLE 14-41. DC Characteristics of Group 28 Input Pins
Symbol
Parameter
Min
VIH
Input High Voltage
2.0
VIL
Input Low Voltage
−0.5 1
VH
Hysteresis
250
Max
VCCH
0.8
Unit
1
V
V
mV
1. Not tested. Guaranteed by design.
243
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Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3 AC ELECTRICAL CHARACTERISTICS
14.3.1 AC Test Conditions TA = 0 °C to 70 °C, VDD = 5.0 V ±10%
Load Circuit (Notes 1, 2, 3)
AC Testing Input, Output Waveform
VDD
S1
2.4
0.1 µf
2.0
0.8
0.4
Test Points
2.0
0.8
RL
Device
Under
Test
Input
Output
CL
FIGURE 14-1. AC Test Conditions, TA = 0 °C to 70 °C, VDD = 5.0 V ±10%
Notes:
1. CL = 100 pF, includes jig and scope capacitance.
2. S1 = Open for push-pull output pins.
S1 = VDD for high impedance to active low and active low to high impedance measurements.
S1 = GND for high impedance to active high and active high to high impedance measurements.
RL = 1.0KΩ for µP interface pins.
3. For the FDC open-drive interface pins, S1 = VDD and RL = 150Ω.
14.3.2 Clock Timing
TABLE 14-42. Clock TimingFor the 14.31818MHz clock, required tolerance is 200 ppm (max).
24MHz
Symbol
48MHz
Parameter
Min
Max
Min
Max
tCH
Clock High Pulse Width 1
16
8.4
nsec
tCL
Clock Low Pulse Width 1
16
8.4
nsec
tCP
Clock Period 1 2
40
43
20
21.5
Internal Clock Period (See TABLE 14-43.)
Data Rate Period (See TABLE 14-43.)
1. Not tested. Guaranteed by design.
2. For the 14.31818MHz clock, required tolerance is 200 ppm (max).
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Unit
244
nsec
Device Specifications
AC ELECTRICAL CHARACTERISTICS
TABLE 14-43. Nominal tICP, tDRP Values
MFM Data Rate
tDRP
tICP
Value
Unit
1 Mbps
1000
3 x tCP
125
nsec
500 Kbps
2000
3 x tCP
125
nsec
300 Kbps
3333
5 x tCP
208
nsec
250 Kbps
4000
6 x tCP
250
nsec
tCH
tCP
X1
tCL
FIGURE 14-2. Clock Timing
14.3.3 Microprocessor Interface Timing
TABLE 14-44. Microprocessor Interface Timing
Symbol
Parameter
Min
Max
Unit
tAR
Valid Address to Read Active
18
nsec
tAW
Valid Address to Write Active
18
nsec
tDH
Data Hold
0
nsec
tDS
Data Setup
18
nsec
tHZ
Read to Floating Data Bus 1
13
tPS
Port Setup
10
nsec
tRA
Address Hold from Inactive Read
0
nsec
tRCU
Read Cycle Update 1
45
nsec
tRD
Read Strobe Width
60
nsec
tRDH
Read Data Hold
10
nsec
tRI
Read Strobe to Clear FDC IRQ
55
nsec
tRVD
Active Read to Valid Data
55
nsec
tWA
Address Hold from Inactive Write
0
nsec
tWCU
Write Cycle Update 1
45
nsec
tWI
Write Strobe to Clear FDC IRQ
55
nsec
tWO
Write Data to Port Update
60
nsec
tWR
Write Strobe Width
60
nsec
RC
Read Cycle = tAR + tRD + tRCU 1
123
nsec
WC
Write Cycle = tAW + tWR + tWC 1
123
nsec
tWRR
RD low after WR high 1
80
nsec
25
nsec
1. Not tested. Guaranteed by design.
245
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Device Specifications
AC ELECTRICAL CHARACTERISTICS
AEN
A15-0,
DACK
Valid
Valid
RC
tAR
tRD
tRCU
RD
tRA
OR
tRVD
WR
Valid Data
D7-0
PME2,1
PD7-0, ERR,
PE, SLCT, ACK,
BUSY, GPIO17-10
GPIO27-20, GPIO37-30
tRDH
tHZ
tPS
FDC IRQ
tRI
FIGURE 14-3. Microprocessor Read Timing
AEN
A15-0,
DACK
Valid
tAW
Valid
WC
tWR
tWCU
WR
tWA
OR
RD
D7-0
Valid Data
tDS
SLIN, INIT, STB,
PD7-0, AFD
tDH
Previous State
tWI
FDC IRQ
FIGURE 14-4. Microprocessor Write Timing
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246
tWO
Device Specifications
AC ELECTRICAL CHARACTERISTICS
AEN
or CS
A15-0
WR
RD
tWRR
D7-0
(Input)
FIGURE 14-5. Read After Write Operation to All Registers and RAM
14.3.4 Baud Output Timing
TABLE 14-45. Baud Output Timing
Symbol
N
Parameter
Conditions
Min
Max
Unit
1
65535
nsec
CLK = 24 MHz/2, 100 pF load
56
nsec
CLK = 24 MHz/2, 100 pF load
56
nsec
Baud Divisor
1
tBHD
Baud Output Positive Edge Delay
tBLD
Baud Output Negative Edge Delay 1
1. Not tested. Guaranteed by design.
N
CLK
tBLD
BAUD OUT
(÷1)
tBHD
tBLD
BAUD OUT
(÷2)
tBHD
tBLD
tBHD
tBLD
tBHD
BAUD OUT
(÷3)
BAUD OUT
(÷N, N > 3)
FIGURE 14-6. Baud Output Timing
247
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Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.5 Transmitter Timing
TABLE 14-46. Transmitter Timing
Symbol
Parameter
Min
Max
Unit
tHR
Delay from WR (WR THR) to Reset IRQ
40
nsec
tIR
Delay from RD (RD IIR) to Reset IRQ (THRE)
55
nsec
tIRS
Delay from Initial IRQ Reset to Transmit Start 1
8
24
Baud Output Cycles
tSI
Delay from Initial Write to IRQ 1
16
24
Baud Output Cycles
tSTI
Delay from Start Bit to IRQ (THRE) 1
8
Baud Output Cycles
1. Not tested. Guaranteed by design.
Serial
Out
(SOUT)
START
DATA (5-8)
PARITY
STOP (1-2) START
tIRS
tSTI
Interrupt
(THRE)
tHR
tSI
tHR
WR
(WR THR)
Note 1
tIR
RD
(RD IIR)
Note 2
Notes:
1. See write cycle timing in FIGURE 14-4 "Microprocessor Write Timing" on page 246.
2. See read cycle timing in FIGURE 14-3 "Microprocessor Read Timing" on page 246.
FIGURE 14-7. Transmitter Timing
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248
Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.6 Receiver Timing
TABLE 14-47. Receiver Timing
Symbol
Parameter
Min
Max
Unit
tRAI1
Delay from Active Edge of RD to Reset IRQ
78
nsec
tRAI2
Delay from Active Edge of RD to Reset IRQ
78
nsec
tRAI3
Delay from Active Edge of RD to Reset IRQ
78
nsec
tRINT
Delay from Inactive Edge of RD (RD LSR) to Reset IRQ
55
nsec
tSCD
Delay from RCLK to Sample Time1
41
nsec
tSINT
Delay from Stop bit to Set Interrupt 2
2
Baud Output Cycles
1. This is internal timing and is therefore not tested.
2. Not tested. Guaranteed by design.
RCLK
tSCD
8 CLKS
Sample
CLK
SIN
DATA (5-8)
STOP
Sample Clock
RDR
Interrupt
tRAI1
tSINT
LSI
Interrupt
tRINT
RD
(RDRBR)
ACTIVE
RD
(RD LSR)
ACTIVE
FIGURE 14-8. Receiver Timing
249
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Device Specifications
AC ELECTRICAL CHARACTERISTICS
SIN
Data (5-8)
Stop
Sample Clock
Trigger
Level
Interrupt
Note
tSINT
LSI
Interrupt
tRAI2
(FIFO at
or above
Trigger
Level)
(FIFO
Below
Trigger
Level)
tRINT
RD
(RD LSR)
Active
RD
(RD RBR)
Active
Note:
If SCR0 = 1, then tSINT = 3 RCLKs. For a time-out interrupt, tSINT = 8 RCLKs.
FIGURE 14-9. FIFO Mode Receiver Timing
SIN
Stop
Sample Clock
Time-Out or
Trigger Level
Interrupt
(FIFO at
or above
Trigger
Level)
Note
tRAI3
tSINT
Top Byte of FIFO
LSI Interrupt
tRINT
tSINT
RD
(RD LSR)
RD
(RD RBR)
Active
Active
Active
Previous Byte
Read From FIFO
Note:
If SCR0 = 1, then tSINT = 3 RCLKs. For a time-out interrupt, tSINT = 8 RCLKs
FIGURE 14-10. Time-Out Receiver Timing
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250
(FIFO
Below
Trigger
Level)
Device Specifications
TABLE 14-48. UART, Sharp-IR, SIR and Consumer Remote Control Timing
Symbol
tBT
Parameter
Conditions
Min
Max
Unit
Transmitter
tBTN − 25 1
tBTN + 25
nsec
Receiver
tBTN − 2%
tBTN + 2%
nsec
tCWN + 25
nsec
Single Bit Time in UART and Sharp-IR
tCMW
tCMP
tSPW
Modulation Signal Pulse Width in
Sharp-IR and Consumer Remote
Control
Transmitter
Receiver
Modulation Signal Period in Sharp-IR
and Consumer Remote Control
SIR Signal Pulse Width
Transmitter
Receiver
tCWN − 25
2
500
nsec
tCPN − 25
tMMIN
4
3
tCPN + 25
nsec
tMMAX 4
nsec
3
1
Transmitter, 3
( /16) x tBTN − 15 1 ( /16) x tBTN + 15
Variable
nsec
Transmitter,
Fixed
1.48
µsec
Receiver
1
1.78
µsec
SDRT
SIR Data Rate Tolerance.
% of Nominal Data Rate.
Transmitter
± 0.87%
Receiver
± 2.0%
tSJT
SIR Leading Edge Jitter.
% of Nominal Bit Duration.
Transmitter
± 2.5%
Receiver
± 6.5%
1. tBTN is the nominal bit time in UART, Sharp-IR, SIR and Consumer Remote Control modes. It is determined by the setting of the Baud Generator Divisor registers.
2. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control
modes. It is determined by the MCPW field (bits 7-5) of the IRTXMC register at bank 7, offset 01h, and
the TXHSC bit (bit 2) of the RCCFG register at bank 7, offset 02h.
3. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It
is determined by the MCFR field (bits 4-0) of the IRTXMC register at offset 01h and the TXHSC bit (bit 2)
of the RCCFG register at offset 02h.
4. tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall
in order for the signal to be accepted by the receiver. These time values are determined by the content of
register IRRXDC at bank 7, offset 00h and the setting of the RXHSC bit (bit 5) of the RCCFG register at
bank 7, offset 02h.
tBT
UART
tCMW
tCMP
Sharp-IR
Consumer Remote Control
tSPW
SIR
FIGURE 14-11. UART, Sharp-IR, SIR and Consumer Remote Control Timing
251
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AC ELECTRICAL CHARACTERISTICS
14.3.7 UART, Sharp-IR, SIR and Consumer Remote Control Timing
Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.8 IRSLn Write Timing
TABLE 14-49. IRSLn Write Timing
Symbol
tWOD
Parameter
Min
IRSLn Output Delay from Write Inactive
Max
Unit
60
nsec
Max
Unit
WR
tWOD
IRSLn
FIGURE 14-12. IRSLn Write Timing
14.3.9 Modem Control Timing
TABLE 14-50. Modem Control Timing
Symbol
Parameter
Min
tHL
RI2,1 High to Low Transition
10
nsec
tLH
RI2,1 Low to High Transition
10
nsec
tMDO
Delay from WR (WR MCR) to Output
40
nsec
tRIM
Delay to Reset IRQ from RD (RD MSR)
78
nsec
tSIM
Delay to Set IRQ from Modem Input
40
nsec
WR
(WR MCR)
Note 1
tMDO
tMDO
RTS, DTR
CTS, DSR, DCD
INTERRUPT
tSIM
RD
(RD MSR)
Note 2
tRIM
tSIM
tRIM
tHL
RI
Notes:
1. See write cycle timing, FIGURE 14-4 "Microprocessor Write Timing" on page 246.
2. See read cycle timing, FIGURE 14-3 "Microprocessor Read Timing" on page 246.
FIGURE 14-13. Modem Control Timing
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252
tSIM
tLH
Device Specifications
TABLE 14-51. FDC DMA Timing
Symbol
Parameter
Min
Max
Unit
tKI
DACK Inactive Pulse Width
25
nsec
tKK
DACK Active Pulse Width
65
nsec
tKQ
DACK Active Edge to DRQ Inactive
tQK
DRQ to DACK Active Edge
65
nsec
10
nsec
1
tQP
DRQ Period (Except Non-Burst DMA)
tQQ
DRQ Inactive Non-Burst Pulse Width
300
tQR
DRQ to RD, WR Active
15
tQW
DRQ to End of RD, WR (DRQ Service Time)
(8 x tDRP) − (16 x tICP) 1 3
tQT
DRQ to TC Active (DRQ Service Time)
(8 x tDRP) − (16 x tICP) 1 3
tRQ
RD, WR Active Edge to DRQ Inactive 4
65
nsec
tTQ
TC Active Edge to DRQ Inactive
75
nsec
tTT
TC Active Pulse Width
8 x tDRP
400 2
nsec
nsec
50
nsec
1. tDRP and tICP are defined in TABLE 14-43 "Nominal tICP, tDRP Values" on page 245.
2. Only in case of pending DRQ.
3. Values shown are with the FIFO disabled, or with FIFO enabled and THRESH = 0. For nonzero values
of THRESH, add (THRESH x 8 x tDRP) to the values shown.
4. The active edge of RD or WR and TC is recognized only when DACK is active.
tQP
tQQ
DRQ
tQK
tKQ
tKK
DACK
tKI
tQW
RD, WR
tQR
tRQ
tQT
TC
tTQ
tTT
FIGURE 14-14. FDC DMA Timing
253
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AC ELECTRICAL CHARACTERISTICS
14.3.10 DMA Timing
Device Specifications
AC ELECTRICAL CHARACTERISTICS
TABLE 14-52. ECP DMA Timing
Symbol
Parameter
tKIP
DACK Inactive Pulse Width
tKKP
DACK Active Pulse Width
Min
Max
Unit
25
nsec
65
nsec
1 2
tKQP
DACK Active Edge to DRQ Inactive
tQKP
DRQ to DACK Active Edge
10
tQPP
DRQ Period
330
65 + (6 x 32 x tCP)
nsec
nsec
nsec
3
tQQP
DRQ Inactive Non-Burst Pulse Width
300
tQRP
DRQ to RD, WR Active
15
tRQP
RD, WR Active Edge to DRQ Inactive 4
65
nsec
tTQP
TC Active Edge to DRQ Inactive
75
nsec
tTT
TC Active Pulse Width
400
nsec
nsec
50
nsec
1. One DMA transaction takes six clock cycles.
2. tCP is defined in TABLE 14-42 "Clock TimingFor the 14.31818MHz clock, required tolerance is 200 ppm
(max)." on page 244.
3. Only in case of pending DRQ.
4. The active edge of RD or WR and TC is recognized only when DACK is active.
tQPP
tQQP
DRQ
tQKP
tKQP
tKKP
DACK
tKIP
RD, WR
tQRP
tRQP
tTQP
TC
tTT
FIGURE 14-15. ECP DMA Timing
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254
Device Specifications
AC ELECTRICAL CHARACTERISTICS
TABLE 14-53. UART2 DMA Timing
Symbol
Parameter
Min
Max
Unit
tACH
AEN Hold from RD, WR Inactive
5
nsec
tACS
AEN Signal Setup
15
nsec
tDCH
DACK Hold from RD, WR Inactive
0
nsec
tDCS
DACK Signal Setup
15
nsec
tDSW
RD, WR Pulse Width
60
tRQ
DRQ Inactive from RD, WR Active
tTCH
TC Hold from RD, WR Inactive
2
nsec
tTCS
TC Signal Setup
60
nsec
1000
nsec
60
nsec
DRQ
AEN
tACH
tDCS
tDCH
DACK
tDSW
RD, WR
tACS
tRQ
TC
tTCS
tTCH
FIGURE 14-16. UART2 DMA Timing
255
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Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.11 Reset Timing
TABLE 14-54. Reset Timing
Symbol
Parameter
Min
Reset Width 1
tRW
tSRC
Reset to Control Inactive
300
tRW
MR
tSRC
DRQ,
INT,
WGATE (Note)
Note:
In PC-AT mode, the DRQ and IRQ signals of the FDC are in TRI-STATE after time tSRC.
FIGURE 14-17. Reset Timing
256
Unit
µsec
100
2
1. The software reset pulse width is 100 nsec.
2. Not tested. Guaranteed by design.
www.national.com
Max
nsec
Device Specifications
TABLE 14-55. Write Data Timing
Symbol
Parameter
Min
Max
Unit
tHDH
HDSEL Hold from WGATE Inactive1
750
µsec
tHDS
HDSEL Setup to WGATE Activea
100
µsec
tWDW
Write Data Pulse Width
See TABLE 14-56
1. Not tested. Guaranteed by design.
TABLE 14-56. Write Data Timing – Minimum tWDW Values
Data Rate
tDRP
tWDW
tWDW Value
Unit
1 Mbps
1000
2 x tICP 1
250
nsec
500 Kbps
2000
2 x tICP 1
250
nsec
300 Kbps
3333
2 x tICP 1
375
nsec
250 Kbps
4000
2 x tICP 1
500
nsec
1. tICP is the internal clock period defined in TABLE 14-43 "Nominal tICP, tDRP
Values" on page 245.
HDSEL
WGATE
tHDS
tHDH
tWDW
WDATA
FIGURE 14-18. Write Data Timing
257
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AC ELECTRICAL CHARACTERISTICS
14.3.12 Write Data Timing
Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.13 Drive Control Timing
TABLE 14-57. Drive Control Timing
Symbol
tDRV
Parameter
Min
DR1,0 and MTR1,0 from End of WR
Max
Unit
110
nsec
6
µsec
Index Pulse Width
100
nsec
tSTD
DIR Hold from STEP Inactive
tSTR
msec
tSTP
STEP Active High Pulse Width
8
µsec
tSTR
STEP Rate Time (See TABLE 5-26.)
1
msec
tDST
DIR Setup to STEP Active
tIW
1
1. Not tested. Guaranteed by design.
WR
tDRV
tDRV
DR1,0
MTR1,0
DIR
tDST
tSTD
STEP
tSTP
tSTR
INDEX
tIW
FIGURE 14-19. Drive Control Timing
14.3.14 Read Data Timing
TABLE 14-58. Read Data Timing
Parameter
Symbol
Read Data Pulse Width
tRDW
Min
50
RDATA
tRDW
FIGURE 14-20. Read Data Timing
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258
Max
Unit
nsec
Device Specifications
TABLE 14-59. Standard Parallel Port Timing
Symbol
Parameter
Conditions
Typ
Max
Unit
tPDH
Port Data Hold
These times are system dependent and are
therefore not tested.
500
nsec
tPDS
Port Data Setup
These times are system dependent and are
therefore not tested.
500
nsec
tPILa
Port Active Low Interrupt, Active
33
nsec
tPILia
Port Active Low Interrupt, Inactive
33
nsec
tPIHa
Port Active High Interrupt, Active
33
nsec
tPIHia
Port Active High Interrupt, Inactive
33
nsec
tPIz
Port Active High Interrupt, TRISTATE
33
nsec
tSW
Strobe Width
These times are system dependent and are
therefore not tested.
500
nsec
ACK
IRQ
tPILa
tPILia
FIGURE 14-21. Parallel Port Interrupt Timing (Compatible Mode)
ACK
IRQ
tPIHia
tPIHa
tPIHa
tPIz
(TRI-STATE)
RD STR
WR CTR4 = 0
FIGURE 14-22. Parallel Port Interrupt Timing (Extended Mode)
BUSY
ACK
tPDH
tPDS
PD7-0
tSW
STB
FIGURE 14-23. Typical Parallel Port Data Exchange
259
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AC ELECTRICAL CHARACTERISTICS
14.3.15 Parallel Port Timing
Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.16 Enhanced Parallel Port 1.7 Timing
TABLE 14-60. Enhanced Parallel Port 1.7 Timing Parameters
Symbol
tWW17
Parameter
Min
WRITE Active or Inactive from WR Active or Inactive
1
Max
Unit
45
nsec
45
nsec
tWST17
DSTRB or ASTRB Active or Inactive from WR or RD Active or Inactive
tWEST17
DSTRB or ASTRB Active after WRITE Becomes Active
0
nsec
tWPD17h
PD7-0 Hold after WRITE Becomes Inactive
50
nsec
tHRW17
IOCHRDY Active or Inactive after WAIT Becomes Active or Inactive
40
nsec
tWPDS17
PD7-0 Valid after WRITE Becomes Active2
15
nsec
tEPDW17
PD7-0 Valid Width
80
nsec
tEPD17h
PD7-0 Hold after DSTRB or ASTRB Becomes Inactive
0
nsec
tZWS17a
ZWS Valid after WR or RD Active
tZWS17h
ZWS Hold after WR or RD Inactive
45
nsec
0
nsec
1. The PC87307VUL design guarantees that WRITE will not change from low to high before DSTRB,
or ASTRB, goes from low to high.
2. D7-0 is stable 15 nsec before WR becomes active.
WR
RD
tZWS17h
tZWS17a
tZWS17h
ZWS
tZWS17a
Valid
D7-0
tWW17
tWW17
WRITE
tWEST17
DSTRB
or
ASTRB
tWST17
tWST17
tWST17
tWST17
tEPD17h
Valid
PD7-0
tWPDS17
tHRW17
tEPDW17
tWPD17h
WAIT
tHRW17
tHRW17
IOCHRDY
FIGURE 14-24. Enhanced Parallel Port 1.7 Timing
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260
Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.17 Enhanced Parallel Port 1.9 Timing
TABLE 14-61. Enhanced Parallel Port 1.9 Timing Parameters
Symbol
Parameter
Min
Max
Unit
tWW119a
WRITE Active from WR Active or WAIT Low 1
45
nsec
tWW19ia
WRITE Inactive from WAIT Low
45
nsec
65
nsec
45
nsec
tWST19a
DSTRB or ASTRB Active from WR or RD Active or WAIT Low1 2
tWST19ia
DSTRB or ASTRB Inactive from WR or RD High
tWEST19
DSTRB or ASTRB Active after WRITE Active
10
nsec
tWPD19h
PD7-0 Hold after WRITE Inactive
0
nsec
tHRW19
IOCHRDY Active after WR or RD Active or Inactive after WAIT High
40
nsec
tWPDS19
PD7-0 Valid after WRITE Active 3
15
nsec
tEPDW19
PD7-0 Valid Width
80
nsec
tEPD19h
PD7-0 Hold after DSTRB or ASTRB Inactive
0
nsec
tZWS19a
ZWS Valid after WR or RD Active
tZWS19h
ZWS Hold after WR or RD Inactive
45
nsec
0
nsec
1. When WAIT is low, tWST19a and tWW19a are measured after WR or RD becomes active; else
tWST19a and tWW19a are measured after WAIT becomes low.
2. The PC87307VUL design guarantees that WRITE will not change from low to high before
DSTRB, or ASTRB, goes from low to high.
3. D7-0 is stable 15 nsec before WR becomes active.
WR
tWW19a
{Note a}
RD
tZWS19h
tZWS19a
tZWS19h
ZWS
tZWS19a
Valid
D7-0
tWW19a
WRITE
tWST19ia
tWST19a
tWST19a
{Note a}
DSTRB
or
ASTRB
tWEST19
tWST19ia
{Note a}
tWPD19h
tWST19a
tEPD19h
tWST19a
Valid
PD7-0
WAIT
tEPDW19
tWW19ia
tWPDS19
tHRW19
tHRW19
tHRW19
tHRW19
IOCHRDY
FIGURE 14-25. Enhanced Parallel Port 1.9 Timing
261
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Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.18 Extended Capabilities Port (ECP) Timing
TABLE 14-62. Extended Capabilities Port (ECP) Timing – Forward
Symbol
Parameter
Min
Max
Unit
tECDSF
Data Setup before STB Active
0
nsec
tECDHF
Data Hold after BUSY Inactive
0
nsec
tECLHF
BUSY Setup after Strobe Active
75
nsec
tECHHF
STB Inactive after BUSY Active
0
1
sec
tECHLF
BUSY Setup after STB Active
0
35
msec
tECLLF
Strobe Active after BUSY Inactive
0
nsec
tECDHF
PD7-0
AFD
tECDSF
STB
tECLLF
tECLHF
tECHLF
BUSY
tECHHF
FIGURE 14-26. ECP Parallel Port Forward Timing Diagram
TABLE 14-63. Extended Capabilities Port (ECP) Timing – Backward
Symbol
Parameter
Min
Max
tECDSB
Data Setup before ACK Active
0
nsec
tECDHB
Data Hold after AFD Active
0
nsec
tECLHB
BUSY Setup after ACK Active
75
nsec
tECHHB
Strobe Inactive after AFD Inactive
0
1
sec
tECHLB
BUSY Setup after ACK Active
0
35
msec
tECLLB
Strobe Active after AFD Active
0
nsec
tECDHB
PD7-0
BUSY
tECDSB
ACK
tECLLB
tECLHB
tECHLB
AFD
tECHHB
FIGURE 14-27. ECP Parallel Port Backward Timing Diagram
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Unit
262
Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.19 GPIO Write Timing
TABLE 14-64. GPIO Write Timing
Symbol
tWGO
Parameter
Min
Write Data to GPIO Update
Max
Unit
300 1
nsec
1. Refer to Section 14.3.3 "Microprocessor Interface Timing" on page 245 for read
timing.
Valid
A15-0
IOW
D7-0
Valid
GPIO17-10
GPIO27-20
Previous State
Valid
tWGO
FIGURE 14-28. GPIO Write Timing Diagram
14.3.20 RTC Timing
TABLE 14-65. RTC Timing
Symbol
Parameter
Min
Max
Unit
tRW
IOR to IRQ TRI-STATE 1
36
nsec
tRCI
MR to IRQ TRI-STATE 1
25
nsec
tRCL
MR High Time
100
µsec
tVMR
VDD (4.5V) to MR 1
10
msec
1. Not tested. Guaranteed by design.
RD
tRW
MR
tRCL
tRCI
IRQ
FIGURE 14-29. IRQ Release Delay
VDD
tVMR
MR
FIGURE 14-30. Master Reset (MR) Timing
263
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Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.21 APC Timing
TABLE 14-66. SWITCH Trigger and ONCTL Timing
Symbol
Parameter
Min
Max
Unit
tSWP
SWITCH Pulse Width1
16
tSWE
Delay from SWITCH Events to ONCTL, and from SWITCH Off Event to POR1
14
16
msec
tPORW
POR Pulse Width (Edge Mode)
15
46
µsec
tPRL
Delay from APCR1 Write to POR Inactive (Level Mode)1
25
nsec
msec
1. Not tested. Guaranteed by design.
:
VOH
SWITCH
VOL
tSWP
tSWP
tSWE
tSWE
HI-Z
ONCTL
VOL
POR
Edge:
tPORW
HI-Z/VOH
VOL
WR
VOH
Level:
tPRL
VOL
FIGURE 14-31. SWITCH Trigger and ONCTL Timing
TABLE 14-67. PME and ONCTL/POR/SCI Timing
Symbol
Parameter
Min
Max
Unit
tPM
Power Management Event to ONCTL/POR(Level)/SCI asserted
45
nsec
tPM1
Power Management Event to POR(Edge) asserted
50
µsec
Power
Management
Event (PME)
ONCTL
SCI
POR(Level)
POR(Edge)
tPM
HI-Z
VOL
tPM1
HI-Z
VOL
Power Management Event = GPIO10, GPIO12, GPIO13, IRRX1, IRRX2, P12, PME1, PME2 Events.
RI1,2 Events for ONCTL and SWITCH Off Event for POR only
FIGURE 14-32. PME and ONCTL/POR/SCI Timing
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264
Device Specifications
Symbol
Parameter
tRIO
Delay from RI2,1 to ONCTL
tRIW
RI width
Min
10
Unit
25
nsec
-
nsec
Max
Unit
25
nsec
0.190
sec
tRIW
VOH
RI2,1
Max
VOL
tRIO
HI-Z
ONCTL
VOL
FIGURE 14-33. RI Trigger and ONCTL Timing
TABLE 14-69. RING Trigger and ONCTL Timing
Symbol
Parameter
Min
tRPO
Delay from RING Pulse to ONCTL
tRTO
Delay from RING Pulse Train to ONCTL 1
tRINW
0.125
RING Width (High and Low Time), Single Pulse Mode
10
nsec
RING Width (High and Low Time), Pulse Train Mode
50
µsec
1. Not tested. Guaranteed by design.
RING
VOH
VOL
tRINW
tRINW
.
tRTO
ONCTL
tRPO
HI-Z
VOL
FIGURE 14-34. RING Trigger and ONCTL Timing
265
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AC ELECTRICAL CHARACTERISTICS
TABLE 14-68. RI Trigger and ONCTL Timing
Device Specifications
AC ELECTRICAL CHARACTERISTICS
TABLE 14-70. VDD and ONCTL Timing
Symbol
Parameter
tVOFF
Min
VDD off to ONCTL deasserted (When bit 4 of APCR7 register is 0)
Max
500
Unit
msec
@ VDD = 4.0 V
tVOFF
600
VDD off to ONCTL deasserted (When bit 4 of APCR7 register is 0)
msec
@ VDD =0.5 V
tONH
ONCTL High time (When bit 4 of APCR7 register is 0)
0.9
sec
VDD
tVOFF
HI-Z
ONCTL VOL
VDD
tVOFF
HI-Z
ONCTL VOL
ONCTL
HI-Z
VOL
tONH
FIGURE 14-35. VDD and ONCTL Timing
TABLE 14-71. SMI_CMD/PM1_CNT_LOW/PM1_CNT_HIGH register’s write to POR Timing
Symbol
Parameter
Min
Delay from SMI_CMD/PM1_CNT_LOW/PM1_CNT_HIGH register’s
write to POR asserted
tWRP
Max
Unit
50
nsec
VOH
WR
VOL
tWRP
HI-Z/VOH
POR
VOL
FIGURE 14-36. SMI_CMD/PM1_CNT_LOW/PM1_CNT_HIGH Register Write to POR Timing
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266
Device Specifications
AC ELECTRICAL CHARACTERISTICS
14.3.22 Chip Select Timing
TABLE 14-72. Chip Select Timing
Symbol
Parameter
Min
Max
Unit
tCE
Delay from Command to Enable Chip Select
0
25
nsec
tCD
Delay from Command to Disable Chip Select
0
25
nsec
A15-1, AEN
WR, RD
tCE
tCD
CS1,0
FIGURE 14-37. Chip Select Timing
14.3.23 LED Timing
TABLE 14-73. LED Timing
Symbol
tWRL
Parameter
Write-strobe to valid LED
Min
Max
Unit
0
80
nsec
Cycle time: 1 sec +/- 0.1 sec, 40% -60% duty cycle
WR (APCR4
register,
Bank 2 of
RTC and APC)
LED
tWRL
HI-Z
VOL
FIGURE 14-38. LED Timing
267
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Glossary
Glossary
Glossary
CFIFO
11-bit address mode
In this mode, the PC87308VUL decodes address
lines A0-A10, A11-A15 are masked to 1, and
UART2 is a fully featured 16550 UART. The mode
is configured during reset, via CFG0 strap pin.
16-bit address mode
In this mode, the PC87308VUL decodes address
lines A0-A15 and UART2 is a 16550 UART with
SIN2/SOUT2 interface signals only. The mode is
configured during reset, via CFG0 strap pin.
Parallel port data FIFO in Extended Capabilities
Port (ECP) mode 010. (Logical device 4, offset
400h.)
CNFGA and CNFGB
Configuration registers A and B for the parallel port
in Extended Capabilities Port (ECP) mode 111.
(Logical device 4, offsets 400h and 401h, respectively.)
Confg0
See PP Confg0.
ABGDH and ABGDL
Alternate Baud rate Generator Divisor register
(High and Low bytes) for the UART2. (Logical device 5, bank 2, offsets 01h and 00h, respectively.)
Consumer Remote Control Mode
This UART mode supports all four protocols currently used in remote-controlled home entertainment equipment. Also called TV-Remote mode.
ACPI
Control0, Control2 and Control4
Internal configuration registers of the parallel port
in Extended Capabilities Port (ECP) modes. (Logical device 4, second level offsets 00h, 02h and
04h.)
Advanced Configuration and Power Interface.
ADDR
Address Register of the parallel port in EPP
modes. (Logical device 4, offset 03h.)
CSN
Card Select Number register - an 8-bit register with
a unique value that identifies an ISA card.
AFIFO
Address FIFO for the parallel port in Extended Capabilities Port (ECP) mode 011. (Logical device 4,
offset 000h.)
APC
Advanced Power Control.
CRA, CRB, CRC, CRD
Control Registers of the Real-Time Clock (RTC).
(Logical device 2, offsets 0Ah, 0Bh, 0Ch and 0Dh,
respectively.)
CTR
APCR1 and APCR2
APC control registers 1 and 2. (Logical device 2,
offsets 40h and 41h, respectively.)
APSR
Control Register of the parallel port in SPP modes.
(Logical device 4, offset 02h.)
DASK-IR
Digital Amplitude Shift Keying Infrared.
Data
Advanced Power Control (APC) status register.
(Logical device 2, offset 42h.)
ASCR
Auxiliary Status and Control Register for the
UART2 in Extended operation modes. (Logical device 5, bank 0, offset 07h.)
ASK-IR
Amplitude Shift Keying Infrared.
BGD(H) and BGD(L)
Baud rate Generator Divisor buffer (High and Low
bytes) for the UART2. (Logical devices 5, bank 1,
offsets 01h and 00h, respectively.)
The Data register contains the data in the register
indicated by the corresponding Index register.
DATA0, DATA1, DATA2 and DATA3
Data Registers of the parallel port in EPP modes.
(Logical device 4, offsets 04h, 05h, 06h and 07h,
respectively.)
DATAR
Data Register for the parallel port in Extended Capability Port (ECP) modes 000 and 001. (Logical
device 4, offset 000h.)
DCR
Data Control Register for the parallel port in Extended Capabilities Port (ECP) modes. (Logical device 4, offset 002h.)
BSR
Bank Selection Register for the UART2, when enabled, i.e., when bit 7 of this register is 1. (Logical
device 5, all banks, offset 03h.)
CCR
Configuration Control Register of the Floppy Disk
Controller (FDC) for write operations. (Logical device 3, offset 07h.)
Device
Any circuit that performs a specific function, such
as a parallel port.
DFIFO
ECP Data FIFO in Extended Capabilities Port
(ECP) mode 011. (Logical device 4, offset 400h.)
DID
Device ID register for the UART2. (Logical device 5,
bank 3, offset 00h.)
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Glossary
FER1 and FER2
Function Enable Registers of the Power Management device (Logical device 8, offsets 00h and 01h,
respectively.).
DIR
Digital Input Register of the Floppy Disk Controller
(FDC) for read operations. (Logical device 3, offset
07h.)
FIFO
DOR
Data register (FIFO queue) of the Floppy Disk Controller (FDC). (Logical device 3, offset 05h.)
Digital Output Register of the Floppy Disk Controller (FDC). (Logical device 3, offset 2h.)
GPIO
DSR
General Purpose I/O - I/O pins available for general
use.
Data rate Select Register of the Floppy Disk Controller (FDC) for write operations (logical device 3,
offset 4h) and the Data Status Register in Extended Capabilities Port (ECP) modes (logical device 4,
offset 001h).
IER
The Interrupt Enable Register for UART1 (logical
device 6, offset 01h, divisor latch registers not accessible, bit 7 of LCR = 0) and for the UART2 (logical device 5, bank 0, offset 01h).
DTR
Data Register of the parallel port in SPP or EPP
modes. (Logical device 4, offset 00h.)
IIR
EAR
The Interrupt Identification Register for UART1.
(Logical device 6, offset 02h.)
Extended Auxiliary Register of the parallel port in
Extended Capabilities Port (ECP) modes. (Logical
device 4, offset 405h.)
Index
Extended Capabilities Port.
IR
Extended Control Register for the parallel port in
Extended Capabilities Port (ECP) modes. (Logical
device 4, offset 402h.)
IRCFG1, IRCFG3 and IRCFG4
Infrared module Configuration registers for the
UART2. (Logical device 5, bank 7, offsets 04h, 06h
and 07h, respectively.)
Extended Data Register for the parallel port in extended Capabilities Port (ECP) modes. (Logical device 4, offset 404h.).
IRCR1, IRCR2 and IRCR3
Infrared Module Control Registers 1, 2 and 3 for
the UART2. (Logical device 5. IRCR1 is in bank 4,
offset 02h; IRCR2 is in bank 5, offset 04h; IRCR3 is
in bank 6, offset 00h.)
The Index register is a pointer that is used to address other registers.
ECP
InfraRed.
ECR
EDR
EIR
Two expressions:
1. Extended Index Register of the parallel port Extended Capabilities Port (ECP) modes (logical device 4, offset 403h).
2. Event Identification Register for UART1 (logical device 6, offset 01h, divisor latch registers not accessible, bit 7 of LCR = 0) and for the UART2 for read
cycles (logical device 5, bank 0, offset 02h).
IrDA
Infrared Data Association.
IrDA-2 mode
In this mode, the PC87308VUL provides the Infrared Data Association standard compliant interface.
IRQ
Interrupt Request.
Extended UART Operation Mode
This UART operation mode supports standard
16450 and 16550A UART operations plus additional interrupts and DMA features. It does not include
infrared or Consumer Remote Control modes.
IRRXDC
Infrared Receiver Demodulator Control register for
the UART2. (Logical device 5, bank 7, offset 00h.)
IRTXMC
Infrared Transmitter Modulator Control register for
the UART2. (Logical device 5, bank 7, offset 01h.)
EPP
Enhanced Parallel Port.
ISA
EXCR1 and EXCR2
Extended Control Registers 1 and 2 for the UART2.
(Logical device 5, bank 2, offsets 02h and 04h, respectively.)
Industry Standard Architecture for the PC bus.
LCR
Line Control Register for UART1 (logical device 6,
offset 03h) and for the UART2 when enabled, i.e.,
when bit 7 of this register is 0 (logical device 5, all
banks, offset 03h).
FCR
The FIFO Control Register for UART1 (logical device 6, offset 02h) and for the UART2 for write cycles (logical device 5, bank 0, offset 02h).
Legacy
Usually refers to older devices or systems that are
not Plug and Play compatible.
FDC
Floppy Disk Controller.
FDD
Floppy Disk Drive.
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269
Glossary
PnP
Legacy Mode
In this mode, the interrupts and the base addresses
of the FDC, UARTs, KBC, RTC and the parallel
port of the PC87308VUL are configured as in earlier SuperI/O chips.
Sometimes used to indicate Plug and Play.
PnP Mode
In this mode, the interrupts, the DMA channels and
the base address of the FDC, UARTs, KBC, RTC,
GPIO, APC and the Parallel Port of the
PC87308VUL are fully Plug and Play.
LFSR
The Linear Feedback Shift Register. In Plug and
Play mode, this register is used to prepare the chip
for operation in Plug and Play (PnP) mode.
PP Confg0
Internal configuration register of the Parallel Port in
Extended Capabilities Port (ECP) modes. (Logical
device 4, second level offset 05h.)
LSB
Least Significant Byte or Bit.
Precompensation
Also called write precompensation, is a way of preconditioning the WDATA output signal to adjust for
the effects of bit shift on the data as it is written to
the disk surface.
LSR
Line Status Register for UART1 (logical device 6,
offset 05h) and for the UART2 in Non-Extended
modes only (logical device 5, bank 0, offset 05h).
MCR
RBR
Modem Control Register for UART1 (logical device
6, offset 04h) and for the UART2 (logical device 5,
bank 0, offset 04h).
Receiver Buffer Register for UART1, read operations only (logical device 6, offset 00h, divisor latch
registers not accessible, bit 7 of LCR = 0).
MSB
RCCFG
Consumer Remote Control Configuration register
for the UART2. (Logical device 5, bank 7, offset
02h.)
Most Significant Byte or Bit.
MSR
Two expressions:
1. Main Status Register of the Floppy Disk Controller
(FDC) (logical device 3, offset 4h).
2. Modem Status Register for UART1 for read operations (logical device 6, offset 06h) and for the
UART2 (logical device 5, bank 0, offset 06h).
RLC
Run Length Count byte for parallel ports.
RLE
Run Length Expander for parallel ports.
RLR
Non-Extended UART Operation Modes
These UART operation modes support only UART
operations that are standard for 15450 or 16550A
devices.
RAM Lock Register for Advanced Power Control
(APC). (Logical device 2, offset 47h.)
RSR
Internal Receiver Shift Register for UART1.
NVM
RTC
Non-volatile memory.
Real-Time Clock.
P_BGDH and P_BGDL
Pipeline Baud rate Generator Divisor buffer (High
and Low bytes) for UARTs. (Logical devices 5 and
6, bank 5, offsets 01h and 00h, respectively.)
RXDR
Receiver Data Register for read cycles for the
UART2. (Logical device 5, bank 0, offset 00h.)
PIO
RXFLV
Programmable Input/Output.
Reception FIFO Level for the UART2. (Logical device 5, bank 2, offset 07h.)
P_MDR
Pipeline Mode Register for UARTs. (Logical devices 5 and 6, bank 5, offset 02h.)
SCI
System Control Interrupt.
Plug and Play
A design philosophy and a set of specifications that
describe hardware and software changes to the PC
and its peripherals that automatically identify and
arbitrate resource requirements among all devices
and buses on the system. Plug and Play is sometimes abbreviated as PnP.
SCR
Scratch Register for UART1 (logical device 6, offset
07h) and for the UART2 in UART operation mode
(logical device 5, bank 0, offset 07h).
SH_FCR
Shadow of the FIFO Control Register (FCR) for the
UART2 for read operations. (Logical device 5, bank
3, offset 02h.)
PM
Power Management.
SH_LCR
Shadow of the Line Control Register (LCR) for the
UART2 for read operations. (Logical device 5, bank
3, offset 01h.)
PME
Power Management Event.
PMC1, PMC2 and PMC3
Power Management Control registers of logical device 8 at offsets 02h, 03h and 04h, respectively.
Sharp IR
Sharp Infrared.
270
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Glossary
Sharp IR Mode
In this mode, the PC87308VUL supports a Sharp
Infrared interface.
WDST
SIO
WDTO
WATCHDOG Status register for Power Management. (Logical device 8 at offset 07h.)
WATCHDOG Time-Out register for Power Management. (Logical device 8 at offset 05h.)
SuperI/O, sometimes used to refer to a chip that
has SuperI/O capabilities, e.g., the PC87317VUL
chip.
XDB
SIR
X-Bus Data Buffer.
Serial Infrared.
SIR_PW
SIR Pulse Width control for the UART2. (Logical
device 5, bank 6, offset 02h.)
SPP
The Standard Parallel Port configuration of the Parallel Port device (Logical device 4) supports the
Compatible SPP mode and the Extended PP
mode.
SRA and SRB
Status Registers A and B of the Floppy Disk Controller (FDC). (Logical device 3, offsets 0h and 1h,
respectively.)
ST0, ST1, ST2 and ST3
Status registers 0, 1, 2 and 3 of the Floppy Disk
Controller (FDC).
STR
Status Register of the parallel port in SPP modes.
(Logical device 4, offset 01h.)
TDR
Tape Drive Register of the Floppy Disk Controller
(FDC). (Logical device 3, offset 03h.)
THR
Transmitter Holding Register for UART1 write operations only. (Logical device 6, offset 00h, divisor
latch registers not accessible, bit 7 of LCR = 0.)
TFIFO
Test FIFO for the parallel port in Extended Capabilities Port (ECP) mode 110. (Logical device 4, offset
400h.)
TSR
Internal Transmitter Shift Register for UART1.
TV-Remote Mode
See Consumer Remote Control mode.
TXDR
Transmitter Data Register for write cycles for the
UART2. (Logical device 5, bank 0, offset 00h.)
TXFLV
Transmission FIFO Level for the UART2. (Logical
devices 5, bank 2, offset 06h.)
UART
Universal Asynchronous Receiver Transmitter. The
PC87308VUL supports two UARTs, UART1 and
UART2. They are identical in UART modes; the
UART2 includes infrared and DMA support.
WDCF
WATCHDOG Configuration register for Power Management module. (Logical device 8 at offset 06h.)
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271
PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender
PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender
Physical Dimensions
inches (millimeters)
PlasticQuad Flatpack (PQFP), EIAJ
Order Number PC87317VUL/PC97317VUL
NS Package Number VUL160A
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