CY22800 Universal Programmable Clock Generator (UPCG) Features Benefits • Spread Spectrum, VCXO, and Frequency Select • Input frequency range: • Make inventory of only one device, CY22800, to use in various applications such as HDTV, STB, DVDR, etc. • Multiple predefined configurations that can be programmed into a single chip • Eliminates the need for expensive and difficult to use higher-order crystal • High-performance PLL tailored for multiple applications • Meets critical timing requirements in complex system designs • Enables application compatibility • Allows up to three different frequency selects — Crystal: 8–30 MHz — CLKIN: 0.5–100 MHz • Output frequency: • • • • — LVCMOS: 1–200 MHz Integrated phase-locked loop Low jitter, high accuracy outputs 3.3V operation 8-pin SOIC package Logic Block Diagram Pin Configuration CY22800 8-pin SOIC XIN/CLKIN OSC Q XOUT CLKC Φ OUTPUT DIVIDER VCO VCXO CLKB P FS2 CLKA PLL FS1 FS0 XIN/CLKIN 1 8 XOUT VDD FS0/VCXO 2 7 3 6 CLKC/FS2/VSS CLKA/FS0 VSS 4 5 CLKB/FS1 (with modulation control) VDD VSS Pin Description Name XIN Pin Number 1 Description Reference Input; Crystal or External Clock VDD 2 3.3V Voltage Supply FS0/VCXO 3 Frequency Select 0/VCXO Analog Control Voltage[1] VSS 4 Ground CLKB/FS1 5 Clock Output B/Frequency Select 1[1] CLKA/FS0 6 Clock Output A/Frequency Select 0[1] CLKC/FS2/VSS 7 Clock Output C/Frequency Select 2/VSS[1] XOUT 8 Reference Output (No Connect when the reference is a clock) Note 1. Pin definition changes for different configurations. Refer to the specific one-page data sheet for more details. Cypress Semiconductor Corporation Document #: 001-07704 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 14, 2006 CY22800 General Description VCXO The CY22800 is a multi-function clock generator that supports various applications in consumer and communications markets. The device uses the Cypress proprietary PLL along with Spread Spectrum and VCXO technology to make it one of the most versatile clock synthesizer in the market place. The CY22800 is a field-programmable synthesizer that can be programmed using an easy-to-use programmer dongle, CY36800, with one of many predefined configuration files for fast sample generation of prototype builds. The CY22800 is a reprogrammable device that can be programmed up to five thousand times. The latest configurations available for this device are summarized in Table 1. One of the key components of the CY22800 device is the VCXO. The VCXO is used to “pull” the reference crystal higher or lower in order to lock the system frequency to an external source. This is ideal for applications where the output frequency needs to track along with an external reference frequency that is constantly shifting. The CY22800 is capable of generating Spread Spectrum Clocks (SSCG) for the purpose of reducing EMI found in today’s high-speed digital electronic systems. The device uses proprietary Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By modulating the frequency of the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency (EMC) requirements and improve time-to-market without degrading system performance. The CY22800 uses a preprogrammed configuration of memory arrays to synthesize output frequency and offers eight different spread percentages (refer to Table 1 – Code numbers -015 to -022), and an additional option to turn the spread on and off. VCXO Profile Figure 1 shows an example of what a VCXO profile looks like. The analog voltage input is on the X-axis and the PPM range is on the Y-axis. An increase in the VCXO input voltage results in a corresponding increase in the output frequency. This has the effect of moving the PPM from a negative to positive offset. Figure 1. VCXO Profile 200 150 100 Tuning [ppm] Spread Spectrum Clock Generation (SSCG) A special pullable crystal must be used in order to have adequate VCXO pull range. Pullable Crystal specifications are included in this data sheet. 50 0 -50 0 0.5 1 1.5 2 2.5 3 3.5 -100 -150 -200 VCXO input [V] For the above-mentioned configurations, the modulation frequency varies with the reference frequency as follows: f mod = f ref 1000 Document #: 001-07704 Rev. ** Page 2 of 8 CY22800 Table 1. CY22800 Configurations Document #: 001-07704 Rev. ** Page 3 of 8 CY22800 Cypress offers a wide range of programmable clock synthesizers that can be used to generate any other frequencies not covered by the CY22800. Table 2 summarizes all Cypress programmable devices including CY22800. Table 2. Cypress Programmable Clocks[2] Part # Output Freq. Package No. of Outputs Spread Spectrum VCXO I2C 1–200 8-SOIC up to 3 Yes Yes No 0.08–200 16-TSSOP up to 6 No No No up to 6 No No Yes up to 2 Yes No No No. of PLL Input Freq. CY22800 1 0.5–100 CY22050 1 1–133 CY22150 1 1–133 0.08–200 16-TSSOP CY25100 1 8–166 3–200 8-SOIC/TSSOP CY25200 1 3–166 3–200 16-TSSOP up to 6 Yes No No CY241V08 1 27/13.5 27/13.5 8-SOIC up to 2 No Yes No CY22392 3 1–166 1–200 16-TSSOP up to 6 No No No CY22381 3 1–166 1–200 8-SOIC up to 3 No No No CY22393 3 1–166 1–200 16-TSSOP up to 6 No No Yes CY22394/5 3 1–166 1–200 16-TSSOP up to 5 No No No CY22388/89/91 4 1–100 4.2–166 16/20-TSSOP, 32-QFN up to 8 No Yes No Note 2. The CY3672 programmer can be used to program all Cypress chips. Refer to the CY3672 data sheet for programming procedures. Document #: 001-07704 Rev. ** Page 4 of 8 CY22800 Absolute Maximum Conditions Parameter Description Min. Max. Unit VDD Supply Voltage –0.5 4.6 V TS Storage Temperature –65 125 °C TJ Junction Temperature – 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V 2 – kV Electro-Static Discharge Recommended Operating Conditions Parameter Description Min. Typ. Max. Unit 3.14 3.3 3.47 V Ambient Temperature 0 – 70 °C Max. Load Capacitance on the CLK output – – 15 pF Reference Frequency 0.5 – 100 MHz Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms VDD Operating Voltage TA CLOAD fREF[3] tPU Pullable Crystal Specifications for VCXO Application ONLY Min. Typ. Max. Unit CLNOM Parameter Crystal Load Capacitance Name – 14 – pF R1 Equivalent Series Resistance – – 25 Ω R3/R1 Ratio of Third Overtone Mode ESR to Fundamental Mode ESR. Ratio used because typical R1 values are much less than the maximum spec 3 – – – DL Crystal Drive Level. No external series resistor assumed – 0.5 2 mW F3SEPHI Third overtone separation from 3*FNOM (High Side) 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM (Low Side) – – –150 ppm 7 pF C0 Crystal shunt capacitance C0/C1 Ratio of Shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 pF Description Min. Typ. Max. Unit Parallel resonance, fundamental mode, and AT cut 8 – 30 MHz Recommended Crystal Specifications for ALL other Applications Parameter Name FNOM Nominal Crystal Frequency CLNOM Nominal Load Capacitance – 12 – pF R1 Equivalent Series Resistance (ESR) Fundamental mode – 35 50 Ω DL Crystal Drive Level No external series resistor assumed – 0.5 2 mW Note 3. Configuration dependent, see the one-page document. Document #: 001-07704 Rev. ** Page 5 of 8 CY22800 DC Electrical Specifications Parameter Name Min. Typ. Max. Unit VOH = VDD – 0.5, VDD = 3.3V (source) 12 24 – mA Output Low Current VOL = 0.5, VDD = 3.3V (sink) 12 24 – mA Input Capacitance All input pins except XIN and XOUT – – 7 pF Input Capacitance XIN and XOUT pins – 24 – pF Input High Current VIH = VDD – 5 10 µA IIL Input Low Current VIL = 0V 50 f∆XO VCXO Pullability Range IOH Output High Current IOL CIN1 CIN2 IIH Description – – ±150 – µA ppm VVCXO VCXO Input Range 0 – VDD V VIH Input High Voltage CMOS levels, 70% of VDD 0.7 – – VDD VIL Input Low Voltage CMOS levels, 30% of VDD – – 0.3 VDD AC Electrical Characteristics (VDD = 3.3V) Description Min. Typ. Max. Unit DC Parameter Output Duty Cycle Name Duty Cycle is defined in Figure 3, 50% of VDD 45 50 55 % t3 Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD 0.8 1.4 – V/ns t4 Falling Edge Slew Rate Output Clock Fall Time, 80% - 20% of VDD 0.8 1.4 – V/ns t10 PLL Lock Time – – 3 ms Test Circuit Figure 2. Test Circuit Diagram VDD 0.1µF Figure 4. Rise and Fall Time Definitions t3 CLKout CLOAD OUTPUTS t4 80% CLK 20% GND Figure 3. Duty Cycle Definition; DC = t2/t1 t1 t2 CLK 50% 50% Document #: 001-07704 Rev. ** Page 6 of 8 CY22800 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY22800FXC 8-Pin SOIC Commercial 3.3V Package Diagram Figure 5. 8-Lead (150-Mil) SOIC S8 51-85066-*C All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-07704 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY22800 Document History Page Document Title: CY22800 Universal Programmable Clock Generator (UPCG) Document Number: 001-07704 REV. ECN NO. Issue Date ** 478688 See ECN Document #: 001-07704 Rev. ** Orig. of Change Description of Change KKVTMP New data sheet Page 8 of 8