W155 Spread Spectrum Frequency Timing Generator Features Table 1. Frequency Selection (14.318-MHz Reference) • Generates a spread spectrum timing signal (SYSCLK) and a non-spread signal (USBCLK) • Requires a 14.318-MHz crystal for operation • Supports MIPS microprocessor clock frequencies • Reduces peak EMI by as much as 12 dB • Integrated loop filter components • Cycle-to-cycle jitter = 250 ps (max) • Operates with a 3.3 or 5.0V power supply • Spread output is selectable from 10 to 133 MHz • TEST mode supports modulation off (High-Z) and special test input reference frequency • Guaranteed 45/55 duty cycle • Packaged in a 16-pin, 300-mil-wide SOIC (Small Outline Integrated Circuit) FS3 FS2 FS1 FS0 SYSCLK (Output Freq.) 0 0 0 0 133.3 MHz 0 0 0 1 120 MHz 0 0 1 0 100 MHz 0 0 1 1 74.77 MHz 0 1 0 0 70 MHz 0 1 0 1 66.6 MHz 0 1 1 0 60 MHz 0 1 1 1 50 MHz 1 0 0 0 40 MHz 1 0 0 1 33.33 MHz 1 0 1 0 30 MHz 1 0 1 1 25 MHz 1 1 0 0 20 MHz 1 1 0 1 16.67 MHz 1 1 1 0 12 MHz 1 1 1 1 10 MHz Overview The W155 incorporates the latest advances in PLL-based spread spectrum frequency synthesizer technology. By frequency modulating the SYSCLK output with a low-frequency carrier, peak EMI can be greatly reduced in a system. Use of this technique allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. In a system that uses the W155, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to SYSCLK. Therefore, the benefits of using this technique increase with the number of address and data lines in the system. Table 2. Spread Percentage Selection SS% Spread Percentage 0 –1.25% 1 –3.75% The W155 is specifically targeted toward MIPS microprocessor based systems where EMI is of particular concern. Each device uses a single 14.318-MHz crystal to generate a selectable spread spectrum output and an unmodulated 48-MHz USB Output. The spreading function can be disabled by taking the SSON# pin high. Spread percentage can be selected with the SS% input (see Table 2 below). [1] Pin Configuration 1 16 TEST X1 2 15 VDD X2 3 14 USBCLK/SS%* GND 4 13 GND FS3* 5 12 SYSCLK VDD 6 11 GND FS2* 7 10 FS0* FS1* 8 9 W155 VDD SSON#^ Note: 1. Internal pull-up resistor present on inputs marked with ‘*’ and pull-down resistor present on input marked with ‘^’. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 September 29, 1999, rev. ** W155 Pin Definitions Pin Name Pin No. Pin Type Pin Description USBCLK/ SS% 14 I/O USB Clock Output/Modulation Width Selection Input: When an input; if spread spectrum feature is enabled, this pin is used to select the amount of frequency variation on the SYSCLK output (see Table 2). Wider variations result in greater peak EMI reduction. When an output: supplies a non-spread 48-MHz signal for USB support. SYSCLK 12 O System Clock Output: Frequency is selected per Table 1. Spread spectrum feature is controlled by pins 9 & 14. 10, 8, 7, 5 I Frequency Select Pins: These pins set the frequency of the signal provided at the SYSCLK output. SSON# 9 I Spread Spectrum Control (active LOW): Pulling this input signal HIGH turns the internal modulating waveform off. This pin has an internal pull-down resistor. X1 2 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as either an external crystal connection, or as an external reference frequency input. X2 3 I Crystal Connection: If using an external reference, this pin must be left unconnected. TEST 16 I Test Mode: For normal operation, tie this pin to ground. VDD 1, 6, 15 P Power Connection: Connected to either 3.3V or 5.0V power supply. All VDD pins must be the same voltage level. GND 4, 11, 13 G Ground Connection: Connect to the common system ground plane. FS0:3 2 W155 that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Functional Description I/O Pin Operation Pin 14 is a dual purpose l/O pin. Upon power-up each I/O pin acts as a logic input, allowing the determination of assigned device functions. A short time after power-up, the logic state of each pin is latched and each pin then becomes a clock output. This feature reduces device pin count by combining clock outputs with input select pins. Output Buffer Configuration Clock Outputs All clock outputs are designed to drive serial terminated clock lines. The device outputs are CMOS-type which provide rail-to-rail output swing. An external 10-kΩ “strapping” resistor is connected between each l/O pin and ground or VDD. Connection to ground sets a “0” bit, connection to V DD sets a “1” bit. See Figure 1. Crystal Oscillator Upon W155 power-up, the first 2 ms of operation is used for input logic selection. During this period, each clock output buffer is three-stated, allowing the output strapping resistor on each l/O pin to pull the pin and its associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic 0 or 1 condition of each l/O pin is then latched. Next the output buffer is enabled converting all l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. The device requires one input reference clock to synthesize all output frequencies. The reference clock can be either an externally generated clock signal or the clock generated by the internal crystal oscillator. When using an external clock signal, pin X1 is used as the clock input and pin X2 is left open. The input threshold voltage of pin X1 is (VDD)/2. The internal crystal oscillator is used in conjunction with a quartz crystal connected to device pins X1 and X2. This forms a parallel resonant crystal oscillator circuit. The device incorporates the necessary feedback resistor and crystal load capacitors. Including typical stray circuit capacitance, the total load presented to the crystal is approximately 20 pF. For optimum frequency accuracy without the addition of external capacitors, a parallel-resonant mode crystal specifying a load of 20 pF should be used. This will typically yield reference frequency accuracies within ±100 ppm. To achieve similar accuracies with a crystal calling for a greater load, external capacitors must be added such that the total load (internal, external, and parasitic capacitors) equals that called for by the crystal. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of the clock outputs is <40Ω (nominal) which is minimally affected by the 10-kΩ strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. When each clock output is enabled following the 2-ms input period, target (normal) output frequency is delivered assuming Jumper Options Output Strapping Resistor VDD Series Termination Resistor 10 kΩ W155 R Output Buffer Power-on Reset Timer Hold Output Low Output Three-state Q D Data Latch Figure 1. Input Logic Selection Through Jumper Option 3 Clock Load W155 Spread Spectrum Frequency Timing Generator Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 2. The output clock is modulated with a waveform depicted in Figure 3. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is specified in Table 2. Figure 3 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local sales representative for details on these devices. As shown in Figure 2, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for pin 9. dB = 6.5 + 9*log10(P) + 9*log10(F) EMI Reduction Spread Spectrum Enabled NonSpread Spectrum Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MIN Figure 3. Typical Modulation Profile 4 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX W155 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit V VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 –65 to +150 °C 0 to +70 °C –55 to +125 °C TSTG Storage Temperature TA Operating Temperature TB Ambient Temperature under Bias DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.30V±10% Parameter Description Test Condition Min Typ Max Unit IDD Supply Current 35 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage VOL Output Low Voltage IOL = 2 mA VOH Output High Voltage IOH = –2 mA 3.10 IOL Output Low Current VOL = 1.5V 80 IOH Output High Current VOH = 1.5V 80 IIL Input Low Current IIH Input High Current CI Input Capacitance 5 CL XTAL Load Capacitance 20 2.0 V 50 mV 110 155 mA 120 175 mA 10 µA 10 µA 10 pF V pF Switching Characteristics Max Unit tTLH, tTHL Parameter Output Rise and Fall Time measured at 10% of 90% of VDD Description Test Conditions 0.8 4.0 ns tTLH, tTHL Output Rise and Fall Time measured at 0.8V–2.0V 0.3 1.0 ns tSYM Output Duty Cycle 45 55 % tJCC Cycle-to-Cycle Jitter EMI EMI Attenuation W155 Typ 250 11th Harmonic, 25 MHz Ordering Information Ordering Code Min Package Name Package Type G 16-pin Plastic SOIC (300-mil, wide body) Document #: 38-00785 5 10 ps dB W155 Package Diagram 16-Pin Small Outlined Integrated Circuit (SOIC, 300 mils, wide body) 1 16 0.399 - 0.412 (10.13 - 10.46) 0.009 - 0.0125 (0.23 - 0.32) 5°Nom 0.024 - 0.040 (0.61 - 1.02) 8 9 0.189 - 0.196 (4.80 - 4.98) 0.285 – 0.299 (7.42 – 7.59) 0.097 - 0.104 (2.46 - 2.64) 0.40 – 0.41 (10.16 – 10.41) 0.014 - 0.019 (0.35 - 0.48) 0.05 (1.27) BSC 0.0020 – 0.015 (0.06 – 0.38) Note: All linear dimensions are in inches and parenthetically in millimeters, min. – max. © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.