16-Bit, 1.5 LSB INL, 250 kSPS PulSAR™ Differential ADC in MSOP/QFN AD7687 Data Sheet FEATURES APPLICATION DIAGRAM APPLICATIONS Battery-powered equipment Data acquisitions Instrumentation Medical instruments Process controls 1.5 POSITIVE INL = +0.32LSB NEGATIVE INL = –0.41LSB 1.0 0.5V TO 5V VREF 0 IN+ IN– VREF 2.5 TO 5V REF VDD VIO SDI AD7687 1.8V TO VDD SCK 3- OR 4-WIRE INTERFACE (SPI, DAISY CHAIN, CS) SDO GND CNV 0 02972-002 16-bit resolution with no missing codes Throughput: 250 kSPS INL: ±0.4 LSB typ, ±1.5 LSB max (±23 ppm of FSR) Dynamic range: 96.5 dB S/(N + D): 95.5 dB @ 20 kHz THD: −118 dB @ 20 kHz True differential analog input range ±VREF 0 V to VREF with VREF up to VDD on both inputs No pipeline delay Single-supply 2.3 V to 5.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible Daisy-chain multiple ADCs and BUSY indicator Power dissipation 1.35 mW @ 2.5 V/100 kSPS, 4 mW @ 5 V/100 kSPS, and 1.4 μW @ 2.5 V/100 SPS Standby current: 1 nA 10-lead MSOP (MSOP-8 size) and 3 mm × 3 mm QFN (LFCSP) (SOT-23 size) Pin-for-pin compatible with AD7685, AD7686, and AD7688 Figure 2. Table 1. MSOP, QFN (LFCSP)/SOT-23 16-Bit PulSAR ADC Type True Differential Pseudo Differential/Unipolar Unipolar 100 kSPS AD7684 AD7683 250 kSPS AD7687 AD7685 AD7694 500 kSPS AD7688 AD7686 AD7680 GENERAL DESCRIPTION The AD7687 is a 16-bit, charge redistribution, successive approximation, analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.3 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes, an internal conversion clock, and a versatile serial interface port. The part also contains a low noise, wide bandwidth, short aperture delay track-and-hold circuit. On the CNV rising edge, it samples the voltage difference between IN+ and IN− pins. The voltages on these pins usually swing in opposite phase between 0 V to REF. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Its power scales linearly with throughput. INL (LSB) 0.5 The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single, 3-wire bus and provides an optional BUSY indicator. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO. 0 –0.5 02972-001 –1.0 –1.5 0 16384 32768 CODE 49152 The AD7687 is housed in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. 65535 Figure 1. Integral Nonlinearity vs. Code Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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AD7687 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 16 Applications....................................................................................... 1 Single-to-Differential Driver .................................................... 16 Application Diagram........................................................................ 1 Voltage Reference Input ............................................................ 16 General Description ......................................................................... 1 Power Supply............................................................................... 16 Revision History ............................................................................... 2 Supplying the ADC from the Reference.................................. 17 Specifications..................................................................................... 3 Digital Interface.......................................................................... 17 Timing Specifications....................................................................... 5 CS MODE 3-Wire, No BUSY Indicator .................................. 18 Absolute Maximum Ratings............................................................ 7 CS Mode 3-Wire with BUSY Indicator ................................... 19 Thermal Resistance ...................................................................... 7 CS Mode 4-Wire, No BUSY Indicator..................................... 20 ESD Caution.................................................................................. 7 CS Mode 4-Wire with BUSY Indicator ................................... 21 Pin Configurations and Function Descriptions ........................... 8 Chain Mode, No BUSY Indicator ............................................ 22 Terminology ...................................................................................... 9 Chain Mode with BUSY Indicator........................................... 23 Typical Performance Characteristics ........................................... 10 Application Hints ........................................................................... 24 Circuit Information.................................................................... 13 Layout .......................................................................................... 24 Converter Operation.................................................................. 13 Evaluating the AD7687’s Performance.................................... 24 Typical Connection Diagram ................................................... 14 Outline Dimensions ....................................................................... 25 Analog Input ............................................................................... 15 Ordering Guide .......................................................................... 26 REVISION HISTORY 8/11—Rev. A to Rev. B Changes to Table 7............................................................................ 7 Changes to Ordering Guide .......................................................... 26 2/11—Rev. 0 to Rev. A Deleted QFN in Development Note............................ Throughout Changes to Table 6............................................................................ 7 Added Thermal Resistance Section and Table 7 .......................... 7 Changes to Figure 6 and Table 8..................................................... 8 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 26 4/05—Revision 0: Initial Version Rev. B | Page 2 of 28 Data Sheet AD7687 SPECIFICATIONS VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Common-Mode Input Range Analog Input CMRR Leakage Current at 25°C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error 2 , TMIN to TMAX Gain Error Temperature Drift Offset Error2, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity THROUGHPUT Conversion Rate Transient Response AC ACCURACY Dynamic Range Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Conditions Min 16 IN+ − IN− IN+, IN− IN+, IN− fIN = 250 kHz Acquisition phase −VREF −0.1 0 Typ Max Unit Bits +VREF VREF + 0.1 VREF/2 + 0.1 V V V dB nA VREF/2 65 1 See the Analog Input section 16 −1 −1.5 REF = VDD = 5 V VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V VDD = 5 V ± 5% VDD = 4.5 V to 5.5 V VDD = 2.3 V to 4.5 V Full-scale step 0 0 VREF = 5 V fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 2.5 V fIN = 20 kHz fIN = 20 kHz fIN = 20 kHz, VREF = 5 V fIN = 20 kHz, VREF = 5 V, −60 dB input fIN = 20 kHz, VREF = 2.5 V 95.8 94 92 Intermodulation Distortion 4 1 94 92 ±0.4 ±0.4 0.35 ±2 ±0.3 ±0.1 ±0.7 ±0.3 ±0.05 +1 +1.5 ±6 ±1.6 ±3.5 250 200 1.8 96.5 95.5 92.5 −118 −118 95.5 36.5 92.5 115 Bits LSB 1 LSB LSB LSB ppm/°C mV mV ppm/°C LSB kSPS kSPS μs dB 3 dB dB dB dB dB dB dB dB LSB means least significant bit. With the ±5 V input range, one LSB is 152.6 μV. See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference. All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full-scale. 2 3 Rev. B | Page 3 of 28 AD7687 Data Sheet VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay Conditions VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation ISINK = +500 μA ISOURCE = −500 μA TEMPERATURE RANGE 3 Specified Performance Min Typ 0.5 Max Unit VDD + 0.3 250 kSPS, REF = 5 V 50 V μA VDD = 5 V 2 2.5 MHz ns −0.3 0.7 × VIO −1 −1 +0.3 × VIO VIO + 0.3 +1 +1 Serial 16-bits twos complement Conversion results available immediately after completed conversion 0.4 VIO − 0.3 Specified performance Specified performance 2.3 2.3 1.8 VDD and VIO = 5 V, 25°C VDD = 2.5 V, 100 SPS throughput VDD = 2.5 V, 100 kSPS throughput VDD = 2.5 V, 200 kSPS throughput VDD = 5 V, 100 kSPS throughput VDD = 5 V, 250 kSPS throughput TMIN to TMAX 1 1.4 1.35 2.7 4 −40 1 With all digital inputs forced to VIO or GND as required. During acquisition phase. 3 Contact sales for extended temperature range. 2 Rev. B | Page 4 of 28 5.5 VDD + 0.3 VDD + 0.3 50 V V μA μA V V 5.5 12.5 V V V nA μW mW mW mW mW +85 °C Data Sheet AD7687 TIMING SPECIFICATIONS −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. See Figure 3 and Figure 4 for load conditions. Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 4.5 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with BUSY indicator) VIO Above 4.5 V VIO Above 2.3 V Rev. B | Page 5 of 28 Symbol tCONV tACQ tCYC tCNVH tSCK tSCK tSCKL tSCKH tHSDO tDSDO Min 0.5 1.8 4 10 15 Typ Max 2.2 17 18 19 20 7 7 5 Unit μs μs μs ns ns ns ns ns ns ns ns ns 14 15 16 17 ns ns ns ns 15 18 22 25 ns ns ns ns ns ns ns ns ns ns 15 26 ns ns tEN tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 15 0 5 5 3 4 AD7687 Data Sheet −40°C to +85°C, VDD = 2.3 V to 4.5 V, VIO = 2.3 V to 4.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated. See Figure 3 and Figure 4 for load conditions. Table 5. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width ( CS Mode ) SCK Period ( CS Mode ) SCK Period ( Chain Mode ) VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 2.7 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (CS Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with BUSY indicator) Rev. B | Page 6 of 28 Symbol tCONV tACQ tCYC tCNVH tSCK tSCK tSCKL tSCKH tHSDO tDSDO Min 0.7 1.8 5 10 25 Typ Max 3.2 29 35 40 12 12 5 Unit μs μs μs ns ns ns ns ns ns ns ns 24 30 35 ns ns ns 18 22 25 ns ns ns ns ns ns ns ns ns ns tEN tDIS tSSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 30 0 5 8 5 4 36 Data Sheet AD7687 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. 1 GND − 0.3 V to VDD + 0.3 V or ±130 mA GND − 0.3 V to VDD + 0.3 V −0.3 V to +7 V ±7 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C JEDEC J-STD-20 THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance Package Type 10-Lead QFN (LFCSP) 10-Lead MSOP See the Analog Input section. θJA 84 200 ESD CAUTION 500μA IOL 1.4V TO SDO CL 50pF 500μA IOH Figure 3. Load Circuit for Digital Interface Timing 70% VIO 30% VIO tDELAY tDELAY 2V OR VIO – 0.5V1 2V OR VIO – 0.5V1 0.8V OR 0.5V2 0.8V OR 0.5V2 12V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V. 20.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V. Figure 4. Voltage Levels for Timing Rev. B | Page 7 of 28 02972-004 REF Supply Voltages VDD, VIO to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature Lead Temperature Range Rating 02972-003 Parameter Analog Inputs IN+ 1 , IN−1 θJC 2.96 44 Unit °C/W °C/W AD7687 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS AD7687 9 SDI IN+ 3 TOP VIEW (Not to Scale) 8 SCK 7 SDO IN– 4 GND 5 6 CNV REF 1 VDD 2 IN+ 3 IN– 4 GND 5 10 VIO AD7687 9 SDI TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV NOTES 1. FOR THE LFCSP PACKAGE ONLY, THE EXPOSED PADDLE MUST BE CONNECTED TO GND. 02972-006 10 VIO 02972-005 REF 1 VDD 2 Figure 6. 10-Lead QFN (LFCSP) Pin Configuration Figure 5. 10-Lead MSOP Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 Mnemonic REF Type 1 AI 2 3 4 5 6 VDD IN+ IN− GND CNV P AI AI P DI 7 8 9 SDO SCK SDI DO DI DI 10 VIO P EPAD N/A Function Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a 10 μF capacitor. Power Supply. Differential Positive Analog Input. Differential Negative Analog Input. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode, chain or CS. In CS mode, it enables the SDO pin when low. In chain mode, the data should be read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 16 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete, the BUSY indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). For the LFCSP package only, the exposed paddle must be connected to GND. 1 AI = Analog Input, DI = Digital Input, DO = Digital Output, P = Power, and N/A = not applicable. Rev. B | Page 8 of 28 Data Sheet AD7687 TERMINOLOGY Integral Nonlinearity Error (INL) It refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (Figure 26). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error It is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error The first transition (from 100 . . . 00 to 100 . . . 01) should occur at a level ½ LSB above nominal negative full scale (−4.999924 V for the ±5 V range). The last transition (from 011…10 to 011…11) should occur for an analog voltage 1½ LSB below the nominal full scale (+4.999771 V for the ±5 V range.) The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula ENOB = (S/[N + D]dB − 1.76)/6.02 and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Dynamic Range It is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB. Aperture Delay Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Transient Response It is the time required for the ADC to accurately acquire its input after a full-scale step function was applied. Rev. B | Page 9 of 28 AD7687 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.5 1.5 POSITIVE DNL = +0.27LSB NEGATIVE DNL = –0.24LSB 1.0 0.5 0.5 DNL (LSB) 1.0 0 –0.5 –0.5 –1.0 –1.0 –1.5 0 16384 32768 CODE 49152 02972-009 0 02972-001 INL (LSB) POSITIVE INL = +0.32LSB NEGATIVE INL = –0.41LSB –1.5 65535 0 16384 Figure 7. Integral Nonlinearity vs. Code 32768 CODE 49152 65535 Figure 10. Differential Nonlinearity vs. Code 300000 250000 VDD = REF = 5V 258680 VDD = REF = 2.5V 200403 250000 200000 200000 COUNTS COUNTS 150000 150000 100000 100000 0 1049 1391 0 02972-007 0 0 0 41 42 43 44 45 CODE IN HEX 46 0 0 60 44 45 46 29918 18 0 0 4A 4B 4C 0 47 Figure 8. Histogram of a DC Input at the Code Center 47 48 49 CODE IN HEX Figure 11. Histogram of a DC Input at the Code Center 0 0 8192 POINT FFT VDD = REF = 5V FS = 250KSPS FIN = 2.1kHz SNR = 95.5dB THD = –118.3dB 2nd HARM = –130dB 3rd HARM = –122.7dB –60 –80 –100 –120 02972-008 –140 –160 –180 0 20 40 60 80 FREQUENCY (kHz) 100 –40 –60 –80 –100 –120 –140 02972-011 –40 32768 POINT FFT VDD = REF = 2.5V FS = 250KSPS FIN = 2kHz SNR = 92.8dB THD = –115.9dB 2nd HARM = –124dB 3rd HARM = –119dB –20 AMPLITUDE (dB of Full Scale) –20 AMPLITUDE (dB of Full Scale) 30721 02972-010 50000 50000 –160 –180 120 Figure 9. FFT Plot 0 20 40 60 80 FREQUENCY (kHz) Figure 12. FFT Plot Rev. B | Page 10 of 28 100 120 Data Sheet AD7687 100 17.0 –100 –105 SNR 16.0 S/[N + D] 70 2.3 2.7 3.1 3.5 3.9 4.3 4.7 REFERENCE VOLTAGE (V) 5.1 13.0 5.5 –115 THD SFDR –120 –125 –130 2.3 Figure 13. SNR, S/(N + D), and ENOB vs. Reference Voltage 02972-015 14.0 85 THD, SFDR (dB) 15.0 90 ENOB (Bits) –110 ENOB 02972-012 SNR, S/(N + D) (dB) 95 2.7 3.1 3.5 3.9 4.3 4.7 REFERENCE VOLTAGE (V) 5.1 5.5 Figure 16. THD, SFDR vs. Reference Voltage 100 –60 VREF = 5V, –10dB 95 –70 VREF = 2.5V, –10dB –80 VREF = 5V, –1dB VREF = 2.5V, –1dB 85 VREF = 2.5V, –1dB THD (dB) S/(N + D) (dB) 90 80 –90 VREF = 5V, –1dB –100 VREF = 2.5V, –10dB 75 70 0 50 100 FREQUENCY (kHz) 150 VREF = 5V, –10dB 02972-016 02972-013 –110 –120 200 0 50 Figure 14. S/(N + D) vs. Frequency 100 FREQUENCY (kHz) 150 200 Figure 17. THD vs. Frequency 100 –90 VREF = 5V 95 –100 THD (dB) 90 VREF = 5V –110 VREF = 2.5V 85 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 –130 –55 Figure 15. SNR vs. Temperature 02972-017 80 –55 –120 02972-014 SNR (dB) VREF = 2.5V –35 –15 5 25 45 65 TEMPERATURE (°C) Figure 18. THD vs. Temperature Rev. B | Page 11 of 28 85 105 125 AD7687 Data Sheet 100 1000 99 fS = 100kSPS VDD = 5V OPERATING CURRENT (μA) 98 97 VREF = 5V SNR (dB) 96 95 94 VREF = 2.5V 93 750 VDD = 2.5V 500 250 91 –8 –6 –4 INPUT LEVEL (dB) –2 VIO 0 –55 0 Figure 19. SNR vs. Input Level OFFSET, GAIN ERROR (LSB) 500 250 VIO 105 125 3.5 3.9 4.3 SUPPLY (V) 4.7 5.1 GAIN ERROR 2 0 –2 OFFSET ERROR –4 –6 –55 5.5 Figure 20. Operating Currents vs. Supply –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 Figure 23. Offset and Gain Error vs. Temperature 1000 25 VDD = 2.5V, 85°C 20 TDSDO DELAY (ns) 750 500 15 VDD = 2.5V, 25°C 10 VDD = 5V, 85°C 250 VDD = 5V, 25°C 5 0 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 VDD = 3.3V, 85°C 02972-023 VDD + VIO 02972-020 POWER-DOWN CURRENT (nA) 85 4 02972-019 OPERATING CURRENT (μA) VDD 750 3.1 5 25 45 65 TEMPERATURE (°C) 6 fS = 100kSPS 2.7 –15 Figure 22. Operating Currents vs. Temperature 1000 0 2.3 –35 02972-022 90 –10 02972-021 02972-018 92 VDD = 3.3V, 25°C 0 0 20 40 60 80 SDO CAPACITIVE LOAD (pF) 100 Figure 24. tDSDO Delay vs. Capacitance Load and Supply Figure 21. Power-Down Currents vs. Temperature Rev. B | Page 12 of 28 120 Data Sheet AD7687 IN+ SWITCHES CONTROL MSB 32,768C 16,384C LSB 4C 2C C SW+ C BUSY REF COMP GND 32,768C 16,384C 4C 2C C CONTROL LOGIC OUTPUT CODE C MSB LSB SW– 02972-024 CNV IN– Figure 25. ADC Simplified Schematic CIRCUIT INFORMATION CONVERTER OPERATION The AD7687 is a fast, low power, single-supply, precise 16-bit ADC using a successive approximation architecture. The AD7687 is a successive approximation ADC based on a charge redistribution DAC. Figure 25 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. The AD7687 is capable of converting 250,000 samples per second (250 kSPS) and powers down between conversions. When operating at 100 SPS, for example, it typically consumes 1.35 μW, which is ideal for battery-powered applications. The AD7687 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7687 is specified from 2.3 V to 5.5 V and can be interfaced to any of the 1.8 V to 5 V digital logic family. It is housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that combines space savings and allows flexible configurations. It is pin-for-pin-compatible with the AD7685, AD7686, and AD7688. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN− captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 . . . VREF/65536). The control logic toggles these switches, starting with the MSB, in order to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code and a BUSY signal indicator. Because the AD7687 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. B | Page 13 of 28 AD7687 Data Sheet TYPICAL CONNECTION DIAGRAM The ideal transfer characteristic for the AD7687 is shown in Figure 26 and Table 9. Figure 27 shows an example of the recommended connection diagram for the AD7687 when multiple supplies are available. ADC CODE (TWOS COMPLEMENT) Transfer Functions 011...111 011...110 011...101 100...010 100...001 –FSR + 1 LSB +FSR – 1 LSB +FSR – 1.5 LSB –FSR + 0.5 LSB 02972-025 100...000 –FSR ANALOG INPUT Figure 26. ADC Ideal Transfer Function Table 9. Output Codes and Ideal Input Voltages Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR Analog Input VREF = 5 V +4.999847 V +152.6 μV 0V −152.6 μV −4.999847 V −5 V Digital Output Code Hexa 7FFF1 0001 0000 FFFF 8001 80002 1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). 2 This is also the code for an underranged analog input (VIN+ − VIN− below −VREF + VGND). ≥7V REF1 5V 10μF2 100nF ≥7V 1.8V TO VDD 100nF 33Ω REF 0 TO VREF VDD IN+ 3 ≤–2V ≥7V VIO SDI 2.7nF SCK AD7687 4 IN– 33Ω 3- OR 4-WIRE INTERFACE5 SDO CNV GND VREF TO 0 3 ≤–2V 2.7nF 1SEE REFERENCE SECTION FOR REFERENCE SELECTION. 2C REF IS USUALLY A 10μF CERAMIC CAPACITOR (X5R). 3SEE DRIVER AMPLIFIER CHOICE SECTION. 4OPTIONAL FILTER. SEE ANALOG INPUT SECTION. 5SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE. Figure 27. Typical Application Diagram with Multiple Supplies Rev. B | Page 14 of 28 02972-026 4 Data Sheet AD7687 ANALOG INPUT Figure 28 shows an equivalent circuit of the input structure of the AD7687. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN+ and IN−. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this causes these diodes to begin to forwardbias and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from VDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. VDD D1 IN+ OR IN– CIN D2 02972-027 CPIN RIN GND During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 3 kΩ and is a lumped component made up of some serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. When the source impedance of the driving circuit is low, the AD7687 can be driven directly. Large source impedances significantly affect the ac performance, especially total harmonic distortion (THD). The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency, as shown in Figure 30. –60 Figure 28. Equivalent Analog Input Circuit 90 –70 –80 THD (dB) The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected, as shown in Figure 29, which represents the typical CMRR over frequency. –90 RS = 250Ω VDD = 5V –100 80 RS = 100Ω RS = 50Ω RS = 33Ω –120 0 60 02972-029 –110 70 25 50 FREQUENCY (kHz) 75 Figure 30. THD vs. Analog Input Frequency and Source Resistance 50 02972-028 CMRR (dB) VDD = 2.5V 40 1 10 100 FREQUENCY (kHz) 1000 Figure 29. Analog Input CMRR vs. Frequency Rev. B | Page 15 of 28 100 AD7687 Data Sheet DRIVER AMPLIFIER CHOICE SINGLE-TO-DIFFERENTIAL DRIVER Although the AD7687 is easy to drive, the driver amplifier needs to meet the following requirements: For applications using a single-ended analog signal, either bipolar or unipolar, a single-ended-to-differential driver allows for a differential input into the part (see Figure 31 for the schematic). When provided a single-ended input signal, this configuration produces a differential ±VREF with midscale at VREF/2. The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7687. Note that the AD7687 has a noise much lower than most of the other 16-bit ADCs and, therefore, can be driven by a noisier op amp while preserving the same or better system performance. The noise coming from the driver is filtered by the AD7687 analog input circuit 1-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used. Because the typical noise of the AD7687 is 53 μV rms, the SNR degradation due to the amplifier is SNRLOSS 590Ω ANALOG INPUT (±10V, ±5V, ..) U1 VREF VREF 10μF 100nF 590Ω IN+ REF ⎛ ⎞ ⎜ ⎟ 53 ⎟ = 20log ⎜ π 2 ⎟ ⎜⎜ 532 + f ( ) 2 Ne ⎟ N 2 −3dB ⎝ ⎠ 590Ω 10kΩ U2 AD7687 IN– VREF 10kΩ 100nF where: Figure 31. Single-Ended-to-Differential Driver Circuit f–3dB is the input bandwidth in MHz of the AD7687 (2 MHz) or the cutoff frequency of the input filter, if one is used. VOLTAGE REFERENCE INPUT The AD7687 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. N is the noise gain of the amplifier (for example, +1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/√Hz. • • For ac applications, the driver should have a THD performance commensurate with the AD7687. Figure 17 shows the THD vs. frequency that the driver should exceed. For multichannel multiplexed applications, the driver amplifier and the AD7687 analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%, 15 ppm). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. Table 10. Recommended Driver Amplifiers. Amplifier AD8021 AD8022 OP184 AD8605, AD8615 AD8519 AD8031 02972-030 • Typical Application Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single-supply, low power Small, low power and low frequency High frequency and low power When REF is driven by a very low impedance source, for example, a reference buffer using the AD8031 or the AD8605, a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, smaller reference decoupling capacitor values down to 2.2 μF can be used with a minimal impact on performance, especially DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. POWER SUPPLY The AD7687 is specified over a wide operating range of 2.3 V to 5.5 V. Unlike other low voltage converters, it has a low enough noise to design a 16-bit resolution system with low supply and respectable performance. It uses two power supply pins: a core supply VDD and a digital input/output interface supply VIO. VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD can be tied together. The AD7687 is independent of power supply sequencing between VIO and VDD. Additionally, it is very Rev. B | Page 16 of 28 Data Sheet AD7687 insensitive to power supply variations over a wide frequency range, as shown in Figure 32, which represents PSRR over frequency. 5V 5V 10Ω 5V 100 10kΩ 1μF 95 AD8031 10μF 1μF 1 VDD = 5V 90 REF VDD VIO AD7687 80 75 1OPTIONAL VDD = 2.5V 70 Figure 34. Example of Application Circuit 65 DIGITAL INTERFACE 02972-031 60 55 50 1 10 100 FREQUENCY (kHz) 1000 10000 Figure 32. PSRR vs. Frequency The AD7687 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure 33. This makes the part ideal for low sampling rate (even a few Hz) and low batterypowered applications. VDD = 5V VDD = 2.5V VIO 02972-032 0.1 100 1000 10000 SAMPLING RATE (SPS) The AD7687, when in CS mode, is compatible with SPI, QSPI, digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or ADSP-219x. This interface can use either 3-wire or 4-wire. A 3wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. 10 0.001 10 Though the AD7687 has a reduced number of pins, it offers flexibility in its serial interface modes. The AD7687, when in chain mode, provides a daisy chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. 1000 OPERATING CURRENT (μA) REFERENCE BUFFER AND FILTER. 02972-033 PSRR (dB) 85 100000 1000000 Figure 33. Operating Currents vs. Sampling Rate In either mode, the AD7687 offers the flexibility to optionally force a start bit in front of the data bits. This start bit can be used as a BUSY signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a BUSY indicator, the user must time out the maximum conversion time prior to readback. The BUSY indicator feature is enabled as: SUPPLYING THE ADC FROM THE REFERENCE For simplified applications, the AD7687, with its low operating current, can be supplied directly using the reference circuit shown in Figure 34. The reference line can be driven by either: • The system power supply directly • A reference voltage with enough current output capability, such as the ADR43x • A reference buffer, such as the AD8031, which can also filter the system power supply, as shown in Figure 34 • In the CS mode, if CNV or SDI is low when the ADC conversion ends (Figure 38 and Figure 42). • In the chain mode, if SCK is high during the CNV rising edge (Figure 46). Rev. B | Page 17 of 28 AD7687 Data Sheet to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE, NO BUSY INDICATOR This mode is usually used when a single AD7687 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 35 and the corresponding timing is given in Figure 36. CONVERT With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. Once a conversion is initiated, it continues to completion irrespective of the state of CNV. For instance, it could be useful to bring CNV low to select other SPI devices, such as analog multiplexers, but CNV must be returned high before the minimum conversion time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7687 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used DIGITAL HOST CNV VIO SDI AD7687 DATA IN SDO 02972-034 SCK CLK Figure 35. CS Mode 3-Wire, No BUSY Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 14 tHSDO 16 tSCKH tDSDO tEN SDO 15 D15 D14 D13 tDIS D1 Figure 36. CS Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High) Rev. B | Page 18 of 28 D0 02972-035 SCK Data Sheet AD7687 a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or when CNV goes high, whichever is earlier, SDO returns to high impedance. CS MODE 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7687 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 37 and the corresponding timing is given in Figure 38. If multiple AD7687s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV could be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7687 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, CONVERT VIO CNV VIO DIGITAL HOST 47kΩ AD7687 DATA IN SDO SCK IRQ 02972-036 SDI CLK Figure 37. CS Mode 3-Wire with BUSY Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 tHSDO 15 16 17 tSCKH tDSDO SDO tDIS D15 D14 D1 Figure 38. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High) Rev. B | Page 19 of 28 D0 02972-037 SCK AD7687 Data Sheet time and held high until the maximum conversion time to avoid the generation of the BUSY signal indicator. When the conversion is complete, the AD7687 enters the acquisition phase and powers down. Each ADC result can be read by bringing low its SDI input, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the 16th SCK falling edge, or when SDI goes high, whichever is earlier, SDO returns to high impedance and another AD7687 can be read. CS MODE 4-WIRE, NO BUSY INDICATOR This mode is usually used when multiple AD7687s are connected to an SPI-compatible digital host. A connection diagram example using two AD7687s is shown in Figure 39 and the corresponding timing is given in Figure 40. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT CNV AD7687 SDO SDI AD7687 SCK SDO SCK 02972-038 SDI DIGITAL HOST CNV DATA IN CLK Figure 39. CS Mode 4-Wire, No BUSY Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL SCK 1 2 14 3 tHSDO 16 17 18 30 31 32 tSCKH tDSDO tEN D15 D14 D13 tDIS D1 D0 D15 D14 D1 D0 02972-039 SDO 15 Figure 40. CS Mode 4-Wire, No BUSY Indicator Serial Interface Timing Rev. B | Page 20 of 28 Data Sheet AD7687 as an interrupt signal to initiate the data readback controlled by the digital host. The AD7687 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate provided it has an acceptable hold time. After the optional 17th SCK falling edge, or SDI going high, whichever is earlier, the SDO returns to high impedance. CS MODE 4-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7687 is connected to an SPI-compatible digital host, which has an interrupt input, and it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This requirement is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 41 and the corresponding timing is given in Figure 42. CS1 CONVERT With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback (if SDI and CNV are low, SDO is driven low). Prior to the minimum conversion time, SDI could be used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time and held low until the maximum conversion time to guarantee the generation of the BUSY signal indicator. When the conversion is complete, SDO goes from high impedance to low. With a pull-up on the SDO line, this transition can be used VIO CNV DIGITAL HOST 47kΩ AD7687 DATA IN SDO SCK IRQ 02972-040 SDI CLK Figure 41. CS Mode 4-Wire with BUSY Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI tSCK tHSDICNV tSCKL 1 2 3 tHSDO 15 16 17 tSCKH tDSDO tDIS tEN SDO D15 D14 D1 Figure 42. CS Mode 4-Wire with BUSY Indicator Serial Interface Timing Rev. B | Page 21 of 28 D0 02972-041 SCK AD7687 Data Sheet onto SDO and the AD7687 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are then clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N clocks are required to readback the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and, consequently more AD7687s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. For instance, with a 3 ns digital host set-up time and 3 V interface, up to eight AD7687s running at a conversion rate of 220 kSPS can be daisy-chained on a 3-wire port. CHAIN MODE, NO BUSY INDICATOR This mode can be used to daisy chain multiple AD7687s on a 3wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7687s is shown in Figure 43 and the corresponding timing is given in Figure 44. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the BUSY indicator. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output CONVERT SDI CNV AD7687 SDO DIGITAL HOST AD7687 SDI A B SCK SCK SDO DATA IN 02972-042 CNV CLK Figure 43. Chain Mode, No BUSY Indicator Connection Diagram SDIA = 0 tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV SCK 1 tHSCKCNV 2 3 14 15 tSSDISCK 16 17 18 DA15 DA14 30 31 32 DA1 DA0 tSCKH SDOA = SDIB DA15 DA14 DA13 DA 1 DA 0 DB15 DB14 DB13 DB 1 DB 0 tHSDO tDSDO SDOB Figure 44. Chain Mode, No BUSY Indicator Serial Interface Timing Rev. B | Page 22 of 28 02972-043 tHSDISC tEN Data Sheet AD7687 Figure 45) SDO is driven high. This transition on SDO can be used as a BUSY indicator to trigger the data readback controlled by the digital host. The AD7687 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are then clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 16 × N + 1 clocks are required to readback the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7687s in the chain, provided the digital host has an acceptable hold time. For instance, with a 3 ns digital host setup time and 3 V interface, up to eight AD7687s running at a conversion rate of 220 kSPS can be daisy-chained to a single 3-wire port. CHAIN MODE WITH BUSY INDICATOR This mode can also be used to daisy-chain multiple AD7687s on a 3-wire serial interface while providing a BUSY indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7687s is shown in Figure 45 and the corresponding timing is given in Figure 46. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the BUSY indicator feature. In this mode, CNV is held high during the conversion phase and the subsequent data readback. When all ADCs in the chain have completed their conversions, the near-end ADC (ADC C in CONVERT SDI AD7687 CNV SDO AD7687 SDI DIGITAL HOST CNV SDO SDI AD7687 A B C SCK SCK SCK DATA IN SDO IRQ 02972-044 CNV CLK Figure 45. Chain Mode with BUSY Indicator Connection Diagram tCYC ACQUISITION tCONV tACQ ACQUISITION CONVERSION tSSCKCNV SCK tSCKH 1 tHSCKCNV 2 tSSDISCK tEN SDOA = SDIB 3 4 tSCK 15 16 18 19 31 32 33 34 35 tSCKL tHSDISC DA15 DA14 DA13 17 DA1 SDOB = SDIC 49 DA0 tDSDOSDI DB15 DB14 DB13 DB1 DB0 DA15 DA14 DA1 DA0 tDSDOSDI SDOC 48 tDSDOSDI tHSDO tDSDO tDSDOSDI 47 tDSDOSDI DC15 DC14 DC13 DC1 DC0 DB15 DB14 DB1 DB0 DA15 DA14 Figure 46. Chain Mode with BUSY Indicator Serial Interface Timing Rev. B | Page 23 of 28 DA1 DA0 02972-045 CNV = SDIA AD7687 Data Sheet APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7687 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7687, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7687 is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided The AD7687 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and connecting it with wide, low impedance traces. 02972-046 At least one ground plane should be used. It could be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7687s. Figure 47. Example of Layout of the AD7687 (Top Layer) Finally, the power supplies VDD and VIO of the AD7687 should be decoupled with ceramic capacitors (typically 100 nF) placed close to the AD7687 and connected using short and wide traces to provide low impedance paths and reduce the effect of glitches on the power supply lines. 02972-047 An example of layout following these rules is shown in Figure 47 and Figure 48. EVALUATING THE AD7687’S PERFORMANCE Other recommended layouts for the AD7687 are outlined in the documentation of the evaluation board for the AD7687 (EVAL-AD7687). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD3. Rev. B | Page 24 of 28 Figure 48. Example of Layout of the AD7687 (Bottom Layer) Data Sheet AD7687 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 49. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 6 0.50 0.40 0.30 5 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 1.74 1.64 1.49 EXPOSED PAD 0.05 MAX 0.02 NOM 0.30 0.25 0.20 1 BOTTOM VIEW PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.20 REF Figure 50. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters Rev. B | Page 25 of 28 121009-A PIN 1 INDEX AREA 10 AD7687 Data Sheet ORDERING GUIDE Model 1, 2, 3 AD7687BRMZ AD7687BRMZRL7 AD7687BCPZRL AD7687BCPZRL7 EVAL-AD7687CBZ EVAL-CONTROL BRD2Z EVAL-CONTROL BRD3Z 1 2 3 Integral Nonlinearity ±1.5 LSB max ±1.5 LSB max ±1.5 LSB max ±1.5 LSB max Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Transport Media, Quantity Tube, 50 Reel, 1,000 Reel, 5,000 Reel, 1,500 Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead QFN (LFCSP_WD) 10-Lead QFN (LFCSP_WD) Evaluation Board Controller Board Controller Board Package Option RM-10 RM-10 CP-10-9 CP-10-9 Branding C3Q C3Q #C03 #C03 Z = RoHS Compliant Part, # denotes RoHS compliant product, may be top or bottom marked. The EVAL-AD7687CB can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. The EVAL-CONTROL BRD2 and EVAL-CONTROL BRD3 allow a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. Rev. B | Page 26 of 28 Data Sheet AD7687 NOTES Rev. B | Page 27 of 28 AD7687 Data Sheet NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02972-0-8/11(B) Rev. B | Page 28 of 28