18-Bit, 1 MSPS PulSAR 7.0 mW ADC in MSOP/QFN AD7982 Data Sheet FEATURES APPLICATION DIAGRAM EXAMPLE 2.5V TO 5V 2.5V IN+ REF VDD VIO SDI AD7982 ±10V, ±5V, .. IN– ADA4941 SCK SDO GND CNV 1.8V TO 5V 3- OR 4-WIRE INTERFACE (SPI, CS DAISY CHAIN) 06513-001 18-bit resolution with no missing codes Throughput: 1 MSPS Low power dissipation 4 mW at 1 MSPS (VDD only) 7 mW at 1 MSPS (total) 70 μW at 10 kSPS INL: ±1 LSB typical, ±2 LSB maximum Dynamic range: 99 dB True differential analog input range: ±VREF 0 V to VREF with VREF between 2.5 V to 5.0 V Allows use of any input range Easy to drive with the ADA4941 No pipeline delay Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic interface Serial interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Ability to daisy-chain multiple ADCs and busy indicator 10-lead package: MSOP (MSOP-8 size) and 3 mm × 3 mm QFN (LFCSP), SOT-23 size Figure 1. GENERAL DESCRIPTION APPLICATIONS The AD7982 is an 18-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power supply, VDD. It contains a low power, high speed, 18-bit sampling ADC and a versatile serial interface port. On the CNV rising edge, the AD7982 samples the voltage difference between the IN+ and IN− pins. The voltages on these pins usually swing in opposite phases between 0 V and VREF. The reference voltage, REF, is applied externally and can be set independent of the supply voltage, VDD. Its power scales linearly with throughput. Battery-powered equipment Data acquisition systems Medical instruments Seismic data acquisition systems The SPI-compatible serial interface also features the ability, using the SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator. It is compatible with 1.8 V, 2.5 V, 3 V, and 5 V logic, using the separate VIO supply. The AD7982 is available in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADCs Type 18-Bit True Differential 100 kSPS 250 kSPS AD7691 400 kSPS to 500 kSPS AD7690 16-Bit True Differential AD7684 AD7687 16-Bit Pseudo Differential AD7680 AD7683 AD7940 AD7685 AD7694 AD7942 AD7688 AD7693 AD7686 14-Bit Pseudo Differential Rev. B AD7946 ≥1000 kSPS AD7982 AD7984 AD7980 ADC Driver ADA4941 ADA4841 ADA4941 ADA4841 ADA4841 ADA4841 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 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Technical Support www.analog.com AD7982 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Driver Amplifier Choice ........................................................... 14 Applications ....................................................................................... 1 Single-to-Differential Driver .................................................... 15 Application Diagram Example........................................................ 1 Voltage Reference Input ............................................................ 15 General Description ......................................................................... 1 Power Supply............................................................................... 15 Revision History ............................................................................... 2 Digital Interface .......................................................................... 16 Specifications..................................................................................... 3 CS Mode, 3-Wire Without Busy Indicator ............................. 17 Timing Specifications .................................................................. 5 CS Mode, 3-Wire with Busy Indicator .................................... 18 Absolute Maximum Ratings ............................................................ 6 CS Mode, 4-Wire Without Busy Indicator ............................. 19 ESD Caution .................................................................................. 6 CS Mode, 4-Wire with Busy Indicator .................................... 20 Pin Configurations and Function Descriptions ........................... 7 Chain Mode Without Busy Indicator ...................................... 21 Terminology ...................................................................................... 8 Chain Mode with Busy Indicator ............................................. 22 Typical Performance Characteristics ............................................. 9 Application Hints ........................................................................... 23 Theory of Operation ...................................................................... 12 Layout .......................................................................................... 23 Circuit Information .................................................................... 12 Evaluating AD7982 Performance............................................. 23 Converter Operation .................................................................. 12 Outline Dimensions ....................................................................... 24 Typical Connection Diagram.................................................... 13 Ordering Guide .......................................................................... 24 Analog Inputs .............................................................................. 14 REVISION HISTORY 7/13—Rev. A to Rev. B Added Low Power Dissipation of 4 mW at 1 MSPS (VDD only) to Features Section............................................................................ 1 Changes to Power Dissipation; Table 3 .......................................... 4 Added EPAD Notation to Figure 5 and Table 6............................ 7 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 10/07—Rev. 0 to Rev. A Changes to Table 1 and Layout ........................................................1 Changes to Table 2.............................................................................3 Changes to Layout .............................................................................5 Changes to Layout .............................................................................6 Changes to Figure 5 ...........................................................................7 Changes to Figure 18 and Figure 20 ............................................ 11 Changes to Figure 23...................................................................... 13 Changers to Figure 26 .................................................................... 15 Changes to Digital Interface Section ........................................... 16 Changes to Figure 38...................................................................... 21 Changes to Figure 40...................................................................... 22 Updated Outline Dimensions ....................................................... 24 Changes to Ordering Guide .......................................................... 24 3/07—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet AD7982 SPECIFICATIONS VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Common-Mode Input Range Analog Input CMRR Leakage Current at 25°C Input Impedance ACCURACY No Missing Codes Differential Linearity Error Integral Linearity Error Transition Noise Gain Error, TMIN to TMAX 2 Gain Error Temperature Drift Zero Error, TMIN to TMAX2 Zero Temperature Drift Power Supply Rejection Ratio THROUGHPUT Conversion Rate Transient Response AC ACCURACY Dynamic Range Oversampled Dynamic Range 4 Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion 5 Signal-to-(Noise + Distortion) Conditions Min 18 Typ IN+ − IN− IN+, IN− IN+, IN− fIN = 450 kHz Acquisition phase −VREF −0.1 VREF × 0.475 Max Unit Bits +VREF VREF + 0.1 VREF × 0.525 V V V dB nA VREF × 0.5 67 200 See the Analog Inputs section 18 −0.85 −2 REF = 5 V −0.023 VDD = 2.5 V ± 5% ±0.5 ±1 1.05 +0.004 ±1 ±100 0.5 90 0 97 95.5 +0.023 +700 1 290 Full-scale step VREF = 5 V VREF = 2.5 V FO = 1 kSPS fIN = 1 kHz, VREF = 5 V, TA = 25°C fIN = 1 kHz, VREF = 2.5 V, TA = 25°C fIN = 10 kHz fIN = 10 kHz fIN = 1 kHz, VREF = 5 V, TA = 25°C +1.5 +2 99 93 129 98 92.5 −115 −120 97 Bits LSB 1 LSB1 LSB1 % of FS ppm/°C µV ppm/°C dB MSPS ns dB 3 dB3 dB3 dB3 dB3 dB3 dB3 dB3 LSB means least significant bit. With the ±5 V input range, 1 LSB is 38.15 µV. See Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference. 3 All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. 4 Dynamic range is obtained by oversampling the ADC running at a throughput Fs of 1 MSPS followed by postdigital filtering with an output word rate of FO. 5 Tested fully in production at fIN = 1 kHz. 1 2 Rev. B | Page 3 of 24 AD7982 Data Sheet VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = −40°C to +85°C, unless otherwise noted. Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels VIL VIH VIL VIH IIL IIH DIGITAL OUTPUTS Data Format Pipeline Delay VOL VOH POWER SUPPLIES VDD VIO VIO Range Standby Current 1, 2 Power Dissipation Total VDD only REF only VIO only Energy per Conversion TEMPERATURE RANGE 3 Specified Performance Conditions Min Typ 2.4 Max Unit 5.1 1 MSPS, REF = 5 V 350 V µA VDD = 2.5 V 10 2 MHz ns VIO > 3 V VIO > 3 V VIO ≤ 3 V VIO ≤ 3 V –0.3 0.7 × VIO –0.3 0.9 × VIO −1 −1 Serial 18 bits, twos complement Conversion results available immediately after completed conversion 0.4 VIO − 0.3 ISINK = +500 µA ISOURCE = −500 µA 2.375 2.3 1.8 Specified performance VDD and VIO = 2.5 V, 25°C VDD = 2.625 V, VREF = 5 V, VIO = 3 V 10 kSPS throughput 1 MSPS throughput TMIN to TMAX +0.3 × VIO VIO + 0.3 +0.1 × VIO VIO + 0.3 +1 +1 2.5 −40 With all digital inputs forced to VIO or GND as required. During acquisition phase. 3 Contact an Analog Devices, Inc. sales representative for the extended temperature range. 1 2 Rev. B | Page 4 of 24 V V 2.625 5.5 5.5 V V V µA 86 8.6 µW mW mW mW mW nJ/sample +85 °C 0.35 70 7 4 1.7 1.3 7.0 V V V V µA µA Data Sheet AD7982 TIMING SPECIFICATIONS TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.1 Table 4. Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions CNV Pulse Width (CS Mode) SCK Period (CS Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Period (Chain Mode) VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid SCK Falling Edge to Data Valid Delay VIO Above 4.5 V VIO Above 3 V VIO Above 2.7 V VIO Above 2.3 V CNV or SDI Low to SDO D15 MSB Valid (CS Mode) VIO Above 3 V VIO Above 2.3 V CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) SDI Valid Setup Time from CNV Rising Edge SDI Valid Hold Time from CNV Rising Edge (CS Mode) SDI Valid Hold Time from CNV Rising Edge (Chain Mode) SCK Valid Setup Time from CNV Rising Edge (Chain Mode) SCK Valid Hold Time from CNV Rising Edge (Chain Mode) SDI Valid Setup Time from SCK Falling Edge (Chain Mode) SDI Valid Hold Time from SCK Falling Edge (Chain Mode) SDI High to SDO High (Chain Mode with Busy Indicator) Min 500 290 1000 10 Typ Max 710 Unit ns ns ns ns 10.5 12 13 15 ns ns ns ns 11.5 13 14 16 4.5 4.5 3 ns ns ns ns ns ns ns tSCK tSCKL tSCKH tHSDO tDSDO 9.5 11 12 14 ns ns ns ns 10 15 20 ns ns ns ns ns ns ns ns ns ns ns tEN tDIS tSSDICNV tHSDICNV tHSDICNV tSSCKCNV tHSCKCNV tSSDISCK tHSDISCK tDSDOSDI 5 2 0 5 5 2 3 15 See Figure 2 and Figure 3 for load conditions. IOL Y% VIO1 X% VIO1 tDELAY 1.4V TO SDO CL 20pF 500µA IOH tDELAY VIH2 VIL2 VIH2 VIL2 1FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30. 2MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS IH IL SPECIFICATIONS IN TABLE 3. Figure 2. Load Circuit for Digital Interface Timing Figure 3. Voltage Levels for Timing Rev. B | Page 5 of 24 06513-003 500µA 06513-002 1 Symbol tCONV tACQ tCYC tCNVH tSCK AD7982 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs IN+, IN− to GND 1 Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θJA Thermal Impedance 10-Lead MSOP 10-Lead QFN (LFCSP_WD) θJC Thermal Impedance 10-Lead MSOP 10-Lead QFN (LFCSP_WD) Lead Temperatures Vapor Phase (60 sec) Infrared (15 sec) 1 Rating −0.3 V to VREF + 0.3 V or ±130 mA −0.3 V to +6.0 V −0.3 V to +3.0 V +3 V to −6 V −0.3 V to VIO + 0.3 V −0.3 V to VIO + 0.3 V −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 200°C/W 48.7°C/W 44°C/W 2.96°C/W 215°C 220°C See the Analog Inputs section for an explanation of IN+ and IN−. Rev. B | Page 6 of 24 Data Sheet AD7982 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS REF 1 9 SDI 8 SCK IN– 4 7 SDO GND 5 6 CNV IN+ 3 10 VIO VDD 2 AD7982 9 SDI IN+ 3 TOP VIEW (Not to Scale) 8 SCK 7 SDO 6 CNV IN– 4 GND 5 TOP VIEW NOTES 1. THE EXPOSED PAD SHOULD BE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. 06513-004 REF 1 AD7982 06513-005 10 VIO VDD 2 Figure 5. 10-Lead QFN (LFCSP) Pin Configuration Figure 4. 10-Lead MSOP Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic REF Type 1 AI 2 3 4 5 6 VDD IN+ IN− GND CNV P AI AI P DI 7 8 9 SDO SCK SDI DO DI DI 10 VIO EPAD P Description Reference Input Voltage. The REF range is 2.4 V to 5.1 V. This pin is referred to the GND pin and should be decoupled closely to the GND pin with a 10 µF capacitor. Power Supply. Differential Positive Analog Input. Differential Negative Analog Input. Power Supply Ground. Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when CNV is low. In chain mode, the data should be read when CNV is high. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock. Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as follows: Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data level on SDI is output on SDO with a delay of 18 SCK cycles. CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable the serial output signals when low. If SDI or CNV is low when the conversion is complete, the busy indicator feature is enabled. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V). Exposed Pad. For the lead frame chip scale package (LFCSP), the exposed pad should be connected to GND. this connection is not required to meet the electrical performances. AI = analog input, DI = digital input, DO = digital output, and P = power. 1 Rev. B | Page 7 of 24 AD7982 Data Sheet TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 22). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Zero Error Zero error is the difference between the ideal midscale voltage, that is, 0 V, from the actual voltage producing the midscale output code, that is, 0 LSB. Gain Error The first transition (from 100 ... 00 to 100 ... 01) should occur at a level ½ LSB above nominal negative full scale (−4.999981 V for the ±5 V range). The last transition (from 011 … 10 to 011 … 11) should occur for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the ±5 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Resolution Effective resolution is calculated as Effective Resolution = log2(2N/RMS Input Noise) and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. It is measured with a signal at −60 dBF so that it includes all noise sources and DNL artifacts. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Signal-to-(Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components that are less than the Nyquist frequency, including harmonics but excluding dc. The value of SINAD is expressed in decibels. Aperture Delay Aperture delay is the measure of the acquisition performance and is the time between the rising edge of the CNV input and when the input signal is held for a conversion. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD as follows Transient Response Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied. ENOB = (SINADdB − 1.76)/6.02 and is expressed in bits. Noise-Free Code Resolution Noise-free code resolution is the number of bits beyond which it is impossible to distinctly resolve individual codes. It is calculated as Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise) and is expressed in bits. Rev. B | Page 8 of 24 Data Sheet AD7982 TYPICAL PERFORMANCE CHARACTERISTICS VDD = 2.5 V, REF = 5.0 V, VIO = 3.3 V. 2.0 POSITIVE INL: +0.79 LSB NEGATIVE INL: –0.68 LSB 1.5 1.0 1.0 0.5 0.5 DNL (LSB) 1.5 0 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 0 65536 131072 CODE 196608 262144 –2.0 0 65536 44806 43239 45000 50975 50000 40000 35000 40000 COUNTS 32476 29064 30000 20000 30000 25000 20013 20000 16682 15000 10000 9064 7795 3FFF0 0 29 3FFF2 745 881 3FFF4 3FFF6 3FFF8 43 0 0 3FFFA 3FFFC CODE IN HEX 06513-007 5000 0 0 0 7 145 0 1 2 3 4 5 6 7 8 9 222 7 0 0 A B C D CODE IN HEX Figure 10. Histogram of a DC Input at the Code Transition Figure 7. Histogram of a DC Input at the Code Center 0 100 SNR (dB REFERRED TO FULL SCALE) fS = 1MSPS fIN = 2kHz –20 SNR = 97.3dB THD = –121.8dB SFDR = 120.2dB SINAD = 97.3dB –40 –60 –80 –100 –120 –140 –160 –180 100 300 200 FREQUENCY (kHz) 400 500 06513-008 AMPLITUDE (dB OF FULL SCALE) 3158 2793 0 06513-010 10000 0 262144 50000 60000 0 196608 Figure 9. Differential Nonlinearity vs. Code Figure 6. Integral Nonlinearity vs. Code COUNTS 131072 CODE 99 98 97 96 95 94 93 92 91 90 –10 –9 –8 –7 –5 –4 –3 –6 INPUT LEVEL (dB) Figure 11. SNR vs. Input Level Figure 8. FFT Plot Rev. B | Page 9 of 24 –2 –1 0 06513-032 –2.0 POSITIVE INL: +0.46 LSB NEGATIVE INL: –0.49 LSB 06513-009 0 06513-006 INL (LSB) 2.0 AD7982 Data Sheet 18 100 SNR, SINAD –100 130 –105 125 17 115 –115 110 –120 THD 15 85 105 –125 2.75 3.25 3.75 4.25 REFERENCE VOLTAGE (V) 4.75 14 5.25 –130 2.25 06513-034 Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage 98 –117 96 –119 THD (dB) –115 100 5.25 4.75 94 92 –121 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 06513-042 –123 –125 –55 Figure 13. SNR vs. Temperature –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 06513-041 SNR (dB) 3.25 3.75 4.25 REFERENCE VOLTAGE (V) Figure 15. THD, SFDR vs. Reference Voltage 100 90 –55 2.75 1000 06513-030 80 2.25 SFDR (dB) ENOB 120 SFDR THD (dB) 16 90 ENOB (Bits) SNR, SINAD (dB) –110 06513-033 95 Figure 16. THD vs. Temperature 100 –80 –85 –90 95 THD (dB) 90 –100 –105 –110 85 –115 –120 80 0.1 1 10 FREQUENCY (kHz) 100 1000 –125 0.1 06513-031 SINAD (dB) –95 1 10 FREQUENCY (kHz) 100 Figure 17. THD vs. Frequency Figure 14. SINAD vs. Frequency Rev. B | Page 10 of 24 Data Sheet AD7982 1.4 1.4 IVDD IVDD 1.2 OPERATING CURRENTS (mA) 1.0 0.8 0.6 IREF 0.4 IVIO 0.2 2.475 2.525 SUPPLY VOLTAGE (V) 2.575 2.625 06513-036 2.425 Figure 18. Operating Currents vs. Supply Voltage 0.6 IREF 0.4 IVIO 7 6 5 4 3 IVDD + IVIO 2 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 06513-038 1 –35 0 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 Figure 20. Operating Currents vs. Temperature 8 POWER-DOWN CURRENTS (µA) 0.8 0.2 0 2.375 0 –55 1.0 Figure 19. Power-Down Currents vs. Temperature Rev. B | Page 11 of 24 125 06513-035 OPERATING CURRENTS (mA) 1.2 AD7982 Data Sheet THEORY OF OPERATION IN+ SWITCHES CONTROL MSB REF 131,072C 65,536C LSB 2C 4C C SW+ C BUSY COMP GND 131,072C 65,536C 2C 4C C CONTROL LOGIC C MSB OUTPUT CODE LSB SW– 06513-011 CNV IN– Figure 21. ADC Simplified Schematic CIRCUIT INFORMATION The AD7982 is a fast, low power, single-supply, precise, 18-bit ADC using a successive approximation architecture. The AD7982 is capable of converting 1,000,000 samples per second (1 MSPS) and powers down between conversions. When operating at 10 kSPS, for example, it typically consumes 70 µW, making it ideal for battery-powered applications. The AD7982 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7982 can be interfaced to any 1.8 V to 5 V digital logic family. It is available in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that allows space savings and flexible configurations. It is pin-for-pin-compatible with the 16-bit AD7980. CONVERTER OPERATION The AD7982 is a successive approximation ADC based on a charge redistribution DAC. Figure 21 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 18 binary-weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the input of the comparator are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs IN+ and IN− captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/262,144). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator. Because the AD7982 has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. Rev. B | Page 12 of 24 Data Sheet AD7982 Transfer Functions Table 7. Output Codes and Ideal Input Voltages Description FSR – 1 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 011...111 011...110 011...101 1 2 100...010 Analog Input VREF = 5 V +4.999962 V +38.15 μV 0V −38.15 μV −4.999962 V −5 V Digital Output Code (Hex) 0x1FFFF1 0x00001 0x00000 0x3FFFF 0x20001 0x200002 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND). This is also the code for an underranged analog input (VIN+ − VIN− below VGND). TYPICAL CONNECTION DIAGRAM 100...001 100...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 23 shows an example of the recommended connection diagram for the AD7982 when multiple supplies are available. 06513-012 Figure 22. ADC Ideal Transfer Function V+ REF1 2.5V 10µF2 100nF V+ 1.8V TO 5V 100nF 20Ω 0 TO VREF REF 2.7nF VDD V– AD7982 4 V+ 20Ω ADA48412, 3 SCK SDO IN– VREF TO 0 VIO SDI IN+ GND 3-WIRE INTERFACE CNV 2.7nF V– 4 NOTES 1SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION. 2C REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R). SEE RECOMMENDED LAYOUT FIGURE 41 AND FIGURE 42. 3SEE DRIVER AMPLIFIER CHOICE SECTION. 4OPTIONAL FILTER. SEE ANALOG INPUT SECTION. Figure 23. Typical Application Diagram with Multiple Supplies Rev. B | Page 13 of 24 06513-013 ADC CODE (TWOS COMPLEMENT) The ideal transfer characteristic for the AD7982 is shown in Figure 22 and Table 7. AD7982 Data Sheet ANALOG INPUTS Figure 24 shows an equivalent circuit of the input structure of the AD7982. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN+ and IN−. Care must be taken to ensure that the analog input signal does not exceed the reference input voltage (REF) by more than 0.3 V. If the analog input signal exceeds this level, the diodes become forward biased and start conducting current. These diodes can handle a forward-biased current of 130 mA maximum. However, if the supplies of the input buffer (for example, the supplies of the ADA4841 in Figure 23) are different from those of the REF, the analog input signal may eventually exceed the supply rails by more than 0.3 V. In such a case (for example, an input buffer with a shortcircuit), the current limitation can be used to protect the part. When the source impedance of the driving circuit is low, the AD7982 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency. DRIVER AMPLIFIER CHOICE Although the AD7982 is easy to drive, the driver amplifier must meet the following requirements: REF D1 RIN The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7982. The noise from the driver is filtered by the AD7982 analog input circuit’s 1-pole, lowpass filter made by RIN and CIN or by the external filter, if one is used. Because the typical noise of the AD7982 is 40 μV rms, the SNR degradation due to the amplifier is CIN IN+ OR IN– D2 06513-014 CPIN GND SNRLOSS Figure 24. Equivalent Analog Input Circuit 90 85 CMRR (dB) 80 75 70 10 100 FREQUENCY (kHz) 1000 10000 06513-040 65 1 Figure 25. Analog Input CMRR vs. Frequency During the acquisition phase, the impedance of the analog inputs (IN+ or IN−) can be modeled as a parallel combination of Capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 400 Ω and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 30 pF and is mainly the ADC sampling capacitor. During the sampling phase, where the switches are closed, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits noise. where: f–3dB is the input bandwidth, in megahertz, of the AD7982 (10 MHz) or the cutoff frequency of the input filter, if one is used. N is the noise gain of the amplifier (for example, 1 in buffer configuration). eN is the equivalent input noise voltage of the op amp, in nV/√Hz. The analog input structure allows the sampling of the true differential signal between IN+ and IN−. By using these differential inputs, signals common to both inputs are rejected. 60 40 20 log π 2 2 40 f 3dB (NeN ) 2 For ac applications, the driver should have a THD performance commensurate with the AD7982. For multichannel multiplexed applications, the driver amplifier and the AD7982 analog input circuit must settle for a full-scale step onto the capacitor array at an 18-bit level (0.0004%, 4 ppm). In the data sheet of the amplifier, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at an 18-bit level and should be verified prior to driver selection. Table 8. Recommended Driver Amplifiers Amplifier ADA4941-1 ADA4841 AD8021 AD8022 OP184 AD8655 AD8605, AD8615 Rev. B | Page 14 of 24 Typical Application Very low noise, low power, single to differential Very low noise, small, and low power Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single supply, low noise 5 V single supply, low power Data Sheet AD7982 SINGLE-TO-DIFFERENTIAL DRIVER POWER SUPPLY For applications using a single-ended analog signal, either bipolar or unipolar, the ADA4941 single-ended-to-differential driver allows for a differential input to the part. The schematic is shown in Figure 26. The AD7982 uses two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5.5 V. To reduce the number of supplies needed, VIO and VDD can be tied together. The AD7982 is independent of power supply sequencing between VIO and VDD. Additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in Figure 27. R1 and R2 set the attenuation ratio between the input range and the ADC range (VREF). R1, R2, and CF are chosen depending on the desired input resistance, signal bandwidth, antialiasing, and noise contribution. For example, for the ±10 V range with a 4 kΩ impedance, R2 = 1 kΩ and R1 = 4 kΩ. 95 90 R3 and R4 set the common mode on the IN− input, and R5 and R6 set the common mode on the IN+ input of the ADC. The common mode should be close to VREF/2. For example, for the ±10 V range with a single supply, R3 = 8.45 kΩ, R4 = 11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ. R4 +5V REF 10µF OUTN 20Ω 2.7nF 2.7nF OUTP +2.5V 20Ω IN IN+ REF 10 100 FREQUENCY (kHz) 1000 Figure 27. PSRR vs. Frequency AD7982 IN– To ensure optimum performance, VDD should be roughly half of REF, the voltage reference input. For example, if REF is 5.0 V, VDD should be set to 2.5 V (±5%). GND ADA4941 –0.2V R2 06513-015 R1 1 VDD FB ±10V, ±5V, .. 65 60 REF 100nF PSRR (dB) 70 +5.2V 100nF 75 06513-039 R3 80 CF Figure 26. Single-Ended-to-Differential Driver Circuit The AD7982 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. This makes the part ideal for low sampling rates (even of a few hertz) and low battery-powered applications. 10.000 VOLTAGE REFERENCE INPUT The AD7982 voltage reference input, REF, has a dynamic input impedance and should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source (for example, a reference buffer using the AD8031 or the AD8605), a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If an unbuffered reference voltage is used, the decoupling value depends on the reference used. For instance, a 22 μF (X5R, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift ADR43x reference. If desired, a reference decoupling capacitor with values as small as 2.2 μF can be used with a minimal impact on performance, especially DNL. Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins. Rev. B | Page 15 of 24 1.000 IVDD 0.100 IREF IVIO 0.010 0.001 10000 100000 SAMPLING RATE (SPS) Figure 28. Operating Currents vs. Sampling Rate 1000000 06513-037 R6 OPERATING CURRENTS (mA) R5 85 AD7982 Data Sheet DIGITAL INTERFACE Although the AD7982 has a reduced number of pins, it offers flexibility in its serial interface modes. When in CS mode, the AD7982 is compatible with SPI, QSPI, digital hosts, and DSPs. In this mode, the AD7982 can use either a 3-wire or 4-wire interface. A 3-wire interface using the CNV, SCK, and SDO signals minimizes wiring connections useful, for instance, in isolated applications. A 4-wire interface using the SDI, CNV, SCK, and SDO signals allows CNV, which initiates the conversions, to be independent of the readback timing (SDI). This is useful in low jitter sampling or simultaneous sampling applications. When in chain mode, the AD7982 provides a daisy-chain feature using the SDI input for cascading multiple ADCs on a single data line similar to a shift register. The mode in which the part operates depends on the SDI level when the CNV rising edge occurs. The CS mode is selected if SDI is high, and the chain mode is selected if SDI is low. The SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. In either mode, the AD7982 offers the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. Otherwise, without a busy indicator, the user must timeout the maximum conversion time prior to readback. The busy indicator feature is enabled • • Rev. B | Page 16 of 24 In the CS mode if CNV or SDI is low when the ADC conversion ends (see Figure 32 and Figure 36). In the chain mode if SCK is high during the CNV rising edge (see Figure 40). Data Sheet AD7982 high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7982 enters the acquisition phase and powers down. When CNV goes low, the MSB is output onto SDO. The remaining data bits are clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 18th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. CS MODE, 3-WIRE WITHOUT BUSY INDICATOR This mode is usually used when a single AD7982 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 29, and the corresponding timing is given in Figure 30. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. Once a conversion is initiated, it continues until completion irrespective of the state of CNV. This can be useful, for instance, to bring CNV low to select other SPI devices, such as analog multiplexers; however, CNV must be returned high before the minimum conversion time elapses and then held CONVERT DIGITAL HOST CNV VIO SDI AD7982 DATA IN SDO 06513-016 SCK CLK Figure 29. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 16 tHSDO 18 tSCKH tDSDO tEN SDO 17 D17 D16 D15 tDIS D1 D0 Figure 30. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 17 of 24 06513-017 SCK AD7982 Data Sheet CS MODE, 3-WIRE WITH BUSY INDICATOR When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data reading controlled by the digital host. The AD7982 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 19th SCK falling edge or when CNV goes high (whichever occurs first), SDO returns to high impedance. This mode is usually used when a single AD7982 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 31, and the corresponding timing is given in Figure 32. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. SDO is maintained in high impedance until the completion of the conversion irrespective of the state of CNV. Prior to the minimum conversion time, CNV can be used to select other SPI devices, such as analog multiplexers, but CNV must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. If multiple AD7982s are selected at the same time, the SDO output pin handles this contention without damage or induced latch-up. Meanwhile, it is recommended to keep this contention as short as possible to limit extra power dissipation. CONVERT VIO CNV AD7982 DATA IN SDO IRQ SCK 06513-018 SDI DIGITAL HOST 47kΩ VIO CLK Figure 31. CS Mode, 3-Wire with Busy Indicator Connection Diagram (SDI High) SDI = 1 tCYC tCNVH CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL 1 2 3 17 tHSDO 18 19 tSCKH tDSDO SDO D17 D16 tDIS D1 D0 Figure 32. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High) Rev. B | Page 18 of 24 06513-019 SCK Data Sheet AD7982 time elapses and then held high for the maximum possible conversion time to avoid the generation of the busy signal indicator. When the conversion is complete, the AD7982 enters the acquisition phase and powers down. Each ADC result can be read by bringing its SDI input low, which consequently outputs the MSB onto SDO. The remaining data bits are then clocked by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 18th SCK falling edge or when SDI goes high (whichever occurs first), SDO returns to high impedance and another AD7982 can be read. CS MODE, 4-WIRE WITHOUT BUSY INDICATOR This mode is usually used when multiple AD7982s are connected to an SPI-compatible digital host. A connection diagram example using two AD7982s is shown in Figure 33, and the corresponding timing is given in Figure 34. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low, SDO is driven low.) Prior to the minimum conversion time, SDI can be used to select other SPI devices, such as analog multiplexers, but SDI must be returned high before the minimum conversion CS2 CS1 CONVERT CNV AD7982 SDO SDI AD7982 SCK DIGITAL HOST SDO SCK DATA IN CLK 06513-020 SDI CNV Figure 33. CS Mode, 4-Wire Without Busy Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI(CS1) tHSDICNV SDI(CS2) tSCK tSCKL 1 2 3 16 tHSDO 18 19 20 D1 D0 D17 D16 34 35 36 D1 D0 tSCKH tDSDO tEN SDO 17 D17 D16 D15 tDIS Figure 34. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Rev. B | Page 19 of 24 06513-021 SCK AD7982 Data Sheet used to select other SPI devices, such as analog multiplexers, but SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. When the conversion is complete, SDO goes from high impedance to low impedance. With a pull-up on the SDO line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. The AD7982 then enters the acquisition phase and powers down. The data bits are then clocked out, MSB first, by subsequent SCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 19th SCK falling edge or SDI going high (whichever occurs first), SDO returns to high impedance. CS MODE, 4-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7982 is connected to an SPI-compatible digital host with an interrupt input and when it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This independence is particularly important in applications where low jitter on CNV is desired. The connection diagram is shown in Figure 35, and the corresponding timing is given in Figure 36. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback. (If SDI and CNV are low, SDO is driven low.) Prior to the minimum conversion time, SDI can be CS1 CONVERT VIO CNV AD7982 DATA IN SDO IRQ SCK 06513-022 SDI DIGITAL HOST 47kΩ CLK Figure 35. CS Mode, 4-Wire with Busy Indicator Connection Diagram tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSSDICNV SDI tSCK tHSDICNV tSCKL 1 2 3 tHSDO 17 18 19 tSCKH tDSDO tDIS tEN SDO D17 D16 D1 Figure 36. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Rev. B | Page 20 of 24 D0 06513-023 SCK Data Sheet AD7982 held high during the conversion phase and the subsequent data readback. When the conversion is complete, the MSB is output onto SDO and the AD7982 enters the acquisition phase and powers down. The remaining data bits stored in the internal shift register are clocked by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 18 × N clocks are required to read back the N ADCs. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7982s in the chain, provided the digital host has an acceptable hold time. The maximum conversion rate may be reduced due to the total readback time. CHAIN MODE WITHOUT BUSY INDICATOR This mode can be used to daisy-chain multiple AD7982s on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using two AD7982s is shown in Figure 37, and the corresponding timing is given in Figure 38. When SDI and CNV are low, SDO is driven low. With SCK low, a rising edge on CNV initiates a conversion, selects the chain mode, and disables the busy indicator. In this mode, CNV is CONVERT CNV AD7982 SDO SDI DIGITAL HOST AD7982 A SCK SDO DATA IN B SCK 06513-024 SDI CNV CLK Figure 37. Chain Mode Without Busy Indicator Connection Diagram SDIA = 0 tCYC CNV ACQUISITION tCONV tACQ CONVERSION ACQUISITION tSCK tSCKL tSSCKCNV SCK 1 tHSCKCNV 2 3 16 17 tSSDISCK 18 19 20 DA17 DA16 34 35 36 DA1 D A0 tSCKH tHSDISCK tEN SDOA = SDIB DA17 DA16 DA15 D A1 DA0 DB17 DB16 DB15 D B1 DB0 SDOB Figure 38. Chain Mode Without Busy Indicator Serial Interface Timing Rev. B | Page 21 of 24 06513-025 tHSDO tDSDO AD7982 Data Sheet subsequent data readback. When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7982 ADC labeled C in Figure 39) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7982 then enters the acquisition phase and powers down. The data bits stored in the internal shift register are clocked out, MSB first, by subsequent SCK falling edges. For each ADC, SDI feeds the input of the internal shift register and is clocked by the SCK falling edge. Each ADC in the chain outputs its data MSB first, and 18 × N + 1 clocks are required to read back the N ADCs. Although the rising edge can be used to capture the data, a digital host using the SCK falling edge allows a faster reading rate and consequently more AD7982s in the chain, provided the digital host has an acceptable hold time. CHAIN MODE WITH BUSY INDICATOR This mode can also be used to daisy-chain multiple AD7982s on a 3-wire serial interface while providing a busy indicator. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. A connection diagram example using three AD7982s is shown in Figure 39, and the corresponding timing is given in Figure 40. When SDI and CNV are low, SDO is driven low. With SCK high, a rising edge on CNV initiates a conversion, selects the chain mode, and enables the busy indicator feature. In this mode, CNV is held high during the conversion phase and the CONVERT SDI CNV AD7982 SDO SDI CNV AD7982 SDO AD7982 SDI B SCK A SCK DIGITAL HOST SDO DATA IN C SCK IRQ 06513-026 CNV CLK Figure 39. Chain Mode with Busy Indicator Connection Diagram tCYC ACQUISITION tCONV tACQ ACQUISITION CONVERSION tSSCKCNV SCK 1 tHSCKCNV tSCK tSCKH 2 tSSDISCK tEN SDOA = SDIB 3 4 17 18 tHSDISCK DA17 DA16 DA15 19 20 21 35 36 37 38 39 tSCKL DA1 SDOB = SDIC 55 DA0 tDSDOSDI DB17 DB16 DB15 DB1 DB0 DA17 DA16 DA1 D A0 DC17 DC16 DC15 DC1 DC0 DB17 DB16 DB1 DB0 DA17 DA16 tDSDOSDI SDOC 54 tDSDOSDI tHSDO tDSDO tDSDOSDI 53 tDSDOSDI Figure 40. Chain Mode with Busy Indicator Serial Interface Timing Rev. B | Page 22 of 24 DA1 DA0 06513-027 CNV = SDIA Data Sheet AD7982 APPLICATION HINTS LAYOUT The printed circuit board that houses the AD7982 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7982, with its analog signals on the left side and its digital signals on the right side, eases this task. AD7982 At least one ground plane should be used. It can be common or split between the digital and analog sections. In the latter case, the planes should be joined underneath the AD7982s. 06513-028 Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7982 is used as a shield. Fast switching signals, such as CNV or clocks, should not run near analog signal paths. Crossover of digital and analog signals should be avoided. Figure 41. Example Layout of the AD7982 (Top Layer) The AD7982 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. This is done by placing the reference decoupling ceramic capacitor close to, ideally right up against, the REF and GND pins and connecting them with wide, low impedance traces. Finally, the power supplies VDD and VIO of the AD7982 should be decoupled with ceramic capacitors, typically 100 nF, placed close to the AD7982 and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. 06513-029 An example of layout following these rules is shown in Figure 41 and Figure 42. EVALUATING AD7982 PERFORMANCE Other recommended layouts for the AD7982 are outlined in the documentation of the evaluation board for the AD7982 (EVAL-AD7982SDZ). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-SDP-CB1Z. Rev. B | Page 23 of 24 Figure 42. Example Layout of the AD7982 (Bottom Layer) AD7982 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.70 0.55 0.40 0.23 0.13 6° 0° 091709-A 0.15 0.05 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 43. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.48 2.38 2.23 3.10 3.00 SQ 2.90 0.50 BSC 10 6 1.74 1.64 1.49 EXPOSED PAD 0.50 0.40 0.30 1 5 BOTTOM VIEW TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.30 0.25 0.20 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 MIN PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 02-05-2013-C PIN 1 INDEX AREA 0.20 REF Figure 44. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)] 3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7982BRMZ AD7982BRMZRL7 AD7982BCPZ-RL7 AD7982BCPZ-RL EVAL-AD7982SDZ EVAL-SDP-CB1Z 1 2 3 Notes Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C 2 3 Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead QFN (LFCSP_WD) 10-Lead QFN (LFCSP_WD) Evaluation Board Controller Board Package Option RM-10 RM-10 CP-10-9 CP-10-9 Ordering Quantity Tube, 50 Reel, 1000 Reel, 1500 Reel, 5000 Z = RoHS compliant part. This board can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes. This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SDZ designator. ©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06513–0–7/13(B) Rev. B | Page 24 of 24 Branding C5F C5F C5F C5F